diff --git a/Arcade_MiST/ArcadeMenu_MIST/Release/menu.rbf b/Arcade_MiST/ArcadeMenu_MIST/Release/menu.rbf deleted file mode 100644 index d8126cc7..00000000 Binary files a/Arcade_MiST/ArcadeMenu_MIST/Release/menu.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf b/Arcade_MiST/Atari BW Raster Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf deleted file mode 100644 index eeebce7b..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/Dominos_MiST/Release/dominos.rbf b/Arcade_MiST/Atari BW Raster Hardware/Dominos_MiST/Release/dominos.rbf deleted file mode 100644 index b03dd890..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/Dominos_MiST/Release/dominos.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf deleted file mode 100644 index 24cc83f5..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf deleted file mode 100644 index 51312c81..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/Release/SuperBreakout.rbf b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/Release/SuperBreakout.rbf deleted file mode 100644 index 7d7dbffa..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/Release/SuperBreakout.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/snapshot/ultratank.rbf b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/snapshot/ultratank.rbf deleted file mode 100644 index d2e2339f..00000000 Binary files a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/snapshot/ultratank.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf deleted file mode 100644 index 079036c6..00000000 Binary files a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Release/Centipede.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/Release/ComputerSpace_MiST.rbf b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/Release/ComputerSpace_MiST.rbf deleted file mode 100644 index cda2c306..00000000 Binary files a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/Release/ComputerSpace_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Tetris/Release/TETRIS.ROM b/Arcade_MiST/Atari Tetris/Release/TETRIS.ROM deleted file mode 100644 index e1eff88d..00000000 Binary files a/Arcade_MiST/Atari Tetris/Release/TETRIS.ROM and /dev/null differ diff --git a/Arcade_MiST/Atari Tetris/Release/Tetris.rbf b/Arcade_MiST/Atari Tetris/Release/Tetris.rbf deleted file mode 100644 index 542aff94..00000000 Binary files a/Arcade_MiST/Atari Tetris/Release/Tetris.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BWIDOW.ROM b/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BWIDOW.ROM deleted file mode 100644 index f5313b9b..00000000 Binary files a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BWIDOW.ROM and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BlackWidow.rbf b/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BlackWidow.rbf deleted file mode 100644 index 3ffcea04..00000000 Binary files a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/BlackWidow.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/GRAVITAR.ROM b/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/GRAVITAR.ROM deleted file mode 100644 index be72a536..00000000 Binary files a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/GRAVITAR.ROM and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/Gravitar.rbf b/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/Gravitar.rbf deleted file mode 100644 index 04be91e7..00000000 Binary files a/Arcade_MiST/Atari Vector/BlackWidow_MiST/Snapshot/Gravitar.rbf and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LLANDER.ROM b/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LLANDER.ROM deleted file mode 100644 index f09eeb5e..00000000 Binary files a/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LLANDER.ROM and /dev/null differ diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LunarLander.rbf b/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LunarLander.rbf deleted file mode 100644 index 700d3af6..00000000 Binary files a/Arcade_MiST/Atari Vector/LunarLander_MiST/Release/LunarLander.rbf and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Bagman_MiST/Release/Bagman.rbf b/Arcade_MiST/Bagman Hardware/Bagman_MiST/Release/Bagman.rbf deleted file mode 100644 index 1b46c5e9..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Bagman_MiST/Release/Bagman.rbf and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Botanic_MiST/Release/Botanic.rbf b/Arcade_MiST/Bagman Hardware/Botanic_MiST/Release/Botanic.rbf deleted file mode 100644 index 907db4b2..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Botanic_MiST/Release/Botanic.rbf and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Pickin_MiST/Release/Pickin.rbf b/Arcade_MiST/Bagman Hardware/Pickin_MiST/Release/Pickin.rbf deleted file mode 100644 index 7b4e57ea..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Pickin_MiST/Release/Pickin.rbf and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Squash_MiST/Release/Squash.rbf b/Arcade_MiST/Bagman Hardware/Squash_MiST/Release/Squash.rbf deleted file mode 100644 index 881d8a11..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Squash_MiST/Release/Squash.rbf and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SBAGMAN.ROM b/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SBAGMAN.ROM deleted file mode 100644 index acf6b9a9..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SBAGMAN.ROM and /dev/null differ diff --git a/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SuperBagman.rbf b/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SuperBagman.rbf deleted file mode 100644 index b024058f..00000000 Binary files a/Arcade_MiST/Bagman Hardware/Super Bagman_MiST/Release/SuperBagman.rbf and /dev/null differ diff --git a/Arcade_MiST/Berzerk Hardware/Berzerk_MiST/Release/Berzerk_MiST.rbf b/Arcade_MiST/Berzerk Hardware/Berzerk_MiST/Release/Berzerk_MiST.rbf deleted file mode 100644 index 725cb1a8..00000000 Binary files a/Arcade_MiST/Berzerk Hardware/Berzerk_MiST/Release/Berzerk_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Berzerk Hardware/Frenzy_MiST/Release/Frenzy_MiST.rbf b/Arcade_MiST/Berzerk Hardware/Frenzy_MiST/Release/Frenzy_MiST.rbf deleted file mode 100644 index 1715cc69..00000000 Binary files a/Arcade_MiST/Berzerk Hardware/Frenzy_MiST/Release/Frenzy_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Berzerk Hardware/MoonWar_MiST/Release/MoonWar_MiST.rbf b/Arcade_MiST/Berzerk Hardware/MoonWar_MiST/Release/MoonWar_MiST.rbf deleted file mode 100644 index 76abefe9..00000000 Binary files a/Arcade_MiST/Berzerk Hardware/MoonWar_MiST/Release/MoonWar_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/Release/CClimber.rbf b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/Release/CClimber.rbf deleted file mode 100644 index 5b615256..00000000 Binary files a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/Release/CClimber.rbf and /dev/null differ diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v1.rbf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v1.rbf deleted file mode 100644 index 657c86f9..00000000 Binary files a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v1.rbf and /dev/null differ diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v2.rbf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v2.rbf deleted file mode 100644 index 59205d2f..00000000 Binary files a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong_v2.rbf and /dev/null differ diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/Release/RiverPatrol.rbf b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/Release/RiverPatrol.rbf deleted file mode 100644 index da212fb4..00000000 Binary files a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/Release/RiverPatrol.rbf and /dev/null differ diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf deleted file mode 100644 index bc0172e6..00000000 Binary files a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/Release/SilverLand.rbf and /dev/null differ diff --git a/Arcade_MiST/Data East Burger Time Hardware/Burger_Time_MiST/Release/burger_time_mist.rbf b/Arcade_MiST/Data East Burger Time Hardware/Burger_Time_MiST/Release/burger_time_mist.rbf deleted file mode 100644 index 3d7e1d50..00000000 Binary files a/Arcade_MiST/Data East Burger Time Hardware/Burger_Time_MiST/Release/burger_time_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Data East Burger Time Hardware/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf b/Arcade_MiST/Data East Burger Time Hardware/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf deleted file mode 100644 index cfdef2ab..00000000 Binary files a/Arcade_MiST/Data East Burger Time Hardware/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/Release/DottoriKun.rbf b/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/Release/DottoriKun.rbf deleted file mode 100644 index fa393b9d..00000000 Binary files a/Arcade_MiST/Dottori-Kun Hardware/DottoriKun_MiST/Release/DottoriKun.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/Bosconian_MiST/Snapshot/BOSCO.ROM b/Arcade_MiST/Galaga Hardware/Bosconian_MiST/Snapshot/BOSCO.ROM deleted file mode 100644 index bb6b48b8..00000000 Binary files a/Arcade_MiST/Galaga Hardware/Bosconian_MiST/Snapshot/BOSCO.ROM and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DIGDUG.ROM b/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DIGDUG.ROM deleted file mode 100644 index 72aebf34..00000000 Binary files a/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DIGDUG.ROM and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DigDug_MiST.rbf b/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DigDug_MiST.rbf deleted file mode 100644 index 59994382..00000000 Binary files a/Arcade_MiST/Galaga Hardware/DigDug_MiST/Release/DigDug_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/Galaga_MiST/Release/galaga_mist.rbf b/Arcade_MiST/Galaga Hardware/Galaga_MiST/Release/galaga_mist.rbf deleted file mode 100644 index 1493ce50..00000000 Binary files a/Arcade_MiST/Galaga Hardware/Galaga_MiST/Release/galaga_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/SXEVIOUS.ROM b/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/SXEVIOUS.ROM deleted file mode 100644 index 64340454..00000000 Binary files a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/SXEVIOUS.ROM and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/XEVIOUS.ROM b/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/XEVIOUS.ROM deleted file mode 100644 index c7eb0704..00000000 Binary files a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/XEVIOUS.ROM and /dev/null differ diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/Xevious_MiST.rbf b/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/Xevious_MiST.rbf deleted file mode 100644 index 99b59050..00000000 Binary files a/Arcade_MiST/Galaga Hardware/Xevious_MiST/Release/Xevious_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Azurian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Azurian.rbf deleted file mode 100644 index a7465ab2..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Azurian.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Blackhole.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Blackhole.rbf deleted file mode 100644 index 77974f87..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Blackhole.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Catacomb.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Catacomb.rbf deleted file mode 100644 index a5abb86e..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Catacomb.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/ChewingGum.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/ChewingGum.rbf deleted file mode 100644 index f919e3de..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/ChewingGum.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/DevilFish.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/DevilFish.rbf deleted file mode 100644 index 856340f9..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/DevilFish.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Galaxian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Galaxian.rbf deleted file mode 100644 index d2658ecd..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Galaxian.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/KingBalloon.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/KingBalloon.rbf deleted file mode 100644 index 1b772292..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/KingBalloon.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MoonCresta.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MoonCresta.rbf deleted file mode 100644 index 36cabea8..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MoonCresta.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MrDosNightmare.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MrDosNightmare.rbf deleted file mode 100644 index 6c17555b..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/MrDosNightmare.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Omega.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Omega.rbf deleted file mode 100644 index 44974189..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Omega.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Orbitron.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Orbitron.rbf deleted file mode 100644 index 4ea5a242..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Orbitron.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Pisces.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Pisces.rbf deleted file mode 100644 index 45bfef98..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Pisces.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/TripleDrawPoker.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/TripleDrawPoker.rbf deleted file mode 100644 index 28046803..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/TripleDrawPoker.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/UniWars.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/UniWars.rbf deleted file mode 100644 index 3574261a..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/UniWars.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Victory.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Victory.rbf deleted file mode 100644 index 52e61e3e..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/Victory.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/WarOfTheBugs.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/WarOfTheBugs.rbf deleted file mode 100644 index 3c6cb536..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Releases/WarOfTheBugs.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ZigZag_MiST/Release/ZigZag.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ZigZag_MiST/Release/ZigZag.rbf deleted file mode 100644 index 5eeed057..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/ZigZag_MiST/Release/ZigZag.rbf and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf deleted file mode 100644 index 1773018d..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/SHTRIDER.ROM b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/SHTRIDER.ROM deleted file mode 100644 index 564012ee..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/SHTRIDER.ROM and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/ShotRider_MiST.rbf b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/ShotRider_MiST.rbf deleted file mode 100644 index 3fbc0042..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/ShotRider_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TRAVRUSA.ROM b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TRAVRUSA.ROM deleted file mode 100644 index c8e576f7..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TRAVRUSA.ROM and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TROPANG.ROM b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TROPANG.ROM deleted file mode 100644 index 3ccdd717..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TROPANG.ROM and /dev/null differ diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TraverseUSA_MiST.rbf b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TraverseUSA_MiST.rbf deleted file mode 100644 index e099817f..00000000 Binary files a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/Release/TraverseUSA_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM deleted file mode 100644 index 70039155..00000000 Binary files a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/POOYAN.ROM b/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/POOYAN.ROM deleted file mode 100644 index 3e7649d5..00000000 Binary files a/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/POOYAN.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/pooyan_mist.rbf b/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/pooyan_mist.rbf deleted file mode 100644 index 096bd5df..00000000 Binary files a/Arcade_MiST/Konami Classic/Pooyan_MiST/Release/pooyan_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/Power_Surge.rbf b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/Power_Surge.rbf deleted file mode 100644 index 329ebb02..00000000 Binary files a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/Power_Surge.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/power_surge_prog.bin b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/power_surge_prog.bin deleted file mode 100644 index e8c66970..00000000 Binary files a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Release/power_surge_prog.bin and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/TIMEPLT.ROM b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/TIMEPLT.ROM deleted file mode 100644 index 541dee55..00000000 Binary files a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/TIMEPLT.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf deleted file mode 100644 index cb043512..00000000 Binary files a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/GBERET.ROM b/Arcade_MiST/Konami Green Beret Hardware/Releases/GBERET.ROM deleted file mode 100644 index a14f58ae..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/GBERET.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/GBeret.rbf b/Arcade_MiST/Konami Green Beret Hardware/Releases/GBeret.rbf deleted file mode 100644 index 38446fdd..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/GBeret.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/MRGOEMON.ROM b/Arcade_MiST/Konami Green Beret Hardware/Releases/MRGOEMON.ROM deleted file mode 100644 index d656e07c..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/MRGOEMON.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/Mr.Goemon.rbf b/Arcade_MiST/Konami Green Beret Hardware/Releases/Mr.Goemon.rbf deleted file mode 100644 index 8aeb25dd..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/Mr.Goemon.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/RUSHNA.ROM b/Arcade_MiST/Konami Green Beret Hardware/Releases/RUSHNA.ROM deleted file mode 100644 index 8bf423d8..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/RUSHNA.ROM and /dev/null differ diff --git a/Arcade_MiST/Konami Green Beret Hardware/Releases/Rush´nAttack.rbf b/Arcade_MiST/Konami Green Beret Hardware/Releases/Rush´nAttack.rbf deleted file mode 100644 index cedc14a4..00000000 Binary files a/Arcade_MiST/Konami Green Beret Hardware/Releases/Rush´nAttack.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Release/Amidar.rbf b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Release/Amidar.rbf deleted file mode 100644 index 03a90820..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Release/Amidar.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/ArmoredCar_MiST/Release/ArmoredCar.rbf b/Arcade_MiST/Konami Scramble Hardware/ArmoredCar_MiST/Release/ArmoredCar.rbf deleted file mode 100644 index cf957c4c..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/ArmoredCar_MiST/Release/ArmoredCar.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Release/Calipso.rbf b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Release/Calipso.rbf deleted file mode 100644 index 9bb7644b..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Release/Calipso.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Release/Frogger.rbf b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Release/Frogger.rbf deleted file mode 100644 index 9c4dacdf..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Release/Frogger.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/Release/MoonWar.rbf b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/Release/MoonWar.rbf deleted file mode 100644 index cbe587e4..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/Release/MoonWar.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Release/Scramble.rbf b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Release/Scramble.rbf deleted file mode 100644 index f2d2c901..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Release/Scramble.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf deleted file mode 100644 index fa5debc4..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf deleted file mode 100644 index 838f3fbd..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf deleted file mode 100644 index c28580fa..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf and /dev/null differ diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf deleted file mode 100644 index b06dd416..00000000 Binary files a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf and /dev/null differ diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf deleted file mode 100644 index e002b801..00000000 Binary files a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf and /dev/null differ diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf deleted file mode 100644 index 72205ceb..00000000 Binary files a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf and /dev/null differ diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf deleted file mode 100644 index 2aa7718d..00000000 Binary files a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf and /dev/null differ diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf deleted file mode 100644 index e9d10e9d..00000000 Binary files a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DPOKER.ROM b/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DPOKER.ROM deleted file mode 100644 index 60a96da4..00000000 Binary files a/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DPOKER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DrawPoker.rbf b/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DrawPoker.rbf deleted file mode 100644 index 3116fa5c..00000000 Binary files a/Arcade_MiST/Midway MCR 1/DrawPoker_MiST/Snapshot/DrawPoker.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/KICKMAN.ROM b/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/KICKMAN.ROM deleted file mode 100644 index 9ecbd5b6..00000000 Binary files a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/KICKMAN.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/Kickman.rbf b/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/Kickman.rbf deleted file mode 100644 index 1b5798a7..00000000 Binary files a/Arcade_MiST/Midway MCR 1/Kickman_MiST/Release/Kickman.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SOLARFOX.ROM b/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SOLARFOX.ROM deleted file mode 100644 index 9c159603..00000000 Binary files a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SOLARFOX.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SolarFox.rbf b/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SolarFox.rbf deleted file mode 100644 index 617f0a69..00000000 Binary files a/Arcade_MiST/Midway MCR 1/SolarFox_MiST/Release/SolarFox.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DOMINO.ROM b/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DOMINO.ROM deleted file mode 100644 index 43c440ce..00000000 Binary files a/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DOMINO.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DominoMan.rbf b/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DominoMan.rbf deleted file mode 100644 index 34398f0c..00000000 Binary files a/Arcade_MiST/Midway MCR 2/DominoMan_MiST/Release/DominoMan.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/JOURNEY.ROM b/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/JOURNEY.ROM deleted file mode 100644 index ec77e4fc..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/JOURNEY.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/Journey.rbf b/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/Journey.rbf deleted file mode 100644 index 6222ea9b..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Journey_MiST/Snapshot/Journey.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/KROOZR.ROM b/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/KROOZR.ROM deleted file mode 100644 index 7c48cb5f..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/KROOZR.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/Kroozr.rbf b/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/Kroozr.rbf deleted file mode 100644 index 5007b1bb..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Kozmik Kroozr_MiST/Release/Kroozr.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SHOLLOW.ROM b/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SHOLLOW.ROM deleted file mode 100644 index 0871fa90..00000000 Binary files a/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SHOLLOW.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SatansHollow.rbf b/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SatansHollow.rbf deleted file mode 100644 index 545baa3c..00000000 Binary files a/Arcade_MiST/Midway MCR 2/SatansHollow_MiST/Release/SatansHollow.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/TRON.ROM b/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/TRON.ROM deleted file mode 100644 index 0ea23149..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/TRON.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/Tron.rbf b/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/Tron.rbf deleted file mode 100644 index 5beab259..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Tron_MiST/Release/Tron.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TWOTIGER.ROM b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TWOTIGER.ROM deleted file mode 100644 index ff465eb4..00000000 Binary files a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TWOTIGER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TwoTigers.rbf b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TwoTigers.rbf deleted file mode 100644 index 597e12c8..00000000 Binary files a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/Release/TwoTigers.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/WACKO.ROM b/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/WACKO.ROM deleted file mode 100644 index a13627b3..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/WACKO.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/Wacko.rbf b/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/Wacko.rbf deleted file mode 100644 index 9cc5123e..00000000 Binary files a/Arcade_MiST/Midway MCR 2/Wacko_MiST/Release/Wacko.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDERBY.ROM b/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDERBY.ROM deleted file mode 100644 index 2b96ac0f..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDERBY.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDerby.rbf b/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDerby.rbf deleted file mode 100644 index 1ab08213..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/Release/DDerby.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DOTRON.ROM b/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DOTRON.ROM deleted file mode 100644 index e3bbc3ca..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DOTRON.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DiscsOfTron.rbf b/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DiscsOfTron.rbf deleted file mode 100644 index a932c297..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/Release/DiscsOfTron.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/TAPPER.ROM b/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/TAPPER.ROM deleted file mode 100644 index b192ff4a..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/TAPPER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/Tapper.rbf b/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/Tapper.rbf deleted file mode 100644 index f01e13ee..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Tapper_MiST/Release/Tapper.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/TIMBER.ROM b/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/TIMBER.ROM deleted file mode 100644 index 2e8a601e..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/TIMBER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/Timber.rbf b/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/Timber.rbf deleted file mode 100644 index 5d837d8e..00000000 Binary files a/Arcade_MiST/Midway MCR 3/Timber_MiST/Release/Timber.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CRATER.ROM b/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CRATER.ROM deleted file mode 100644 index e2a08e6a..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CRATER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CraterRaider.rbf b/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CraterRaider.rbf deleted file mode 100644 index 147645c1..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/CraterRaider_MiST/Release/CraterRaider.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SHUNTER.ROM b/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SHUNTER.ROM deleted file mode 100644 index 48a0e6b8..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SHUNTER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SpyHunter.rbf b/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SpyHunter.rbf deleted file mode 100644 index a11fcca0..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/SpyHunter_MiST/Release/SpyHunter.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM deleted file mode 100644 index 48a0e6b8..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM and /dev/null differ diff --git a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf b/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf deleted file mode 100644 index a11fcca0..00000000 Binary files a/Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf deleted file mode 100644 index 78f1c762..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "280ZZZAP" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf deleted file mode 100644 index d88d2228..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf +++ /dev/null @@ -1,172 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 20:51:02 August 09, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# 280ZZZAP_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_memory.sv -set_global_assignment -name VHDL_FILE rtl/D280ZZZAP_Overlay.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY D280ZZZAP_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ---------------------------- -# start ENTITY(D280ZZZAP_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(D280ZZZAP_mist) -# -------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt deleted file mode 100644 index 50120049..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt +++ /dev/null @@ -1,27 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: 280zzzap port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- -ToDo: Color Prom - Controls + DIP - - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf deleted file mode 100644 index 8a3c2931..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/Snapshot/280ZZZAP.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png deleted file mode 100644 index 14892003..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/doc/Schematic.png and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd deleted file mode 100644 index 54588682..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd +++ /dev/null @@ -1,111 +0,0 @@ ---Datsun 280 ZZZAP Color Overlay Gehstock 2019 - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity D280ZZZAP_Overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end D280ZZZAP_Overlay; - -architecture rtl of D280ZZZAP_Overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_B1 : boolean; - signal Overlay_B1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); - signal col_data : std_logic_vector(3 downto 0); - signal col_addr : std_logic_vector(9 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_B1_VCnt <= false; - Overlay_B1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt >= x"C4") then - Overlay_B1_VCnt <= true; - else - Overlay_B1_VCnt <= false; - end if; - end if; - - if (HCnt <= x"0") and Overlay_B1_VCnt then - Overlay_B1 <= true; - elsif (HCnt >= x"228") then - Overlay_B1 <= false; - end if; - end if; - end process; - - p_video_out_comb : process(Video, Overlay_B1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_B1 then - VideoRGB <= "001"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv deleted file mode 100644 index fd2ac6a0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv +++ /dev/null @@ -1,104 +0,0 @@ -module D280ZZZAP_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - - -sprom #( - .init_file("./roms/zzzap_h.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/zzzap_g.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/zzzap_f.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/zzzap_e.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_3) - ); - -sprom #( - .init_file("./roms/zzzap_d.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_d ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_4) - ); - -sprom #( - .init_file("./roms/zzzap_c.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_c ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_5) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin - Rom_out = 8'b00000000; - case (Addr[15:10]) - 6'b000000 : Rom_out = rom_data_0; //0 - 6'b000001 : Rom_out = rom_data_1; //0400 - 6'b000010 : Rom_out = rom_data_2; //0800 - 6'b000011 : Rom_out = rom_data_3; //0c00 - 6'b000100 : Rom_out = rom_data_4; //1000 - 6'b000101 : Rom_out = rom_data_5; //1400 - - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv deleted file mode 100644 index da613e03..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv +++ /dev/null @@ -1,228 +0,0 @@ -module D280ZZZAP_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "280ZZZAP;;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v0.00.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; -/* -Dip Switch:E3 -1 2 3 4 5 6 7 8 Function Option -Coinage -On On 1 Coin/1 Credit* -Off On 1 Coin/2 Credits -On Off 2 Coins/1 Credit -Off Off 2 Coins/3 Credits -Game Time - Off On Test Mode -When Extended Time At not set to None - Off Off 60 seconds + 30 extended - On On 80 seconds + 40 extended* - On Off 99 seconds + 50 extended -When Extended Time At set to None - Off Off 60 seconds - On On 80 seconds* - On Off 99 seconds -Extended Time At - Off On 2.00 - On On 2.50* - Off Off None - On Off None -Language - On On English* - On Off French - Off On German - Off Off Spanish -*/ - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP("00000000"), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -D280ZZZAP_memory D280ZZZAP_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -D280ZZZAP_Overlay D280ZZZAP_Overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_left = btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd deleted file mode 100644 index ce639856..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,245 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; ---IN0 - GDB0(0) <= '0'; -- PEDAL - GDB0(1) <= '0'; -- PEDAL - GDB0(2) <= '0'; -- PEDAL - GDB0(3) <= '1'; -- PEDAL - GDB0(4) <= not Fire; -- fire - GDB0(5) <= '1'; -- UNUSED - GDB0(6) <= not Coin; -- coin - GDB0(7) <= not Sel1Player; -- start ---IN1 - GDB1(0) <= '0'; -- steering wheel - GDB1(1) <= '0'; -- steering wheel - GDB1(2) <= '0'; -- steering wheel - GDB1(3) <= '0'; -- steering wheel - GDB1(4) <= '0'; -- steering wheel - GDB1(5) <= '0'; -- steering wheel - GDB1(6) <= '0'; -- steering wheel - GDB1(7) <= '1'; -- steering wheel ---IN2 - GDB2(0) <= '0';--Coinage - GDB2(1) <= '0';--Coinage - GDB2(2) <= '1';--Game_Time - GDB2(3) <= '1';--Game_Time - GDB2(4) <= '1';--Extended Time At - GDB2(5) <= '1';--Extended Time At - GDB2(6) <= '0';--Language - GDB2(7) <= '0';--Language - - - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd deleted file mode 100644 index 1d9ad578..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,335 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex deleted file mode 100644 index 11797d04..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex +++ /dev/null @@ -1,65 +0,0 @@ -:10000000821491141F139B14AA14BE145F13D014EE -:10001000931228142F143614051511151F152C15BD -:10002000D013D013870000000C313630404BCD0C7C -:10003000313230404BCD0D3830404BCD0A5A454916 -:100040005440505241454D49C50647414E474041F5 -:100050005546404C4F40534348414C5445CE0647CB -:10006000414E474041554640484940534348414C22 -:100070005445CE0947454C444045494E57455246A4 -:1000800045CE094B4E4F50464044525545434B4593 -:10009000CE0B535049454C454E44C5025A45495430 -:1000A0003A080350554E4B5445BA03484F45434810 -:1000B0005354454050554E4B545A41484CBA034C4A -:1000C00045545A54454050554E4B545A41484CBAE9 -:1000D0000247524154554C494552453F0253494508 -:1000E00040484142454E4045494E45CE044E455656 -:1000F000454E4052454B4F5244404155464745536B -:1001000054454C4CD40A3102414E4641454E474578 -:10011000D209320253504F52544641485245D209F7 -:10012000330252454E4E4641485245D206340247AC -:1001300052414E444050524958404641485245D29F -:100140000752414E47464F4C474540314042495384 -:100150004035BA97151D163C130516AC15CF158FF3 -:1001600016A316C7151F1389156E167E165F13E9A1 -:1001700015931228142F1436142E164116491656AC -:10018000165F165F16000000000254454D50533AAA -:100190000B53434F5245BA0654454D5053405355A7 -:1001A00050504C454D454E54414952C50350415362 -:1001B00053455A404C41405052454D4945524540A7 -:1001C000564954455353C50C5445524D494EC503E9 -:1001D00050415353455A404C41405345434F4E4480 -:1001E0004540564954455353C502425241564F3F2C -:1001F00002564F5553404156455A405245414C498D -:1002000053454055CE044E4F5556454155405245F5 -:10021000434F52444044454050495354C508564FFB -:100220005452454043415445474F524945BA0752FD -:10023000455052454E455A40554E45404C45434F1A -:10024000CE0C414D41544555D20A50524F4645536C -:1002500053494F4E45CC0C4348414D50494FCE0970 -:100260005355504552404348414D50494FCE03539A -:10027000434F5245404140424154545245BA0353C2 -:10028000434F524540505245434544454E54BA06AB -:10029000494E54524F4455495345524031404652BD -:1002A000414EC307504F555353455A404C45404269 -:1002B0004F55544FCEFC167617F4165F170D1728BE -:1002C00017DC17EC1740171F13EB16CE17BE175F7E -:1002D000135017931228142F14361483179717AB43 -:1002E00017BD17CD17CD1700000000025449454D2A -:1002F000504F3A060350554E54454FBA085449459D -:100300004D504F40455854454E444944CF03434116 -:100310004D4249454C4F4041404D454E4F5340564C -:10032000454C4F43494441C40443414D4249454C27 -:100330004F40414D41534056454C4F43494441C4C1 -:10034000084A5545474F405445524D494E4144CFC8 -:100350000946454C494349544143494F4E45D3050D -:100360004849434953544540554E404E5545564FD4 -:10037000405245434FD20A54554050554E54454F74 -:100380004045D3064C4C45564153404C41404445B2 -:100390004C414E544552C107564140454E4053458D -:1003A00047554E444F404C554741D2074C4C414E67 -:1003B0005441534043414C49454E5445D3060353A1 -:1003C0004547554E444F405055455354CF06035072 -:1003D00052494D4552405055455354CF08504F4E09 -:1003E0004741404C41404D4F4E4544C10841474173 -:1003F00043484140454C40424F544FCEFFFFFFFF22 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex deleted file mode 100644 index c9b37f45..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex +++ /dev/null @@ -1,65 +0,0 @@ -:10000000DB02070707E6065F1600195E2356C93AAA -:100010004A20A7F8213620467E23BECA3710AE7884 -:10002000FA2B10BED22F1035C33010BED227103499 -:100030003A3920324A20C9237EA7C22710473A23E3 -:10004000204F07814F217C1009113620CD8810E602 -:1000500007CA6F10CD8810E67FD640121313CD88E3 -:1000600010A6121323CD8810A62386C6FC12C9122F -:100070001313CD8810E63FC620C3621003030003AC -:100080000300030102030003E5C521092006087EE1 -:10009000070707AE17172109207E1777237E1777EA -:1000A000237E1777237E177705C29010C1E1C921FF -:1000B0004421363511E710014000CDC91023EB066D -:1000C00008CDDF0AEB2B013EFF1AD5160407075FA8 -:1000D000E603A8F2D7103C862377157BC2CD10D15A -:1000E000130DC2C910C9D525555515151504511143 -:1000F00011044411041041041041010104040404DA -:10010000040101004010040100401001001004002F -:1001100040040010010010004001001000400100E8 -:10012000010004001000407F7974706B676460FE0A -:10013000EEA699655555545145111111044104100D -:100140004041004040100400400400100010001026 -:100150000001000004000004000000400000001046 -:1001600000000000400000000001000000818FA29C -:10017000ADB5BBC0C4C8CBCED0D3D5D7D9DBDCDEC0 -:10018000DFE1E2E3E4E6E7E8E9EAEBECEDEDEEEFF0 -:10019000F0F1F1F2F3F4F4F5F6F6F7F7F8F9F9FA0D -:1001A000FAFBFBFCFCFDFDFEFEFFFFFFFFFF010174 -:1001B0000101010101010101010202020202020228 -:1001C0000202020202020202030303030303030307 -:1001D00003040404040404040505050505060606D5 -:1001E0000606070707070808080909090A0A0A0B8B -:1001F0000B0C0C0C0D0D0E0E0F1010111112131311 -:10020000141516161718191A1B1C1D1E1F20212342 -:10021000242527282A2B2D2F30323436383A3C3EDD -:10022000414346484B4E5154575A5C616468000143 -:10023000131E262C313335393B3D3F414243444D5B -:1002400012F0135115B316C83AC83AC93ACA3AB8A7 -:1002500012DB133C138113C612E012FD12091315B1 -:10026000131F13351343134F135F1370139312812E -:10027000129412A6129C13A713B713C413D013D051 -:1002800013074D4158404355525645403136304092 -:100290004D5048C0074D4158404355525645403196 -:1002A0003230404D50C8074D415840435552564595 -:1002B00040403830404D50C80A455854454E44459A -:1002C000444054494DC5045348494654404745416C -:1002D0005240494E544F404C4F574053504545C4EF -:1002E00002534849465440544F40484947484046C5 -:1002F0004F52404D41584053434F5245BF0A494E1B -:100300005345525440434F49CE0A505553484042FA -:100310005554544FCE0C47414D45404F5645D2059C -:100320005B3B5C3B5D3B5E3B5F3C5B3C5C3C5D3C0C -:100330005E3C5F3DDB0254494D453A090353434F50 -:100340005245BA03484947484053434F5245BA03C0 -:1003500050524556494F55534053434F5245BA08A2 -:1003600044415453554E40323830405A5A5A41D085 -:1003700008434F4E47524154554C4154494F4E53F8 -:10038000BF03594F5540484156454053455440419D -:10039000404E4557405245434F5244BF0A310252E6 -:1003A0004F414440484FC708320246454E444552EB -:1003B0004042454E4445D2093302484F54405748C5 -:1003C00045454CD30A340250524F4052414345D226 -:1003D0000A35024348414D50494FCE06594F5552B8 -:1003E00040524154494E47403140544F4035BA0085 -:1003F00000003C144015A214EC1449145E1473144C -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex deleted file mode 100644 index 305e1499..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex +++ /dev/null @@ -1,65 +0,0 @@ -:10000000B60D3E033223203A4420324220F781CD00 -:10001000F10F2123207EFE01C03A3D20FE01D8349D -:10002000C9CD88103A4520E680C02130207EA7C87F -:1000300035310024AF3222202A3D202229201132DE -:10004000200628121305C2430C67DB020FE6066F79 -:1000500011D70F197E324220237E3244203E0032D7 -:100060002D203E20D302CD980E3E013223203EFFAC -:100070003241203EF8324820DB00E610CA810CF7FE -:1000800065EF04210B04224D203EE03254203EFF58 -:10009000322220EFE8CD800B2140217E23B6CAB06A -:1000A0000C3A3E21A7CAB00CCD330F0400C3B50CE7 -:1000B000CD330F00002122207EEE05C2C70C3A404E -:1000C00020A7C2C70C36017EEE02CA590E21482075 -:1000D0007EA7FAEE0C36F82A322023223220213E67 -:1000E000207EC6012777D2EB0C2B34CDDF0FCD77E6 -:1000F0000D3A3720CD87080F0F0F0FE603C610CD3E -:10010000480F3A452047E60F57074F07814F78E6DB -:10011000103A3E21CA390DFE28D2270DF7650E0090 -:100120003E20D302C34F0D79074F7AF610D3023E1B -:1001300001325A20F760C34F0DFE28DA430DF766EF -:10014000C3450DF7607AF620D3023E02325A207979 -:10015000323F213A4620CD600D2F323A20C3950C14 -:100160003A46202FC681FE81DA710DFEC0D03EC016 -:10017000C9FE40D83E3FC93A3E21470F0F0FE61F48 -:100180002F3C80214221BEC8DA8F0D34C3900D353B -:100190007E0F0F0FE61FC6A55F16397EE6074F06D6 -:1001A0000021950A097E2FEB0E1F11FF04772373A0 -:1001B0000915C2AD0DC93100243E04322220CD4BB9 -:1001C0000E322320CDF10FCD440F092A2B20EB2A2C -:1001D0003D207DBBDAEF0DC2DF0D7ABCD2EF0D22E0 -:1001E0002B20CD5700CD5A0F6FCD5A0F84EFFFCD86 -:1001F0005700CD5A0F623A34204F06FF582A32205A -:100200007CA7FA0A0E091CC3000E3A3520A77BC250 -:10021000130E3CC694CD5E0FEFFFEFFFCDB30E3E45 -:100220000A323120CD4B0E3A3020A7CA350ECD44CC -:100230000F08C3390ECD440F07EFFFCD440F0EEF6B -:10024000FF21312035C2240EC31C0ECD330F020016 -:100250003E02322D20AFD302C9310024CD330F032B -:100260003CCDC40321352034CD280FAFD302CD338C -:100270000F020ACD280FCD330F0A50CD280FCD988D -:100280000E3A2320FE013EFFCA8D0E3E78324020FA -:100290003E05322220C3950CCDDE0ECD5A0F4BCD3C -:1002A000F10FCDDF0F3E013222203A2320EE03C0B2 -:1002B000F781C9CDDE0ECD5A0F43F76CF78DCDDF38 -:1002C0000F212B2011B93CCDE50F21292011993E9A -:1002D000CDE50F3E033222203E50323F21C9AF32DE -:1002E0002220CD5F0101FF1411803ACD6501215A12 -:1002F000200EEAAF77230DC2F40E3E01325A2021C0 -:10030000622022272021D0202225202180002200C7 -:1003100020CD5A0F2AC9E37E23E3323F20CD800B44 -:100320003A3F20A7C21D0FC9CD800B3A2E20A7C28D -:10033000280FC9E34E234623E3212E207EA7C07059 -:1003400079D305C9E37E23E3CD910F77F501000A48 -:10035000114025CD6501F1C35E0FE37E23E3E50780 -:10036000F5070707E60E4F060021C50F095E235665 -:10037000F1E63ECA8F0FD54F213F12CD0010EB0999 -:100380005E2356EBD17ECD81037E23A7F2850FE15C -:10039000C9C5F5070707E6074F0600215B2009F1ED -:1003A000C1BEC0E1C9504F573F5A41503F57414D20 -:1003B0003F42414D3F5A4F524B42414E47424F4FB1 -:1003C0004D5A4F4E4B00244038C03AA03C803E016D -:1003D00001010202010203804001019950603021B5 -:1003E0003D2011D93ACD66033E3ECD810323C3742F -:1003F00003214712CD0010214220C36603A700004D -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex deleted file mode 100644 index a5046190..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex +++ /dev/null @@ -1,65 +0,0 @@ -:10000000FF2A0020092200207CA7CA22083A2220C9 -:10001000EE05CA1A0821222034C97C2F6F2600223F -:1000200000207DCD8708FE287C8F324021C3310817 -:10003000F1214520DB007723DB0177CD4E08213FFE -:1000400020CD490823CD4908237EA7C835C9212ED4 -:10005000207EA7C835C03A2D20D305C9A7F5CD8786 -:10006000085F216D11197E4759212E121986F27BE6 -:10007000085AFEEEDA81081CC381085F21AE11190F -:100080005EF17BF02F3CC9A7F02FC93A2220A7F8D8 -:100090000FD02A272011460019CDC909CDC9092A38 -:1000A000252011460019CD5C0ACD5C0A2A272011B3 -:1000B0003C0019CDC909CDC9092A2520113C0019D8 -:1000C000CD5C0ACD5C0A2A2720EB2A252022272096 -:1000D000EB2225202260203E05D304AFD3033A0350 -:1000E00020CD0D092103207EC62077D2E108C92A40 -:1000F00060207CB5C83E05D304AFD3032103207E26 -:10010000E61F77CD0D092103207EC620774F06001C -:10011000214521094E3A022081A7F22B09FEEED299 -:10012000260968C331092E01C331094F21AE1109D7 -:100130006E603A3720A7F23F09AF956F789C67EB66 -:100140002A0020192204203A03204F214522097E4B -:10015000320820577E2106200FE67F5F0FE61F77CB -:10016000230F0FE6074F3C777A50835FD52A042090 -:1001700019E5097CE1CD8D09D1AF935F3E009A5717 -:10018000AF914F3E0098472A042009197CA7C2BCB2 -:1001900009EB2A60203A072077233A062077237B51 -:1001A000D303E60777233A0820D303DB037723AF93 -:1001B000D303DB03C6247723226020C92A602036BC -:1001C0000011050019226020C97EA7CA610A2346D2 -:1001D00023235E235623E5EB111F007223721905BA -:1001E000C2DB09E1C97EA7CA610A237E23235E23FD -:1001F0005623EB70093DC2F309EBC97EA7CA610A19 -:100200004F2346237E235E235623E5EBD304AFD34F -:100210000357E55921940A197ED303DB034FAFD36B -:10022000031E1FE17EB17723DB03B6771905C224D5 -:100230000AE1C97EA7CA610A2346237ED304AFD34D -:10024000033E01D303DB034F235E235623E5EB116B -:1002500020007EB1771905C2520AE1C97EA7C266A5 -:100260000A11050019C94F2346237E235E23562316 -:10027000E5D5D304AFD303575921940A197ED3038C -:10028000DB034FAFD303DB031E1FE1712377190597 -:10029000C28B0AE1C90103070F1F3F7FFFCDAA0AE6 -:1002A000CDE80A21DA06E3C33108214B2035F2BA42 -:1002B0000AEB2A4D200609CDDF0A2154203A4C20B2 -:1002C0008677234FE6077723790F0F0FE61FC6A027 -:1002D00077233629214F2035F0EB2A522006057E60 -:1002E00023121305C2DF0AC92A56207CB5C82A5832 -:1002F000207CB5CA080B012605111B007872233D2E -:10030000C2FD0A190DC2FC0A2A4D207CB5C2180B89 -:100310003E01322220C3520B2A50204E2346235E38 -:10032000235623E52A5620192258203A5520D30473 -:10033000AFD303D1C5E51A13D303DB0377230DC273 -:10034000360BAFD303DB0377012000E109C105C2FF -:10035000340B2A2520113C0019CDFB09CDFB09C91E -:100360007F0100FF310520CD6201310024CDAF10A7 -:1003700021FFFF220920220B20CDB30EFBC31F0E4D -:10038000D3072121207EA7CAB80BAF77473E0A3298 -:100390002E203E22D305DB0207E6064F21CF0F09B0 -:1003A0005E2356212F20347EBBC2B80B70237E8281 -:1003B000773A2320A7CA2A0CCD0F103A2320A7CAC8 -:1003C000210C2141207EA7C2120C363C213420355D -:1003D0002142207EC6992777C20F0C3A2320EE03D4 -:1003E000CAB60DDB020F0F0FE6064F0600211D00F7 -:1003F000094E213E207EE6F02B860F0F0F0FB9DA53 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex deleted file mode 100644 index 10f77477..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex +++ /dev/null @@ -1,65 +0,0 @@ -:1000000008112000711905C20404E76DFF190405E9 -:100010003E042B000527050F043B002704139D0514 -:100020002204271D06220436FE3504033E04300454 -:1000300003B40439047F0000000327052B040326C2 -:100040000000800100800700E00F00BC1F00E61BDD -:1000500000671B007F0F03EE81073CC00F10FC1FE1 -:1000600010C00F20400F40E00F80F00F80C10F80C4 -:10007000C10700030300830700FE3F00FE7F00E08E -:10008000EF0080CF0080CF0080CF0080CF0080DFE6 -:1000900000C0DF00C01F00E01F00F00E00700E0067 -:1000A000380E00381C00303800707000606000604E -:1000B0006000787803252000800100800700E00FB1 -:1000C00000BC1900F61900FF1F03EF8F07EEC10FE8 -:1000D0003CFC1F10C00F20400F40E00F80F00F804D -:1000E000C10F80C10700030300830700FE0F00FE5D -:1000F0000F00E00F00800F00800F00800F00800FC6 -:1001000000801F00801F00801F00801F00800F00E4 -:1001100080070080070080070080030000030000C4 -:100120000300000300C003032600008001008007D5 -:1001300000E00D00F81D009E1F009F1B00FF0F0335 -:10014000F681073CC00F10FC1F10C00F20400F406D -:10015000E00F80F00F80C10F80C107000303008310 -:100160000700FE0F00FE1F00E03F00806F00806F61 -:1001700000806F00806F00803F00801F00801F00A4 -:10018000C01F00C01F00C00700E00300E01900E02E -:100190001C006038006070006060007878041FDF29 -:1001A0000000003000000078000000FC0000C0FFEC -:1001B000013303FC003303F400CC00FE00CC00FF4D -:1001C000003303FC0033037C00CC003000CC00F88B -:1001D00000FFFFFF1F00F0FF3F0000FF700000FC6A -:1001E000E00000FCC00000F8810000F8810000F889 -:1001F000810000FC030000FC030000DE0300008E11 -:1002000003000007070080030E008001FC0080014E -:10021000F8008001800080018000E00180041FDF81 -:10022000009F0F3000930D7800830DFC0083CDFFFD -:10023000019B0DFC00930DF4009F0FFE000000FCDD -:10024000000020F80000807C00000030000000F872 -:1002500000FFFFFF1F33E3FF3F3303FF70CC00FCC1 -:10026000E0CC00FCC03303F8813303F881CC00F804 -:1002700081CC00FC030000FC030000DE0300008EC4 -:1002800003000007070080030E008001FC008001CE -:10029000F8008001800080018000E00180E0E5DB63 -:1002A0000047DB00A8E640C2BE0678212020AE70E1 -:1002B000E640CABE0678E640C2BE062336012124C7 -:1002C000207EA9C2DA067E21D206E5A7C28B08C32A -:1002D000E0062124207E3CE60177E1D1C1F1FBC993 -:1002E0003A2220A7FA9D0AC80FD231082A2720CD2A -:1002F000C909CDC909CDC909CDC909CDC909CDC91A -:1003000009012000CDE509CDE509CDE509CDE509D7 -:10031000CDE509CDE5092A2520CDFB09CDFB09CD89 -:10032000FB09CDFB09CDFB09CDFB09CD330ACD334C -:100330000ACD330ACD330ACD330ACD330ACDEF08C7 -:100340003A3E2121432135F26D073603213E217EBD -:1003500023BECA6D07DA6607FE04D26107AFC36B1E -:1003600007D604C36B075F3A5A20832B775F1600CA -:100370002A47207CA7CA7C07192247202A49207CCB -:10038000A7CA880719224920EB29292929EB2A3BEA -:100390002019223B207C2FE61FC6403203204A163C -:1003A000003A3720CD5C08F5783202203A2220EE60 -:1003B00003CA30083A3E21A7CA30083A372047CD51 -:1003C00087080F0F0FE6062F3CC60BB9D2E8072FA0 -:1003D0003C813C0FE6034F324121F17842A7F20104 -:1003E00008792F3C4FC3FF07AF324121790FE60751 -:1003F00081793A3A20CD5C0842D1824FF201080659 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex deleted file mode 100644 index c013d6e0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex +++ /dev/null @@ -1,65 +0,0 @@ -:100000000000AFD305C36400F5C5D50E00C39E063E -:10001000F5C5D50E01C39E06E3D5C5F5E92530200B -:10002000E1F1C1D1E1C93500C3160F05B4041404D0 -:10003000E37E23E3CD910F77DF215E207E23B6E6BA -:100040001FCA5D0001FF1DCD6201215E207ECD5ED5 -:100050000F237ECD5E0FE701FF1DC3620101001D6E -:10006000CD6201E7DB02E60CFE04C2610B06011162 -:100070000000210020D307707EA8CA8C004F7DE6C7 -:100080000179C28A00B257C38C00B35F237CFE4063 -:10009000C27500D3072B7CFE1FCAC9007EA8CAB058 -:1000A000004F7DE60179C2AE00B257C3B000B35F26 -:1000B000782F77AECA93004F7DE60179C2C400B2B3 -:1000C00057C3C600B35FC39300D307237CFE40CA67 -:1000D000EC00782FAECAE7004F7DE60179C2E5005B -:1000E000B257C3E700B35FAF77C3C900780747D201 -:1000F00072007AB3CA1B01EBF9110020060021003F -:1001000000390E10AF29DA0A012F12133E1812130C -:100110000DC2040105C2FE00C35401310024210CAC -:1001200028E5210000115901010004AF86D30723FF -:100130000DC22C0105C22C01A7CA46011AE3EBC56A -:10014000CD8103C1EBE3137CFE18C22801E17DFEE3 -:100150000CCA0000D307C354014847464544430135 -:1001600000E011004021000039EBF3F9EB7841C5C4 -:10017000C5C5C5C5C5C5C5C5C5C5C5C5C5C5C53DB7 -:10018000C26F01F9FBC93C7E6666666666667E3CA8 -:10019000181C1818181818183C3C3C7E66607C3EE9 -:1001A00006067E7E3C7E6660387860667E3C6666CB -:1001B00066667E7E606060603E3E06063E7E6066ED -:1001C0007E3C3C3E06063E7E66667E3C7E7E6070E1 -:1001D0003038181C0C0C3C7E66663C7E66667E3CA5 -:1001E0003C7E66667E7C60607C3C001818000000E7 -:1001F00000181800FFFFFFFFFFFF7777FFFF7F7FEB -:100200007F7F7FFF7777FFFF1F7F1FDF1FFF7777DE -:10021000FFFF000000000000000018181818181850 -:10022000181800001818000000000000000000006E -:10023000183C7E6666667E7E66663E7E66663E7EAE -:1002400066667E3E3C7E6606060606667E3C3E7E12 -:100250006666666666667E3E7E7E06063E3E0606EE -:100260007E7E7E7E06063E3E060606063C7E6606D0 -:10027000067676667E3C666666667E7E6666666640 -:100280003C3C1818181818183C3C606060606060AE -:1002900060667E3C6666763E1E1E3E766666060696 -:1002A0000606060606067E7EC3C3E7E7FFFFDBC33E -:1002B000C3C366666E6E7E7E767666663C7E6666D6 -:1002C000666666667E3C3E7E66667E3E0606060680 -:1002D0003C7E6666666666667E5C3E7E66667E3EE2 -:1002E000766666663C7E66063E7C60667E3C7E7E0A -:1002F000181818181818181866666666666666660E -:100300007E3C66666666667E3C3C1818C3C3C3DBEB -:10031000FFFFE7E7C3C366667E3C18183C7E66664F -:1003200066667E3C1818181818187E7E6070381C97 -:100330000E067E7E1155555511FF7777F7F7115749 -:10034000515D11FF7777F7F71555515717FF7777FD -:10035000F7F7115D515511FF7777F7F711555155A3 -:1003600011FF7777F7F77EE6F0C275033E40CD8147 -:1003700003C37C037E07070707CD7D037EE60FC618 -:1003800030E67FFE300600D28F034FEB09EBC9E564 -:10039000D5CDB2037CFE3B3E00DA9D032F4FC51A3C -:1003A00013A97701200009C105C29E03D113E1C939 -:1003B0000600D6304F6069292929090901860109FB -:1003C000060AEBC9CD8810E61C4F060021A50F09CF -:1003D0001100280604CDE2037BC6085F2305C2D5C1 -:1003E00003C97EDFCDB003E51A131FDCFA0323A790 -:1003F000C2EA03E12405C2E703E7E5D5C5F501FF3D -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf deleted file mode 100644 index e97e5097..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "BalloonBomber" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf deleted file mode 100644 index 37310fc8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf +++ /dev/null @@ -1,177 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 02:57:11 June 09, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# BalloonBomber_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name TOP_LEVEL_ENTITY BalloonBomber_mist -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# --------------------------- -# start ENTITY(OzmaWars_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(OzmaWars_mist) -# ------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_memory.sv -set_global_assignment -name VHDL_FILE rtl/BalloonBomber_Overlay.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip -set_global_assignment -name VHDL_FILE rtl/roms/tn07.vhd -set_global_assignment -name VHDL_FILE rtl/roms/tn06.vhd -set_global_assignment -name VHDL_FILE "rtl/roms/tn05-1.vhd" -set_global_assignment -name VHDL_FILE rtl/roms/tn04.vhd -set_global_assignment -name VHDL_FILE rtl/roms/tn03.vhd -set_global_assignment -name VHDL_FILE rtl/roms/tn02.vhd -set_global_assignment -name VHDL_FILE rtl/roms/tn01.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat deleted file mode 100644 index ac9bf0a8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat +++ /dev/null @@ -1,16 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s build_id.v -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd deleted file mode 100644 index ceecfaf1..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd +++ /dev/null @@ -1,366 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - - ---Not Cleaned, iam to lazy for this - - -entity BalloonBomber_Overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - CAB : in std_logic_vector(9 downto 0); - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end BalloonBomber_Overlay; - -architecture rtl of BalloonBomber_Overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_A1 : boolean; - signal Overlay_A1_VCnt : boolean; - signal Overlay_A2 : boolean; - signal Overlay_A3 : boolean; - signal Overlay_A3_VCnt : boolean; - signal Overlay_A4 : boolean; - signal Overlay_A4_VCnt : boolean; - - signal Overlay_R1 : boolean; - signal Overlay_R1_VCnt : boolean; - signal Overlay_R2 : boolean; - signal Overlay_R3 : boolean; - - signal Overlay_Y1 : boolean; - signal Overlay_Y1_VCnt : boolean; - signal Overlay_Y2 : boolean; - signal Overlay_Y3 : boolean; - signal Overlay_Y4 : boolean; - signal Overlay_Y4_VCnt : boolean; - signal Overlay_Y5 : boolean; - signal Overlay_Y5_VCnt : boolean; - - signal Overlay_G1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal Overlay_G2 : boolean; - signal Overlay_G3 : boolean; - signal Overlay_G4 : boolean; - signal Overlay_G4_VCnt : boolean; - - signal Overlay_P1 : boolean; - signal Overlay_P2 : boolean; - signal Overlay_P2_VCnt : boolean; - signal Overlay_P3 : boolean; - signal Overlay_P3_VCnt : boolean; - signal Overlay_P4 : boolean; - signal Overlay_P4_VCnt : boolean; - - signal VideoRGB : std_logic_vector(2 downto 0); - signal COLOR : std_logic_vector(3 downto 0); - -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - - Overlay_G1 <= false; - Overlay_G1_VCnt <= false; - Overlay_G2 <= false; - Overlay_G3 <= false; - Overlay_G4 <= false; - Overlay_G4_VCnt <= false; - - Overlay_A1 <= false; - Overlay_A1_VCnt <= false; - Overlay_A2 <= false; - Overlay_A3 <= false; - Overlay_A3_VCnt <= false; - Overlay_A4 <= false; - Overlay_A4_VCnt <= false; - - Overlay_R1 <= false; - Overlay_R1_VCnt <= false; - Overlay_R2 <= false; - Overlay_R3 <= false; - - Overlay_Y1 <= false; - Overlay_Y1_VCnt <= false; - Overlay_Y2 <= false; - Overlay_Y3 <= false; - Overlay_Y4 <= false; - Overlay_Y4_VCnt <= false; - Overlay_Y5 <= false; - Overlay_Y5_VCnt <= false; - - Overlay_P1 <= false; - Overlay_P3 <= false; - Overlay_P3_VCnt <= false; - Overlay_P4 <= false; - Overlay_P4_VCnt <= false; - - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt >= 0) and (Vcnt <= 99) then - Overlay_A1_VCnt <= true; - else - Overlay_A1_VCnt <= false; - end if; - - if (Vcnt >= 100) and (Vcnt <= 149 ) then - Overlay_R1_VCnt <= true; - else - Overlay_R1_VCnt <= false; - end if; - - if (Vcnt >= 150) and (Vcnt <= 240) then - Overlay_Y1_VCnt <= true; - else - Overlay_Y1_VCnt <= false; - end if; - - if (Vcnt >= 236) and (Vcnt <= 16) then - Overlay_G1_VCnt <= true; - else - Overlay_G1_VCnt <= false; - end if; - - if (Vcnt >= 0) and (Vcnt <= 72) then - Overlay_G4_VCnt <= true; - Overlay_Y5_VCnt <= true; - else - Overlay_G4_VCnt <= false; - Overlay_Y5_VCnt <= false; - end if; - - if (Vcnt >= 73) and (Vcnt <= 200) then - Overlay_P3_VCnt <= true; - else - Overlay_P3_VCnt <= false; - end if; - - if (Vcnt >= 224) and (Vcnt <= 230) then - Overlay_P4_VCnt <= true; - else - Overlay_P4_VCnt <= false; - end if; - - if (Vcnt >= 160) and (Vcnt <= 166 ) then - Overlay_A3_VCnt <= true; - else - Overlay_A3_VCnt <= false; - end if; - - if (Vcnt >= 24 ) and (Vcnt <= 230 ) then - Overlay_A4_VCnt <= true; - else - Overlay_A4_VCnt <= false; - end if; - - if (Vcnt >= 32 ) and (Vcnt <= 222 ) then - Overlay_P2_VCnt <= true; - else - Overlay_P2_VCnt <= false; - end if; - end if; - - if (Vcnt >= 42 ) and (Vcnt <= 216 ) then------------------------------------ - Overlay_Y4_VCnt <= true; - else - Overlay_Y4_VCnt <= false; - end if; - - if (HCnt = 518)then--ok - if Overlay_A1_VCnt then Overlay_A1 <= true; end if; - if Overlay_R1_VCnt then Overlay_R1 <= true; end if; - if Overlay_Y1_VCnt then Overlay_Y1 <= true; end if; - elsif (HCnt >= 540) then - if Overlay_A1_VCnt then Overlay_A1 <= false; end if; - if Overlay_R1_VCnt then Overlay_R1 <= false; end if; - if Overlay_Y1_VCnt then Overlay_Y1 <= false; end if; - end if; - - if (HCnt = 528)then--check - if Overlay_G1_VCnt then Overlay_G1 <= true; end if; - elsif (HCnt >= 540) then - if Overlay_G1_VCnt then Overlay_G1 <= false; end if; - end if; - - if (HCnt = 486) then--ok - Overlay_R2 <= true; - elsif (HCnt = 502) then - Overlay_R2 <= false; - end if; - - if (HCnt = 438) then--ok - Overlay_Y2 <= true; - elsif (HCnt = 470) then - Overlay_Y2 <= false; - end if; - - if (HCnt = 373) then--ok - Overlay_G2 <= true; - elsif (HCnt = 445) then - Overlay_G2 <= false; - end if; - - if (HCnt = 324) then--ok - Overlay_P1 <= true; - elsif (HCnt = 380) then - Overlay_P1 <= false; - end if; - - if (HCnt = 275) then--ok - Overlay_A2 <= true; - elsif (HCnt = 327) then - Overlay_A2 <= false; - end if; - - if (HCnt = 210) then--ok - Overlay_Y3 <= true; - elsif (HCnt = 274) then - Overlay_Y3 <= false; - end if; - - if (HCnt = 166) then--ok - Overlay_R3 <= true; - elsif (HCnt = 214) then - Overlay_R3 <= false; - end if; - - if (HCnt = 70) then--ok - Overlay_G3 <= true; - elsif (HCnt = 170) then - Overlay_G3 <= false; - end if; - - if (HCnt = 70) then--check - if Overlay_P4_VCnt then Overlay_P4 <= true; end if; - elsif (HCnt = 86) then - if Overlay_P4_VCnt then Overlay_P4 <= false; end if; - end if; - - if (HCnt = 0) then--ok - if Overlay_Y5_VCnt then Overlay_Y5 <= true; end if; - if Overlay_P3_VCnt then Overlay_P3 <= true; end if; - elsif (HCnt = 70) then - if Overlay_Y5_VCnt then Overlay_Y5 <= false; end if; - if Overlay_P3_VCnt then Overlay_P3 <= false; end if; - end if; - - if (HCnt = 164) then--check - if Overlay_A3_VCnt then Overlay_A3 <= true; end if; - elsif (HCnt = 172) then - if Overlay_A3_VCnt then Overlay_A3 <= false; end if; - end if; - - if (HCnt = 118) then--check - if Overlay_A4_VCnt then Overlay_A4 <= true; end if; - elsif (HCnt = 134) then - if Overlay_A4_VCnt then Overlay_A4 <= false; end if; - end if; - - if (HCnt = 102) then--check - if Overlay_P2_VCnt then Overlay_P2 <= true; end if; - elsif (HCnt = 118) then - if Overlay_P2_VCnt then Overlay_P2 <= false; end if; - end if; - - if (HCnt = 86) then--check - if Overlay_Y4_VCnt then Overlay_Y4 <= true; end if; - elsif (HCnt = 102) then - if Overlay_Y4_VCnt then Overlay_Y4 <= false; end if; - end if; - - if (HCnt = 486) then--ok - if Overlay_G4_VCnt then Overlay_G4 <= true; end if; - elsif (HCnt = 470) then - if Overlay_G4_VCnt then Overlay_G4 <= false; end if; - end if; - - end if; - end process; - - p_video_out_comb : process(Video) - begin - if (Video = '0') then - VideoRGB <= "000"; - elsif Overlay_R1 or Overlay_R2 or (Overlay_R3 and not Overlay_A3) then--Red - VideoRGB <= "100"; - elsif Overlay_A1 or Overlay_A2 or Overlay_A3 or Overlay_A4 then--Aqua - VideoRGB <= "011"; - elsif (Overlay_Y1 and not Overlay_G1) or Overlay_Y2 or Overlay_Y3 or Overlay_Y4 or Overlay_Y5 then--Yellow - VideoRGB <= "110"; - elsif Overlay_G1 or Overlay_G2 or (Overlay_G3 and not (Overlay_P4 or Overlay_A4 or Overlay_P2 or Overlay_Y4))-- or Overlay_G4 - then - VideoRGB <= "010"; - elsif Overlay_P1 or Overlay_P2 or Overlay_P3 or Overlay_P4 then--Purple - VideoRGB <= "101"; --- elsif not (Overlay_G4) then--white - else - VideoRGB <= "111";-- end if; - end if; - end process; - ---colPROM: entity work.col ---port map( --- clk => Clk, --- addr => CAB, --should be Video Counters --- data => COLOR ---); - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - --- O_VIDEO_R <= COLOR(2); --- O_VIDEO_G <= COLOR(1); --- O_VIDEO_B <= COLOR(0); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv deleted file mode 100644 index 2dda36ca..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv +++ /dev/null @@ -1,72 +0,0 @@ - -module BalloonBomber_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]}; - -tn01 tn01 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_0) -); - -tn02 tn02 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_1) -); - -tn03 tn03 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_2) -); - -tn04 tn04 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_3) -); - -tn05_1 tn05_1 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_4) -); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4;//0100 0000 0000 0000 - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv deleted file mode 100644 index b596dae0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv +++ /dev/null @@ -1,208 +0,0 @@ -module BalloonBomber_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "BallBomb;;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys, clk_core; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hs, vs; -wire r,g,b; - - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .MoveUp(~m_up), - .MoveDown(~m_down), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -BalloonBomber_memory BalloonBomber_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -BalloonBomber_Overlay BalloonBomber_Overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd deleted file mode 100644 index ca17b82c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - MoveUp : in std_logic; - MoveDown : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; - signal GDB_A : unsigned(1 downto 0); -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => '1',--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - --- with AD_i(9 downto 8) select --- GDB <= GDB0 when "00", --- GDB1 when "01", --- GDB2 when "10", --- S when others; - - GDB_A <= not AD_i(9) & AD_i(8); - - with GDB_A select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - GDB0(0) <= '0'; - GDB0(1) <= '0'; - GDB0(2) <= '0'; - GDB0(3) <= '0'; - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= '0'; - - GDB1(0) <= Coin; - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1'; - GDB1(4) <= not Fire;--controller - GDB1(5) <= not MoveLeft;--controller - GDB1(6) <= not MoveRight;--controller - GDB1(7) <= '1'; - - GDB2(0) <= '0';--active high - GDB2(1) <= '0';--active high - GDB2(2) <= '0';--active high - GDB2(3) <= '0';--active high - GDB2(4) <= '0';--active high - GDB2(5) <= '0';--active high - GDB2(6) <= '0';--active high - GDB2(7) <= '0';--active high - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip deleted file mode 100644 index 02178e7f..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/ballbomb.zip and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01 deleted file mode 100644 index 44a8c6ac..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01 and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd deleted file mode 100644 index d27bab74..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn01 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn01 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"C3",X"18",X"00",X"00",X"00",X"FB",X"C9",X"00",X"00",X"00",X"00",X"00",X"00", - X"E5",X"D5",X"C5",X"F5",X"C3",X"D8",X"04",X"FF",X"31",X"00",X"24",X"CD",X"76",X"01",X"06",X"00", - X"CD",X"BC",X"04",X"CD",X"C5",X"04",X"CD",X"D0",X"04",X"CD",X"4C",X"00",X"FB",X"AF",X"D3",X"03", - X"D3",X"05",X"CD",X"BC",X"00",X"CD",X"BB",X"01",X"CD",X"C1",X"00",X"CD",X"24",X"01",X"CD",X"01", - X"01",X"CD",X"BB",X"01",X"CD",X"55",X"00",X"D3",X"06",X"C3",X"2D",X"00",X"21",X"3C",X"09",X"CD", - X"7B",X"1A",X"C3",X"35",X"1B",X"CD",X"BA",X"04",X"CD",X"C5",X"04",X"21",X"2F",X"20",X"34",X"21", - X"E0",X"20",X"34",X"CD",X"52",X"1A",X"2E",X"06",X"06",X"12",X"70",X"2E",X"0A",X"70",X"2E",X"0E", - X"70",X"2E",X"12",X"70",X"2E",X"16",X"70",X"2E",X"1A",X"70",X"21",X"35",X"20",X"AF",X"BE",X"C2", - X"A5",X"00",X"CD",X"94",X"00",X"21",X"54",X"20",X"34",X"CD",X"DB",X"16",X"CD",X"18",X"12",X"D3", - X"06",X"C3",X"7A",X"00",X"21",X"14",X"20",X"AF",X"BE",X"C0",X"3A",X"01",X"20",X"E6",X"7F",X"C0", - X"23",X"23",X"36",X"01",X"C9",X"CD",X"9A",X"18",X"21",X"E0",X"20",X"36",X"00",X"CD",X"BA",X"04", - X"CD",X"C5",X"04",X"C3",X"C1",X"00",X"3E",X"FF",X"32",X"DF",X"20",X"C9",X"AF",X"32",X"DF",X"20", - X"C9",X"3E",X"50",X"C3",X"D5",X"14",X"21",X"05",X"26",X"11",X"D7",X"00",X"01",X"08",X"01",X"CD", - X"D5",X"01",X"06",X"17",X"C3",X"60",X"02",X"3C",X"42",X"99",X"A5",X"A5",X"81",X"42",X"3C",X"1B", - X"21",X"29",X"28",X"20",X"1B",X"13",X"00",X"08",X"13",X"0E",X"1B",X"02",X"0E",X"11",X"0F",X"0E", - X"11",X"00",X"13",X"08",X"0E",X"0D",X"01",X"0E",X"0C",X"01",X"04",X"11",X"3E",X"20",X"C3",X"D5", - X"14",X"CD",X"BB",X"01",X"CD",X"C6",X"00",X"CD",X"FC",X"00",X"21",X"11",X"2C",X"06",X"0C",X"11", - X"18",X"01",X"CD",X"60",X"02",X"C3",X"C1",X"00",X"08",X"0D",X"12",X"04",X"11",X"13",X"1B",X"1B", - X"02",X"0E",X"08",X"0D",X"11",X"A0",X"20",X"21",X"A0",X"46",X"06",X"15",X"CD",X"8B",X"03",X"CD", - X"82",X"17",X"21",X"AA",X"20",X"34",X"3A",X"AA",X"20",X"A7",X"D3",X"06",X"C2",X"36",X"01",X"CD", - X"FC",X"00",X"21",X"0C",X"2E",X"11",X"F6",X"00",X"06",X"06",X"CD",X"60",X"02",X"CD",X"C1",X"00", - X"CD",X"C6",X"00",X"11",X"A0",X"20",X"21",X"81",X"18",X"06",X"15",X"CD",X"8B",X"03",X"CD",X"82", - X"17",X"21",X"AA",X"20",X"34",X"3A",X"AA",X"20",X"A7",X"D3",X"06",X"C2",X"65",X"01",X"3E",X"80", - X"CD",X"D5",X"14",X"C3",X"76",X"01",X"21",X"00",X"24",X"AF",X"77",X"23",X"7C",X"FE",X"40",X"DA", - X"79",X"01",X"C9",X"21",X"1E",X"25",X"11",X"E0",X"43",X"06",X"1A",X"CD",X"60",X"02",X"21",X"1D", - X"26",X"11",X"C3",X"20",X"CD",X"B1",X"01",X"21",X"1D",X"30",X"11",X"DC",X"20",X"CD",X"B1",X"01", - X"3A",X"DA",X"20",X"A7",X"CA",X"B0",X"01",X"21",X"1D",X"39",X"11",X"C6",X"20",X"CD",X"B1",X"01", - X"C9",X"22",X"D6",X"20",X"EB",X"22",X"D4",X"20",X"C3",X"A3",X"02",X"CD",X"76",X"01",X"CD",X"83", - X"01",X"CD",X"23",X"03",X"CD",X"15",X"03",X"21",X"02",X"24",X"01",X"E0",X"01",X"3E",X"7F",X"C3", - X"8D",X"08",X"01",X"20",X"03",X"C5",X"E5",X"1A",X"77",X"23",X"13",X"05",X"C2",X"D7",X"01",X"E1", - X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"D5",X"01",X"C9",X"21",X"B0",X"04",X"11",X"D8",X"20", - X"06",X"02",X"C3",X"8B",X"03",X"21",X"B2",X"04",X"C3",X"ED",X"01",X"21",X"E6",X"20",X"46",X"B0", - X"D3",X"03",X"77",X"C9",X"21",X"E6",X"20",X"46",X"2F",X"A0",X"D3",X"03",X"77",X"C9",X"21",X"E5", - X"20",X"46",X"B0",X"D3",X"05",X"77",X"C9",X"21",X"E5",X"20",X"46",X"2F",X"A0",X"D3",X"05",X"77", - X"C9",X"21",X"C3",X"20",X"3A",X"D8",X"20",X"6F",X"2B",X"2B",X"22",X"C9",X"20",X"06",X"03",X"11", - X"DC",X"20",X"AF",X"1A",X"BE",X"DA",X"41",X"02",X"96",X"C0",X"23",X"13",X"05",X"C2",X"33",X"02", - X"C9",X"06",X"03",X"2A",X"C9",X"20",X"11",X"DC",X"20",X"7E",X"12",X"23",X"13",X"05",X"C2",X"49", - X"02",X"21",X"1D",X"30",X"22",X"D6",X"20",X"2A",X"C9",X"20",X"22",X"D4",X"20",X"C3",X"A3",X"02", - X"D5",X"1A",X"CD",X"2E",X"03",X"CD",X"45",X"03",X"D1",X"13",X"05",X"C2",X"60",X"02",X"C9",X"21", - X"C2",X"20",X"11",X"C5",X"20",X"3A",X"D8",X"20",X"5F",X"CD",X"E1",X"02",X"13",X"23",X"06",X"03", - X"CD",X"8B",X"03",X"21",X"C0",X"20",X"11",X"03",X"00",X"C3",X"64",X"03",X"3A",X"E4",X"20",X"A7", - X"C8",X"CD",X"6F",X"02",X"21",X"D8",X"20",X"7E",X"3D",X"3D",X"2E",X"D4",X"77",X"2E",X"D9",X"7E", - X"2E",X"D7",X"77",X"2A",X"D4",X"20",X"7E",X"23",X"22",X"D4",X"20",X"E6",X"0F",X"CD",X"D1",X"02", - X"06",X"02",X"C5",X"2A",X"D4",X"20",X"7E",X"F5",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"CD",X"D1", - X"02",X"F1",X"E6",X"0F",X"CD",X"D1",X"02",X"21",X"D4",X"20",X"34",X"C1",X"05",X"C2",X"B2",X"02", - X"C9",X"C6",X"20",X"CD",X"2E",X"03",X"2A",X"D6",X"20",X"CD",X"45",X"03",X"21",X"D7",X"20",X"34", - X"C9",X"06",X"03",X"AF",X"1A",X"8E",X"27",X"77",X"2B",X"1B",X"05",X"C2",X"E4",X"02",X"C9",X"1A", - X"77",X"13",X"23",X"1A",X"77",X"13",X"23",X"23",X"23",X"7E",X"FE",X"FF",X"C2",X"EF",X"02",X"C9", - X"06",X"06",X"C5",X"7D",X"12",X"13",X"7C",X"12",X"01",X"00",X"06",X"09",X"13",X"13",X"13",X"C1", - X"05",X"C2",X"02",X"03",X"C9",X"3A",X"E7",X"20",X"C6",X"20",X"CD",X"2E",X"03",X"21",X"01",X"3E", - X"C3",X"45",X"03",X"21",X"01",X"37",X"11",X"B4",X"04",X"06",X"06",X"C3",X"60",X"02",X"11",X"94", - X"03",X"A7",X"C8",X"E5",X"21",X"00",X"00",X"C5",X"01",X"05",X"00",X"09",X"3D",X"C2",X"38",X"03", - X"19",X"EB",X"C1",X"E1",X"C9",X"C5",X"06",X"05",X"D3",X"06",X"C5",X"1A",X"07",X"77",X"13",X"01", - X"20",X"00",X"09",X"C1",X"05",X"C2",X"48",X"03",X"AF",X"77",X"01",X"20",X"00",X"09",X"77",X"09", - X"77",X"09",X"C1",X"C9",X"AF",X"77",X"23",X"1B",X"BA",X"C2",X"65",X"03",X"BB",X"C2",X"65",X"03", - X"C9",X"7D",X"E6",X"07",X"D3",X"02",X"C5",X"06",X"03",X"7C",X"1F",X"67",X"7D",X"1F",X"6F",X"05", - X"C2",X"79",X"03",X"7C",X"E6",X"3F",X"F6",X"20",X"67",X"C1",X"C9",X"7E",X"12",X"23",X"13",X"05", - X"C2",X"8B",X"03",X"C9",X"1F",X"24",X"44",X"24",X"1F",X"7F",X"49",X"49",X"49",X"36",X"3E",X"41", - X"41",X"41",X"22",X"7F",X"41",X"41",X"41",X"3E",X"7F",X"49",X"49",X"49",X"41",X"7F",X"48",X"48", - X"48",X"40",X"3E",X"41",X"41",X"45",X"47",X"7F",X"08",X"08",X"08",X"7F",X"00",X"41",X"7F",X"41", - X"00",X"02",X"01",X"01",X"01",X"7E",X"7F",X"08",X"14",X"22",X"41",X"7F",X"01",X"01",X"01",X"01", - X"7F",X"20",X"18",X"20",X"7F",X"7F",X"10",X"08",X"04",X"7F",X"3E",X"41",X"41",X"41",X"3E",X"7F", - X"48",X"48",X"48",X"30",X"3E",X"41",X"45",X"42",X"3D",X"7F",X"48",X"4C",X"4A",X"31",X"32",X"49", - X"49",X"49",X"26",X"40",X"40",X"7F",X"40",X"40",X"7E",X"01",X"01",X"01",X"7E",X"7C",X"02",X"01", - X"02",X"7C",X"7F",X"02",X"0C",X"02",X"7F",X"63",X"14",X"08",X"14",X"63",X"60",X"10",X"0F",X"10", - X"60",X"43",X"45",X"49",X"51",X"61",X"00",X"00",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00", - X"10",X"10",X"10",X"10",X"10",X"22",X"14",X"7F",X"14",X"22",X"08",X"14",X"22",X"41",X"00",X"00", - X"41",X"22",X"14",X"08",X"3E",X"45",X"49",X"51",X"3E",X"00",X"21",X"7F",X"01",X"00",X"23",X"45", - X"49",X"49",X"31",X"42",X"41",X"49",X"59",X"66",X"0C",X"14",X"24",X"7F",X"04",X"72",X"51",X"51", - X"51",X"4E",X"1E",X"29",X"49",X"49",X"46",X"40",X"47",X"48",X"50",X"60",X"36",X"49",X"49",X"49", - X"36",X"31",X"49",X"49",X"4A",X"3C",X"14",X"14",X"14",X"14",X"14",X"01",X"02",X"04",X"08",X"10", - X"00",X"00",X"00",X"00",X"00",X"18",X"18",X"18",X"18",X"18",X"00",X"00",X"18",X"18",X"00",X"0F", - X"14",X"12",X"07",X"1B",X"0E",X"0D",X"0B",X"18",X"1B",X"21",X"1B",X"0F",X"0B",X"00",X"18",X"04", - X"11",X"12",X"1B",X"01",X"14",X"13",X"13",X"0E",X"0D",X"1B",X"21",X"1B",X"0E",X"11",X"1B",X"22", - X"1B",X"0F",X"0B",X"00",X"18",X"04",X"11",X"12",X"1B",X"01",X"14",X"13",X"13",X"0E",X"0D",X"00", - X"C5",X"26",X"C8",X"39",X"02",X"11",X"04",X"03",X"08",X"13",X"06",X"C0",X"21",X"00",X"46",X"11", - X"00",X"20",X"C3",X"8B",X"03",X"06",X"50",X"11",X"00",X"21",X"21",X"00",X"47",X"C3",X"8B",X"03", - X"06",X"50",X"11",X"00",X"22",X"C3",X"CA",X"04",X"21",X"00",X"20",X"35",X"23",X"34",X"CD",X"EC", - X"13",X"DB",X"01",X"0F",X"DA",X"28",X"05",X"21",X"E8",X"20",X"7E",X"A7",X"CA",X"03",X"05",X"2B", - X"7E",X"FE",X"09",X"D2",X"FF",X"04",X"C6",X"01",X"27",X"32",X"E7",X"20",X"CD",X"15",X"03",X"AF", - X"32",X"E8",X"20",X"3A",X"DF",X"20",X"A7",X"C2",X"22",X"05",X"3A",X"E4",X"20",X"A7",X"C2",X"D3", - X"08",X"3A",X"E7",X"20",X"A7",X"C2",X"2D",X"05",X"3A",X"E0",X"20",X"A7",X"C2",X"D3",X"08",X"CD", - X"3D",X"17",X"F1",X"C1",X"D1",X"E1",X"FB",X"C9",X"3E",X"01",X"C3",X"00",X"05",X"3A",X"02",X"20", - X"A7",X"C2",X"22",X"05",X"3E",X"01",X"32",X"02",X"20",X"31",X"00",X"24",X"FB",X"CD",X"B6",X"00", - X"21",X"E0",X"20",X"36",X"00",X"2E",X"AA",X"36",X"00",X"CD",X"BB",X"01",X"21",X"13",X"30",X"11", - X"7F",X"04",X"06",X"04",X"CD",X"60",X"02",X"3A",X"E7",X"20",X"3D",X"D3",X"06",X"21",X"11",X"27", - X"06",X"16",X"C2",X"A7",X"07",X"11",X"83",X"04",X"CD",X"60",X"02",X"D3",X"06",X"DB",X"01",X"E6", - X"04",X"CA",X"57",X"05",X"06",X"99",X"AF",X"32",X"DA",X"20",X"3A",X"E7",X"20",X"80",X"27",X"32", - X"E7",X"20",X"CD",X"15",X"03",X"21",X"C3",X"20",X"11",X"06",X"00",X"CD",X"64",X"03",X"CD",X"BA", - X"04",X"CD",X"C5",X"04",X"CD",X"D0",X"04",X"CD",X"BB",X"01",X"21",X"2F",X"20",X"34",X"2E",X"E4", - X"34",X"CD",X"BC",X"00",X"21",X"01",X"01",X"22",X"E9",X"20",X"CD",X"18",X"1A",X"CD",X"0D",X"19", - X"3E",X"20",X"CD",X"FB",X"01",X"CD",X"B6",X"00",X"CD",X"2A",X"1A",X"CD",X"0E",X"06",X"CD",X"BC", - X"00",X"CD",X"78",X"1A",X"CD",X"18",X"12",X"D3",X"06",X"CD",X"6B",X"07",X"CD",X"A1",X"1A",X"21", - X"35",X"20",X"AF",X"BE",X"C2",X"48",X"06",X"CD",X"E6",X"18",X"CD",X"FB",X"18",X"CD",X"F2",X"18", - X"CD",X"04",X"19",X"CD",X"E9",X"05",X"C3",X"C4",X"05",X"2E",X"24",X"CD",X"52",X"1A",X"7E",X"FE", - X"03",X"21",X"9B",X"20",X"D2",X"FA",X"05",X"36",X"00",X"C9",X"36",X"01",X"CD",X"07",X"13",X"7E", - X"0F",X"0F",X"01",X"40",X"00",X"DA",X"FE",X"12",X"01",X"C0",X"FF",X"C3",X"FE",X"12",X"06",X"07", - X"C5",X"CD",X"52",X"1A",X"21",X"1E",X"25",X"D2",X"1C",X"06",X"26",X"38",X"01",X"38",X"01",X"CD", - X"24",X"14",X"3E",X"08",X"CD",X"D5",X"14",X"CD",X"52",X"1A",X"11",X"F3",X"43",X"21",X"1E",X"38", - X"DA",X"38",X"06",X"11",X"E0",X"43",X"26",X"25",X"06",X"07",X"CD",X"60",X"02",X"3E",X"08",X"CD", - X"D5",X"14",X"C1",X"05",X"C2",X"10",X"06",X"C9",X"CD",X"B6",X"00",X"E5",X"CD",X"4C",X"00",X"CD", - X"0D",X"19",X"E1",X"CD",X"9A",X"18",X"3A",X"DA",X"20",X"A7",X"C2",X"91",X"06",X"CD",X"44",X"1A", - X"35",X"CA",X"7A",X"07",X"CD",X"7A",X"06",X"CD",X"BA",X"04",X"CD",X"BB",X"01",X"21",X"2F",X"20", - X"34",X"CD",X"FC",X"00",X"CD",X"BC",X"00",X"C3",X"B5",X"05",X"7E",X"3D",X"21",X"01",X"25",X"CA", - X"88",X"06",X"24",X"24",X"3D",X"C2",X"82",X"06",X"01",X"10",X"01",X"CD",X"8C",X"08",X"C3",X"C1", - X"00",X"CD",X"B6",X"00",X"3A",X"DB",X"20",X"0F",X"DA",X"C8",X"06",X"CD",X"44",X"1A",X"35",X"C2", - X"F5",X"06",X"CD",X"5D",X"07",X"21",X"07",X"30",X"3E",X"21",X"CD",X"2E",X"03",X"CD",X"45",X"03", - X"CD",X"21",X"02",X"CD",X"C1",X"00",X"21",X"DB",X"20",X"36",X"01",X"CD",X"44",X"1A",X"A7",X"C2", - X"04",X"07",X"CD",X"1E",X"14",X"C3",X"7D",X"07",X"CD",X"44",X"1A",X"35",X"C2",X"46",X"07",X"CD", - X"5D",X"07",X"21",X"07",X"30",X"3E",X"22",X"CD",X"2E",X"03",X"CD",X"45",X"03",X"CD",X"21",X"02", - X"CD",X"C1",X"00",X"21",X"DB",X"20",X"36",X"00",X"CD",X"44",X"1A",X"A7",X"C2",X"38",X"07",X"CD", - X"1E",X"14",X"C3",X"7D",X"07",X"CD",X"7A",X"06",X"21",X"DB",X"20",X"36",X"01",X"CD",X"44",X"1A", - X"A7",X"CA",X"3E",X"07",X"CD",X"F5",X"01",X"CD",X"1E",X"14",X"CD",X"16",X"07",X"CD",X"EF",X"12", - X"CD",X"B6",X"00",X"C3",X"67",X"06",X"3A",X"DB",X"20",X"0F",X"DA",X"33",X"07",X"AF",X"21",X"E5", - X"20",X"77",X"F3",X"D3",X"05",X"06",X"0A",X"0E",X"00",X"0D",X"C2",X"29",X"07",X"05",X"C2",X"27", - X"07",X"FB",X"C9",X"3E",X"20",X"C3",X"1E",X"07",X"CD",X"EA",X"01",X"C3",X"07",X"07",X"21",X"DB", - X"20",X"36",X"00",X"C3",X"38",X"07",X"CD",X"7A",X"06",X"21",X"DB",X"20",X"36",X"00",X"CD",X"44", - X"1A",X"A7",X"C2",X"38",X"07",X"21",X"DB",X"20",X"36",X"01",X"C3",X"04",X"07",X"21",X"07",X"28", - X"11",X"D4",X"44",X"06",X"14",X"CD",X"60",X"02",X"C3",X"FC",X"00",X"CD",X"52",X"1A",X"2E",X"25", - X"7E",X"FE",X"02",X"D8",X"21",X"54",X"20",X"36",X"01",X"C9",X"CD",X"21",X"02",X"21",X"00",X"00", - X"22",X"DA",X"20",X"22",X"E4",X"20",X"22",X"E5",X"20",X"22",X"E9",X"20",X"21",X"DA",X"20",X"36", - X"01",X"21",X"14",X"2D",X"11",X"DF",X"44",X"06",X"09",X"CD",X"60",X"02",X"3E",X"80",X"CD",X"D5", - X"14",X"CD",X"EA",X"01",X"C3",X"2D",X"00",X"11",X"99",X"04",X"CD",X"60",X"02",X"DB",X"01",X"0F", - X"0F",X"DA",X"BB",X"07",X"0F",X"DA",X"74",X"05",X"C3",X"57",X"05",X"3E",X"01",X"06",X"98",X"C3", - X"77",X"05",X"21",X"05",X"20",X"AF",X"BE",X"C8",X"CD",X"77",X"08",X"22",X"07",X"20",X"2A",X"09", - X"20",X"01",X"60",X"00",X"09",X"22",X"09",X"20",X"44",X"21",X"0B",X"20",X"AF",X"BE",X"C2",X"E7", - X"07",X"78",X"FE",X"2B",X"D2",X"32",X"08",X"23",X"AF",X"BE",X"C2",X"F3",X"07",X"78",X"FE",X"31", - X"D2",X"4D",X"08",X"23",X"AF",X"BE",X"C2",X"FF",X"07",X"78",X"FE",X"37",X"D2",X"5B",X"08",X"23"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02 deleted file mode 100644 index 1fc488a6..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02 and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd deleted file mode 100644 index 85fd82b9..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn02 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn02 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AF",X"BE",X"C2",X"0B",X"08",X"78",X"FE",X"3E",X"D2",X"69",X"08",X"78",X"FE",X"3C",X"DA",X"25", - X"08",X"2A",X"09",X"20",X"01",X"1E",X"02",X"CD",X"8C",X"08",X"21",X"05",X"20",X"36",X"00",X"21", - X"BF",X"20",X"36",X"00",X"C9",X"2A",X"07",X"20",X"EB",X"2A",X"09",X"20",X"01",X"1E",X"02",X"C3", - X"D5",X"01",X"36",X"FF",X"21",X"05",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"06",X"CD",X"52",X"1A", - X"E5",X"C1",X"0A",X"6F",X"03",X"0A",X"67",X"CD",X"D2",X"01",X"C3",X"25",X"08",X"36",X"FF",X"21", - X"09",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"0A",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"0D",X"21", - X"CD",X"A0",X"08",X"EB",X"2E",X"0E",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"11",X"21",X"CD",X"A0", - X"08",X"EB",X"2E",X"12",X"C3",X"3D",X"08",X"21",X"06",X"20",X"34",X"7E",X"E6",X"01",X"C2",X"85", - X"08",X"21",X"72",X"40",X"C9",X"21",X"36",X"40",X"C9",X"01",X"20",X"03",X"AF",X"C5",X"E5",X"77", - X"23",X"05",X"C2",X"8F",X"08",X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"8D",X"08",X"C9", - X"7E",X"21",X"1D",X"41",X"3D",X"C8",X"11",X"60",X"00",X"19",X"C3",X"A4",X"08",X"AF",X"7C",X"1F", - X"57",X"7D",X"1F",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"5F",X"7A",X"E6",X"0F",X"07",X"07",X"07", - X"07",X"B3",X"C9",X"11",X"DD",X"43",X"06",X"02",X"C3",X"AD",X"0E",X"11",X"DD",X"43",X"06",X"02", - X"C3",X"9A",X"19",X"CD",X"38",X"14",X"CD",X"53",X"14",X"CD",X"40",X"10",X"CD",X"42",X"09",X"CD", - X"F8",X"08",X"CD",X"65",X"09",X"3A",X"E4",X"20",X"A7",X"CA",X"22",X"05",X"CD",X"89",X"1A",X"CD", - X"13",X"09",X"CD",X"35",X"1B",X"C3",X"22",X"05",X"21",X"1F",X"20",X"7E",X"A7",X"C8",X"46",X"36", - X"00",X"21",X"24",X"20",X"7E",X"0F",X"D0",X"36",X"00",X"2A",X"22",X"20",X"EB",X"21",X"38",X"20", - X"C3",X"0D",X"0A",X"CD",X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"03",X"D8",X"21",X"BF",X"20",X"AF", - X"BE",X"C0",X"34",X"21",X"35",X"09",X"C3",X"7B",X"1A",X"00",X"00",X"07",X"07",X"01",X"00",X"01", - X"00",X"06",X"06",X"01",X"00",X"00",X"00",X"04",X"04",X"01",X"00",X"00",X"02",X"00",X"01",X"01", - X"01",X"00",X"3A",X"E4",X"20",X"A7",X"C8",X"21",X"38",X"20",X"7E",X"FE",X"FF",X"CA",X"60",X"09", - X"0F",X"D2",X"59",X"09",X"3E",X"10",X"C3",X"0E",X"02",X"23",X"23",X"23",X"23",X"C3",X"4A",X"09", - X"3E",X"10",X"C3",X"17",X"02",X"21",X"04",X"20",X"34",X"7E",X"E6",X"03",X"77",X"A7",X"CA",X"28", - X"19",X"FE",X"01",X"CA",X"38",X"19",X"FE",X"02",X"CA",X"66",X"19",X"FE",X"03",X"CA",X"85",X"19", - X"C9",X"21",X"38",X"20",X"CD",X"21",X"0A",X"21",X"3C",X"20",X"CD",X"21",X"0A",X"11",X"9D",X"20", - X"CD",X"DF",X"09",X"CD",X"07",X"13",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"40",X"20",X"CD", - X"21",X"0A",X"21",X"44",X"20",X"CD",X"21",X"0A",X"11",X"9E",X"20",X"CD",X"DF",X"09",X"2E",X"0C", - X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"CD",X"D9",X"09",X"C3",X"15",X"15",X"21",X"48",X"20",X"CD", - X"21",X"0A",X"21",X"4C",X"20",X"CD",X"21",X"0A",X"11",X"9F",X"20",X"CD",X"DF",X"09",X"2E",X"14", - X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"9C",X"20",X"36",X"00",X"C9",X"21", - X"9B",X"20",X"7E",X"A7",X"CA",X"EB",X"09",X"23",X"36",X"00",X"C9",X"EB",X"34",X"7E",X"FE",X"02", - X"D2",X"F8",X"09",X"EB",X"23",X"36",X"FF",X"C9",X"36",X"00",X"EB",X"23",X"36",X"00",X"C9",X"57", - X"3A",X"9C",X"20",X"A7",X"7A",X"C2",X"0A",X"0A",X"37",X"C9",X"37",X"3F",X"C9",X"78",X"3D",X"CA", - X"19",X"0A",X"23",X"23",X"23",X"23",X"C3",X"0E",X"0A",X"36",X"01",X"23",X"23",X"73",X"23",X"72", - X"C9",X"7E",X"0F",X"D0",X"23",X"23",X"E5",X"CD",X"6C",X"11",X"CD",X"5B",X"0A",X"E1",X"E5",X"CD", - X"6C",X"11",X"7D",X"FE",X"18",X"DA",X"48",X"0A",X"01",X"F9",X"FF",X"09",X"EB",X"E1",X"73",X"23", - X"72",X"EB",X"11",X"DA",X"43",X"C3",X"CF",X"0E",X"E1",X"E5",X"CD",X"6C",X"11",X"22",X"B7",X"20", - X"E1",X"2B",X"AF",X"77",X"2B",X"77",X"21",X"B5",X"20",X"34",X"C9",X"11",X"DA",X"43",X"C3",X"AB", - X"0E",X"7C",X"B5",X"37",X"C8",X"7B",X"95",X"7A",X"9C",X"C9",X"E5",X"7E",X"47",X"07",X"D2",X"8A", - X"0A",X"23",X"23",X"CD",X"15",X"0B",X"78",X"0F",X"0F",X"7A",X"D2",X"DA",X"0A",X"FE",X"4B",X"DA", - X"A1",X"0A",X"36",X"25",X"E1",X"E5",X"3E",X"DF",X"A6",X"77",X"21",X"37",X"20",X"34",X"E1",X"23", - X"23",X"23",X"23",X"3A",X"37",X"20",X"FE",X"02",X"DA",X"6A",X"0A",X"21",X"37",X"20",X"36",X"00", - X"C9",X"FE",X"3C",X"D2",X"CC",X"0A",X"78",X"0F",X"E1",X"E5",X"23",X"7E",X"23",X"4E",X"23",X"46", - X"2B",X"2B",X"DA",X"2F",X"0B",X"CD",X"FF",X"09",X"D2",X"BF",X"0A",X"3D",X"CA",X"23",X"0B",X"77", - X"CD",X"A1",X"08",X"EB",X"60",X"69",X"CD",X"D2",X"01",X"C3",X"8A",X"0A",X"E1",X"E5",X"CD",X"03", - X"0B",X"E1",X"E5",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"2B",X"2B",X"2B",X"FE",X"25",X"DA", - X"EE",X"0A",X"FE",X"3C",X"DA",X"FB",X"0A",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"CD",X"08", - X"0B",X"E1",X"E5",X"23",X"23",X"23",X"36",X"48",X"C3",X"8A",X"0A",X"46",X"3E",X"DF",X"A6",X"77", - X"C3",X"A6",X"0A",X"7E",X"07",X"07",X"07",X"D8",X"3E",X"20",X"B6",X"77",X"23",X"23",X"5E",X"23", - X"56",X"EB",X"C3",X"89",X"08",X"E5",X"5E",X"23",X"56",X"2A",X"28",X"21",X"19",X"EB",X"E1",X"73", - X"23",X"72",X"C9",X"36",X"01",X"2B",X"3E",X"01",X"B6",X"77",X"3E",X"01",X"C3",X"C0",X"0A",X"CD", - X"FF",X"09",X"D2",X"BF",X"0A",X"3C",X"FE",X"08",X"DA",X"BF",X"0A",X"36",X"07",X"2B",X"3E",X"FE", - X"A6",X"77",X"3E",X"07",X"C3",X"C0",X"0A",X"CD",X"56",X"0B",X"CD",X"AB",X"0B",X"CD",X"D6",X"0B", - X"CD",X"40",X"15",X"C3",X"27",X"16",X"AF",X"21",X"B5",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE", - X"01",X"CA",X"01",X"0C",X"FE",X"04",X"CA",X"07",X"0C",X"FE",X"07",X"D8",X"11",X"3C",X"44",X"CD", - X"0A",X"0C",X"CD",X"E0",X"15",X"21",X"B8",X"20",X"D2",X"81",X"0B",X"CD",X"9B",X"0B",X"C3",X"84", - X"0B",X"CD",X"8B",X"0B",X"21",X"00",X"00",X"22",X"B5",X"20",X"C9",X"AF",X"3A",X"34",X"20",X"BE", - X"D8",X"7E",X"21",X"7D",X"20",X"BE",X"D8",X"77",X"C3",X"0D",X"16",X"AF",X"3A",X"34",X"20",X"BE", - X"D0",X"7E",X"21",X"7F",X"20",X"BE",X"D0",X"77",X"C3",X"ED",X"15",X"AF",X"21",X"1D",X"20",X"BE", - X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"16",X"0C",X"FE",X"04",X"CA",X"1C",X"0C",X"FE",X"07", - X"D8",X"2A",X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00", - X"22",X"1D",X"20",X"C3",X"7D",X"15",X"AF",X"21",X"27",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE", - X"01",X"CA",X"2B",X"0C",X"FE",X"04",X"CA",X"47",X"0C",X"FE",X"07",X"D8",X"2A",X"2D",X"20",X"01", - X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",X"22",X"27",X"20",X"CD",X"6F",X"1A",X"C3",X"7D", - X"15",X"11",X"0C",X"44",X"C3",X"0A",X"0C",X"11",X"24",X"44",X"2A",X"B7",X"20",X"CD",X"76",X"03", - X"01",X"0C",X"02",X"C3",X"D5",X"01",X"11",X"54",X"44",X"C3",X"1F",X"0C",X"11",X"74",X"44",X"2A", - X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"C3",X"D5",X"01",X"2A",X"29",X"20",X"11",X"DA", - X"43",X"CD",X"AD",X"0E",X"2A",X"29",X"20",X"CD",X"76",X"03",X"22",X"2D",X"20",X"11",X"94",X"44", - X"01",X"10",X"02",X"CD",X"D5",X"01",X"C9",X"2A",X"2D",X"20",X"11",X"B4",X"44",X"C3",X"40",X"0C", - X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"DB",X"20",X"0F",X"DB",X"01",X"D0",X"DB",X"02",X"C9",X"21", - X"2F",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"6E",X"0C",X"34",X"CD",X"E4",X"0C",X"3A",X"E4", - X"20",X"A7",X"C2",X"9D",X"0C",X"2A",X"E2",X"20",X"3A",X"E1",X"20",X"3C",X"32",X"E1",X"20",X"E6", - X"0F",X"C2",X"8B",X"0C",X"7D",X"FE",X"13",X"CC",X"9A",X"0C",X"23",X"22",X"E2",X"20",X"7E",X"0F", - X"DA",X"06",X"0D",X"0F",X"DA",X"23",X"0D",X"C3",X"A9",X"0C",X"2E",X"00",X"C9",X"CD",X"50",X"0C", - X"07",X"07",X"DA",X"06",X"0D",X"07",X"DA",X"23",X"0D",X"06",X"00",X"21",X"32",X"20",X"70",X"CD", - X"E4",X"0C",X"21",X"31",X"20",X"CD",X"A1",X"0D",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02", - X"0E",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"A6",X"CA",X"D0",X"0C",X"3E",X"01",X"32",X"35",X"20", - X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"C6",X"0C",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05", - X"C2",X"C4",X"0C",X"C9",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02",X"0E",X"CD",X"71",X"03", - X"C5",X"E5",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"F2",X"0C",X"E1",X"01",X"20",X"00",X"09", - X"C1",X"05",X"C2",X"F0",X"0C",X"C9",X"3A",X"34",X"20",X"FE",X"DA",X"D2",X"A9",X"0C",X"2A",X"33", - X"20",X"01",X"F8",X"0F",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"02", - X"C3",X"AB",X"0C",X"3A",X"34",X"20",X"FE",X"38",X"DA",X"A9",X"0C",X"2A",X"33",X"20",X"01",X"F8", - X"FC",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"FE",X"C3",X"AB",X"0C", - X"23",X"23",X"5E",X"23",X"7E",X"C6",X"02",X"57",X"EB",X"CD",X"AD",X"08",X"57",X"7D",X"E6",X"1F", - X"07",X"07",X"07",X"5F",X"EB",X"C9",X"21",X"54",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"73", - X"0D",X"34",X"23",X"BE",X"21",X"00",X"FD",X"22",X"58",X"20",X"21",X"C8",X"D0",X"C4",X"1A",X"0E", - X"22",X"5A",X"20",X"3A",X"56",X"20",X"A7",X"21",X"5B",X"20",X"7E",X"C2",X"AD",X"0D",X"FE",X"28", - X"DA",X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"AE",X"40",X"CC",X"C1",X"0D",X"22", - X"5C",X"20",X"21",X"5A",X"20",X"CD",X"F0",X"0D",X"CD",X"02",X"0E",X"CD",X"24",X"0E",X"21",X"58", - X"20",X"4E",X"23",X"46",X"23",X"79",X"86",X"77",X"23",X"78",X"86",X"77",X"C9",X"FE",X"D0",X"D2", - X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"36",X"40",X"CC",X"C5",X"0D",X"C3",X"8F", - X"0D",X"21",X"E5",X"40",X"C9",X"21",X"72",X"40",X"C9",X"2A",X"5A",X"20",X"01",X"1B",X"02",X"CD", - X"76",X"03",X"CD",X"8C",X"08",X"06",X"0C",X"21",X"54",X"46",X"11",X"54",X"20",X"CD",X"8B",X"03", - X"21",X"13",X"20",X"34",X"7E",X"E6",X"01",X"21",X"56",X"20",X"36",X"01",X"C0",X"36",X"00",X"C9", - X"E5",X"23",X"23",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"E1",X"D5",X"5E",X"23",X"56",X"EB", - X"D1",X"C9",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"77",X"23",X"13",X"0D",X"C2",X"07",X"0E",X"E1", - X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"05",X"0E",X"C9",X"21",X"00",X"03",X"22",X"58",X"20", - X"21",X"C8",X"28",X"C9",X"3A",X"56",X"20",X"A7",X"C2",X"A1",X"0E",X"CD",X"35",X"0E",X"D6",X"0A", - X"B8",X"DA",X"3D",X"0E",X"C9",X"2A",X"34",X"20",X"44",X"3A",X"0A",X"20",X"C9",X"21",X"B0",X"20", - X"AF",X"BE",X"CA",X"47",X"0E",X"35",X"C9",X"E5",X"CD",X"4B",X"1A",X"23",X"7E",X"FE",X"04",X"06", - X"50",X"D2",X"56",X"0E",X"06",X"60",X"E1",X"70",X"FE",X"0B",X"D2",X"7A",X"0E",X"FE",X"09",X"CD", - X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"04",X"D2",X"8F",X"0E",X"21",X"60",X"20",X"34",X"2E",X"67", - X"34",X"2E",X"6E",X"34",X"21",X"95",X"20",X"36",X"00",X"C9",X"21",X"FB",X"03",X"22",X"63",X"20", - X"21",X"FA",X"02",X"22",X"6A",X"20",X"21",X"FB",X"FA",X"22",X"71",X"20",X"C3",X"6A",X"0E",X"21", - X"FC",X"02",X"22",X"63",X"20",X"21",X"FB",X"01",X"22",X"6A",X"20",X"21",X"FB",X"FD",X"C3",X"89", - X"0E",X"CD",X"35",X"0E",X"C6",X"08",X"B8",X"D2",X"3D",X"0E",X"C9",X"06",X"03",X"CD",X"71",X"03", - X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"2F",X"A6",X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB", - X"03",X"2F",X"A6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"B0",X"0E",X"C9",X"06", - X"03",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"AE",X"77",X"23",X"13",X"AF", - X"D3",X"04",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"D4",X"0E", - X"C9",X"21",X"60",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"FE",X"0E",X"35",X"C9",X"23",X"BE", - X"C2",X"0A",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"65",X"20",X"CD",X"3B",X"0F",X"21",X"66",X"20", - X"7E",X"FE",X"30",X"DC",X"46",X"0F",X"FE",X"E8",X"D4",X"53",X"0F",X"2B",X"7E",X"FE",X"18",X"DA", - X"5E",X"0F",X"21",X"63",X"20",X"CD",X"A1",X"0D",X"2A",X"65",X"20",X"11",X"DA",X"0F",X"06",X"08", - X"C3",X"D1",X"0E",X"2A",X"5A",X"20",X"01",X"00",X"08",X"09",X"C9",X"2A",X"65",X"20",X"11",X"DA", - X"0F",X"06",X"08",X"C3",X"AD",X"0E",X"F5",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36", - X"E0",X"F1",X"C9",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36",X"34",X"C9",X"CD",X"3B", - X"0F",X"21",X"60",X"46",X"11",X"60",X"20",X"06",X"07",X"C3",X"8B",X"03",X"21",X"67",X"20",X"AF", - X"BE",X"C8",X"23",X"BE",X"CA",X"79",X"0F",X"35",X"C9",X"23",X"BE",X"C2",X"85",X"0F",X"34",X"CD", - X"33",X"0F",X"22",X"6C",X"20",X"2A",X"6C",X"20",X"CD",X"3E",X"0F",X"21",X"6D",X"20",X"7E",X"FE", - X"30",X"DC",X"BC",X"0F",X"FE",X"E8",X"D4",X"C4",X"0F",X"2B",X"7E",X"47",X"CD",X"52",X"1A",X"2E", - X"24",X"7E",X"FE",X"05",X"0E",X"13",X"D2",X"AB",X"0F",X"0E",X"18",X"78",X"B9",X"DA",X"CB",X"0F", - X"21",X"6A",X"20",X"CD",X"A1",X"0D",X"2A",X"6C",X"20",X"C3",X"2B",X"0F",X"F5",X"E5",X"2A",X"6C", - X"20",X"C3",X"57",X"0F",X"E5",X"2A",X"6C",X"20",X"C3",X"4B",X"0F",X"2A",X"6C",X"20",X"CD",X"3E", - X"0F",X"21",X"67",X"46",X"11",X"67",X"20",X"C3",X"67",X"0F",X"60",X"F0",X"F0",X"F0",X"F0",X"60", - X"90",X"90",X"21",X"6E",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"CA",X"EF",X"0F",X"35",X"C9",X"23", - X"BE",X"C2",X"FB",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"73",X"20",X"2A",X"73",X"20",X"CD",X"3E"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03 deleted file mode 100644 index e0ab28e6..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03 and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd deleted file mode 100644 index d35cb0d4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn03 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn03 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"0F",X"21",X"74",X"20",X"7E",X"FE",X"30",X"DC",X"22",X"10",X"FE",X"E8",X"D4",X"2A",X"10",X"2B", - X"7E",X"FE",X"18",X"DA",X"31",X"10",X"21",X"71",X"20",X"CD",X"A1",X"0D",X"2A",X"73",X"20",X"C3", - X"2B",X"0F",X"F5",X"E5",X"2A",X"73",X"20",X"C3",X"4B",X"0F",X"E5",X"2A",X"73",X"20",X"C3",X"57", - X"0F",X"2A",X"73",X"20",X"CD",X"3E",X"0F",X"21",X"6E",X"46",X"11",X"6E",X"20",X"C3",X"67",X"0F", - X"21",X"11",X"20",X"AF",X"BE",X"C8",X"36",X"00",X"21",X"14",X"20",X"34",X"21",X"00",X"00",X"22", - X"16",X"20",X"2A",X"1A",X"20",X"CD",X"C3",X"08",X"21",X"60",X"20",X"AF",X"BE",X"CA",X"B0",X"10", - X"21",X"65",X"20",X"CD",X"8F",X"10",X"D4",X"6C",X"10",X"C3",X"B0",X"10",X"CD",X"96",X"10",X"DA", - X"73",X"10",X"C9",X"CD",X"9D",X"10",X"D2",X"7A",X"10",X"C9",X"CD",X"A9",X"10",X"DA",X"81",X"10", - X"C9",X"E1",X"2A",X"65",X"20",X"22",X"93",X"20",X"21",X"91",X"20",X"34",X"C3",X"5E",X"0F",X"3A", - X"1A",X"20",X"C6",X"08",X"BE",X"C9",X"F5",X"3E",X"10",X"86",X"C3",X"A5",X"10",X"3A",X"1B",X"20", - X"23",X"F5",X"7E",X"D6",X"08",X"47",X"F1",X"B8",X"C9",X"F5",X"3E",X"10",X"86",X"C3",X"A5",X"10", - X"21",X"67",X"20",X"AF",X"BE",X"CA",X"E7",X"10",X"21",X"6C",X"20",X"CD",X"8F",X"10",X"D4",X"C4", - X"10",X"C3",X"E7",X"10",X"CD",X"96",X"10",X"DA",X"CB",X"10",X"C9",X"CD",X"9D",X"10",X"D2",X"D2", - X"10",X"C9",X"CD",X"A9",X"10",X"DA",X"D9",X"10",X"C9",X"E1",X"2A",X"6C",X"20",X"22",X"93",X"20", - X"21",X"91",X"20",X"34",X"C3",X"CB",X"0F",X"21",X"6E",X"20",X"AF",X"BE",X"CA",X"1E",X"11",X"21", - X"73",X"20",X"CD",X"8F",X"10",X"D4",X"FB",X"10",X"C3",X"1E",X"11",X"CD",X"96",X"10",X"DA",X"02", - X"11",X"C9",X"CD",X"9D",X"10",X"D2",X"09",X"11",X"C9",X"CD",X"A9",X"10",X"DA",X"10",X"11",X"C9", - X"E1",X"2A",X"73",X"20",X"22",X"93",X"20",X"21",X"91",X"20",X"34",X"C3",X"31",X"10",X"21",X"38", - X"20",X"22",X"75",X"20",X"0E",X"06",X"7E",X"A7",X"CA",X"33",X"11",X"23",X"23",X"CD",X"8F",X"10", - X"D4",X"44",X"11",X"2A",X"75",X"20",X"11",X"04",X"00",X"19",X"22",X"75",X"20",X"0D",X"C2",X"26", - X"11",X"C3",X"71",X"11",X"CD",X"96",X"10",X"DA",X"4B",X"11",X"C9",X"CD",X"9D",X"10",X"D2",X"52", - X"11",X"C9",X"CD",X"A9",X"10",X"DA",X"59",X"11",X"C9",X"F1",X"2B",X"2B",X"2B",X"36",X"00",X"CD", - X"6A",X"11",X"22",X"29",X"20",X"21",X"27",X"20",X"34",X"C9",X"23",X"23",X"5E",X"23",X"56",X"EB", - X"C9",X"CD",X"07",X"13",X"22",X"77",X"20",X"0E",X"06",X"E5",X"21",X"1F",X"20",X"34",X"E1",X"7E", - X"07",X"DC",X"9D",X"11",X"2A",X"77",X"20",X"11",X"04",X"00",X"19",X"22",X"77",X"20",X"0D",X"C2", - X"79",X"11",X"21",X"1F",X"20",X"36",X"00",X"CD",X"E2",X"14",X"C3",X"7D",X"15",X"CD",X"6A",X"11", - X"7C",X"FE",X"3C",X"D0",X"C5",X"CD",X"49",X"0D",X"22",X"79",X"20",X"C1",X"21",X"79",X"20",X"3A", - X"1A",X"20",X"C6",X"0A",X"BE",X"D2",X"B9",X"11",X"C9",X"F5",X"3E",X"20",X"86",X"47",X"F1",X"B8", - X"DA",X"C4",X"11",X"C9",X"3A",X"1B",X"20",X"23",X"F5",X"7E",X"D6",X"08",X"47",X"F1",X"B8",X"D2", - X"D3",X"11",X"C9",X"F5",X"3E",X"23",X"86",X"47",X"F1",X"B8",X"DA",X"DE",X"11",X"C9",X"F1",X"E5", - X"21",X"1D",X"20",X"34",X"2A",X"1A",X"20",X"01",X"00",X"F6",X"09",X"22",X"22",X"20",X"2A",X"77", - X"20",X"7E",X"E6",X"0F",X"77",X"CD",X"6A",X"11",X"CD",X"89",X"08",X"E1",X"2B",X"3E",X"05",X"86", - X"47",X"3A",X"1A",X"20",X"B8",X"D2",X"0E",X"12",X"CD",X"67",X"1A",X"C3",X"0C",X"13",X"21",X"24", - X"20",X"34",X"CD",X"5F",X"1A",X"C3",X"0C",X"13",X"2E",X"24",X"CD",X"52",X"1A",X"7E",X"FE",X"06", - X"D2",X"24",X"12",X"C9",X"E5",X"3A",X"1D",X"20",X"A7",X"D3",X"06",X"C2",X"25",X"12",X"E1",X"36", - X"00",X"CD",X"0D",X"19",X"CD",X"4C",X"00",X"21",X"7B",X"20",X"34",X"21",X"00",X"46",X"11",X"00", - X"20",X"06",X"31",X"CD",X"8B",X"03",X"21",X"35",X"46",X"11",X"35",X"20",X"06",X"46",X"CD",X"8B", - X"03",X"21",X"81",X"46",X"11",X"81",X"20",X"06",X"3F",X"CD",X"8B",X"03",X"21",X"14",X"20",X"34", - X"CD",X"1E",X"14",X"CD",X"52",X"1A",X"2E",X"26",X"34",X"7E",X"47",X"0F",X"DA",X"71",X"12",X"2B", - X"34",X"78",X"FE",X"08",X"CC",X"13",X"13",X"FE",X"0F",X"CC",X"13",X"13",X"CD",X"AD",X"12",X"CD", - X"07",X"13",X"23",X"23",X"5E",X"23",X"56",X"21",X"09",X"20",X"73",X"23",X"72",X"3E",X"30",X"CD", - X"D5",X"14",X"21",X"05",X"20",X"34",X"7E",X"A7",X"D3",X"06",X"C2",X"96",X"12",X"21",X"7B",X"20", - X"36",X"00",X"2E",X"2F",X"34",X"2E",X"14",X"36",X"00",X"CD",X"78",X"1A",X"C9",X"CD",X"52",X"1A", - X"2E",X"25",X"7E",X"FE",X"0B",X"DA",X"BB",X"12",X"3E",X"03",X"77",X"47",X"FE",X"07",X"DA",X"C3", - X"12",X"06",X"06",X"3E",X"18",X"D6",X"03",X"05",X"C2",X"C5",X"12",X"4F",X"CD",X"07",X"13",X"23", - X"23",X"EB",X"69",X"26",X"27",X"CD",X"00",X"03",X"2E",X"25",X"CD",X"52",X"1A",X"7E",X"0F",X"0F", - X"11",X"E8",X"44",X"DA",X"E9",X"12",X"11",X"F8",X"44",X"CD",X"07",X"13",X"CD",X"EF",X"02",X"CD", - X"07",X"13",X"7E",X"0F",X"0F",X"01",X"20",X"00",X"DA",X"FE",X"12",X"01",X"E0",X"FF",X"21",X"28", - X"21",X"71",X"23",X"70",X"C3",X"BC",X"00",X"2E",X"04",X"C3",X"52",X"1A",X"2E",X"24",X"CD",X"52", - X"1A",X"34",X"C9",X"F5",X"3E",X"FF",X"CD",X"04",X"02",X"3E",X"04",X"CD",X"FB",X"01",X"CD",X"C1", - X"00",X"3E",X"20",X"CD",X"FB",X"01",X"CD",X"83",X"1A",X"CD",X"BC",X"00",X"CD",X"69",X"13",X"3E", - X"04",X"CD",X"04",X"02",X"2E",X"26",X"CD",X"52",X"1A",X"7E",X"0F",X"DA",X"49",X"13",X"21",X"12", - X"30",X"11",X"14",X"40",X"06",X"04",X"C3",X"51",X"13",X"21",X"12",X"2D",X"11",X"18",X"40",X"06", - X"0A",X"CD",X"60",X"02",X"CD",X"B6",X"00",X"CD",X"4C",X"00",X"3E",X"80",X"CD",X"D5",X"14",X"CD", - X"92",X"13",X"21",X"30",X"20",X"36",X"00",X"F1",X"C9",X"21",X"03",X"24",X"22",X"2D",X"21",X"21", - X"1C",X"40",X"22",X"2F",X"21",X"0E",X"71",X"C5",X"2A",X"2D",X"21",X"CD",X"BB",X"13",X"22",X"2D", - X"21",X"2A",X"2F",X"21",X"CD",X"CF",X"13",X"22",X"2F",X"21",X"C1",X"0D",X"C2",X"77",X"13",X"CD", - X"FC",X"00",X"0E",X"79",X"21",X"1C",X"33",X"22",X"2D",X"21",X"21",X"03",X"32",X"22",X"2F",X"21", - X"C5",X"AF",X"2A",X"2D",X"21",X"CD",X"D1",X"13",X"22",X"2D",X"21",X"AF",X"2A",X"2F",X"21",X"CD", - X"BD",X"13",X"22",X"2F",X"21",X"C1",X"0D",X"C2",X"A0",X"13",X"C9",X"3E",X"FF",X"06",X"1A",X"E5", - X"77",X"23",X"CD",X"E3",X"13",X"05",X"C2",X"C0",X"13",X"E1",X"11",X"20",X"00",X"19",X"C9",X"3E", - X"FF",X"06",X"1A",X"E5",X"77",X"2B",X"CD",X"E3",X"13",X"05",X"C2",X"D4",X"13",X"E1",X"11",X"E0", - X"FF",X"19",X"C9",X"1E",X"20",X"D3",X"06",X"1D",X"C2",X"E5",X"13",X"C9",X"DB",X"02",X"E6",X"04", - X"C8",X"3A",X"03",X"20",X"A7",X"C0",X"31",X"00",X"24",X"06",X"04",X"C5",X"CD",X"1E",X"14",X"C1", - X"05",X"C2",X"FB",X"13",X"3E",X"01",X"32",X"03",X"20",X"CD",X"B6",X"00",X"FB",X"11",X"22",X"40", - X"21",X"16",X"30",X"06",X"04",X"CD",X"60",X"02",X"CD",X"C1",X"00",X"C3",X"18",X"00",X"21",X"03", - X"24",X"01",X"DF",X"1A",X"C5",X"E5",X"36",X"00",X"23",X"05",X"C2",X"26",X"14",X"E1",X"11",X"20", - X"00",X"19",X"C1",X"0D",X"C2",X"24",X"14",X"C9",X"CD",X"50",X"0C",X"E6",X"10",X"CA",X"4D",X"14", - X"21",X"14",X"20",X"AF",X"BE",X"C0",X"23",X"BE",X"C0",X"34",X"23",X"34",X"C9",X"21",X"15",X"20", - X"36",X"00",X"C9",X"21",X"16",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"69",X"14",X"34",X"2A", - X"33",X"20",X"01",X"10",X"05",X"09",X"22",X"1A",X"20",X"2A",X"1A",X"20",X"CD",X"C3",X"08",X"2A", - X"1A",X"20",X"3A",X"54",X"20",X"A7",X"7D",X"C2",X"88",X"14",X"FE",X"E0",X"D2",X"8D",X"14",X"C6", - X"03",X"6F",X"22",X"1A",X"20",X"C3",X"CB",X"08",X"FE",X"C0",X"C3",X"7C",X"14",X"2A",X"1A",X"20", - X"22",X"BD",X"20",X"21",X"BB",X"20",X"34",X"21",X"16",X"46",X"11",X"16",X"20",X"06",X"07",X"C3", - X"8B",X"03",X"21",X"BB",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"BD",X"14",X"34",X"2A",X"BD", - X"20",X"11",X"CD",X"14",X"01",X"08",X"01",X"CD",X"76",X"03",X"C3",X"D5",X"01",X"AF",X"77",X"2B", - X"77",X"2A",X"BD",X"20",X"01",X"08",X"01",X"CD",X"76",X"03",X"C3",X"8C",X"08",X"A9",X"5C",X"BE", - X"7F",X"FE",X"7F",X"7E",X"95",X"32",X"00",X"20",X"3A",X"00",X"20",X"A7",X"D3",X"06",X"C2",X"D8", - X"14",X"C9",X"21",X"82",X"20",X"AF",X"BE",X"C8",X"3A",X"1A",X"20",X"D6",X"08",X"21",X"83",X"20", - X"BE",X"D0",X"C6",X"12",X"BE",X"D8",X"3A",X"1B",X"20",X"23",X"D6",X"03",X"BE",X"D0",X"C6",X"09", - X"BE",X"D8",X"2A",X"83",X"20",X"22",X"8D",X"20",X"CD",X"5B",X"0A",X"21",X"82",X"20",X"36",X"00", - X"21",X"8B",X"20",X"34",X"C9",X"21",X"82",X"20",X"AF",X"BE",X"C8",X"23",X"5E",X"23",X"56",X"EB", - X"E5",X"CD",X"5B",X"0A",X"E1",X"11",X"F9",X"FF",X"19",X"22",X"83",X"20",X"7D",X"FE",X"18",X"D2", - X"42",X"0A",X"22",X"87",X"20",X"21",X"85",X"20",X"36",X"FF",X"21",X"82",X"20",X"36",X"00",X"C9", - X"21",X"85",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"83",X"15",X"FE",X"04", - X"C2",X"59",X"15",X"11",X"24",X"44",X"C3",X"86",X"15",X"FE",X"07",X"D8",X"11",X"3C",X"44",X"CD", - X"86",X"15",X"21",X"00",X"00",X"22",X"81",X"20",X"22",X"85",X"20",X"CD",X"E0",X"15",X"21",X"88", - X"20",X"D2",X"7A",X"15",X"CD",X"E7",X"15",X"C3",X"7D",X"15",X"CD",X"07",X"16",X"21",X"14",X"20", - X"36",X"00",X"C9",X"11",X"0C",X"44",X"2A",X"87",X"20",X"CD",X"76",X"03",X"01",X"0C",X"02",X"C3", - X"D5",X"01",X"21",X"8B",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"CE",X"15", - X"FE",X"04",X"C2",X"AB",X"15",X"11",X"B4",X"44",X"C3",X"D1",X"15",X"FE",X"07",X"D8",X"2A",X"8D", - X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",X"22",X"8B",X"20", - X"21",X"81",X"20",X"36",X"00",X"CD",X"6F",X"1A",X"CD",X"D7",X"15",X"C3",X"7D",X"15",X"11",X"94", - X"44",X"2A",X"8D",X"20",X"C3",X"89",X"15",X"CD",X"E0",X"15",X"DA",X"ED",X"15",X"C3",X"0D",X"16", - X"CD",X"07",X"13",X"7E",X"0F",X"0F",X"C9",X"AF",X"3A",X"34",X"20",X"BE",X"D0",X"21",X"80",X"20", - X"34",X"7E",X"FE",X"03",X"DA",X"FF",X"15",X"36",X"00",X"3E",X"E8",X"2B",X"86",X"77",X"C9",X"FE", - X"02",X"3E",X"F0",X"DA",X"FB",X"15",X"C9",X"AF",X"3A",X"34",X"20",X"BE",X"D8",X"21",X"7E",X"20", - X"34",X"7E",X"FE",X"03",X"DA",X"1F",X"16",X"36",X"00",X"3E",X"15",X"2B",X"86",X"77",X"C9",X"FE", - X"02",X"3E",X"0D",X"DA",X"1B",X"16",X"C9",X"21",X"91",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E", - X"FE",X"01",X"CA",X"BA",X"16",X"FE",X"04",X"CA",X"C9",X"16",X"FE",X"07",X"D8",X"CD",X"CF",X"16", - X"21",X"00",X"00",X"22",X"91",X"20",X"CD",X"5F",X"1A",X"21",X"95",X"20",X"34",X"7E",X"FE",X"03", - X"D2",X"5E",X"16",X"3E",X"50",X"32",X"C2",X"20",X"CD",X"8C",X"02",X"C3",X"7D",X"15",X"CD",X"88", - X"16",X"21",X"C1",X"20",X"70",X"78",X"C6",X"20",X"CD",X"2E",X"03",X"2A",X"93",X"20",X"CD",X"76", - X"03",X"CD",X"45",X"03",X"11",X"34",X"04",X"CD",X"45",X"03",X"11",X"34",X"04",X"CD",X"45",X"03", - X"21",X"96",X"20",X"34",X"23",X"36",X"0A",X"C9",X"3A",X"01",X"20",X"0F",X"0F",X"06",X"03",X"0F", - X"D8",X"06",X"05",X"0F",X"D8",X"06",X"07",X"0F",X"D8",X"06",X"09",X"C9",X"21",X"96",X"20",X"AF", - X"BE",X"C8",X"23",X"BE",X"CA",X"A9",X"16",X"35",X"C9",X"CD",X"8C",X"02",X"01",X"18",X"01",X"CD", - X"D2",X"16",X"21",X"96",X"20",X"36",X"00",X"C3",X"7D",X"15",X"11",X"94",X"44",X"2A",X"93",X"20", - X"CD",X"76",X"03",X"01",X"10",X"02",X"C3",X"D5",X"01",X"11",X"B4",X"44",X"C3",X"BD",X"16",X"01", - X"10",X"02",X"2A",X"93",X"20",X"CD",X"76",X"03",X"C3",X"8C",X"08",X"21",X"81",X"20",X"AF",X"BE", - X"C0",X"CD",X"07",X"13",X"E5",X"7E",X"FE",X"FF",X"C2",X"ED",X"16",X"E1",X"C9",X"07",X"DA",X"F9", - X"16",X"E1",X"23",X"23",X"23",X"23",X"C3",X"E4",X"16",X"E1",X"E5",X"CD",X"40",X"0D",X"4D",X"44", - X"CD",X"E0",X"15",X"21",X"7F",X"20",X"DA",X"2F",X"17",X"2E",X"7D",X"7E",X"B8",X"D2",X"F1",X"16", - X"C6",X"04",X"B8",X"DA",X"F1",X"16",X"21",X"83",X"20",X"71",X"23",X"78",X"FE",X"30",X"DA",X"F1", - X"16",X"FE",X"F0",X"D2",X"F1",X"16",X"70",X"21",X"FF",X"FF",X"22",X"81",X"20",X"E1",X"C9",X"7E", - X"B8",X"D2",X"F1",X"16",X"C6",X"06",X"B8",X"DA",X"F1",X"16",X"C3",X"16",X"17",X"3A",X"AA",X"20", - X"A7",X"C8",X"21",X"A2",X"20",X"CD",X"F0",X"0D",X"CD",X"5D",X"17",X"21",X"AE",X"20",X"35",X"7E", - X"A7",X"C2",X"57",X"17",X"C3",X"82",X"17",X"21",X"A0",X"20",X"C3",X"A1",X"0D",X"7D",X"E6",X"07", - X"D3",X"02",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"23",X"13", - X"AF",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"65", - X"17",X"C9",X"2A",X"A8",X"20",X"EB",X"1A",X"2A",X"AF",X"20",X"2D",X"CA",X"BA",X"17",X"22",X"AF", - X"20",X"32",X"AE",X"20",X"13",X"1A",X"E6",X"0F",X"07",X"01",X"BF",X"17",X"26",X"00",X"6F",X"09", - X"E5",X"C1",X"21",X"A0",X"20",X"0A",X"77",X"03",X"23",X"0A",X"77",X"13",X"1A",X"6F",X"13",X"1A", - X"67",X"22",X"A2",X"20",X"EB",X"23",X"22",X"A8",X"20",X"C9",X"AF",X"32",X"AA",X"20",X"C9",X"00", - X"02",X"02",X"02",X"02",X"00",X"02",X"FE",X"00",X"FE",X"FE",X"FE",X"FE",X"00",X"FE",X"02",X"01", - X"02",X"02",X"01",X"02",X"FF",X"01",X"FE",X"FF",X"FE",X"FE",X"FF",X"FE",X"01",X"FF",X"02",X"FF", - X"FF",X"24",X"06",X"D7",X"30",X"10",X"00",X"D7",X"30",X"04",X"07",X"D7",X"50",X"0A",X"06",X"CF", - X"58",X"04",X"05",X"BC",X"58",X"04",X"07",X"B4",X"50",X"0A",X"06",X"AC",X"58",X"04",X"05",X"98"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04 deleted file mode 100644 index 2097c45c..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04 and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd deleted file mode 100644 index de61c21a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn04 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn04 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"58",X"10",X"00",X"90",X"31",X"0C",X"06",X"D0",X"38",X"08",X"00",X"D0",X"38",X"08",X"00",X"D0", - X"38",X"04",X"07",X"D0",X"48",X"05",X"06",X"C8",X"50",X"04",X"05",X"BE",X"4E",X"08",X"00",X"B8", - X"38",X"0C",X"06",X"B0",X"38",X"08",X"00",X"B0",X"38",X"04",X"07",X"B0",X"48",X"05",X"06",X"A8", - X"50",X"04",X"05",X"9E",X"4E",X"08",X"00",X"98",X"38",X"0C",X"09",X"90",X"59",X"0C",X"0E",X"A6", - X"67",X"08",X"00",X"98",X"60",X"0B",X"06",X"A6",X"78",X"0A",X"00",X"90",X"78",X"0B",X"06",X"A6", - X"90",X"0A",X"00",X"90",X"90",X"0C",X"06",X"A6",X"A8",X"0A",X"00",X"A6",X"A8",X"0C",X"06",X"A6", - X"BC",X"0B",X"00",X"90",X"A8",X"0C",X"06",X"A6",X"C0",X"0A",X"00",X"A6",X"C0",X"0C",X"06",X"A6", - X"D4",X"0B",X"00",X"90",X"C0",X"0C",X"06",X"A6",X"D8",X"0C",X"07",X"A6",X"D8",X"0C",X"06",X"A6", - X"F0",X"00",X"00",X"00",X"00",X"92",X"18",X"01",X"04",X"E1",X"17",X"00",X"00",X"00",X"00",X"00", - X"17",X"00",X"1E",X"1E",X"1E",X"1E",X"FF",X"FF",X"FF",X"FF",X"36",X"00",X"CD",X"DC",X"18",X"3E", - X"04",X"CD",X"FB",X"01",X"2A",X"33",X"20",X"CD",X"76",X"03",X"0E",X"05",X"E5",X"C5",X"11",X"D0", - X"19",X"D5",X"06",X"02",X"C5",X"E5",X"01",X"12",X"02",X"CD",X"D5",X"01",X"3E",X"05",X"CD",X"D5", - X"14",X"E1",X"C1",X"05",X"C2",X"B4",X"18",X"D1",X"C1",X"E1",X"0D",X"C2",X"AC",X"18",X"01",X"12", - X"02",X"CD",X"8C",X"08",X"CD",X"C1",X"00",X"3E",X"04",X"C3",X"04",X"02",X"21",X"2F",X"20",X"36", - X"00",X"2E",X"14",X"36",X"00",X"C9",X"3A",X"17",X"20",X"A7",X"3E",X"02",X"C2",X"FB",X"01",X"C3", - X"04",X"02",X"3A",X"1D",X"20",X"A7",X"3E",X"01",X"C3",X"EC",X"18",X"3A",X"27",X"20",X"A7",X"3E", - X"08",X"C3",X"EC",X"18",X"3A",X"91",X"20",X"A7",X"3E",X"08",X"C3",X"EC",X"18",X"3E",X"DF",X"CD", - X"04",X"02",X"3E",X"DF",X"C3",X"17",X"02",X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"54",X"20",X"A7", - X"3E",X"01",X"C2",X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C",X"CD", - X"47",X"0B",X"CD",X"17",X"19",X"C3",X"92",X"15",X"CD",X"C2",X"07",X"CD",X"95",X"19",X"D8",X"CD", - X"81",X"09",X"CD",X"F1",X"0E",X"CD",X"4B",X"19",X"C3",X"A2",X"14",X"CD",X"5A",X"19",X"21",X"34", - X"20",X"7E",X"2E",X"7F",X"BE",X"D8",X"C6",X"08",X"77",X"C9",X"21",X"34",X"20",X"7E",X"2E",X"7D", - X"BE",X"D0",X"D6",X"08",X"77",X"C9",X"CD",X"79",X"19",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C", - X"CD",X"9C",X"09",X"CD",X"DB",X"16",X"C3",X"6C",X"0F",X"3A",X"05",X"20",X"A7",X"3E",X"04",X"C2", - X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"BC",X"09",X"CD",X"E2",X"0F",X"CD", - X"56",X"0D",X"C3",X"9C",X"16",X"3A",X"7B",X"20",X"0F",X"C9",X"CD",X"71",X"03",X"C5",X"E5",X"1A", - X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"AD",X"19",X"3E",X"01",X"32",X"11",X"20",X"DB",X"03",X"AE", - X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"C1",X"19",X"3E",X"01",X"32",X"11", - X"20",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"9D",X"19",X"C9", - X"00",X"00",X"07",X"00",X"00",X"00",X"42",X"00",X"00",X"00",X"15",X"02",X"11",X"49",X"8F",X"00", - X"EF",X"05",X"2F",X"08",X"D1",X"21",X"1D",X"20",X"00",X"00",X"17",X"00",X"09",X"11",X"07",X"00", - X"07",X"00",X"47",X"00",X"00",X"02",X"21",X"40",X"49",X"10",X"05",X"00",X"00",X"80",X"01",X"08", - X"09",X"40",X"07",X"00",X"03",X"00",X"01",X"00",X"49",X"02",X"49",X"44",X"00",X"80",X"09",X"02", - X"00",X"40",X"87",X"08",X"02",X"00",X"03",X"00",X"DB",X"02",X"E6",X"03",X"21",X"27",X"21",X"F5", - X"86",X"77",X"F1",X"2E",X"27",X"26",X"22",X"86",X"77",X"C9",X"CD",X"44",X"1A",X"7E",X"3D",X"C8", - X"4F",X"21",X"01",X"25",X"11",X"26",X"40",X"C5",X"01",X"10",X"01",X"CD",X"D5",X"01",X"C1",X"0D", - X"C2",X"34",X"1A",X"C9",X"CD",X"52",X"1A",X"2E",X"27",X"7E",X"C9",X"CD",X"52",X"1A",X"2E",X"25", - X"7E",X"C9",X"3A",X"DB",X"20",X"0F",X"DA",X"5C",X"1A",X"26",X"21",X"C9",X"26",X"22",X"C9",X"3E", - X"50",X"32",X"C2",X"20",X"C3",X"8C",X"02",X"3E",X"01",X"32",X"C1",X"20",X"C3",X"8C",X"02",X"21", - X"01",X"50",X"22",X"C1",X"20",X"C3",X"8C",X"02",X"21",X"29",X"09",X"11",X"36",X"21",X"06",X"06", - X"C3",X"8B",X"03",X"21",X"2F",X"09",X"C3",X"7B",X"1A",X"21",X"12",X"20",X"AF",X"BE",X"3E",X"10", - X"CA",X"04",X"02",X"35",X"C3",X"FB",X"01",X"21",X"E9",X"20",X"3A",X"DB",X"20",X"0F",X"D0",X"23", - X"C9",X"CD",X"97",X"1A",X"AF",X"BE",X"C8",X"CD",X"52",X"1A",X"21",X"C4",X"20",X"D2",X"B2",X"1A", - X"2E",X"C7",X"7E",X"06",X"15",X"B8",X"D8",X"CD",X"44",X"1A",X"34",X"CD",X"2A",X"1A",X"CD",X"97", - X"1A",X"36",X"00",X"21",X"12",X"20",X"36",X"50",X"C9",X"FE",X"FF",X"CA",X"25",X"1B",X"FE",X"FE", - X"CA",X"1A",X"1B",X"21",X"3B",X"21",X"36",X"80",X"23",X"77",X"23",X"EB",X"21",X"5D",X"1B",X"87", - X"4F",X"06",X"00",X"09",X"7E",X"23",X"66",X"6F",X"C3",X"F9",X"1A",X"3A",X"3B",X"21",X"A7",X"C8", - X"21",X"3D",X"21",X"35",X"C0",X"EB",X"2A",X"3E",X"21",X"7E",X"A7",X"CA",X"25",X"1B",X"FE",X"FF", - X"CA",X"14",X"1B",X"12",X"23",X"7E",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"08",X"1B",X"23", - X"22",X"3E",X"21",X"C9",X"3A",X"3C",X"21",X"F2",X"D3",X"1A",X"3E",X"01",X"32",X"3D",X"21",X"3E", - X"80",X"32",X"3B",X"21",X"C9",X"3E",X"FF",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"29",X"1B", - X"AF",X"32",X"3B",X"21",X"C9",X"21",X"39",X"21",X"7E",X"3D",X"77",X"C0",X"2B",X"7E",X"23",X"77", - X"23",X"7E",X"A7",X"C2",X"49",X"1B",X"C3",X"EB",X"1A",X"3A",X"36",X"21",X"CD",X"C9",X"1A",X"AF", - X"32",X"3A",X"21",X"C9",X"AF",X"32",X"37",X"21",X"3C",X"32",X"3A",X"21",X"C9",X"08",X"45",X"9C", - X"45",X"C6",X"45",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1 deleted file mode 100644 index a52cdde5..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1 and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd deleted file mode 100644 index 0efc0ad1..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn05_1 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn05_1 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"01",X"01",X"00",X"00",X"02",X"02",X"01",X"00",X"01",X"02",X"02",X"02",X"02",X"00",X"00",X"01", - X"01",X"00",X"00",X"00",X"06",X"0E",X"0E",X"03",X"15",X"04",X"11",X"18",X"1B",X"1B",X"05",X"08", - X"0D",X"04",X"13",X"08",X"0B",X"13",X"00",X"00",X"07",X"07",X"02",X"1C",X"8B",X"77",X"8B",X"1C", - X"02",X"07",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0", - X"00",X"70",X"00",X"30",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C", - X"00",X"3E",X"00",X"BE",X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD", - X"C0",X"DC",X"00",X"9E",X"00",X"9E",X"00",X"1E",X"00",X"04",X"00",X"38",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0",X"00",X"70",X"00",X"30", - X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"3E",X"00",X"BE", - X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD",X"C0",X"DC",X"00",X"9E", - X"00",X"9E",X"00",X"1E",X"00",X"04",X"80",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38", - X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0",X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C", - X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00",X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C", - X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00",X"70",X"00",X"F0",X"00",X"38",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"80",X"03",X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0", - X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00", - X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00", - X"70",X"00",X"F0",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"30",X"00",X"80",X"1B",X"00",X"C0",X"FF",X"00",X"C0", - X"67",X"00",X"C0",X"0B",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"10", - X"1E",X"00",X"10",X"3F",X"00",X"90",X"7F",X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF", - X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"80", - X"01",X"00",X"80",X"07",X"00",X"80",X"03",X"00",X"F0",X"00",X"00",X"78",X"01",X"00",X"78",X"02", - X"1E",X"38",X"04",X"3F",X"38",X"88",X"7F",X"00",X"D0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF", - X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"40",X"02",X"00",X"C0",X"01",X"00",X"C0",X"00", - X"1E",X"40",X"00",X"3F",X"F0",X"81",X"7F",X"78",X"C6",X"FF",X"78",X"D8",X"FF",X"38",X"E0",X"FF", - X"38",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"00",X"00",X"34",X"00", - X"1E",X"34",X"00",X"3F",X"3C",X"80",X"7F",X"3C",X"C0",X"FF",X"18",X"C0",X"FF",X"F8",X"FF",X"FF", - X"1C",X"C0",X"FF",X"3C",X"C0",X"FF",X"3C",X"80",X"7F",X"38",X"00",X"3F",X"10",X"00",X"1E",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"20",X"E0",X"FF", - X"24",X"D8",X"FF",X"38",X"C6",X"FF",X"B0",X"81",X"7F",X"60",X"00",X"3F",X"E0",X"00",X"1E",X"E0", - X"00",X"00",X"E0",X"01",X"00",X"E0",X"01",X"00",X"C0",X"01",X"00",X"80",X"01",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF", - X"00",X"E0",X"FF",X"00",X"D0",X"FF",X"40",X"88",X"7F",X"40",X"04",X"3F",X"40",X"02",X"1E",X"F8", - X"01",X"00",X"E0",X"00",X"00",X"80",X"03",X"00",X"80",X"07",X"00",X"00",X"07",X"00",X"00",X"07", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"1E",X"00",X"00",X"3F",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF", - X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"00",X"90",X"7F",X"00",X"10",X"3F",X"00",X"10",X"1E",X"00", - X"08",X"00",X"00",X"08",X"00",X"80",X"05",X"00",X"00",X"0B",X"00",X"00",X"06",X"00",X"C0",X"7F", - X"00",X"00",X"FB",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"00", - X"1F",X"00",X"1F",X"00",X"06",X"00",X"F2",X"00",X"2D",X"C0",X"DE",X"7F",X"DE",X"7F",X"2D",X"C0", - X"F2",X"00",X"06",X"00",X"1F",X"00",X"1F",X"00",X"15",X"00",X"DE",X"3F",X"DE",X"7C",X"7C",X"7C", - X"12",X"02",X"0E",X"11",X"04",X"1C",X"21",X"1B",X"1B",X"07",X"08",X"1C",X"12",X"02",X"0E",X"11", - X"04",X"1B",X"1B",X"12",X"02",X"0E",X"11",X"04",X"1C",X"22",X"00",X"00",X"03",X"30",X"03",X"30", - X"1D",X"26",X"1D",X"29",X"1D",X"2F",X"05",X"23",X"1D",X"26",X"00",X"00",X"7F",X"04",X"0F",X"03", - X"83",X"40",X"01",X"38",X"11",X"0C",X"01",X"00",X"01",X"01",X"03",X"8C",X"07",X"1A",X"0F",X"40", - X"0F",X"20",X"9F",X"0C",X"FF",X"00",X"1F",X"00",X"0F",X"20",X"27",X"00",X"07",X"00",X"13",X"04", - X"03",X"00",X"07",X"00",X"13",X"01",X"07",X"20",X"1F",X"00",X"7F",X"00",X"7F",X"00",X"3F",X"00", - X"0F",X"00",X"01",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"07",X"00",X"0F",X"00", - X"3F",X"00",X"7F",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"A4",X"04",X"00",X"10", - X"C8",X"54",X"E0",X"1B",X"E0",X"03",X"8C",X"01",X"20",X"12",X"00",X"0C",X"30",X"11",X"00",X"00", - X"00",X"00",X"00",X"00",X"0C",X"C0",X"07",X"F1",X"0F",X"11",X"56",X"00",X"82",X"21",X"08",X"45", - X"0A",X"00",X"A0",X"63",X"B0",X"42",X"40",X"01",X"04",X"00",X"0E",X"70",X"4A",X"78",X"03",X"31", - X"0B",X"C0",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"A0",X"13",X"C8",X"04", - X"E0",X"01",X"50",X"07",X"A0",X"1E",X"C0",X"0B",X"C0",X"02",X"88",X"10",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"10",X"90",X"1C",X"38",X"48",X"21",X"04",X"8C",X"20", - X"18",X"40",X"08",X"08",X"24",X"00",X"20",X"1C",X"14",X"48",X"68",X"20",X"22",X"01",X"00",X"0B", - X"08",X"43",X"00",X"00",X"0F",X"0B",X"00",X"18",X"04",X"11",X"1B",X"1E",X"1B",X"1F",X"1B",X"06", - X"00",X"0C",X"04",X"1B",X"0E",X"15",X"04",X"11",X"C3",X"01",X"C2",X"04",X"C3",X"05",X"C2",X"06", - X"C3",X"02",X"C2",X"03",X"FF",X"FF",X"FF",X"FF",X"C1",X"02",X"C0",X"05",X"C1",X"06",X"C0",X"01", - X"C1",X"03",X"C0",X"04",X"FF",X"FF",X"FF",X"FF",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC", - X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7", - X"02",X"DD",X"02",X"FF",X"02",X"E1",X"02",X"FF",X"06",X"E1",X"02",X"FF",X"02",X"DD",X"01",X"FF", - X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC", - X"01",X"FF",X"01",X"D7",X"02",X"D2",X"02",X"FF",X"02",X"DD",X"02",X"FF",X"06",X"B9",X"02",X"FF", - X"02",X"DD",X"01",X"FF",X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"01",X"FF", - X"01",X"D7",X"02",X"CC",X"01",X"FF",X"01",X"D7",X"02",X"DD",X"02",X"FF",X"02",X"E1",X"02",X"FF", - X"06",X"E4",X"02",X"FF",X"02",X"E6",X"02",X"FF",X"01",X"E4",X"01",X"E1",X"01",X"DD",X"01",X"D9", - X"02",X"D7",X"01",X"FF",X"01",X"D2",X"02",X"CC",X"01",X"FF",X"01",X"C9",X"02",X"CC",X"02",X"FF", - X"02",X"E6",X"02",X"FF",X"03",X"CC",X"06",X"FF",X"FF",X"00",X"00",X"00",X"04",X"D9",X"02",X"D7", - X"01",X"FF",X"01",X"D9",X"01",X"D2",X"01",X"FF",X"04",X"D9",X"01",X"DD",X"01",X"FF",X"01",X"DF", - X"01",X"FF",X"01",X"E1",X"01",X"FF",X"01",X"E2",X"01",X"FF",X"01",X"E4",X"01",X"FF",X"02",X"E6", - X"07",X"FF",X"FF",X"00",X"00",X"00",X"01",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"18",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"C8",X"D0",X"00",X"00",X"02",X"1B", - X"00",X"00",X"00",X"FD",X"00",X"00",X"00",X"00",X"04",X"00",X"FD",X"00",X"00",X"00",X"00",X"08", - X"00",X"FD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"E8", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"B1",X"46",X"10",X"02",X"E1",X"17",X"00",X"00",X"00",X"00",X"00",X"29", - X"00",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1D",X"25", - X"1D",X"38",X"1D",X"2E",X"00",X"00",X"00",X"00",X"C5",X"26",X"01",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"FF",X"FF",X"FF",X"FF",X"C3",X"01",X"18",X"27",X"C2",X"04",X"18",X"2D",X"C3",X"05",X"18",X"33", - X"C2",X"06",X"18",X"39",X"C3",X"02",X"18",X"3F",X"C2",X"03",X"18",X"45",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06 deleted file mode 100644 index 2000072a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06 +++ /dev/null @@ -1 +0,0 @@ -                                                                                                                    \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd deleted file mode 100644 index 0715686a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd +++ /dev/null @@ -1,86 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn06 is -port ( - clk : in std_logic; - addr : in std_logic_vector(9 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn06 is - type rom is array(0 to 1023) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07 b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07 deleted file mode 100644 index 7d88e647..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07 +++ /dev/null @@ -1 +0,0 @@ -                                                                                                                 \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd deleted file mode 100644 index 580a92a7..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd +++ /dev/null @@ -1,86 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity tn07 is -port ( - clk : in std_logic; - addr : in std_logic_vector(9 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of tn07 is - type rom is array(0 to 1023) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", - X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D", - X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D", - X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf deleted file mode 100644 index 9f69ea50..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "BlueShark" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf deleted file mode 100644 index 981a7773..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf +++ /dev/null @@ -1,172 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 15:17:52 June 06, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# BlueShark_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_memory.sv -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/BlueShark_Overlay.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY BlueShark_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ---------------------------- -# start ENTITY(BlueShark_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(BlueShark_mist) -# -------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt deleted file mode 100644 index 07c9cf12..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Blue Shark port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- -ToDo: Color Prom - Controls + DIP - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf deleted file mode 100644 index 5eec0415..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/Snapshot/BlueShark.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf deleted file mode 100644 index efc34017..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/doc/Blue_Shark_-_1978_-_Midway_Games.pdf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd deleted file mode 100644 index 627256ff..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd +++ /dev/null @@ -1,112 +0,0 @@ ---Blue Shark Color Overlay Gehstock 2019 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity BlueShark_Overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - AD : in std_logic_vector(15 downto 0); - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end BlueShark_Overlay; - -architecture rtl of BlueShark_Overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_B1 : boolean; - signal Overlay_B1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); - signal col_data : std_logic_vector(3 downto 0); - signal col_addr : std_logic_vector(9 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_B1_VCnt <= false; - Overlay_B1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt>= x"28") and (Vcnt <= x"35") then--Top Start - Overlay_B1_VCnt <= true; - else - Overlay_B1_VCnt <= false; - end if; - end if; - - if (HCnt <= x"0") and Overlay_B1_VCnt then--Left Start - Overlay_B1 <= true; - elsif (HCnt >= x"228") then--Right End - Overlay_B1 <= false; - end if; - end if; - end process; - - p_video_out_comb : process(Video, Overlay_B1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_B1 then - VideoRGB <= "001"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv deleted file mode 100644 index 59940ca0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv +++ /dev/null @@ -1,68 +0,0 @@ -module BlueShark_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; - - -sprom #( - .init_file("./roms/blueshrk_h.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/blueshrk_g.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/blueshrk_f.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - - -always @(Addr, rom_data_0, rom_data_1, rom_data_2) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv deleted file mode 100644 index 14647137..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv +++ /dev/null @@ -1,214 +0,0 @@ -module BlueShark_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "BlueShark;;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v0.00.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; -/*Dip Switch:SW -1 2 3 4 5 6 7 8 Function Option -Unused - Off* - On -Unused - Off* - On -Replay - Off On 14000 - On Off* 18000* - Off Off 22000 - On On None -*/ - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP("00000000"), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -BlueShark_memory BlueShark_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -BlueShark_Overlay BlueShark_Overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .AD(AD), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_left = btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd deleted file mode 100644 index e362f4b0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,243 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(7 downto 0); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '1'; -- Unused - GDB0(1) <= '1'; -- Unused - GDB0(2) <= '1'; -- Unused - GDB0(3) <= '1'; -- Unused - GDB0(4) <= '1'; -- Unused - GDB0(5) <= '1'; -- Unused - GDB0(6) <= '1'; -- Unused - GDB0(7) <= '1'; -- Unused - - GDB1(0) <= '1'; -- PADDLE - GDB1(1) <= '1'; -- PADDLE - GDB1(2) <= '1'; -- PADDLE - GDB1(3) <= '1'; -- PADDLE - GDB1(4) <= '1'; -- PADDLE - GDB1(5) <= '1'; -- PADDLE - GDB1(6) <= '1'; -- PADDLE - GDB1(7) <= '0'; -- PADDLE - - GDB2(0) <= not Fire; - GDB2(1) <= not Coin; - GDB2(2) <= '1'; -- unknown - GDB2(3) <= '1'; -- TILT - GDB2(4) <= '1'; -- unknown - GDB2(5) <= '1'; -- Replay - GDB2(6) <= '1'; -- Replay - GDB2(7) <= '1'; -- TEST - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd deleted file mode 100644 index 1d9ad578..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,335 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex deleted file mode 100644 index 557f06b1..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000066667E3C181C1818181818183C3C3C7E74 -:1000100066607C3E06067E7E3C7E66603878606662 -:100020007E3C666666667E7E606060603E3E06067A -:100030003E7E60667E3C3C3E06063E7E66667E3CBC -:100040007E7E60703038181C0C0C3C7E66663C7EF0 -:1000500066667E3C3C7E66667E7C60667E3C00001A -:100060000000000000000000183C7E6666667E7E90 -:1000700066663E7E66663E7E66667E3E3C7E6606C2 -:10008000060606667E3C3E7E6666666666667E3E62 -:100090007E7E06063E3E06067E7E7E7E06063E3E50 -:1000A000060606063C7E6606067676667E3C666634 -:1000B00066667E7E666666663C3C181818181818D8 -:1000C0003C3C60606060606060667E3C6666763E78 -:1000D0001E1E3E76666606060606060606067E7E38 -:1000E000C3C3E7E7FFFFDBC3C3C366666E6E7E7EF6 -:1000F000767666663E7E66667E3E060606063C7E32 -:100100006666666666767E5C3E7E66667E3E766681 -:1001100066663C7E66063E7C60667E3C7E7E181887 -:1001200018181818181866666666666666667E3C55 -:1001300066666666667E3C3C1818C3C3C3DBFFFF79 -:10014000E7E7C3C366667E3C18183C7E6666666653 -:100150007E3C1818181818187E7E6070381C0E0621 -:100160007E7E3C7E6666703818001818000000001D -:100170003C3C00000000050D0000C000000100F83C -:1001800001000300FF030086E0FF0F000CFFFF7F6C -:1001900000FCFFFFDF01F8FFFFFFFF18FFFF7F00FC -:1001A0008C01FFFF00068001060003000002000131 -:1001B000000001000000800000050D00008001002B -:1001C0004000F003004000FE070040C4FF1F00C0D5 -:1001D000F8FF7F0080FFFFDF0180FFFFFFFFC0F817 -:1001E000FFFF004008FCFF014000060C0040000239 -:1001F000060000000003000000000000041E0001D3 -:1002000000000000000000000000000000000000EE -:10021000000000400000000000000000000000009E -:1002200000000000000000000000000000000000CE -:100230000E0000FC1E0000CC1E0000301E0000FE60 -:100240000F0000F7C77F00FF6F0280F71F07800FC6 -:10025000FC03C107F800FF030000FF010000FF00DE -:10026000000001000000010000000100000001008A -:10027000000000000000041E00000000000000005C -:10028000000000000004000000000000000000006A -:10029000000000000000010000400000000000001D -:1002A000000002000000000000001C0000F83D00FB -:1002B00000983D0004603C000EFC1F001EEE8FFF06 -:1002C0003BFFDF04F1EF3F0EE11FF807C003F00131 -:1002D0008000000020000000700000001C000000F2 -:1002E0000C000000040000000400000004000000F6 -:1002F00002118003C007E007E007A006E0036003E7 -:10030000C0018003C007F60FEC5BB073D8064E0C3B -:100310004238C000021100008007C00FE00F400FFC -:10032000F00FF0C78483CCC7F06FD83BED06A74D24 -:1003300030791003180E0000021500002000200084 -:1003400038003C0060006001C000C000C000C00177 -:10035000C001D009700D200740034001C001C0005A -:10036000C001800102150001000100010007800F9B -:10037000A001C000C000C000E000E000E402AC0347 -:100380003801B000A000E000C000E0006000000004 -:1003900002158001C001C000C001400140032007D8 -:1003A000700DD009C001C001C000C000C0006001D4 -:1003B00060003C0038002000200000000215000012 -:1003C0006000E000C000E000A000B0003801AC0315 -:1003D000E402E000E000C000C000C000A001800F07 -:1003E0000007000100010001040C000008000100EA -:1003F00018000300380006007C008CC0FF071CFFBB -:10040000FF3FF8FFFFDFF8FFFFFF0C81DF3F06C073 -:10041000C0000000600000003000040C000010006C -:1004200000003000200070002000F8002084FF0F42 -:1004300060FCFF3FC0FFFFDFC0FFFFFF6004BF1F86 -:10044000200081012000C0000000400003100000D7 -:10045000E00000F800F0BF00E07F00C01F00E00FE8 -:1004600000F809047F080C5E00980700F005007092 -:1004700000002000002000002000002000000310E9 -:10048000080000180000300000600000C00402F006 -:100490000502001F03007E0300F90300E00700F0DF -:1004A0001F00803F00007E0000FF0080D90000E0B8 -:1004B000040B0000080060001800C0003800800134 -:1004C00078000013FC0300FFFF3F00FFFFDF8013F5 -:1004D000FF7FC08000030000800100008000011346 -:1004E0000814080808080808080808080808080880 -:1004F000080808011008140808080808080808086F -:100500000808080808010D08000808080808080875 -:1005100008080808010A0800080808080808080868 -:10052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB -:10053000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB -:10054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB -:10055000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAB -:10056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B -:10057000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8B -:10058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B -:10059000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6B -:1005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B -:1005B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4B -:1005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B -:1005D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2B -:1005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B -:1005F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0B -:10060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA -:10061000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA -:10062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA -:10063000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA -:10064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA -:10065000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA -:10066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A -:10067000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A -:10068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A -:10069000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A -:1006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A -:1006B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A -:1006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A -:1006D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A -:1006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A -:1006F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A -:10070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9 -:10071000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9 -:10072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9 -:10073000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9 -:10074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9 -:10075000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA9 -:10076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99 -:10077000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF89 -:10078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79 -:10079000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF69 -:1007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59 -:1007B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF49 -:1007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39 -:1007D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF29 -:1007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19 -:1007F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF09 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex deleted file mode 100644 index 8923d41f..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000A7F2050837171213230605CD7D0F21022D -:1000100021CD930DC83A3620A7C8AF323620210132 -:10002000217EE6F0F60677C90606C30B08CD860FDB -:10003000210221E6014F3A2020CA5D08A7F24508B7 -:100040003606C3470836032B7881C24F08F60447AB -:100050007EE6F0B0772B36022323C31108A7F266A1 -:100060000836F9C3470836FCC347083A3620A713B9 -:10007000EBCA7D08CD9D0DCA8008C32209CD8D0D28 -:100080003A0121E603475F160021F508195E235661 -:100090003A0421BBDAD208BAD22D083A0121E6404F -:1000A0003A0621CAB708FE76C2B10821B911C3C504 -:1000B00008217611C3C508FEFCC2C208217612C30E -:1000C000C50821FC1122062121002136012323C36A -:1000D000110805C32D0801E103001082761101B15A -:1000E00003001080FC1101E3FC00C882761101B30B -:1000F000FC00C880FC11104890C83A3620A713EBCA -:10010000CA0C09CD9D0DCA0F09C32209CD8D0DCD95 -:10011000860FF60FE67F6F2680220021C913EBCDF4 -:100120008D0DAF3236202A0421CD2F0E222B203EFA -:10013000FF3238203E043232203A0121E640CA9E86 -:10014000092100213601237EE6F7F6077723CD8DBE -:100150000D0604C3F30C13EBCD8D0D21322035CAEF -:1001600080093A0621FE76C2700921B911C37309CC -:1001700021761122062121002136012323C38D0D72 -:10018000AF3238202100213606237EE640CA92098C -:100190003EFFF6803226207EE6F0F60577C906108F -:1001A000CDF30CC3800906EBCDFF0C1AE640CAB3B1 -:1001B000093EFFF680322520211080220021C90649 -:1001C00020CDF30C3A22203223202101612210217C -:1001D000210000221221CD860FE60E4F06002107D6 -:1001E0000A091114217E1213237E1221F012221605 -:1001F00021211221CD930DC83A3620A7C8AF32363F -:10020000203E63321121C910E820D028D870B08078 -:10021000D0A0E8C0A0E0E006DFCDFF0C3A3620A772 -:1002200013EBCA2E0ACD9D0DCA310AC3660ACD8DC5 -:100230000D3A23203D322320CA5A0A3E01321021B2 -:100240003A1621FEF0C24E0A211413C3510A21F0BE -:1002500012221621211221C3F409210200221021A9 -:10026000C913EBCD8D0DAF3236202A1421CD2F0EC0 -:10027000222F203EFF3238203E043234202110212C -:10028000360123360423CD8D0D0604CDF30C06DF95 -:10029000C3FF0C13EBCD8D0D21342035CABD0A3AB6 -:1002A0001621FEF0C2AD0A211413C3B00A21F012C8 -:1002B00022162121102136012323C38D0DAF3238A0 -:1002C000203EFF322A20210602221021C906FBCD42 -:1002D000FF0C3EFF322920210400221021C9060212 -:1002E000CDF30C3EFF323720211C213A3920D608AD -:1002F00087772336FD211D20360023360421DE14A6 -:10030000221E212101012218212100F4221A21217B -:100310001A21CD930DAF323520323620C913EBCDE3 -:100320009D0DCA360B3A1D21FEECD2360B211A2147 -:10033000CD8D0DC36F0B211E2035C25C0B2B7EFEB5 -:1003400003D2990B3C77878623EBC6B46F3E00CE71 -:100350000B677E12235E2356EB221E212101012210 -:100360001821211A21CD930DC83A1D21FEECD03E53 -:10037000FF323620210202221821C93A3620A7CAAC -:10038000890B210104221821C92101032218213AD5 -:100390003820A7C013EBCD8D0DAF32362032372079 -:1003A00021000022182106FDC3FF0C13EBCD8D0D9B -:1003B000AF323620C3360B04F314040515041415AC -:1003C000E5C3CA0BE5010400CD3E0C11E50F2A2F51 -:1003D00020CD080DE1AF77C9E57EE67FC2FE0B11A7 -:1003E000E90FC3010CE57EE67FC2F80B019509CD4C -:1003F000780C11E90FC3010C010200CD3E0C11D99C -:100400000F2A2B20CD080DE1AF77C9E57EE67FCA24 -:10041000310C11E10FC3340CE57EE67FCA2B0C01D1 -:100420000500CD3E0C11E10FC3340C010300CD3E9D -:100430000C11DD0F2A2D20CD080DE1AF77C9C511B4 -:100440000F2021D5253E03CD0A0DC1111120213FDA -:10045000207E812777F54FE60F121B790F0F0F0FC4 -:10046000E60F121B23F17E8827E60F1277110F206B -:1004700021D5253E03C30A0DC5110F2021D5253EE8 -:1004800003CD0A0DC1111120213F207E812777F570 -:100490004FE60F121B790F0F0F0FE60F121B23F100 -:1004A0007E88277712E6F0CABA0C7EE60F12771123 -:1004B0000F2021D5253E03C30A0DAF772B771213EA -:1004C000121312C3AF0CCD630F119C0F214324CD27 -:1004D000080D110A2021C6253E05CD0A0D11142054 -:1004E00021CF253E02CD0A0D110F2021D5253E0535 -:1004F000C30A0D2141207E0FD007B077D303C92155 -:1005000041207EA077D303C91A13F5D5CD770DE529 -:10051000060A1AF3AE77FBC501200009C11305C214 -:10052000120DE123D113F13DC20A0DC91A13F5D5FD -:10053000CD770D060AC51AD5010300E5210000118B -:100540000800292907D2490D091DC2420DEB011FE0 -:1005500000E17BF3AE77237AAE77097BAE77237A1F -:10056000AE77FB09D113C105C2350D0182FD09D15A -:1005700013F13DC22E0DC9E51A6F260029292987DE -:10058000856F7CCE006701FA0F09EBE1C9CDF00D54 -:10059000C31A0FAF323520CDA70DC3AB0EAF323526 -:1005A00020CDF00DC3420E7EF5234623A7F2D30DD6 -:1005B0003C86775F2FD3012378867757EBCD2F0EBC -:1005C000EBD5235E2356EB4E793D835F234623D143 -:1005D000EBF1C986775FD3012378867757EBCD2F70 -:1005E0000EEBD5235E2356EB4E234623D1EBF1C908 -:1005F0007EF52323A7F2160E7E5F2FD3012356EB41 -:10060000CD2F0EEBD5235E2356EB4E793D835F2332 -:100610004623D1EBF1C97E5FD3012356EBCD2F0EDC -:10062000EBD5235E2356EB4E234623D1EBF1C906CF -:10063000037C1F677D1F6F05C2310E7CE63FF620ED -:1006400067C9A7FA770EC5E51AD302DB03AE77DBDD -:1006500003A6C4140F13230DC2480EAFD302DB034D -:10066000AE77DB03A6C4140F012000E109C105C267 -:10067000460E3A3520A7C97D816FC5E51AD302DB46 -:1006800000AE77DB00A6C4140F132B0DC27C0EAF97 -:10069000D302DB00AE77DB00A6C4140F012000E11B -:1006A00009C105C27A0E3A3520A7C9A7FAE00EC5DE -:1006B000E51AD302DB03A6C4140FDB03AE771323C2 -:1006C0000DC2B10EAFD302DB03A6C4140FDB03AE21 -:1006D00077012000E109C105C2AF0E3A3520A7C954 -:1006E0007D816FC5E51AD302DB00A6C4140FDB00C1 -:1006F000AE77132B0DC2E50EAFD302DB00A6C414F8 -:100700000FDB00AE77012000E109C105C2E30E3A1C -:100710003520A7C93EFF323520C9A7FA3F0FC5E5EE -:100720001AD302DB03AE7713230DC2200FAFD3021F -:10073000DB03AE77012000E109C105C21E0FC97DB0 -:10074000816FC5E51AD302DB00AE77132B0DC244CF -:100750000FAFD302DB00AE77012000E109C105C273 -:10076000420FC92100240120E0C5E53600230DC257 -:100770006B0FE101200009C105C2690FC97E121388 -:100780002305C27D0FC9E52A0520291717AD17AD2E -:100790001F1F2FE601B56F220520E1C9171213258F -:1007A0001C0D001B0F0A0A0A1D13170F0A0A0A1C48 -:1007B0000D001B0F07251C1D0B1B1D2509110B17F9 -:1007C0000F0A001F0F1B061B0F19160B220B110B14 -:1007D000170F0A1B0F0B0E22240302000003030055 -:1007E00000030500000304000004250500000B13AE -:1007F000181C0F1B1D0A0D0013183C7E66666666EA -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex deleted file mode 100644 index 212503d2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000310024C31800FFFFF5E5D5C5FBC342024C -:10001000F5E5D5C5FBC3710321002001201FCD6983 -:100020000FDB02E680CA3300CDC60CAFD302D30388 -:10003000C3B100CD630FFBC33700AF3200200120F6 -:1000400018211420F3CD690FAFD303FBCD630F113B -:100050000A20210F2006031ABECA6200DA6B00D202 -:100060007300132305C25700C373007E12132305C8 -:10007000C26B00CDC60C11BC0F210630CD2C0D3E3D -:10008000783208203A0820A7D304C2840001201443 -:10009000210630CD690F210220AFBECAA60036006E -:1000A0002B3600C3B1002BBECAB1002336FFC313E9 -:1000B00001012018211420F3CD690FAFD303FBCD2C -:1000C000C60C3E20323E203A0420A7C23901F3CDAF -:1000D000FB00FB11EE0F210430CD2C0D3E783208D1 -:1000E000203A0420A7C239013A0820A7D304C2E16C -:1000F00000213E2035C2D300C3B10021018022007F -:100100002121010022082121010022102121222089 -:100110003618C9CD630F11C60F210A2CCD2C0D1135 -:10012000CD0F210432CD2C0D3E5A3208203A082042 -:10013000A7D304C22D01C33E01F3210420350120C1 -:1001400018210F20CD690F3E01D303324120FB213E -:1001500014203609233609CD630FCDC60C3E9932E3 -:100160003C2011B40F210930CD2C0D3E4032082027 -:100170003A0820A7C27001CD630FCDC60CCDFB009D -:100180003EFF320020D304AF212520BEC4D80B236C -:10019000BEC4E50B23BEC40B0C23BEC4180C23BE87 -:1001A000C4C00B23BEC4C40B2A3F2029292929E53A -:1001B0003A1F20A7C2CA017CFE07DACA01211F200C -:1001C0003EFF7723772377233610E13A0220A7C238 -:1001D00007023A0120A7C20702DB02E660CA070253 -:1001E000FE40CAED01D2F2010614C3F4010618C3A1 -:1001F000F40106227CB8DA07023EFF32012011C664 -:100200000F215427CD080D3A3D20A7F23F02AF320F -:100210003D2021CF251114203E02CD0A0D211520AD -:100220003A3C20F547E60F77780F0F0F0FE60F2BBC -:1002300077EB21CF253E02CD0A0DF1A7CA3A00C3C4 -:1002400085012117203EFFBECA440377DB02E60882 -:10025000C2CA02F300000000AF3209203E01323C66 -:10026000203E01323B203EFF323D2011C502210CD1 -:100270002CCD2C0D1E0121FFFF2DC2790225C27944 -:10028000021DC27902D3041E0121FF0FDB02E60228 -:10029000CAAC022DC28C0225C28C021DC28C021176 -:1002A000C502210C2CCD2C0DFBC3DA0211C5022195 -:1002B0000C2CCD2C0DFBDB02E602C2DA023E023230 -:1002C0000920C3DA02041D13161D210920AFBECA7E -:1002D000B60235C2B602210420343A0020A7CA046F -:1002E000033A3720A7C20403211C20DB02E601CA1F -:1002F000F7023600C30403AFBEC2040336FF210178 -:10030000002218213A1A20A7C23D03211620357E6B -:10031000E603CA1D03E601C22603C36503111F04D9 -:10032000210121C33103112F042109217EA7F26588 -:1003300003CD4B03AF321720C1D1E1F1C921182001 -:1003400034C3340321182034C338032BAFBECA642E -:100350000335C26403237EE60F874F0600EB097E58 -:1003600023666FE9C1211820AFBECA340335C30B21 -:1003700003DB02E680CA5704211A203EFFBECADD15 -:100380000377DB01323920213B2035CCE4032108FF -:1003900020AFBECA9703353A1720A7C2D60321194A -:1003A00020357EE603CAB603E601C2BF03114D0441 -:1003B000211921C3C503114304211121C3CA03110B -:1003C0002F042109217EA7FA1304CDF903AF321AB5 -:1003D00020C1D1E1F1C9211B2034C3CD03211B2051 -:1003E00034C3D103363C3A3C20A7CAF303C699274D -:1003F000323C203EFF323D20C92BAFBECA1204352D -:10040000C21204237EE60F874F0600EB097E2366A7 -:100410006FE9C1211B20AFBECACD0335C39E03DAED -:10042000076B086B086B08FA08A6091D095609AE88 -:10043000045805F905580539068206D106C2071089 -:10044000074107BF09170ACD0A610A930ADE0A1D90 -:100450000B7B0B890BAB0BF3214220AFBEDB0132D0 -:100460003920C26A0436FFC370043A1C21CD8204CD -:100470003A3920D60887321C21CD8204C1D1E1F15E -:10048000FBC96F2690D301CD2F0E010138C5E53E83 -:10049000FFD302DB03AE77230DC28F04AFD302DBA1 -:1004A00003AE77012000E109C105C28D04C9060829 -:1004B000CDF30CCD860FE638C3C1043A0520E6081B -:1004C000B04F0600211805091108217E1213237E62 -:1004D0001213233A2120A7F210057EA7F2E0043779 -:1004E000171213237EA7F2EA043717121323060408 -:1004F000CD7D0F210A21CD930DC83A3620A7C8AF74 -:100500003236202109217E323120E6F0F60877C903 -:100510007E1213237EC3EB0404A604FD08704C1462 -:1005200004E1000408703813046100FB08B0901364 -:100530000462040008C0E8130462FB00E0C0E81392 -:100540000463FFFBE0B0901304E3FF04E070381392 -:1005500004A4FBFDE0704C141A47E690CABD05EEFA -:1005600080CAC8053A3620A713EBC5CA7805CD9DC9 -:100570000DCA7B05C1C30707CD8D0DC13A0D21FE04 -:1005800070DAD905FEB0D2E9053A0E21FE38CAADBF -:1005900005FE64CAA705FE90CAA105219013C3B049 -:1005A0000521BC13C3B005213813C3B00521641362 -:1005B000220E2121082136022323C3F6043A0D21FD -:1005C000FE80DAD005C364053A0D21FE80DA6405A9 -:1005D00078F610EE8012C3640578E602CAE40506D8 -:1005E00030C3BB040600C3BB0478E602CAF40506A8 -:1005F00020C3BB040610C3BB043A3620A713EBCAC2 -:100600000B06CD9D0DCA0E06C30707CD8D0D3A0C06 -:1006100021FE08DAF405FEE0D2EF053A0E21FEE8ED -:10062000C22906211A14C32C0621E813220E212107 -:10063000082136022323C3F6043A3620A713EBCA57 -:100640004B06CD9D0DCA4E06C30707CD8D0D3A0C46 -:1006500021FEB0DA6506FEE0D2DF05210821360171 -:100660002323C3F6042108213601233423237E2FBC -:100670003C322420360021B014220E21210A21C34D -:10068000930D3A3620A713EBCA9406CD9D0DCA9759 -:1006900006C30707CD8D0D3A0C21FE40DAAE06FEEB -:1006A000B0D2C70621082136012323C3F60421084E -:1006B000213601233423233A242077217E14220E6D -:1006C00021210A21C3F60421082136012335C3B5AF -:1006D000063A3620A713EBCAE306CD9D0DCAE606FF -:1006E000C30707CD8D0D3A0C21FE40D2FD06FE0852 -:1006F000DAE40521082136012323C3F60421082169 -:1007000036012335C36C063A0921323120C315075F -:1007100013EBCD8D0DAF3236202A0C21CD2F0E22BA -:100720002D203EFF3238203E08323320210821366A -:1007300001237EE6F9F6097723CD8D0D0604C3F378 -:100740000C13EBCD8D0D21332035CAA1073A312092 -:10075000E60FFE04D29707FE023A0E21CA8607FE74 -:1007600038CA8007FE64CA7A07FE90CA74072190CF -:1007700013C3940721BC13C39407213813C39407F0 -:10078000216413C39407FEE8CA910721E813C394B8 -:1007900007211A14220E2121082136012323C38D9B -:1007A0000DAF323820210821360B237EE64007C2E8 -:1007B000B4073EFF3228207EE6F0F6077706F7C33F -:1007C000FF0C06FBCDFF0C1AE64007C2D0073EFF28 -:1007D000322720210400220821C9CD860FE638FEE9 -:1007E00020DAE607E6104F060021D608091100219D -:1007F0007E1213237E1213233A2020A7F228087EAC -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf deleted file mode 100644 index 56216d46..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "Boothill" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf deleted file mode 100644 index b07599dd..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf +++ /dev/null @@ -1,176 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 20:29:53 August 09, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Boothill_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VHDL_FILE rtl/roms/romh.vhd -set_global_assignment -name VHDL_FILE rtl/roms/romg.vhd -set_global_assignment -name VHDL_FILE rtl/roms/romf.vhd -set_global_assignment -name VHDL_FILE rtl/roms/rome.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip -set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ---------------------------- -# start ENTITY(SpaceWalk_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SpaceWalk_mist) -# -------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt deleted file mode 100644 index f5cc3629..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Booth Hill port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- - -Work in Progress - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv deleted file mode 100644 index b828472b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv +++ /dev/null @@ -1,198 +0,0 @@ -module SpaceWalk_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Boot Hill;;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire [5:0]SoundCtrl6; -wire Rst_n_s; -wire RWE_n; -wire Video; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(btn_one_player), - .Sel2Player(btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .MoveUp(~m_up), - .MoveDown(~m_down), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .SoundCtrl6(SoundCtrl6), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -invaders_memory invaders_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S0(SoundCtrl3 | SoundCtrl4), - .S1(SoundCtrl4), - .S2(SoundCtrl5 | SoundCtrl6),//hi - .S3(SoundCtrl6),//lo - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B({Video,Video,Video}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .ce_divider(0), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd deleted file mode 100644 index f3c51b25..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,283 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - MoveUp : in std_logic; - MoveDown : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0);--audio1 - SoundCtrl4 : out std_logic_vector(5 downto 0);--audio2 - SoundCtrl5 : out std_logic_vector(5 downto 0);--low - SoundCtrl6 : out std_logic_vector(5 downto 0);--hi - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(7 downto 0); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(4) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= not MoveUp;--active low - GDB0(1) <= not MoveDown;--active low - GDB0(2) <= not MoveLeft;--active low - GDB0(3) <= not MoveRight;--active low - GDB0(4) <= '0';--active low - GDB0(5) <= '1';--active low - GDB0(6) <= '0';--active low - GDB0(7) <= not Fire; - - GDB1(0) <= not MoveUp;--active low - GDB1(1) <= not MoveDown;--active low - GDB1(2) <= not MoveLeft;--active low - GDB1(3) <= not MoveRight;--active low - GDB1(4) <= '0';--active low - GDB1(5) <= '1';--active low - GDB1(6) <= '0';--active low - GDB1(7) <= not Fire;--active low - - GDB2(0) <= '1';--coin - GDB2(1) <= '0';--coin - GDB2(2) <= '1';--time - GDB2(3) <= '1';--time - GDB2(4) <= '0';--DIPLOCK --active high - GDB2(5) <= not Sel1Player;--active low - GDB2(6) <= not Coin;--active low - GDB2(7) <= not Sel2Player;--active low - --- PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; ---- PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; ---- PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; --- PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; --- PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl4 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - SoundCtrl6 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0);--audio_1_w - end if; --- if PortWr(4) = '1' and OldSample = '0' then --- D5(15 downto 8) <= DB; --- D5(7 downto 0) <= D5(15 downto 8); --- end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0);--tone_generator_lo_w - end if; - if PortWr(6) = '1' then - SoundCtrl6 <= DB(5 downto 0);--tone_generator_hi_w - end if; - if PortWr(7) = '1' then - SoundCtrl4 <= DB(5 downto 0);--audio_2_w - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index d48ec86a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,498 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S0 : in std_logic_vector(5 downto 0); - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - S3 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S0) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s0_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s0_t1 <= S0; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S0(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S0(3) = '1') and (s0_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S0(2) = '1') and (s0_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S0(1) = '1') and (s0_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv deleted file mode 100644 index 382edd1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_memory.sv +++ /dev/null @@ -1,66 +0,0 @@ - -module invaders_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; - - - -romh romh ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_0) -); - -romg romg ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_1) -); - -romf romf ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_2) -); - -rome rome ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_3) -); - - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin - Rom_out = 8'b00000000; - case (Addr[13:11]) - 3'b000 : Rom_out = rom_data_0; - 3'b001 : Rom_out = rom_data_1; - 3'b010 : Rom_out = rom_data_2; - 3'b011 : Rom_out = rom_data_3; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd deleted file mode 100644 index 77ac2478..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/invaders_video.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity invaders_video is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end invaders_video; - -architecture rtl of invaders_video is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= not HSync; - O_VSYNC <= not VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd deleted file mode 100644 index de22ea71..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/rome.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rome is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rome is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"A7",X"32",X"48",X"20",X"FC",X"41",X"18",X"78",X"91",X"C8",X"44",X"4D",X"6F",X"9F",X"67",X"CD", - X"41",X"18",X"EB",X"3E",X"11",X"21",X"00",X"00",X"E5",X"19",X"D2",X"1E",X"18",X"E3",X"E1",X"F5", - X"79",X"17",X"4F",X"78",X"17",X"47",X"7D",X"17",X"6F",X"7C",X"17",X"67",X"F1",X"3D",X"C2",X"18", - X"18",X"AF",X"7C",X"1F",X"57",X"7D",X"1F",X"5F",X"3A",X"48",X"20",X"A7",X"79",X"F0",X"2F",X"3C", - X"C9",X"7C",X"2F",X"67",X"7D",X"2F",X"6F",X"23",X"C9",X"11",X"4A",X"20",X"1A",X"3D",X"CA",X"66", - X"18",X"12",X"F6",X"30",X"21",X"29",X"20",X"77",X"11",X"B0",X"3E",X"3E",X"01",X"CD",X"30",X"01", - X"3E",X"1E",X"32",X"25",X"20",X"C9",X"AF",X"32",X"57",X"20",X"32",X"58",X"20",X"32",X"27",X"20", - X"CD",X"79",X"18",X"FA",X"60",X"18",X"C3",X"10",X"19",X"21",X"86",X"20",X"11",X"0B",X"00",X"19", - X"7E",X"A7",X"F8",X"7D",X"FE",X"B2",X"C2",X"7F",X"18",X"C9",X"21",X"55",X"20",X"7E",X"A7",X"11", - X"5E",X"20",X"C2",X"98",X"18",X"11",X"70",X"20",X"23",X"34",X"4E",X"06",X"00",X"21",X"7C",X"19", - X"09",X"7E",X"EB",X"56",X"2B",X"5E",X"2B",X"77",X"2B",X"1F",X"3E",X"47",X"DA",X"B0",X"18",X"3D", - X"B6",X"77",X"21",X"22",X"1A",X"09",X"09",X"7E",X"23",X"66",X"6F",X"E9",X"3E",X"0F",X"32",X"24", - X"20",X"CD",X"D9",X"11",X"D6",X"04",X"FE",X"25",X"D2",X"CD",X"18",X"C6",X"07",X"57",X"EB",X"22", - X"4E",X"20",X"EB",X"3A",X"09",X"20",X"E6",X"1C",X"4F",X"06",X"00",X"21",X"2E",X"1E",X"09",X"3E", - X"04",X"C3",X"30",X"01",X"21",X"C8",X"1D",X"3A",X"55",X"20",X"A7",X"CA",X"F1",X"18",X"21",X"E0", - X"1D",X"CD",X"82",X"1C",X"3E",X"0A",X"32",X"24",X"20",X"2A",X"4E",X"20",X"EB",X"3E",X"0F",X"C3", - X"6E",X"1B",X"3E",X"0F",X"32",X"24",X"20",X"2A",X"4E",X"20",X"EB",X"3E",X"10",X"C3",X"6E",X"1B", - X"AF",X"32",X"23",X"20",X"2A",X"0F",X"20",X"22",X"06",X"20",X"C9",X"2A",X"06",X"20",X"23",X"22", - X"06",X"20",X"C9",X"AF",X"32",X"57",X"20",X"32",X"58",X"20",X"32",X"27",X"20",X"32",X"25",X"20", - X"CD",X"79",X"18",X"FA",X"4D",X"19",X"3A",X"06",X"20",X"D6",X"67",X"C2",X"4D",X"19",X"32",X"0A", - X"20",X"21",X"91",X"1A",X"22",X"06",X"20",X"21",X"F6",X"1D",X"C3",X"87",X"1C",X"3E",X"01",X"32", - X"08",X"20",X"C9",X"8A",X"1B",X"68",X"1B",X"81",X"1B",X"8B",X"1B",X"9D",X"1B",X"A6",X"1B",X"B2", - X"1B",X"49",X"12",X"11",X"1C",X"24",X"1C",X"5C",X"1C",X"6F",X"1C",X"2B",X"1D",X"48",X"1D",X"7B", - X"1C",X"7F",X"1C",X"A0",X"80",X"60",X"30",X"0E",X"74",X"74",X"78",X"78",X"7A",X"B0",X"C0",X"D0", - X"D1",X"58",X"71",X"8F",X"A8",X"FF",X"80",X"50",X"0E",X"9E",X"5E",X"2E",X"0D",X"2A",X"0C",X"30", - X"0B",X"38",X"12",X"2A",X"13",X"30",X"14",X"38",X"15",X"00",X"12",X"00",X"11",X"00",X"0F",X"00", - X"0E",X"00",X"00",X"00",X"15",X"01",X"12",X"01",X"11",X"00",X"0F",X"00",X"0E",X"01",X"00",X"00", - X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"BC",X"15",X"D5",X"15", - X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"C5",X"15",X"61",X"16", - X"06",X"06",X"1A",X"15",X"06",X"FE",X"1A",X"04",X"06",X"00",X"1A",X"09",X"06",X"FA",X"1A",X"FE", - X"06",X"04",X"1A",X"11",X"06",X"FC",X"1A",X"02",X"06",X"02",X"1A",X"0E",X"FA",X"06",X"FC",X"15", - X"FA",X"FE",X"FC",X"04",X"FA",X"00",X"FC",X"09",X"FA",X"FA",X"FC",X"FE",X"FA",X"04",X"FC",X"11", - X"FA",X"FC",X"FC",X"02",X"FA",X"02",X"FC",X"0E",X"E4",X"0A",X"0B",X"38",X"00",X"0B",X"0C",X"30", - X"17",X"0B",X"0D",X"2A",X"E4",X"0A",X"14",X"38",X"00",X"0B",X"13",X"30",X"17",X"0B",X"12",X"2A", - X"08",X"09",X"0A",X"09",X"BC",X"18",X"E4",X"18",X"02",X"19",X"8A",X"1B",X"00",X"00",X"00",X"01", - X"01",X"00",X"01",X"01",X"01",X"02",X"02",X"01",X"02",X"02",X"02",X"03",X"03",X"02",X"03",X"03", - X"03",X"04",X"04",X"03",X"04",X"04",X"00",X"02",X"FE",X"00",X"02",X"FE",X"00",X"01",X"FF",X"00", - X"01",X"FF",X"00",X"00",X"FE",X"02",X"00",X"06",X"FA",X"00",X"FF",X"01",X"00",X"FF",X"01",X"00", - X"01",X"40",X"03",X"42",X"05",X"44",X"06",X"45",X"07",X"46",X"A8",X"E8",X"AA",X"E8",X"AC",X"E8", - X"AD",X"E8",X"AE",X"E8",X"05",X"02",X"05",X"06",X"09",X"06",X"01",X"0A",X"19",X"01",X"04",X"17", - X"05",X"06",X"15",X"07",X"02",X"13",X"03",X"03",X"11",X"02",X"07",X"0F",X"06",X"05",X"01",X"04", - X"01",X"06",X"01",X"11",X"20",X"06",X"00",X"44",X"20",X"04",X"0A",X"AE",X"1A",X"02",X"0E",X"00", - X"24",X"03",X"1E",X"00",X"02",X"07",X"00",X"24",X"03",X"1E",X"00",X"05",X"9D",X"1A",X"0E",X"08", - X"0A",X"02",X"09",X"00",X"28",X"03",X"3C",X"00",X"02",X"11",X"00",X"30",X"03",X"3C",X"00",X"02", - X"0A",X"00",X"3C",X"03",X"3C",X"00",X"08",X"0A",X"09",X"5F",X"20",X"00",X"10",X"08",X"32",X"80", - X"09",X"71",X"20",X"00",X"10",X"DE",X"36",X"88",X"04",X"00",X"AE",X"1A",X"06",X"01",X"28",X"20", - X"03",X"5A",X"00",X"0D",X"05",X"E0",X"1A",X"08",X"0F",X"95",X"1C",X"08",X"10",X"9C",X"1D",X"0B", - X"11",X"20",X"FB",X"1A",X"02",X"12",X"00",X"2C",X"05",X"FF",X"1A",X"02",X"13",X"00",X"30",X"03", - X"69",X"00",X"08",X"06",X"01",X"44",X"20",X"0A",X"07",X"09",X"5F",X"20",X"01",X"B0",X"01",X"38", - X"80",X"0B",X"11",X"20",X"26",X"1B",X"06",X"84",X"5B",X"20",X"06",X"35",X"5C",X"20",X"06",X"1E", - X"28",X"20",X"06",X"50",X"27",X"20",X"09",X"71",X"20",X"01",X"B0",X"DE",X"34",X"88",X"02",X"0B", - X"A0",X"34",X"03",X"1E",X"00",X"02",X"0C",X"A0",X"34",X"03",X"0F",X"00",X"02",X"08",X"A0",X"34", - X"02",X"0D",X"A2",X"3E",X"0B",X"47",X"20",X"52",X"1B",X"0C",X"09",X"83",X"20",X"00",X"B0",X"74", - X"01",X"80",X"06",X"01",X"58",X"20",X"06",X"01",X"57",X"20",X"0B",X"11",X"20",X"63",X"1B",X"06", - X"00",X"57",X"20",X"04",X"00",X"02",X"1B",X"00",X"1A",X"13",X"CD",X"8B",X"1C",X"EB",X"4F",X"21", - X"4E",X"1E",X"7E",X"23",X"A7",X"F2",X"72",X"1B",X"0D",X"C2",X"72",X"1B",X"E6",X"7F",X"C3",X"30", - X"01",X"EB",X"7E",X"32",X"23",X"20",X"23",X"22",X"06",X"20",X"C9",X"EB",X"7E",X"32",X"22",X"20", - X"23",X"5E",X"23",X"56",X"23",X"22",X"06",X"20",X"EB",X"22",X"0F",X"20",X"C9",X"EB",X"5E",X"23", - X"56",X"EB",X"22",X"06",X"20",X"C9",X"EB",X"7E",X"23",X"5E",X"23",X"56",X"23",X"22",X"06",X"20", - X"12",X"C9",X"21",X"0D",X"20",X"7E",X"23",X"B6",X"FE",X"04",X"F2",X"BE",X"1B",X"AF",X"32",X"47", - X"20",X"21",X"AF",X"0D",X"11",X"0D",X"3A",X"CD",X"F7",X"1B",X"21",X"14",X"1A",X"3A",X"0D",X"20", - X"CD",X"D9",X"1B",X"21",X"08",X"1A",X"3A",X"0E",X"20",X"A7",X"C8",X"FE",X"03",X"FA",X"E2",X"1B", - X"3E",X"03",X"F5",X"5E",X"23",X"56",X"23",X"D5",X"5E",X"23",X"56",X"23",X"E3",X"CD",X"F7",X"1B", - X"E1",X"F1",X"3D",X"C2",X"E2",X"1B",X"C9",X"4E",X"23",X"46",X"23",X"EB",X"C5",X"E5",X"1A",X"13", - X"77",X"23",X"0D",X"C2",X"FE",X"1B",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"FC",X"1B", - X"C9",X"EB",X"5E",X"23",X"56",X"23",X"0E",X"05",X"7E",X"23",X"12",X"1B",X"0D",X"C2",X"18",X"1C", - X"22",X"06",X"20",X"C9",X"11",X"0D",X"20",X"01",X"29",X"20",X"CD",X"44",X"1C",X"13",X"CD",X"44", - X"1C",X"11",X"00",X"24",X"21",X"29",X"20",X"3E",X"02",X"CD",X"30",X"01",X"11",X"1E",X"24",X"3E", - X"02",X"C3",X"30",X"01",X"1A",X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"C2",X"50",X"1C",X"3E",X"10", - X"C6",X"30",X"02",X"03",X"1A",X"E6",X"0F",X"C6",X"30",X"02",X"03",X"C9",X"EB",X"4E",X"23",X"46", - X"23",X"5E",X"23",X"56",X"23",X"0A",X"A7",X"C2",X"6B",X"1C",X"EB",X"22",X"06",X"20",X"C9",X"21", - X"0D",X"3A",X"11",X"BD",X"20",X"01",X"06",X"24",X"C3",X"FC",X"1B",X"CD",X"8B",X"1C",X"E9",X"CD", - X"8B",X"1C",X"3A",X"0A",X"20",X"A7",X"C8",X"22",X"00",X"20",X"C9",X"EB",X"5E",X"23",X"56",X"23", - X"22",X"06",X"20",X"EB",X"C9",X"3A",X"12",X"20",X"0E",X"05",X"FE",X"04",X"D2",X"B0",X"1C",X"3D", - X"07",X"07",X"47",X"DB",X"02",X"E6",X"03",X"B0",X"4F",X"06",X"00",X"21",X"17",X"1D",X"09",X"4E", - X"11",X"00",X"28",X"11",X"00",X"28",X"04",X"79",X"A7",X"1F",X"4F",X"D2",X"CE",X"1C",X"C5",X"D5", - X"78",X"CD",X"6E",X"1B",X"E1",X"11",X"00",X"02",X"19",X"EB",X"C1",X"C3",X"B6",X"1C",X"C2",X"B6", - X"1C",X"D3",X"04",X"DB",X"02",X"2F",X"E6",X"A0",X"CA",X"D1",X"1C",X"07",X"E6",X"01",X"4F",X"DB", - X"02",X"07",X"E6",X"06",X"B1",X"4F",X"06",X"00",X"21",X"23",X"1D",X"09",X"46",X"21",X"12",X"20", - X"7E",X"90",X"FA",X"D1",X"1C",X"F3",X"7E",X"90",X"77",X"79",X"E6",X"01",X"3D",X"32",X"11",X"20", - X"3D",X"32",X"0A",X"20",X"DB",X"02",X"E6",X"0C",X"07",X"07",X"C6",X"64",X"32",X"08",X"20",X"AF", - X"32",X"0D",X"20",X"32",X"0E",X"20",X"C9",X"2B",X"05",X"08",X"08",X"05",X"05",X"33",X"05",X"05", - X"05",X"2B",X"05",X"01",X"02",X"01",X"01",X"02",X"04",X"02",X"02",X"3A",X"49",X"20",X"A7",X"C0", - X"3E",X"01",X"CD",X"C2",X"17",X"32",X"71",X"20",X"21",X"6E",X"20",X"7E",X"E6",X"0F",X"B0",X"77", - X"2B",X"7E",X"F6",X"42",X"77",X"C3",X"61",X"16",X"3A",X"12",X"20",X"A7",X"C2",X"D1",X"16",X"C9", - X"00",X"00",X"3F",X"13",X"1D",X"16",X"33",X"18",X"3F",X"1A",X"05",X"1D",X"01",X"1F",X"39",X"20", - X"27",X"22",X"11",X"24",X"35",X"25",X"13",X"27",X"2B",X"28",X"3F",X"29",X"0F",X"2B",X"19",X"2C", - X"1F",X"2D",X"21",X"2E",X"21",X"2F",X"1D",X"30",X"15",X"31",X"09",X"32",X"3B",X"32",X"29",X"33", - X"17",X"34",X"3F",X"34",X"27",X"35",X"0D",X"36",X"31",X"36",X"11",X"37",X"31",X"37",X"0F",X"38", - X"2B",X"38",X"05",X"39",X"1D",X"39",X"35",X"39",X"0B",X"3A",X"21",X"3A",X"84",X"06",X"14",X"02", - X"12",X"03",X"11",X"01",X"0F",X"0A",X"11",X"01",X"08",X"01",X"08",X"04",X"0D",X"01",X"0D",X"01", - X"0D",X"03",X"0D",X"01",X"0C",X"02",X"0D",X"0A",X"0F",X"00",X"84",X"01",X"15",X"02",X"00",X"02", - X"0E",X"01",X"11",X"03",X"10",X"03",X"0C",X"00",X"84",X"04",X"0F",X"03",X"0F",X"01",X"0F",X"04", - X"0F",X"03",X"12",X"01",X"11",X"03",X"11",X"01",X"0F",X"03",X"0F",X"01",X"0E",X"08",X"0F",X"00", - X"84",X"02",X"08",X"01",X"0D",X"01",X"0D",X"02",X"11",X"0A",X"14",X"01",X"14",X"01",X"14",X"02", - X"11",X"02",X"0D",X"0A",X"11",X"00",X"86",X"03",X"0A",X"01",X"0A",X"06",X"0F",X"03",X"0A",X"01", - X"0F",X"06",X"13",X"03",X"0A",X"01",X"0F",X"02",X"13",X"03",X"0A",X"01",X"0F",X"02",X"13",X"03", - X"0A",X"01",X"0F",X"06",X"13",X"03",X"0F",X"01",X"13",X"04",X"16",X"02",X"13",X"02",X"0F",X"06", - X"0A",X"03",X"0A",X"01",X"0A",X"06",X"0F",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"55",X"47", - X"48",X"5B",X"50",X"4F",X"57",X"5B",X"5A",X"41",X"50",X"5B",X"57",X"41",X"4D",X"5B",X"42",X"41", - X"4D",X"5B",X"54",X"48",X"55",X"44",X"55",X"4D",X"46",X"5B",X"41",X"52",X"47",X"5B",X"8D",X"27", - X"54",X"4F",X"40",X"53",X"54",X"41",X"52",X"54",X"40",X"47",X"41",X"4D",X"45",X"95",X"2B",X"50", - X"52",X"45",X"53",X"53",X"40",X"31",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"42",X"55", - X"54",X"54",X"4F",X"4E",X"9A",X"2D",X"50",X"52",X"45",X"53",X"53",X"40",X"31",X"40",X"4F",X"52", - X"40",X"32",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"42",X"55",X"54",X"54",X"4F",X"4E", - X"92",X"29",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"31",X"40",X"4D",X"4F",X"52",X"45",X"40", - X"43",X"4F",X"49",X"4E",X"93",X"2A",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"32",X"40",X"4D", - X"4F",X"52",X"45",X"40",X"43",X"4F",X"49",X"4E",X"53",X"93",X"2A",X"46",X"4F",X"52",X"40",X"54", - X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"47",X"41",X"4D",X"45",X"89",X"89", - X"24",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"89",X"25",X"42",X"4F",X"4F",X"54", - X"40",X"48",X"49",X"4C",X"4C",X"8B",X"26",X"49",X"4E",X"53",X"45",X"52",X"54",X"40",X"43",X"4F", - X"49",X"4E",X"40",X"89",X"24",X"47",X"45",X"54",X"40",X"52",X"45",X"41",X"44",X"59",X"89",X"24", - X"40",X"40",X"44",X"52",X"41",X"57",X"5B",X"40",X"40",X"8C",X"5C",X"5C",X"5C",X"5C",X"5C",X"5C", - X"20",X"5C",X"5C",X"5C",X"5C",X"5C",X"5C",X"89",X"24",X"47",X"41",X"4D",X"45",X"40",X"4F",X"56", - X"45",X"52",X"87",X"53",X"48",X"4F",X"54",X"13",X"4D",X"45",X"5B",X"87",X"40",X"40",X"40",X"40", - X"13",X"40",X"40",X"40",X"9A",X"27",X"54",X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52", - X"40",X"4F",X"52",X"1D",X"53",X"49",X"4E",X"47",X"4C",X"45",X"40",X"50",X"4C",X"41",X"59",X"45", - X"52",X"B2",X"2A",X"55",X"53",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"31",X"40", - X"48",X"41",X"4E",X"44",X"4C",X"45",X"53",X"28",X"43",X"4F",X"4D",X"50",X"55",X"54",X"45",X"52", - X"40",X"43",X"4F",X"4E",X"54",X"52",X"4F",X"4C",X"53",X"40",X"4F",X"54",X"48",X"45",X"52",X"40", - X"43",X"4F",X"57",X"42",X"4F",X"59",X"99",X"2D",X"4D",X"41",X"59",X"40",X"54",X"48",X"45",X"40", - X"42",X"45",X"54",X"54",X"45",X"52",X"40",X"43",X"4F",X"57",X"42",X"4F",X"59",X"40",X"57",X"49", - X"4E",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd deleted file mode 100644 index 032ba6d3..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romf.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity romf is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of romf is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"7E",X"A7",X"CA",X"0E",X"10",X"C6",X"99",X"27",X"77",X"C2",X"0E",X"10",X"06",X"01",X"21",X"22", - X"20",X"CD",X"32",X"10",X"21",X"23",X"20",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD", - X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"23",X"CD",X"32",X"10",X"32",X"4B", - X"20",X"C9",X"7E",X"A7",X"CA",X"3C",X"10",X"35",X"C2",X"3C",X"10",X"37",X"78",X"17",X"47",X"C9", - X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"E5",X"CD",X"A6",X"10",X"E1",X"7D",X"FE",X"B2", - X"C2",X"43",X"10",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1",X"CD",X"0D",X"12",X"E1", - X"C3",X"0D",X"12",X"11",X"54",X"20",X"1A",X"3C",X"FE",X"03",X"C2",X"6E",X"10",X"AF",X"12",X"21", - X"49",X"20",X"11",X"12",X"00",X"19",X"3D",X"F2",X"75",X"10",X"C9",X"7E",X"E6",X"20",X"C8",X"7E", - X"E6",X"9F",X"77",X"01",X"06",X"00",X"09",X"11",X"33",X"20",X"CD",X"91",X"10",X"23",X"23",X"23", - X"23",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"23",X"13",X"13",X"13",X"1A",X"13",X"3C",X"77", - X"23",X"1A",X"13",X"77",X"23",X"C9",X"3A",X"0B",X"20",X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"20", - X"C8",X"7E",X"E6",X"40",X"C2",X"B9",X"10",X"36",X"00",X"01",X"05",X"00",X"09",X"5E",X"23",X"56", - X"23",X"EB",X"CD",X"C8",X"10",X"0E",X"1F",X"09",X"1A",X"13",X"77",X"23",X"1A",X"13",X"77",X"C9", - X"7E",X"E6",X"20",X"C8",X"23",X"01",X"05",X"00",X"09",X"5E",X"23",X"56",X"23",X"7B",X"B2",X"C8", - X"D5",X"5E",X"23",X"56",X"09",X"E3",X"CD",X"F6",X"10",X"E1",X"5E",X"23",X"56",X"23",X"7B",X"B2", - X"C8",X"D5",X"5E",X"23",X"56",X"E1",X"01",X"20",X"00",X"E5",X"7B",X"36",X"00",X"23",X"3D",X"C2", - X"FB",X"10",X"E1",X"09",X"15",X"C2",X"F9",X"10",X"C9",X"21",X"33",X"20",X"5E",X"23",X"56",X"23", - X"7A",X"B3",X"C8",X"D5",X"7E",X"23",X"D3",X"01",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23", - X"E3",X"E6",X"08",X"CC",X"94",X"11",X"C4",X"EB",X"11",X"E1",X"C3",X"0C",X"11",X"7E",X"E6",X"40", - X"C8",X"7E",X"E6",X"BF",X"F6",X"20",X"77",X"E6",X"08",X"47",X"23",X"23",X"5E",X"23",X"7B",X"E6", - X"07",X"05",X"FA",X"46",X"11",X"2F",X"32",X"35",X"20",X"32",X"3C",X"20",X"56",X"23",X"CD",X"D9", - X"11",X"EB",X"22",X"33",X"20",X"EB",X"D5",X"CD",X"B3",X"11",X"23",X"23",X"23",X"23",X"E5",X"21", - X"36",X"20",X"CD",X"87",X"11",X"E1",X"C1",X"5E",X"23",X"7B",X"A7",X"C8",X"16",X"00",X"3E",X"05", - X"EB",X"29",X"3D",X"C2",X"71",X"11",X"09",X"EB",X"7E",X"23",X"83",X"5F",X"EB",X"22",X"3A",X"20", - X"EB",X"CD",X"B3",X"11",X"21",X"3D",X"20",X"73",X"23",X"72",X"23",X"71",X"23",X"70",X"23",X"AF", - X"77",X"23",X"77",X"C9",X"C5",X"E5",X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"23",X"0D",X"C2", - X"96",X"11",X"AF",X"D3",X"02",X"DB",X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2", - X"94",X"11",X"C9",X"5E",X"23",X"E5",X"16",X"00",X"21",X"01",X"03",X"19",X"19",X"5E",X"23",X"56", - X"EB",X"E3",X"5E",X"23",X"E3",X"16",X"00",X"19",X"19",X"5E",X"23",X"56",X"E1",X"EB",X"4E",X"23", - X"46",X"23",X"EB",X"C9",X"7B",X"E6",X"07",X"D3",X"01",X"06",X"03",X"AF",X"7A",X"1F",X"57",X"7B", - X"1F",X"5F",X"05",X"C2",X"DB",X"11",X"7A",X"C6",X"24",X"57",X"C9",X"79",X"85",X"6F",X"C5",X"E5", - X"1A",X"13",X"D3",X"02",X"DB",X"03",X"77",X"2B",X"0D",X"C2",X"F0",X"11",X"AF",X"D3",X"02",X"DB", - X"03",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"EE",X"11",X"C9",X"3A",X"0B",X"20", - X"AE",X"E6",X"10",X"C0",X"7E",X"E6",X"40",X"C8",X"7E",X"F6",X"20",X"77",X"23",X"23",X"5E",X"23", - X"23",X"56",X"23",X"CD",X"D4",X"11",X"73",X"23",X"72",X"23",X"EB",X"CD",X"32",X"12",X"01",X"1F", - X"00",X"09",X"7E",X"12",X"13",X"3E",X"03",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"23",X"7E",X"12", - X"13",X"AF",X"D3",X"02",X"DB",X"03",X"B6",X"77",X"C9",X"F3",X"E1",X"01",X"00",X"00",X"11",X"00", - X"00",X"31",X"20",X"40",X"3E",X"10",X"C5",X"13",X"BA",X"C2",X"56",X"12",X"31",X"00",X"24",X"E9", - X"7E",X"A7",X"F0",X"E6",X"04",X"01",X"00",X"00",X"11",X"04",X"FC",X"CA",X"71",X"12",X"11",X"06", - X"FA",X"23",X"7E",X"E6",X"0F",X"CA",X"A9",X"12",X"1F",X"D2",X"7D",X"12",X"42",X"1F",X"D2",X"82", - X"12",X"43",X"1F",X"D2",X"87",X"12",X"4A",X"1F",X"D2",X"8C",X"12",X"4B",X"79",X"0E",X"00",X"23", - X"A7",X"C4",X"D0",X"12",X"23",X"78",X"A7",X"C4",X"C6",X"12",X"2B",X"2B",X"79",X"A7",X"CA",X"A9", - X"12",X"2B",X"7E",X"E6",X"ED",X"F6",X"60",X"77",X"C9",X"2B",X"7E",X"E6",X"02",X"C2",X"A2",X"12", - X"54",X"5D",X"01",X"0C",X"00",X"09",X"7E",X"FE",X"08",X"C8",X"36",X"08",X"EB",X"7E",X"E6",X"10", - X"C0",X"7E",X"F6",X"70",X"77",X"C9",X"86",X"FE",X"11",X"D8",X"FE",X"B4",X"D0",X"77",X"0C",X"C9", - X"86",X"E5",X"F5",X"23",X"23",X"23",X"5E",X"16",X"00",X"7D",X"FE",X"60",X"21",X"60",X"1A",X"CA", - X"E5",X"12",X"21",X"6A",X"1A",X"19",X"19",X"5E",X"23",X"56",X"F1",X"E1",X"BB",X"D8",X"BA",X"D0", - X"77",X"0C",X"C9",X"21",X"5B",X"20",X"7E",X"A7",X"F2",X"10",X"13",X"CD",X"39",X"13",X"11",X"46", - X"1A",X"3A",X"5C",X"20",X"CD",X"50",X"13",X"21",X"98",X"19",X"CD",X"99",X"13",X"22",X"65",X"20", - X"21",X"6D",X"20",X"7E",X"A7",X"F2",X"2D",X"13",X"CD",X"39",X"13",X"11",X"53",X"1A",X"3A",X"6E", - X"20",X"CD",X"50",X"13",X"21",X"A4",X"19",X"CD",X"99",X"13",X"22",X"77",X"20",X"21",X"7F",X"20", - X"7E",X"A7",X"F0",X"CD",X"39",X"13",X"23",X"71",X"C9",X"23",X"23",X"22",X"50",X"20",X"23",X"7E", - X"23",X"EB",X"21",X"73",X"19",X"01",X"FF",X"00",X"0C",X"BE",X"23",X"DA",X"48",X"13",X"EB",X"C9", - X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"C2",X"5B",X"13",X"3E",X"01",X"77",X"23",X"F5",X"E5",X"46", - X"71",X"CD",X"7A",X"13",X"E1",X"F1",X"11",X"08",X"00",X"42",X"19",X"71",X"FE",X"0B",X"FA",X"73", - X"13",X"0E",X"05",X"2B",X"7E",X"A7",X"C0",X"36",X"08",X"C9",X"21",X"2C",X"1A",X"78",X"BE",X"C2", - X"8F",X"13",X"23",X"79",X"BE",X"C2",X"90",X"13",X"1A",X"2A",X"50",X"20",X"86",X"77",X"C9",X"23", - X"23",X"13",X"7D",X"FE",X"06",X"C2",X"7D",X"13",X"C9",X"09",X"09",X"5E",X"23",X"56",X"EB",X"C9", - X"3A",X"43",X"20",X"A7",X"C0",X"21",X"91",X"20",X"CD",X"BD",X"13",X"21",X"9C",X"20",X"CD",X"BD", - X"13",X"21",X"A7",X"20",X"CD",X"F0",X"13",X"21",X"B2",X"20",X"C3",X"F0",X"13",X"7E",X"A7",X"F0", - X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"07",X"F8",X"CD",X"5A",X"14",X"FE",X"0A",X"F8", - X"D6",X"09",X"21",X"90",X"19",X"FE",X"04",X"FA",X"A0",X"14",X"21",X"6E",X"20",X"3E",X"30",X"77", - X"32",X"5C",X"20",X"23",X"7E",X"FE",X"DE",X"DA",X"EC",X"13",X"36",X"DE",X"AF",X"C3",X"1F",X"14", - X"7E",X"A7",X"F0",X"CD",X"95",X"14",X"C8",X"CD",X"6C",X"14",X"FE",X"0A",X"F0",X"CD",X"5A",X"14", - X"FE",X"07",X"F0",X"D6",X"03",X"FE",X"01",X"21",X"8A",X"19",X"F2",X"A0",X"14",X"21",X"5C",X"20", - X"3E",X"30",X"77",X"32",X"6E",X"20",X"23",X"7E",X"FE",X"30",X"DA",X"1F",X"14",X"36",X"30",X"32", - X"55",X"20",X"AF",X"32",X"25",X"20",X"32",X"27",X"20",X"32",X"28",X"20",X"32",X"57",X"20",X"32", - X"58",X"20",X"32",X"22",X"20",X"3C",X"32",X"49",X"20",X"32",X"45",X"20",X"32",X"24",X"20",X"32", - X"43",X"20",X"3A",X"0A",X"20",X"A7",X"C8",X"3E",X"04",X"32",X"26",X"20",X"3A",X"55",X"20",X"A7", - X"3E",X"48",X"CA",X"57",X"14",X"3E",X"88",X"D3",X"03",X"C9",X"7E",X"E6",X"BF",X"77",X"11",X"07", - X"00",X"19",X"AF",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"78",X"C9",X"E5",X"23",X"23",X"7E", - X"E5",X"21",X"81",X"19",X"06",X"01",X"04",X"04",X"04",X"BE",X"23",X"D2",X"76",X"14",X"E1",X"23", - X"23",X"7E",X"21",X"85",X"19",X"11",X"88",X"19",X"05",X"13",X"23",X"BE",X"DA",X"88",X"14",X"EB", - X"96",X"4F",X"78",X"E1",X"C9",X"E5",X"11",X"07",X"00",X"19",X"7E",X"23",X"23",X"B6",X"E1",X"C9", - X"23",X"23",X"3D",X"C2",X"A0",X"14",X"5E",X"23",X"56",X"2E",X"01",X"61",X"EB",X"C3",X"F6",X"10", - X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"CD",X"C3",X"14",X"E1",X"7D",X"FE",X"B2",X"C2", - X"B3",X"14",X"C9",X"7E",X"A7",X"F0",X"23",X"23",X"7E",X"FE",X"08",X"DA",X"E4",X"14",X"FE",X"F8", - X"D2",X"E4",X"14",X"23",X"23",X"7E",X"FE",X"10",X"DA",X"DE",X"14",X"FE",X"CC",X"D8",X"2B",X"7E", - X"2F",X"3C",X"77",X"C9",X"2B",X"2B",X"7E",X"E6",X"BF",X"77",X"C9",X"21",X"6D",X"20",X"11",X"0D", - X"20",X"CD",X"FA",X"14",X"21",X"5B",X"20",X"11",X"0E",X"20",X"7E",X"A7",X"F0",X"E6",X"01",X"C8", - X"23",X"23",X"23",X"7E",X"FE",X"17",X"D0",X"AF",X"32",X"45",X"20",X"2B",X"2B",X"7E",X"E6",X"0F", - X"F6",X"E0",X"77",X"2B",X"7E",X"E6",X"FE",X"77",X"3E",X"02",X"32",X"22",X"20",X"3A",X"0A",X"20", - X"A7",X"C8",X"1A",X"3C",X"27",X"12",X"C3",X"24",X"1C",X"3A",X"09",X"20",X"D6",X"05",X"F8",X"C2", - X"2C",X"15",X"2A",X"4C",X"20",X"7D",X"FE",X"20",X"D2",X"3E",X"15",X"21",X"23",X"1A",X"46",X"2B", - X"22",X"4C",X"20",X"3A",X"5C",X"20",X"E6",X"0F",X"CA",X"4F",X"15",X"78",X"32",X"67",X"20",X"3A", - X"6E",X"20",X"E6",X"0F",X"C8",X"78",X"32",X"79",X"20",X"C9",X"3A",X"57",X"20",X"A7",X"CA",X"70", - X"15",X"DB",X"00",X"47",X"DB",X"00",X"21",X"20",X"20",X"11",X"B0",X"19",X"B8",X"CC",X"82",X"15", - X"3A",X"58",X"20",X"A7",X"C8",X"DB",X"01",X"47",X"DB",X"01",X"21",X"21",X"20",X"11",X"C0",X"19", - X"B8",X"C0",X"E5",X"2F",X"F5",X"0F",X"0F",X"0F",X"0F",X"E6",X"07",X"4F",X"06",X"00",X"21",X"B4", - X"15",X"09",X"F1",X"E6",X"8F",X"B6",X"E1",X"AE",X"C8",X"4F",X"06",X"01",X"79",X"0F",X"DA",X"AA", - X"15",X"4F",X"78",X"07",X"47",X"13",X"13",X"C3",X"9C",X"15",X"78",X"AE",X"77",X"A0",X"EB",X"4E", - X"23",X"66",X"69",X"E9",X"30",X"70",X"40",X"50",X"20",X"50",X"60",X"10",X"21",X"5B",X"20",X"11", - X"20",X"20",X"C3",X"CB",X"15",X"21",X"6D",X"20",X"11",X"21",X"20",X"7E",X"F6",X"02",X"77",X"1A", - X"E6",X"7F",X"23",X"77",X"C9",X"C8",X"21",X"91",X"20",X"7E",X"A7",X"F2",X"E4",X"15",X"21",X"9C", - X"20",X"7E",X"A7",X"F8",X"11",X"59",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04", - X"00",X"19",X"E5",X"21",X"28",X"1E",X"11",X"A2",X"3E",X"CD",X"30",X"01",X"21",X"5F",X"20",X"5E", - X"16",X"00",X"2B",X"E5",X"21",X"CC",X"19",X"06",X"18",X"3A",X"0A",X"20",X"A7",X"CA",X"18",X"16", - X"78",X"D3",X"03",X"3E",X"04",X"32",X"26",X"20",X"19",X"19",X"19",X"19",X"5E",X"23",X"56",X"23", - X"4E",X"23",X"46",X"E1",X"7E",X"80",X"47",X"2B",X"7E",X"81",X"4F",X"E1",X"70",X"2B",X"72",X"2B", - X"71",X"2B",X"73",X"2B",X"36",X"C0",X"D1",X"1A",X"FE",X"06",X"C0",X"3C",X"12",X"13",X"7B",X"FE", - X"5A",X"CA",X"46",X"16",X"1B",X"1B",X"06",X"0A",X"3A",X"11",X"20",X"A7",X"CA",X"51",X"16",X"06", - X"05",X"1A",X"FE",X"06",X"FA",X"59",X"16",X"06",X"02",X"78",X"32",X"25",X"20",X"32",X"4A",X"20", - X"C9",X"C8",X"21",X"A7",X"20",X"7E",X"A7",X"F2",X"70",X"16",X"21",X"B2",X"20",X"7E",X"A7",X"F8", - X"11",X"5A",X"20",X"1A",X"FE",X"07",X"F0",X"D5",X"3C",X"12",X"11",X"04",X"00",X"19",X"E5",X"21", - X"28",X"1E",X"11",X"B8",X"3E",X"CD",X"30",X"01",X"21",X"71",X"20",X"5E",X"16",X"00",X"2B",X"E5", - X"21",X"E8",X"19",X"06",X"28",X"C3",X"09",X"16",X"21",X"0C",X"20",X"DB",X"02",X"2F",X"47",X"DB", - X"02",X"2F",X"B8",X"C0",X"E6",X"40",X"47",X"AE",X"C8",X"70",X"78",X"A7",X"C8",X"3E",X"0C",X"D3", - X"03",X"01",X"64",X"00",X"D3",X"04",X"05",X"C2",X"B4",X"16",X"0D",X"C2",X"B4",X"16",X"3E",X"08", - X"D3",X"03",X"21",X"12",X"20",X"34",X"21",X"BA",X"1D",X"CD",X"87",X"1C",X"3A",X"0A",X"20",X"A7", - X"C0",X"21",X"E7",X"1A",X"22",X"06",X"20",X"31",X"00",X"24",X"C3",X"7E",X"0F",X"3A",X"44",X"20", - X"A7",X"C8",X"11",X"08",X"20",X"01",X"29",X"20",X"CD",X"44",X"1C",X"21",X"29",X"20",X"11",X"0F", - X"24",X"3E",X"02",X"C3",X"30",X"01",X"21",X"7F",X"20",X"7E",X"A7",X"F0",X"23",X"23",X"23",X"7E", - X"FE",X"17",X"D2",X"08",X"17",X"3E",X"B6",X"77",X"EB",X"21",X"72",X"19",X"01",X"77",X"19",X"23", - X"03",X"BE",X"DA",X"0F",X"17",X"EB",X"0A",X"2B",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C8", - X"36",X"00",X"1F",X"F5",X"DC",X"54",X"17",X"F1",X"1F",X"F5",X"DC",X"A8",X"17",X"F1",X"1F",X"F5", - X"DC",X"4F",X"17",X"F1",X"1F",X"F5",X"DC",X"49",X"18",X"F1",X"1F",X"F5",X"DC",X"8A",X"18",X"F1", - X"1F",X"DC",X"1B",X"19",X"1F",X"F5",X"DC",X"10",X"19",X"F1",X"1F",X"DC",X"23",X"19",X"C9",X"3E", - X"08",X"D3",X"03",X"C9",X"21",X"13",X"20",X"06",X"08",X"7E",X"07",X"07",X"07",X"AE",X"17",X"17", - X"21",X"13",X"20",X"7E",X"17",X"77",X"23",X"7E",X"17",X"77",X"05",X"C2",X"59",X"17",X"F6",X"02", - X"E6",X"1F",X"32",X"28",X"20",X"E6",X"07",X"4F",X"06",X"00",X"21",X"74",X"1A",X"09",X"46",X"21", - X"5E",X"20",X"7E",X"FE",X"A0",X"DA",X"8A",X"17",X"06",X"01",X"FE",X"18",X"D2",X"91",X"17",X"06", - X"02",X"2B",X"7E",X"FE",X"38",X"DA",X"9A",X"17",X"06",X"04",X"FE",X"10",X"D2",X"A1",X"17",X"06", - X"08",X"2B",X"7E",X"E6",X"F0",X"B0",X"77",X"C9",X"3A",X"09",X"20",X"F6",X"20",X"32",X"27",X"20", - X"AF",X"CD",X"C2",X"17",X"32",X"5F",X"20",X"21",X"5C",X"20",X"7E",X"E6",X"0F",X"B0",X"77",X"C3", - X"D5",X"15",X"F5",X"21",X"5D",X"20",X"4E",X"23",X"5E",X"21",X"6F",X"20",X"46",X"23",X"56",X"CD", - X"EF",X"17",X"C6",X"14",X"21",X"7A",X"1A",X"23",X"23",X"BE",X"23",X"DA",X"D7",X"17",X"F1",X"A7", - X"CA",X"E4",X"17",X"23",X"7E",X"4F",X"17",X"17",X"17",X"17",X"E6",X"F0",X"47",X"79",X"C9",X"7A", - X"93",X"C8",X"5F",X"9F",X"57",X"21",X"00",X"00",X"3E",X"06",X"19",X"3D",X"C2",X"FA",X"17",X"7C"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd deleted file mode 100644 index 1c8074d2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romg.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity romg is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of romg is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0", - X"00",X"FC",X"07",X"FE",X"7F",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE", - X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8", - X"00",X"60",X"00",X"F0",X"E0",X"FC",X"3F",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9", - X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8", - X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"70",X"FC",X"1F",X"FE",X"07",X"FF",X"00",X"F9", - X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8", - X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"E0",X"F0",X"1C",X"FC",X"07",X"FE", - X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50", - X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8",X"40",X"F8",X"61",X"F8",X"30",X"60",X"18",X"F0", - X"0C",X"FC",X"07",X"FE",X"03",X"FF",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE", - X"01",X"02",X"09",X"FC",X"01",X"F8",X"03",X"98",X"03",X"18",X"07",X"1C",X"07",X"8E",X"03",X"86", - X"01",X"C7",X"01",X"9E",X"07",X"02",X"09",X"FC",X"01",X"F8",X"01",X"F8",X"01",X"F0",X"01",X"E0", - X"01",X"E0",X"00",X"C0",X"00",X"E0",X"00",X"C0",X"03",X"02",X"09",X"FC",X"00",X"F8",X"01",X"F0", - X"03",X"C8",X"07",X"9C",X"07",X"0E",X"03",X"06",X"03",X"87",X"03",X"3E",X"0F",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", - X"00",X"FE",X"01",X"7F",X"03",X"79",X"04",X"79",X"08",X"79",X"10",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", - X"00",X"FE",X"03",X"7F",X"0F",X"79",X"38",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"00",X"FC", - X"07",X"FE",X"3F",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"00",X"30",X"78",X"FC", - X"0F",X"FE",X"00",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"18",X"30",X"0E",X"FC", - X"07",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"01",X"58",X"00",X"F8",X"00",X"78",X"18",X"30",X"0E",X"FC", - X"07",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"0F",X"28", - X"00",X"68",X"00",X"78",X"00",X"FE",X"11",X"58",X"08",X"F8",X"04",X"78",X"02",X"30",X"03",X"FC", - X"01",X"FE",X"01",X"7F",X"00",X"79",X"00",X"79",X"00",X"79",X"00",X"7E",X"00",X"02",X"07",X"7E", - X"00",X"EC",X"00",X"CC",X"01",X"8C",X"01",X"C6",X"00",X"63",X"00",X"CE",X"01",X"02",X"07",X"7C", - X"00",X"78",X"00",X"78",X"00",X"70",X"00",X"30",X"00",X"20",X"00",X"E0",X"00",X"02",X"07",X"7E", - X"00",X"F8",X"00",X"E0",X"01",X"CC",X"01",X"86",X"00",X"C3",X"00",X"8E",X"03",X"02",X"0E",X"14", - X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"7C", - X"00",X"FE",X"00",X"3F",X"01",X"3D",X"02",X"3D",X"04",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34", - X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"FC",X"00",X"FE", - X"03",X"3F",X"0E",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C", - X"00",X"FF",X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"00",X"FC",X"01",X"FE",X"0F",X"3F", - X"00",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF", - X"00",X"2C",X"00",X"7C",X"00",X"3C",X"00",X"18",X"0E",X"FC",X"03",X"7E",X"00",X"3F",X"00",X"3D", - X"00",X"3D",X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C", - X"00",X"7C",X"00",X"3C",X"00",X"18",X"0E",X"FC",X"03",X"FE",X"00",X"3F",X"00",X"3D",X"00",X"3D", - X"00",X"3D",X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2C",X"00",X"7C", - X"00",X"3C",X"08",X"18",X"06",X"FC",X"03",X"FE",X"00",X"3F",X"00",X"3D",X"00",X"3D",X"00",X"3D", - X"00",X"02",X"0E",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"04",X"2C",X"02",X"7C",X"02",X"3C", - X"01",X"98",X"01",X"FC",X"00",X"7E",X"00",X"3F",X"00",X"3D",X"00",X"3D",X"00",X"3D",X"00",X"01", - X"05",X"7E",X"64",X"32",X"11",X"77",X"01",X"05",X"3E",X"38",X"18",X"10",X"70",X"01",X"05",X"7E", - X"70",X"26",X"21",X"E7",X"01",X"1A",X"18",X"38",X"38",X"38",X"38",X"38",X"3A",X"3A",X"BE",X"B8", - X"B8",X"F8",X"FB",X"3B",X"3B",X"3B",X"3F",X"3C",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38", - X"01",X"15",X"08",X"18",X"18",X"18",X"18",X"1A",X"1E",X"D8",X"58",X"78",X"78",X"19",X"19",X"1F", - X"1E",X"18",X"18",X"18",X"18",X"18",X"18",X"01",X"0F",X"10",X"10",X"10",X"18",X"50",X"70",X"14", - X"14",X"14",X"1C",X"10",X"10",X"10",X"10",X"10",X"03",X"1C",X"00",X"7E",X"00",X"80",X"FF",X"01", - X"E0",X"FF",X"07",X"F0",X"FF",X"0F",X"F0",X"FF",X"0F",X"F8",X"FF",X"1F",X"F8",X"FF",X"1F",X"F8", - X"FF",X"1F",X"F8",X"E7",X"1F",X"F0",X"C3",X"0F",X"F0",X"81",X"0F",X"E0",X"81",X"07",X"C0",X"81", - X"03",X"80",X"C3",X"01",X"F0",X"FF",X"0F",X"E0",X"FF",X"07",X"E0",X"FF",X"07",X"F4",X"FF",X"2F", - X"84",X"C3",X"21",X"04",X"81",X"20",X"04",X"81",X"20",X"06",X"81",X"60",X"F7",X"FF",X"EF",X"06", - X"81",X"60",X"04",X"00",X"20",X"04",X"00",X"20",X"04",X"00",X"20",X"04",X"00",X"20",X"03",X"19", - X"00",X"1E",X"00",X"80",X"7F",X"00",X"C0",X"FF",X"00",X"E0",X"FF",X"01",X"F0",X"FF",X"03",X"F0", - X"FF",X"03",X"F8",X"F3",X"07",X"F8",X"E1",X"07",X"F8",X"C0",X"07",X"F0",X"C0",X"03",X"E0",X"C0", - X"01",X"C0",X"E1",X"00",X"80",X"7F",X"00",X"F0",X"FF",X"03",X"E0",X"FF",X"01",X"E0",X"FF",X"01", - X"F4",X"FF",X"0B",X"C4",X"E1",X"08",X"84",X"40",X"08",X"86",X"40",X"18",X"F7",X"FF",X"3B",X"86", - X"40",X"18",X"04",X"00",X"08",X"04",X"00",X"08",X"04",X"00",X"08",X"02",X"13",X"E0",X"03",X"F8", - X"0F",X"FC",X"1F",X"7C",X"1F",X"3E",X"3E",X"1E",X"3C",X"1E",X"3C",X"3C",X"1E",X"F8",X"0F",X"F0", - X"07",X"FC",X"1F",X"F8",X"0F",X"FD",X"5F",X"39",X"4E",X"11",X"44",X"FD",X"5F",X"11",X"44",X"01", - X"40",X"01",X"40",X"02",X"0F",X"C0",X"01",X"F0",X"07",X"F8",X"0F",X"78",X"0F",X"3C",X"1E",X"38", - X"0E",X"70",X"07",X"E0",X"03",X"F8",X"0F",X"F0",X"07",X"3A",X"2E",X"12",X"24",X"FB",X"6F",X"02", - X"20",X"02",X"20",X"02",X"0B",X"20",X"00",X"F8",X"00",X"FC",X"01",X"DE",X"03",X"8E",X"03",X"DC", - X"01",X"F8",X"00",X"DC",X"01",X"89",X"04",X"FD",X"05",X"01",X"04",X"03",X"20",X"04",X"00",X"00", - X"19",X"02",X"00",X"7A",X"01",X"00",X"FC",X"00",X"00",X"7E",X"05",X"00",X"FE",X"03",X"80",X"FC", - X"03",X"40",X"FE",X"07",X"68",X"F9",X"03",X"3E",X"F0",X"FF",X"0F",X"A0",X"FF",X"03",X"80",X"FF", - X"00",X"80",X"FF",X"00",X"C0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"01",X"70",X"FF",X"03", - X"30",X"FE",X"07",X"30",X"FC",X"0F",X"30",X"FE",X"0F",X"30",X"FE",X"0F",X"30",X"F8",X"0F",X"20", - X"F0",X"07",X"00",X"F0",X"07",X"00",X"F0",X"07",X"00",X"C0",X"07",X"00",X"80",X"07",X"00",X"00", - X"07",X"00",X"00",X"03",X"00",X"40",X"03",X"00",X"80",X"03",X"00",X"00",X"0F",X"02",X"19",X"14", - X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"3C",X"00",X"2E",X"00",X"7E",X"00",X"3C",X"40",X"18", - X"30",X"F8",X"1F",X"FC",X"07",X"FE",X"01",X"FE",X"01",X"F7",X"01",X"E3",X"03",X"C3",X"07",X"E3", - X"0F",X"E2",X"1F",X"82",X"1F",X"00",X"1F",X"00",X"1F",X"00",X"0E",X"00",X"0C",X"00",X"0E",X"00", - X"3C",X"02",X"13",X"14",X"00",X"34",X"00",X"3C",X"00",X"FF",X"00",X"2E",X"00",X"7E",X"00",X"38", - X"10",X"18",X"0C",X"FC",X"07",X"7E",X"00",X"7A",X"00",X"F2",X"01",X"F2",X"01",X"E0",X"03",X"E0", - X"03",X"C0",X"01",X"80",X"01",X"C0",X"01",X"80",X"07",X"04",X"0B",X"A0",X"00",X"00",X"00",X"B0", - X"01",X"00",X"00",X"B0",X"01",X"3C",X"00",X"F0",X"01",X"7E",X"00",X"F9",X"13",X"FF",X"00",X"FF", - X"9F",X"FF",X"81",X"F8",X"C7",X"FF",X"9F",X"FC",X"FF",X"FF",X"FF",X"FE",X"FF",X"FF",X"FF",X"00", - X"00",X"FC",X"41",X"00",X"00",X"00",X"20",X"04",X"09",X"80",X"02",X"00",X"00",X"C0",X"06",X"00", - X"00",X"C0",X"07",X"1C",X"00",X"C8",X"27",X"3E",X"00",X"F8",X"3F",X"7F",X"10",X"E0",X"0F",X"FF", - X"13",X"F0",X"FF",X"FF",X"1F",X"F0",X"FF",X"FF",X"1F",X"00",X"00",X"7E",X"08",X"03",X"08",X"14", - X"00",X"00",X"34",X"00",X"00",X"3C",X"F0",X"00",X"FF",X"F8",X"41",X"3C",X"FC",X"4F",X"FE",X"FF", - X"7F",X"FE",X"FF",X"7F",X"00",X"E0",X"23",X"03",X"08",X"A0",X"00",X"00",X"A0",X"01",X"00",X"E0", - X"C1",X"01",X"F8",X"E7",X"43",X"E0",X"F1",X"4F",X"F0",X"FF",X"7F",X"F0",X"FF",X"7F",X"00",X"C0", - X"23",X"02",X"07",X"0A",X"00",X"1A",X"00",X"1E",X"00",X"7F",X"8E",X"1E",X"9F",X"FF",X"FF",X"00", - X"40",X"02",X"16",X"01",X"04",X"08",X"1E",X"3C",X"0F",X"F8",X"4F",X"FC",X"07",X"FE",X"07",X"7F", - X"0F",X"FE",X"3F",X"FC",X"7F",X"F0",X"3F",X"F9",X"39",X"F8",X"7F",X"D0",X"3F",X"FC",X"0F",X"FC", - X"47",X"FE",X"07",X"FF",X"0D",X"E4",X"1F",X"C2",X"3F",X"C9",X"77",X"80",X"03",X"80",X"21",X"06", - X"24",X"30",X"00",X"00",X"00",X"00",X"0C",X"F0",X"01",X"00",X"00",X"80",X"0F",X"F0",X"1F",X"00", - X"00",X"F8",X"0F",X"E0",X"FF",X"FF",X"FF",X"FF",X"07",X"E0",X"FF",X"FF",X"FF",X"FF",X"07",X"E0", - X"FF",X"FF",X"FF",X"FF",X"07",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF", - X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"80",X"FF",X"FF",X"FF",X"FF",X"01",X"80",X"FF",X"FF", - X"FF",X"FF",X"01",X"80",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00", - X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF", - X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"C0",X"FF",X"FF",X"FF",X"FF",X"03",X"00", - X"7C",X"00",X"00",X"3E",X"00",X"00",X"93",X"01",X"80",X"C9",X"00",X"80",X"10",X"02",X"40",X"08", - X"01",X"40",X"11",X"05",X"A0",X"88",X"02",X"40",X"92",X"04",X"20",X"49",X"02",X"20",X"54",X"08", - X"10",X"2A",X"04",X"20",X"38",X"08",X"10",X"1C",X"04",X"F0",X"EF",X"1F",X"F8",X"F7",X"0F",X"20", - X"38",X"08",X"10",X"1C",X"04",X"20",X"54",X"08",X"10",X"2A",X"04",X"40",X"92",X"04",X"20",X"49", - X"02",X"40",X"11",X"05",X"A0",X"88",X"02",X"80",X"10",X"02",X"40",X"08",X"01",X"00",X"93",X"01", - X"80",X"C9",X"00",X"00",X"7C",X"00",X"00",X"3E",X"00",X"01",X"0F",X"18",X"3C",X"7E",X"FF",X"E7", - X"E7",X"81",X"81",X"E7",X"E7",X"E7",X"E7",X"E7",X"FF",X"FF",X"CD",X"F5",X"0E",X"11",X"0B",X"20", - X"1A",X"EE",X"FF",X"12",X"C2",X"EC",X"0E",X"CD",X"40",X"10",X"CD",X"E6",X"0F",X"C3",X"EC",X"0E", - X"3A",X"0B",X"20",X"A7",X"CA",X"DE",X"0E",X"CD",X"40",X"10",X"CD",X"A0",X"13",X"CD",X"B7",X"0F", - X"CD",X"B0",X"14",X"CD",X"29",X"15",X"CD",X"63",X"10",X"22",X"52",X"20",X"CD",X"60",X"12",X"21", - X"00",X"00",X"22",X"33",X"20",X"2A",X"52",X"20",X"CD",X"2D",X"11",X"C3",X"EC",X"0E",X"2A",X"52", - X"20",X"E5",X"CD",X"D0",X"10",X"CD",X"09",X"11",X"E1",X"CD",X"7B",X"10",X"CD",X"98",X"16",X"E1", - X"D1",X"C1",X"F1",X"FB",X"C9",X"21",X"02",X"20",X"7E",X"A7",X"CA",X"FF",X"0E",X"35",X"C9",X"23", - X"7E",X"A7",X"CA",X"0C",X"0F",X"35",X"2B",X"3A",X"05",X"20",X"77",X"C9",X"23",X"7E",X"A7",X"CA", - X"18",X"0F",X"35",X"3E",X"00",X"D3",X"05",X"C9",X"2A",X"00",X"20",X"7E",X"A7",X"C2",X"2C",X"0F", - X"3E",X"00",X"D3",X"05",X"3A",X"0A",X"20",X"A7",X"C0",X"D3",X"03",X"C9",X"F2",X"3B",X"0F",X"E6", - X"7F",X"32",X"05",X"20",X"23",X"22",X"00",X"20",X"C3",X"1B",X"0F",X"32",X"03",X"20",X"23",X"3A", - X"05",X"20",X"3D",X"32",X"02",X"20",X"3E",X"01",X"32",X"04",X"20",X"7E",X"23",X"22",X"00",X"20", - X"E6",X"7F",X"07",X"4F",X"06",X"00",X"21",X"50",X"1D",X"09",X"7E",X"D3",X"05",X"23",X"7E",X"D3", - X"06",X"C9",X"31",X"00",X"24",X"CD",X"49",X"12",X"AF",X"06",X"13",X"11",X"00",X"20",X"12",X"13", - X"05",X"C2",X"6E",X"0F",X"3D",X"12",X"13",X"12",X"21",X"91",X"1A",X"22",X"06",X"20",X"21",X"7E", - X"0F",X"E5",X"FB",X"D3",X"04",X"2A",X"06",X"20",X"7E",X"A7",X"CA",X"9F",X"0F",X"23",X"22",X"06", - X"20",X"EB",X"21",X"51",X"19",X"07",X"4F",X"06",X"00",X"09",X"7E",X"23",X"66",X"6F",X"E9",X"CD", - X"F3",X"12",X"CD",X"1A",X"17",X"CD",X"F6",X"16",X"CD",X"EB",X"14",X"3A",X"0A",X"20",X"A7",X"C8", - X"CD",X"5A",X"15",X"CD",X"DD",X"16",X"C9",X"21",X"86",X"20",X"11",X"0B",X"00",X"19",X"E5",X"CD", - X"D8",X"0F",X"E1",X"01",X"EF",X"00",X"FE",X"70",X"D2",X"CD",X"0F",X"06",X"10",X"7E",X"A1",X"B0", - X"77",X"7D",X"FE",X"B2",X"C2",X"BA",X"0F",X"C9",X"7E",X"A7",X"F0",X"23",X"7E",X"23",X"86",X"77", - X"23",X"7E",X"23",X"86",X"77",X"C9",X"21",X"4B",X"20",X"7E",X"A7",X"C0",X"47",X"21",X"09",X"20", - X"35",X"C2",X"14",X"10",X"36",X"1E",X"3A",X"45",X"20",X"A7",X"C2",X"0E",X"10",X"21",X"08",X"20"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd deleted file mode 100644 index d1853f40..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/roms/romh.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity romh is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of romh is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"AF",X"D3",X"03",X"C3",X"17",X"00",X"F5",X"C5",X"D5",X"E5",X"C3",X"9A",X"0E",X"00", - X"F5",X"C5",X"D5",X"E5",X"C3",X"B0",X"0E",X"DB",X"02",X"E6",X"10",X"CA",X"62",X"0F",X"06",X"01", - X"11",X"00",X"00",X"21",X"00",X"20",X"D3",X"04",X"70",X"7E",X"A8",X"CA",X"3D",X"00",X"4F",X"7D", - X"E6",X"01",X"79",X"C2",X"3B",X"00",X"B2",X"57",X"C3",X"3D",X"00",X"B3",X"5F",X"23",X"7C",X"FE", - X"40",X"C2",X"26",X"00",X"D3",X"04",X"2B",X"7C",X"FE",X"1F",X"CA",X"7A",X"00",X"7E",X"A8",X"CA", - X"61",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"5F",X"00",X"B2",X"57",X"C3",X"61",X"00",X"B3", - X"5F",X"78",X"2F",X"77",X"AE",X"CA",X"44",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"75",X"00", - X"B2",X"57",X"C3",X"77",X"00",X"B3",X"5F",X"C3",X"44",X"00",X"D3",X"04",X"23",X"7C",X"FE",X"40", - X"CA",X"9D",X"00",X"78",X"2F",X"AE",X"CA",X"98",X"00",X"4F",X"7D",X"E6",X"01",X"79",X"C2",X"96", - X"00",X"B2",X"57",X"C3",X"98",X"00",X"B3",X"5F",X"AF",X"77",X"C3",X"7A",X"00",X"78",X"07",X"47", - X"D2",X"23",X"00",X"7A",X"B3",X"CA",X"CC",X"00",X"EB",X"F9",X"11",X"00",X"20",X"06",X"00",X"21", - X"00",X"00",X"39",X"0E",X"10",X"AF",X"29",X"DA",X"BB",X"00",X"2F",X"12",X"13",X"3E",X"08",X"12", - X"13",X"0D",X"C2",X"B5",X"00",X"05",X"C2",X"AF",X"00",X"C3",X"1A",X"01",X"31",X"00",X"24",X"21", - X"00",X"00",X"11",X"00",X"00",X"0E",X"04",X"AF",X"86",X"D3",X"04",X"23",X"47",X"79",X"BC",X"78", - X"C2",X"D8",X"00",X"E5",X"21",X"1F",X"01",X"19",X"BE",X"3E",X"40",X"CA",X"F7",X"00",X"21",X"00", - X"20",X"34",X"21",X"28",X"01",X"19",X"7E",X"21",X"29",X"20",X"19",X"77",X"E1",X"13",X"0C",X"0C", - X"0C",X"0C",X"3E",X"24",X"B9",X"C2",X"D7",X"00",X"21",X"29",X"20",X"3A",X"00",X"20",X"A7",X"CA", - X"00",X"00",X"11",X"08",X"30",X"3E",X"08",X"CD",X"30",X"01",X"D3",X"04",X"C3",X"1A",X"01",X"00", - X"CA",X"40",X"19",X"47",X"E8",X"B8",X"00",X"BC",X"48",X"48",X"47",X"47",X"46",X"46",X"45",X"44", - X"F5",X"7E",X"23",X"A7",X"FA",X"31",X"01",X"D6",X"30",X"F2",X"4D",X"01",X"47",X"13",X"7B",X"E6", - X"1F",X"C2",X"46",X"01",X"14",X"14",X"04",X"C2",X"3D",X"01",X"C3",X"31",X"01",X"E5",X"D5",X"3C", - X"FE",X"0B",X"FA",X"57",X"01",X"D6",X"06",X"21",X"71",X"01",X"01",X"0A",X"00",X"09",X"3D",X"C2", - X"5D",X"01",X"EB",X"01",X"20",X"00",X"3E",X"0A",X"F5",X"1A",X"13",X"77",X"09",X"F1",X"3D",X"C2", - X"68",X"01",X"D1",X"E1",X"13",X"F1",X"3D",X"C2",X"30",X"01",X"C9",X"3C",X"7E",X"66",X"66",X"66", - X"66",X"66",X"66",X"7E",X"3C",X"18",X"1C",X"18",X"18",X"18",X"18",X"18",X"18",X"3C",X"3C",X"3C", - X"7E",X"66",X"60",X"7C",X"3E",X"06",X"06",X"7E",X"7E",X"3C",X"7E",X"66",X"60",X"38",X"78",X"60", - X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"7E",X"7E",X"60",X"60",X"60",X"60",X"3E",X"3E",X"06", - X"06",X"3E",X"7E",X"60",X"66",X"7E",X"3C",X"3C",X"3E",X"06",X"06",X"3E",X"7E",X"66",X"66",X"7E", - X"3C",X"7E",X"7E",X"60",X"70",X"30",X"38",X"18",X"1C",X"0C",X"0C",X"3C",X"7E",X"66",X"66",X"3C", - X"7E",X"66",X"66",X"7E",X"3C",X"3C",X"7E",X"66",X"66",X"7E",X"7C",X"60",X"60",X"7C",X"3C",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"3C",X"7E",X"66",X"66",X"66",X"7E", - X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"3C",X"7E",X"66", - X"06",X"06",X"06",X"06",X"66",X"7E",X"3C",X"3E",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E", - X"3E",X"7E",X"7E",X"06",X"06",X"3E",X"3E",X"06",X"06",X"7E",X"7E",X"7E",X"7E",X"06",X"06",X"3E", - X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"06",X"06",X"76",X"76",X"66",X"7E",X"3C",X"66", - X"66",X"66",X"66",X"7E",X"7E",X"66",X"66",X"66",X"66",X"3C",X"3C",X"18",X"18",X"18",X"18",X"18", - X"18",X"3C",X"3C",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"66",X"7E",X"3C",X"66",X"66",X"76", - X"3E",X"1E",X"1E",X"3E",X"76",X"66",X"66",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"7E", - X"7E",X"C3",X"C3",X"E7",X"E7",X"FF",X"FF",X"DB",X"C3",X"C3",X"C3",X"66",X"66",X"6E",X"6E",X"7E", - X"7E",X"76",X"76",X"66",X"66",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"3E", - X"7E",X"66",X"66",X"7E",X"3E",X"06",X"06",X"06",X"06",X"3C",X"7E",X"66",X"66",X"66",X"66",X"66", - X"66",X"7E",X"5C",X"3E",X"7E",X"66",X"66",X"7E",X"3E",X"76",X"66",X"66",X"66",X"3C",X"7E",X"66", - X"06",X"3E",X"7C",X"60",X"66",X"7E",X"3C",X"7E",X"7E",X"18",X"18",X"18",X"18",X"18",X"18",X"18", - X"18",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"7E",X"3C",X"66",X"66",X"66",X"66",X"66", - X"7E",X"3C",X"3C",X"18",X"18",X"C3",X"C3",X"C3",X"DB",X"FF",X"FF",X"E7",X"E7",X"C3",X"C3",X"66", - X"66",X"7E",X"3C",X"18",X"18",X"3C",X"7E",X"66",X"66",X"66",X"66",X"7E",X"3C",X"18",X"18",X"18", - X"18",X"18",X"18",X"7E",X"7E",X"60",X"70",X"38",X"1C",X"0E",X"06",X"7E",X"7E",X"C0",X"C0",X"C0", - X"C0",X"C0",X"C0",X"00",X"00",X"C0",X"C0",X"10",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38", - X"7C",X"47",X"03",X"51",X"03",X"79",X"03",X"6F",X"03",X"8D",X"03",X"5B",X"03",X"83",X"03",X"65", - X"03",X"97",X"03",X"A1",X"03",X"AB",X"03",X"29",X"03",X"33",X"03",X"3D",X"03",X"1F",X"03",X"89", - X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"89",X"0E",X"81",X"0D",X"81",X"0D",X"81",X"0D",X"81", - X"0D",X"81",X"0D",X"2B",X"0C",X"2B",X"0C",X"8D",X"0C",X"8D",X"0C",X"C1",X"0C",X"E9",X"0C",X"17", - X"0D",X"3D",X"0D",X"57",X"0D",X"71",X"0D",X"28",X"0B",X"7E",X"0B",X"CB",X"0B",X"F3",X"0B",X"13", - X"0C",X"C1",X"03",X"D6",X"05",X"B5",X"07",X"ED",X"08",X"FD",X"09",X"02",X"04",X"11",X"06",X"D9", - X"07",X"0D",X"09",X"1B",X"0A",X"43",X"04",X"4C",X"06",X"FD",X"07",X"2D",X"09",X"39",X"0A",X"84", - X"04",X"87",X"06",X"21",X"08",X"4D",X"09",X"57",X"0A",X"C5",X"04",X"C2",X"06",X"45",X"08",X"6D", - X"09",X"75",X"0A",X"06",X"05",X"FD",X"06",X"69",X"08",X"8D",X"09",X"93",X"0A",X"47",X"05",X"38", - X"07",X"8D",X"08",X"AD",X"09",X"B1",X"0A",X"88",X"05",X"73",X"07",X"B1",X"08",X"CD",X"09",X"CF", - X"0A",X"A2",X"05",X"89",X"07",X"C5",X"08",X"DD",X"09",X"D6",X"0A",X"BC",X"05",X"9F",X"07",X"D9", - X"08",X"ED",X"09",X"DD",X"0A",X"CD",X"09",X"DD",X"09",X"ED",X"09",X"CF",X"0A",X"D6",X"0A",X"DD", - X"0A",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00",X"C8", - X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0",X"1F", - X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F",X"00", - X"CE",X"FF",X"01",X"C6",X"FF",X"03",X"C6",X"1F",X"17",X"C6",X"1F",X"0E",X"C6",X"1F",X"14",X"FA", - X"3F",X"20",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F",X"00", - X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00",X"C0", - X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC",X"7F", - X"00",X"CE",X"FF",X"01",X"C6",X"FF",X"07",X"C6",X"1F",X"1E",X"C6",X"1F",X"70",X"C6",X"1F",X"00", - X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80",X"0F", - X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F",X"00", - X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"00",X"80",X"0F",X"00",X"F8",X"3F",X"00",X"FC", - X"FF",X"01",X"CE",X"FF",X"0F",X"C6",X"1F",X"7F",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F", - X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00",X"80", - X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0",X"7F", - X"00",X"C0",X"1F",X"00",X"80",X"1F",X"00",X"00",X"07",X"08",X"80",X"0F",X"F0",X"F8",X"FF",X"1F", - X"FC",X"FF",X"0F",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6", - X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D",X"00", - X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00",X"C0", - X"7F",X"00",X"C0",X"1F",X"00",X"80",X"1F",X"C0",X"00",X"07",X"38",X"80",X"0F",X"0C",X"F8",X"FF", - X"0F",X"FC",X"FF",X"03",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00", - X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80",X"0D", - X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"00",X"C0",X"3F",X"00", - X"C0",X"7F",X"00",X"C0",X"1F",X"C0",X"80",X"1F",X"70",X"00",X"07",X"3C",X"80",X"0F",X"0F",X"F8", - X"FF",X"03",X"FC",X"FF",X"01",X"CE",X"FF",X"00",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6",X"1F", - X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"03",X"15",X"00",X"05",X"00",X"80",X"0D",X"00",X"80", - X"0D",X"00",X"80",X"0F",X"00",X"C8",X"9F",X"00",X"F8",X"FF",X"00",X"C0",X"17",X"80",X"C0",X"3F", - X"50",X"C0",X"7F",X"60",X"C0",X"1F",X"30",X"80",X"1F",X"38",X"00",X"07",X"1C",X"80",X"0F",X"0E", - X"F8",X"FF",X"07",X"FC",X"FF",X"03",X"CE",X"FF",X"01",X"C6",X"1F",X"00",X"C6",X"1F",X"00",X"C6", - X"1F",X"00",X"C6",X"1F",X"00",X"FA",X"3F",X"00",X"02",X"0C",X"F0",X"3F",X"F0",X"3F",X"E0",X"3D", - X"C0",X"79",X"C0",X"71",X"C0",X"E1",X"C0",X"E1",X"E0",X"60",X"70",X"70",X"34",X"34",X"38",X"38", - X"F0",X"F0",X"02",X"0C",X"F0",X"3F",X"E0",X"3F",X"C0",X"1F",X"C0",X"1F",X"C0",X"1F",X"00",X"1F", - X"00",X"1E",X"00",X"1C",X"00",X"0C",X"00",X"0D",X"00",X"0E",X"00",X"3C",X"02",X"0C",X"F0",X"3F", - X"F0",X"3F",X"E0",X"1F",X"C0",X"0F",X"80",X"1F",X"00",X"3E",X"C0",X"7D",X"E0",X"78",X"70",X"30", - X"34",X"34",X"38",X"38",X"F0",X"F0",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03", - X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00", - X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"3F",X"00",X"F3", - X"7F",X"00",X"F3",X"E3",X"02",X"F3",X"C3",X"01",X"F1",X"83",X"02",X"FE",X"03",X"04",X"FC",X"07", - X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC", - X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01", - X"00",X"E0",X"03",X"00",X"FC",X"0F",X"00",X"FE",X"1F",X"00",X"F3",X"7F",X"00",X"F3",X"E3",X"01", - X"F3",X"03",X"07",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01", - X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00", - X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"00",X"C0",X"01",X"00",X"E0",X"03",X"00",X"FC", - X"1F",X"00",X"FE",X"FF",X"00",X"F3",X"FF",X"07",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03", - X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0", - X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03", - X"00",X"E0",X"03",X"00",X"C0",X"01",X"01",X"E0",X"03",X"1E",X"FC",X"FF",X"03",X"FE",X"FF",X"03", - X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC", - X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00", - X"FC",X"1F",X"00",X"E0",X"02",X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"0C",X"C0", - X"81",X"03",X"E0",X"C3",X"00",X"FC",X"FF",X"00",X"FE",X"3F",X"00",X"F3",X"0F",X"00",X"F3",X"03", - X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40", - X"01",X"00",X"60",X"03",X"00",X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02", - X"00",X"E0",X"0F",X"00",X"E0",X"03",X"00",X"E0",X"03",X"06",X"C0",X"C1",X"03",X"E0",X"F3",X"00", - X"FC",X"3F",X"00",X"FE",X"1F",X"00",X"F3",X"0F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1", - X"03",X"00",X"FE",X"03",X"00",X"FC",X"07",X"00",X"03",X"13",X"40",X"01",X"00",X"60",X"03",X"00", - X"E0",X"03",X"00",X"F4",X"17",X"00",X"FC",X"1F",X"00",X"E0",X"02",X"04",X"E0",X"8F",X"06",X"E0", - X"03",X"03",X"E0",X"83",X"03",X"C0",X"C1",X"01",X"E0",X"E3",X"00",X"FC",X"7F",X"00",X"FE",X"3F", - X"00",X"F3",X"1F",X"00",X"F3",X"03",X"00",X"F3",X"03",X"00",X"F1",X"03",X"00",X"FE",X"03",X"00", - X"FC",X"07",X"00",X"02",X"0A",X"F8",X"07",X"70",X"0F",X"70",X"0E",X"70",X"1C",X"30",X"1C",X"38", - X"0C",X"1C",X"0E",X"0C",X"06",X"0E",X"07",X"3C",X"1E",X"02",X"0A",X"FC",X"03",X"F8",X"03",X"F0", - X"03",X"F0",X"03",X"C0",X"03",X"C0",X"03",X"80",X"03",X"80",X"01",X"C0",X"01",X"80",X"07",X"02", - X"0A",X"FC",X"03",X"F8",X"01",X"F0",X"00",X"E0",X"01",X"C8",X"03",X"9C",X"07",X"0E",X"07",X"06", - X"03",X"87",X"03",X"1E",X"0F",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8",X"00",X"FE",X"03",X"B8", - X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE",X"07",X"FF",X"06",X"F9", - X"0C",X"F9",X"18",X"F9",X"20",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50",X"00",X"D8",X"00",X"F8", - X"00",X"FE",X"03",X"B8",X"00",X"F8",X"01",X"F8",X"00",X"60",X"00",X"F0",X"00",X"FC",X"03",X"FE", - X"0F",X"FF",X"3C",X"F9",X"60",X"F9",X"00",X"F9",X"00",X"FE",X"01",X"FE",X"01",X"02",X"11",X"50"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf deleted file mode 100644 index e03e4c0b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "BowlingAlley" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf deleted file mode 100644 index 872504f6..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.qsf +++ /dev/null @@ -1,171 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 13:13:10 June 05, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Invaders_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BowlingAlley_memory.sv -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY BowlingAlley_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# --------------------------- -# start ENTITY(Invaders_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Invaders_mist) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/BowlingAlley.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt deleted file mode 100644 index 7f6452b7..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Bowling Alley port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- -ToDo: Color Prom - Controls + DIP - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf deleted file mode 100644 index 23ba8587..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/Snapshot/BowlingAlley.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv deleted file mode 100644 index 57bd1c17..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_memory.sv +++ /dev/null @@ -1,92 +0,0 @@ - -module BowlingAlley_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; - - -sprom #( - .init_file("./roms/h.cpu.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/g.cpu.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/f.cpu.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/e.cpu.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -sprom #( - .init_file("./roms/d.cpu.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_d ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_4) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv deleted file mode 100644 index a04fbd65..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/BowlingAlley_mist.sv +++ /dev/null @@ -1,196 +0,0 @@ -module BowlingAlley_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Bow.Alley;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire Video; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; - - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(btn_one_player), - .Sel2Player(btn_two_players), - .Fire(m_fire), - .Fire2(m_bomb), - .MoveLeft(m_left), - .MoveRight(m_right), - .DIP("00000000"), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -BowlingAlley_memory BowlingAlley_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B({Video,Video,Video}), - .HSync(~hs), - .VSync(~vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd deleted file mode 100644 index db58d70b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/dac.vhd +++ /dev/null @@ -1,48 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity dac is - generic ( - C_bits : integer := 8 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); -end dac; - -architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); -begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; -end rtl; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd deleted file mode 100644 index 0a4a7814..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,283 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - Fire2 : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(7 downto 0); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal GDB3 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - GDB3 when "11"; --- S when others; - - GDB0(0) <= '0'; -- Language - GDB0(1) <= '0'; -- Language - GDB0(2) <= '0'; -- Demo_Sounds - GDB0(3) <= '0'; -- Game_Time - GDB0(4) <= '0'; -- Coinage - GDB0(5) <= '0'; -- Difficulty - GDB0(6) <= '1'; -- Cabinet - GDB0(7) <= '1'; -- Unused - - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Fire; - GDB1(2) <= not Sel1Player; - GDB1(3) <= not Fire2; - GDB1(4) <= '1'; -- - GDB1(5) <= '1'; -- - GDB1(6) <= '1'; -- - GDB1(7) <= '1'; -- Unused ? - - GDB2(0) <= '1'; -- TRACKBALL Y - GDB2(1) <= '1'; -- TRACKBALL Y - GDB2(2) <= '1'; -- TRACKBALL Y - GDB2(3) <= '1'; -- TRACKBALL Y - GDB2(4) <= '0'; -- TRACKBALL Y - GDB2(5) <= '0'; -- TRACKBALL Y - GDB2(6) <= '0'; -- TRACKBALL Y - GDB2(7) <= '0'; -- TRACKBALL Y - - GDB3(0) <= '1'; -- TRACKBALL X - GDB3(1) <= '1'; -- TRACKBALL X - GDB3(2) <= '1'; -- TRACKBALL X - GDB3(3) <= '1'; -- TRACKBALL X - GDB3(4) <= '0'; -- TRACKBALL X - GDB3(5) <= '0'; -- TRACKBALL X - GDB3(6) <= '0'; -- TRACKBALL X - GDB3(7) <= '0'; -- TRACKBALL X - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex deleted file mode 100644 index 3bf22e70..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/d.cpu.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C03AAC22B7CAA7402139222200223A19AD -:100010002257FE01CA7740060A48592200223E0FA5 -:10002000CDC8007EB8F2294047237EB9F230404F58 -:10003000237EBBF237405F3E12CD184315C21B40F2 -:100040007B3225221E0FCD2845C26540411CCD289C -:1000500045C265401C3A252247CD2845C26540CDA2 -:100060000745C3A7403A1922572139222200227B93 -:10007000CD1B43B8CA9A403E06CD18433AAC2286FF -:100080003212203E923214203E0C3210203E0432B6 -:100090001F20C5D5CDE90001D1C13E12CD184315B1 -:1000A000C26C40AF32AC223A9222B7F2BD40210E70 -:1000B00033221622118309CDB303C345053A3722F3 -:1000C0003C323722FE0BCA45053D0707C688321071 -:1000D000203E2A3212203E9F3214203E04321F203E -:1000E000CDE900013A1020C604321020CDE900010C -:1000F000AF323622213922228122CDD1433A372212 -:10010000FE0ACA3141FE05C216413A9222B7C21D0B -:10011000413E01C348413A9222B7CA9D13210E3392 -:10012000221622118309CDB3033EFF329222C39DD2 -:1001300013211511CD4042219B22229822AF329AE1 -:10014000223EB0328B223E0932AC22210E0ACD4132 -:1001500044CD0745C39D133A342221302032032277 -:100160002200203E0FCD50023621CDEC003E10CDB6 -:1001700050023A03223DC25D41C9AF321122D3047D -:100180003A1122FE02DA7E41AF321122C9D5CDD515 -:1001900041D12A81223E01CDC8000602131A86FEF3 -:1001A0000AFAA941D60A23342B772305C29C41C3FE -:1001B000D541F5CDD541F12A81228623FE0AFAC721 -:1001C0004134D60AC3BC412B77237EFE0AFAD541BF -:1001D000D60A7723342A81223E06CDC8007EC60483 -:1001E0003212203EBF3214203E04321F20AF3207AD -:1001F000220103002A8122097EB7C204423A072263 -:10020000B7CA15427E0707C624320722321020C51E -:10021000CDE90001C11114201AD608120DF8C2F45C -:10022000413E01320722C3F4413E123212203ECA3F -:10023000321420228122CDE841213922228122C993 -:10024000111020AF321F2006057E1223131305C2A2 -:1002500049427E1B1223221C20CDE900013A1220C4 -:100260002116208632122023233A142086321420AD -:100270002335C25942D3042A1C207EFEFFC24042CD -:10028000C9EBCDC8004E2100000DFA914219C38977 -:10029000420E047CB7F29942371F677D1F6F0DC273 -:1002A0009342C9F5CD18434E2346F1D60BCD1843E2 -:1002B0007E8177237E8877C9F52A0422CDC8005E27 -:1002C0002356F1CD1843935F237E9A572100000DEA -:1002D000FAD74219C3CF423A2522B7F07C2F677D67 -:1002E0002F6F23C9320A222A00222200200600CDC5 -:1002F000C8005E23567AB7FAFF4205792F4F03EB09 -:1003000009EB722B730E02EBCD9342EB3A0A22C635 -:1003100007CD5002732372C92A0022856FD2214370 -:10032000247EB7C97CB7CA3543FEFFC07DFEF0D836 -:100330002600C339437DFE10D02E003A03223C3202 -:100340000322C93A8822B7C83A8322B7C02187223C -:1003500035F036102A84223A862207B7F263432109 -:100360005F450701050009228422328622F680D3E8 -:10037000077E32E420CDE9000E3E0532EF20C9F5BC -:10038000CD96432A81223E07CDC8000603F14E7761 -:10039000237905C28E432A81223E06CDC8007E3CC9 -:1003A0003212203E9D3214203E04321F203E023283 -:1003B0000322232289227E321020CDE900012A89DE -:1003C000223A1220C6083212203A03223DC2AF431D -:1003D000C9CDDA43C3E443CDE4433EB23214203EF8 -:1003E00078C3EB433E943214203E7C3210202A81A5 -:1003F000223E06CDC8007ED6073212203E04321FB0 -:1004000020CDE90001C93EB23214203E80C3EB4347 -:100410002A8E22CD4144214009228E22C9218D22DB -:1004200035F036103A0922EE01320922CDD541CD00 -:10043000E443C9214022713E12CDC80005C23644B2 -:10044000C9228E22EB214A33221622CDB303C921C1 -:100450000E3322162211B0093A8822B7CA6244111B -:10046000D009CDB303CD1507C315072A98223A9EAC -:10047000227723229822219A22343210203E0532FC -:1004800012203A8B22321420D608328B223E0432BC -:100490001F20CDE90001C921B145C3A04421A345D6 -:1004A0003E0532A92222AA223EFF32A82221A922F9 -:1004B00035FACA442AAA22EB2122201A77132323D1 -:1004C0001A7713EB22AA22C3DA1A2AAA227E32381A -:1004D00020237E323920237E324820237E32492059 -:1004E000AF32A822D308D30AC3F3162A8122E5210A -:1004F000AD222281223E283212203E67321420CDC6 -:10050000E841E1228122C93A19224F2139222200F1 -:10051000223E0FCDC80036002336002336003E129F -:10052000CD18430DC20E45C92139223A1922577BF5 -:10053000CDC8007EB8C03E1293CDC80015C22F456D -:10054000C911580B21670B3A9422B7CA4F45EBE506 -:1005500021DC3F221622CDB30311220BCDB303D1F0 -:10056000CDB303C976000201016D000402026400EC -:100570000503035B0007050552000503034900045A -:100580000202400002010120FDEAFE48FB60FE205D -:10059000FD00FF00FAD8FE00FEC0FE70FCF0FE4831 -:1005A000FAA0FF1B301A2F182E162D142C00010351 -:1005B000001B6C1A6D186E166F1470FE000001752A -:1005C0006E6420474C4F42414C1D556E61626C6514 -:1005D00020746F2061737369676E20494E434C55D8 -:1005E00068452066696C6521526567697374657238 -:1005F0002065787072657373696F6E206973206E01 -:10060000CA56143A1522B7C25614C35414616C6901 -:100610006420726567697374657220706169722203 -:10062000526567697374657220657870726573735B -:10063000696F6E2067726561746572207468616E9F -:1006400020371A4D697373696E67206F7220696E67 -:1006500076616C6964206F706572616E64CA424F26 -:100660004C574F4225000009000006010000000021 -:10067000BE45C8D441524353FB0F0100200000C8BF -:1006800043414DD50F0100000000D9414C50B0024C -:100690000100240000CB43415453A8210100240051 -:1006A00000D4554F48538C030102000000CE494846 -:1006B000530A0F0101000000D254434853150F01A3 -:1006C00001000000D250575354B421010200000031 -:1006D000D34D5753542D0F0180000000C3534D4F8D -:1006E00052CD1E010C320000DA4953504843EE0F40 -:1006F0000100040000C44154534C2D0201FF1F00AF -:1007000000B04A424F750F0100200401C3454A4220 -:100710004F810F0100200401CF4E4A424FD33401D4 -:1007200002200401D443434D4C320105200401C38F -:100730004353D42E0107200401D4554F444E53E0B7 -:10074000170108200401CC5648444C4FBD0F010945 -:10075000200401CC5656444C4FD015010C20040106 -:10076000D44243454D57340102000000D2544E4359 -:100770004DC90F0105000000D25057534E43FF00F2 -:100780000104000000CB53414D43E20F0101000082 -:1007900000CE454552435361210100240000C4416D -:1007A000564D4711010F210401D354494253960F6E -:1007B0000111210401D4455345522D2E010000049E -:1007C00001C35653544E4977120110000401B1562B -:1007D00053544E492B100136000401B1544F4D497A -:1007E000548F260153000401D454414D49549B3782 -:1007F000015A000401C54C504D4153191B016400BE -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex deleted file mode 100644 index 2d1a15fc..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/e.cpu.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000CA051816043E09856F7EFEFECA3518B76C -:10001000C277183E0ECDA34282FE34D22318362674 -:10002000C32A18FE7BDA3518367F7AFE02CA5318C7 -:100030001EFEC36D183E0CCDA3424F82FE10D24669 -:10004000183602C353183A3322B7CA771879FE5CC0 -:10005000DA77181EFD0E013E0506042A0022856F80 -:1000600036002305C260183E0C0DCA59183E09D34C -:100070000A2A0022856F732A00227EFE6CC29F1816 -:100080003AA822B7CA9F1823237EFE1BC29C1823BE -:10009000237EFE72CA9744FE30CA9D442A00220184 -:1000A0001000093A03223DC2F5172120203A02220E -:1000B0003203222200223DCAD31A3208223E098589 -:1000C0006F7EB7FAC41A2A002232072201100009F3 -:1000D0002204223A0722473E09856F7EB7FAB71AF3 -:1000E000A0C2B71A3209222A042223234623234E10 -:1000F0002A002216097ED64CCAFF183E02160B3281 -:100100002E222323869047322422F216192F3C47B1 -:100110003E0132092278322C22BAD2B71A7A322F13 -:100120002223235621B01178856FD22E19245E3AEE -:100130002E2282914F322522F247192F3C4F3A0945 -:1001400022EE0132092279212F22BED2B71A322D96 -:10015000227E21AF11856FD25B19247EC6025779AA -:1001600021B011856FD26919247E83BAD2B71A3EA5 -:1001700007CDB842220F22EB220D22483A24223228 -:1001800025223E05CDB842EB220B222A0F22197CF4 -:10019000B7CA9719F2C41A2A04223E09CDC8007EB4 -:1001A000FE013600CAB1193E09CD1843FE01C2C393 -:1001B000193A2E22B7CABF19D308D30AC3C319D319 -:1001C00009D30A3E09CD184336002A0B22118011AB -:1001D0003A2E22B7CAE81978FE09FAE5193A2D2213 -:1001E000D60E2F3C4711921178CD8142220F221159 -:1001F00089113A2E22B7CAFC1911A111782A0D22B1 -:10020000CD8142EB3E05320A223283223A0922B7DF -:10021000CA1A1A7B2F5F7A2F57132A0F2219220F1F -:1002200022EB2A04223A0A22220020856F7E83775D -:100230005F237E8A7757CD05432A0F223A2E22B7B5 -:10024000CA5C1A3A0A22FE07C27C1A0E017CB7F277 -:10025000531A371F677D1F6F0DC24D1AEB2A0022FC -:100260002200203A0A22856F7E93775F237E9A7759 -:1002700057CD05433A0A22FE07CAB71A2A0D223A79 -:100280002E22B7CA8E1A3E0E119211C3931A1180F4 -:10029000113E0890CD8142220F223E07320A222AC7 -:1002A0000B221189113A2E22B7CAAF1A11A1117867 -:1002B000CD8142EBC30C1A2A04223A08223D3208AF -:1002C00022C2CC180110002A0022093A03223DC3A1 -:1002D000B0182B3A06223DC2EC17D3043A1122FE85 -:1002E00001DADA1A3A2220070707E607D306AF3207 -:1002F00011222120202200203E09CD5002B7C21930 -:100300001B3E06CD50021100FFB7F2111BBAC219F5 -:100310001B722B733E06CD05432120203A02222278 -:1003200000222200203203223E09CD1843CA3C1B82 -:10033000FEFECA3C1BFEFDC2A01B36FF2346234E19 -:100340002A00227EFE4CCA701B23237EB8C2571B94 -:1003500023237EB9CAA01B78FE58D2751B3A3422DB -:100360003C3202223233222A00227EFE6CCA751BE6 -:100370001621C3771B16053E0FCD1843F572CDEC41 -:10038000003E0FCD1843FE21C29E1B36042A0022D8 -:100390007EFE68C2981B3E48C60477C37E1BF17779 -:1003A0003E10CD18433A03223DC21F1BCD4343C329 -:1003B000F3163E05322F20CDE900020610CD7A411A -:1003C00005C2BD1B3A8822B7CAEC1B3A9622B7C2B7 -:1003D000EC1B3A1222B7C2E01B3A8322B7CAEC1BCD -:1003E0003E2132EF20329622CDE9000E2122203626 -:1003F0000123233625CD5741210E11CD4042CD7A20 -:1004000041212020220020CDEC003E0A320822AFFC -:10041000322E223A34224F3238222130201130201D -:100420003203222200203E09CD5002FE01C25B1C95 -:10043000D5C5CDEC00C1D1060F2A00207E122313B2 -:1004400005C23C1C3E0512133A0822FE0ACA5C1C77 -:10045000FE07CA5C1C322E22C35C1C0D3E10CD5020 -:10046000023A08223D3208223A03223DC2201C797A -:10047000FE02C2811C3A2E22B7C2811C3E0132A864 -:10048000223A1522B7CA8E1C2139222281222A81C2 -:10049000223E05CDC80079323422B7CAA31C3600EB -:1004A000C3F91C3A1222B7CABA1C360021A0083E72 -:1004B00024D30F3E20D306C3CF1C7EFE05CAC21C28 -:1004C0003C3421C11123233DC2C51C5E2356EBCD14 -:1004D00041443A8822B7CAF91C2A84223A1222B728 -:1004E000CAE51C232323EB21AD223600231A7723F0 -:1004F000131A77233600CDEB44CD7A412A81223A74 -:100500003522C60FCDC8003A3422473A38229077B8 -:10051000AFD3062A81223E05CDC8007EB7CA421D50 -:100520003E12D30FF33A0820F620D305320820FB01 -:10053000CD7A41CD7A41F33A0820E6DF320820D364 -:1005400005FB3E08D3063E0432DF203E3532D42080 -:100550003E3732D2203E1432D020CDE9000D212288 -:10056000207EC60477FEF3D29A1DFED0DA721DAF4C -:10057000D306CDE90002CD7A413AD220FE07CA5E09 -:100580001D3E1032D020CDE9000D3AD220D60132E6 -:10059000D220FE07C2521DC35E1D3A8822B7CAA8E8 -:1005A0001D3A3422B7CCEB44CD10443A1522B7CAD9 -:1005B0002B1E3A3422B7CACA1D3A1222B7C2C71D2F -:1005C0003C321222C38614CD57413A9122B7CAF168 -:1005D0001DF33A0820E604C2E51DF604320820D3D4 -:1005E00005FBC3F11DE6FB320820D305FBAF3291BA -:1005F00022CD4F443A8822EE01328822CD43073A79 -:100600008822B7CA1A1E3E0432EF2021A022CD292B -:100610004221A422CD2942C39D13D30721A422CD78 -:10062000294221A022CD2942C39D13213522343AEB -:100630003422473A3822904F3A1222B7CA541E3A0F -:100640003422B7CA541ECD7A413A3722FE0ACA5420 -:100650001ECD57413A3422473A382290473E0A2A63 -:100660008122CDC8007EB7CAAB1E237886772B3592 -:10067000CA781E2323C3651EE5C5237ECDB241CDB6 -:1006800096432A81223E09CDC8007EFE20C2941ED8 -:100690002BC38A1E3620CD9643C1E1545D13131A35 -:1006A00077AF1223131A772BC3651E2225223A3403 -:1006B00022B7CAF41E3A1222B7C2D31E3C3212220B -:1006C0003A3722FE0AC286143A3522FE03C2861445 -:1006D000C3621F3E20CD7F433A3522FE03CA621F0C -:1006E0003E0A21342296CDB2413A3722D60AC28739 -:1006F0001FC3621F3A1222B73E18CAFF1E3E1C32A9 -:100700009E22CD7F433A12224F3A3722FE0AC21A66 -:100710001FAF321222C5CD6B44C13A8822B7CA3905 -:100720001F2A84220DC22A1F2323EBCD8D413A3587 -:1007300022FE03CA621FC3511F3A3522FE03CA625A -:100740001F2A252236010DCA4B1F3423360A2336B1 -:10075000003A3722FE0AC2871F210909CD4144C34E -:10076000E9133A3422B7CA6F1FCD7A41CD57413AC7 -:100770003522FE03C2871F3A8822B7CA871F3E0A66 -:1007800021342296CDB241CDD743CD41453A3722CF -:10079000FE0AC2CE1F219B222298223E0532122041 -:1007A0003E04321F203EB0328B223214203A9A226D -:1007B0003DFACE1F329A227E32102023222522CDEE -:1007C000E900012A25223A1420D608C3AA1FAF3215 -:1007D0003522213622343A1922BECA01402A81220A -:1007E0003E12CDC800228122CDD143C39D13643770 -:1007F00023EB2B732372EB11E905CD2437D20620AE -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex deleted file mode 100644 index 952f245b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/f.cpu.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000010101010101010101010101FF01FF1FC6 -:10001000011001100110FD1705140514FD17011042 -:1000200001100110FF1F00000000001C001400144C -:10003000FF170110011001100110FD170514051420 -:10004000071C3C247F7D7D7D7F00D034000318FF9A -:1000500000002400016800103400014800FF240063 -:10006000016804002408002004008B08002004110B -:100070003408001804117B08001800D02400011176 -:1000800000D07B00011100289C00014200389C0038 -:10009000014204289C0800020428DD0800028C2A82 -:1000A0009F000001842EBF000001744A9C000001E3 -:1000B0008C4ECA000001244EA70000017843B20014 -:1000C0000001FF74749C0000019078CA00000124B4 -:1000D00078A7000001786DB2000001FF749E9C00BB -:1000E000000194A2CA00000124A2A7000001789791 -:1000F000B2000001FF74C89C00000198CCCA000047 -:100100000124CCA700000178C1B2000001FF081152 -:1001100035000146FF00009C00014200109C0001D8 -:100120004204019C0800020401DE0800028802C8A3 -:10013000000001840BC0000001B4049F000803FF0D -:100140004040404040404040043332313141414121 -:10015000042333323231313104132333323232311A -:100160000413232333323232041413232333323261 -:10017000041413232323333204141313232332339D -:1001800000010205080B0E0F100003060708070602 -:10019000030000000102030506080A0C0D0E0F10F3 -:1001A00010000203050607080808070605030200F9 -:1001B00000010409101924314051640102004B4A26 -:1001C000749EC88F0ABC0AED0A000B140B5E3E0435 -:1001D000322F2021E03F2D3600C2D611D304257CDA -:1001E000FE23C2D611C9CDCE112110201610360023 -:1001F0002315C2EE113E7032E0203E6232E2203E14 -:100200000432EF20AF328322329F223A902232888A -:1002100022214910CD4042215010CD4042232204DA -:10022000223A1922FE04CA51122A13223A07204701 -:100230007E90323022CA3B12F25112789632072059 -:100240003A19223C3219222A04223DCA2912C31A21 -:10025000123A1922B7C27B123A0720B7C27B123C6E -:10026000321522CDA50621603F118D07221622CD21 -:10027000B30321A022CD2942C39D13CDA506D304EB -:100280003A9F22B7C2C712DB04E608219322BECAF6 -:10029000C71277B7CAC212CD59073A8822EE013287 -:1002A0008822B7C2B412D3073E2132EF20CDE90035 -:1002B0000EC3BF123E0432EF20218722CD5243CD20 -:1002C00043073E06329F223A1122B7CADE12AF32EE -:1002D0001122219F227EB7CADB1235CD43433A1942 -:1002E000224FB7CAF312DB04E604C2071379FE04F7 -:1002F000CA7E122A13223A0720477E90473A3022BC -:10030000B8CA7E12C32912F33A0820F60432082034 -:10031000D305FBCD2C07214910CD4042215010CDF3 -:1003200040423A8C22E6F7328C22D30E2139222227 -:1003300081223A19224711BF110E007123712371D6 -:10034000237123712371231A771323362023362038 -:1003500023362023713E08CDC80005C23B13AF32BF -:10036000362232152232352232922232952232AC96 -:10037000223C323722CDD14321BD11DB02E608CA2F -:1003800089133A1922233297227E3228223A882270 -:10039000B7CA9D133E2132EF20CDE9000EAF3212D5 -:1003A0002232A8223A1522B7C2E9132A81223E043A -:1003B000CD1B433294220604B7CABE1306023A8C00 -:1003C00022E6F9B0328C22D30ECD4145DB02E64065 -:1003D000CAE9133A362217171717E610F321082037 -:1003E000477EE6EFB077D305FBAF32832232962209 -:1003F0003A8822B7CA05143E0432EF20CDE9000E38 -:100400003E0532EF203E0A323422213020017212A2 -:1004100016003E0432032278323222793231223AF7 -:100420000322320822364C23722370237223712355 -:100430003E0472233DC2321436011E0619360423CF -:1004400079D6144F3A08223DC222140610DB02E688 -:1004500020C30046060E3A322280473A3122D60A9D -:100460004F3A03223DC214142130203A3422320282 -:1004700022220020CDEC003E0FCD50023605233A5B -:1004800002223DC26E14AF3233223C320222AF321E -:100490002B22212020220020220022366C2A00203C -:1004A0002336002336F3233600233663CDEC003E9B -:1004B00005322F203A1522B7CAE0142A1A223A1C14 -:1004C000223DF2CA142183453E0601040009221A86 -:1004D00022321C223A0720B7C25306EBC3D7168438 -:1004E0003A2B22B7C209153E09D30FF33A0820F67A -:1004F00001320820D305FBCD7A41F33A0820E6FE0D -:10050000320820D305FBC37115CDEC0021BB08CD0B -:100510004144F33A0820F608320820D305FB3E0593 -:10052000320322FE04C228151120003E4621BA2AB9 -:100530003600193DC23015321122D3043A1122FE81 -:1005400004C23A15214910CD4042AF321122D304E2 -:100550003A1122FE04C24E153A03223DC22015F381 -:100560003A0820E6F7320820D305FB2A00222200B1 -:10057000203A2322FEFFF28915D3043A1122B7CA8A -:100580007915AF321122C37115AF320922328D2293 -:10059000320822329F22CDEC00CD1D44CD43432AA8 -:1005A0000022220020AF321122D3043A9F22B7C288 -:1005B0002516DB02E640CAD61506103A36220FDAB7 -:1005C000C4150602DB04A0CACC153E01219422BE4C -:1005D000CA2516C3EB15DB04E602219522BECA2507 -:1005E0001677B7CA25163A9422EE01F5CD4145F1AA -:1005F000329422CD41453A1222B7C209162A8122ED -:100600003E04CDC8003A9422773A8C22E6F94F3A5C -:100610009422B73E04CA1A163E02B1D30E328C227F -:100620003E06329F223A1122B7CAA915219F227E87 -:10063000B7CA3516353A0822B7CA5C163C320822CA -:10064000FE0CCAB1162A1E223A2322BCFA5C16C23C -:10065000B1163A2222BDFA5C16C2B1162A00202336 -:100660004E2346EB2A2222221E22CD2443097CEB74 -:10067000FE58DA7A16FEF2DA7C163EF277FED0D217 -:100680008D163A0822B7C28D163C3208222B7323EE -:10069000234E2346EB2A2022CD244309EB723E252C -:1006A000BADAA516773E7EBED2AC16772B73C39608 -:1006B000153A0922B7C42C44CD10443A1F22210018 -:1006C000FEBCFACA163E01C38F142100F9BCF2D455 -:1006D00016221E22111E223E05CD18433E10D306BF -:1006E00006041A77132305C2E216702120203E016A -:1006F000C330173A2920B7C217173A9422B7C21746 -:10070000170106002A272009222720EB212020227A -:1007100000203E07CD05433A3322B7CAEA172130FD -:1007200020AF3207223AA822B7FAAD443A02223D5E -:100730002200223203223E09856F7EB7CA4717FE88 -:10074000FDC2CD17C3C8173E052A0022856F5E2360 -:10075000567AB7F25C172F577B2F5F13234E234631 -:1007600078B7F26B172F47792F4F033E05F57AE6DE -:1007700004C2A21778E604C2A217EB29EB6069094C -:10078000444DF13DC26D172A00227EFE4CCAC817A7 -:100790003E09856F360306042B360005C29817C341 -:1007A000CD17F12140117807070782856FD2B11765 -:1007B000247EF50F0F0F0FE60F4F3E05CDE442F1FB -:1007C000E60F4F3E07CDE4423E0132072201100002 -:1007D0002A0022093A03223DC230173A0722B7C243 -:1007E000EA173A2920FEFFCAB21B3E043206222134 -:1007F00020203A022222002232032216087EFE6CBA -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex deleted file mode 100644 index 30dd2127..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/g.cpu.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000005B034F525B034F555B054F4445525B0802 -:100010005B504C4159455253085B4A4F5545555228 -:1000200053085B535049454C4552084445504F5383 -:1000300049545B074D455454455A5B0B574552464E -:10004000454E5B53494530055B434F494E065B5077 -:1000500049454345075B4D55454E5A4501530153AC -:10006000014E12505553485B53544152545B425514 -:1000700054544F4E3013415050555945525B5355CF -:100080005230424F55544F4E301653544152544BF8 -:100090004E4F5046304245544145544947454E30F5 -:1000A000085B5B5B5350415245085B5B5B535041BF -:1000B0005245085B5B5B5350415245175B5B5B46A7 -:1000C0004F554C305B5B53484F4F54305B5B41475F -:1000D00041494E1B5B5B4641555445305B5B54497F -:1000E0005245525B41305B5B4E4F55564541551969 -:1000F0005B5B464F554C305B5B4E4F43484D414C2C -:10010000305B5B57455246454E0F5B5B53484F4F44 -:1001100054305B5B414741494E135B5B5449524548 -:10012000525B41305B5B4E4F5556454155125B5B10 -:100130004E4F43484D414C305B5B57455246454E10 -:10014000015B015B015B075B5B5B5B5B4F52075BCA -:100150005B5B5B5B4F55095B5B5B5B5B4F44455295 -:100160000F5B5B5B47414D45305B5B5B4F564552D8 -:10017000075B5B5B5B46494E0A5B535049454C4508 -:100180004E44450E5B5B4C415354305B5B465241E1 -:100190004D450E5B4445524E494552305B434F55E9 -:1001A000500E5B4C45545A544552305B575552469D -:1001B0000A524547554C4154494F4E095245474C08 -:1001C000454D454E540A42455354494D4D554E47B1 -:1001D000085B5B5B464C415348085B5B5B464C41AC -:1001E0005348085B5B5B424C49545A05464C4153AB -:1001F0004805464C41534805424C49545A04464F21 -:10020000525B05504F55525B05465545525B0E5BA0 -:100210005B42454552305B5B4652414D450E5B5B50 -:10022000434F5550305B5B42494552450E5B5B4244 -:10023000494552305B5B52554E4445175C5B50520A -:100240004553535B53454C454354305B5B425554D7 -:10025000544F4E215C5B415050555945525B5355AC -:100260005230424F55544F4E5B44453053454C45F8 -:100270004354494F4E195C5B574145484C4B4E4FD8 -:100280005046305B5B4245544145544947454E0E0C -:100290005B5B5B535452494B45305B5B5B580E5B79 -:1002A0005B5B535452494B45305B5B5B580E5B5B69 -:1002B0005B535452494B45305B5B5B580F5B5B5B58 -:1002C000444F55424C45305B5B5B58580F5B5B5B62 -:1002D000444F55424C45305B5B5B5858105B5B5B51 -:1002E000444F5050454C54305B5B5B58580E5B5B41 -:1002F0005455524B4559305B5B585858015B015B74 -:100300000F5B5B484559484559305B5B5858585816 -:10031000015B015B095B484F4C595B434F57015BE5 -:10032000015B1130505553485B425554544F4E3089 -:10033000464F525B1130505553485B425554544F11 -:100340004E30464F525B1130505553485B42555426 -:10035000544F4E30464F525B04484F4F4B04484F6A -:100360004F4B04484F4F4B08535452414947485450 -:10037000085354524149474854085354524149473D -:100380004854D201013C0C01013F0C0106400C070E -:1003900001421046022A0D3301B80D0701460C0731 -:1003A000014D0C0701540C06025B0C0602670C069B -:1003B00002730C06027F0C06028B0C0602970C06D9 -:1003C00002A30C0602AF0C0602BB0C0602C70C0807 -:1003D00001EB0C0801F30C0801FB0C0801030D08EC -:1003E000010B0D0801130D08011B0D0801230D0C55 -:1003F00002D30C02013D0C2C039E0E2301170E416B -:10040000013A0E23017B0E1A01EB0D1201050E0CB1 -:1004100002220F0C023A0F0C02520F0C026A0F0C50 -:1004200002820F0C029C0F0C02B40F0C02CC0F0CBA -:1004300002E40F1A020E100902FC0F15010707FF54 -:10044000FFFFFFFFFFFF41221408142241406070AC -:10045000787C7E7F00000000000000FE01FF0303A7 -:10046000030303FF03FE0100000003FF03FF030279 -:100470000300001E033F0333033303F703E603EED9 -:1004800001FF033303330387038601FF03FF0330B8 -:100490000030003F003F00E001F30333033303BFAC -:1004A00003BF01E001F30333033303FF03FE010F36 -:1004B000003F00FB00E30383030300EE01FF03336F -:1004C000033303FF03EE01FE01FF03330333033F56 -:1004D000031E00F000FC03FE07FE07FF0FFF0FFFE7 -:1004E0000FFF0FFE07FE07FC03F000000078FFFF80 -:1004F0007800000070787C3C1C0303183C3C3C3CBA -:1005000018181800070F1F1E1C606000001EFFFF58 -:100510001E000060601C1E1F0F07001818183C3CCE -:100520003C3C1803031C3C7C787000020002000273 -:1005300000020002000200020002000200020002AB -:10054000000200020002000200020602080270021D -:10055000080206020002780214021602140278024F -:1005600000023E024002780240023E0200023C02CB -:100570004202420242027E020002420242027E0225 -:100580004202420200027E020402080204027E02CB -:10059000000200020002000200020002000200024B -:1005A000000200020002000200020002000200023B -:1005B0000002000200020002000000000000000033 -:1005C0000000000000000000060870080600781413 -:1005D000161478003E4078403E003C4242427E0085 -:1005E00042427E4242007E0408047E11151F000034 -:1005F0001F0608061F00001F091F0000171D051F0A -:10060000000105051F1E081E00041E0400001F1126 -:10061000111F0000101F11261909093F0021292967 -:10062000293F00202020203F001F203C201F001ECB -:100630002121211E001A2525253F3A2921211F00AD -:100640003F100C023F0021213F21210020202020CB -:100650003F001F203C201F001E2121211E001A25C3 -:1006600025253F000000000000001F203C201F0047 -:100670001E2121211E003F100C023F261909093FAF -:1006800000212929293F003F100C023F003F100C98 -:10069000023F0021213F2121001F203C201FFFFF9E -:1006A000010101010101010101010101010101013A -:1006B000010101010101FFFF010100010100010130 -:1006C0000001010001010001010001010001010020 -:1006D000010100010100010100010100010100010F -:1006E00001000101000101000101000101000101FF -:1006F00000010100010100010100010100010100F0 -:1007000001010001010001010001010001010001DE -:10071000010001010001010001010001010001FFD0 -:10072000FF01001C00140014FF170110011001103C -:100730000110FD1705140514071CFF1E81128112FC -:100740008112AD16A514A514AD1729102910291072 -:10075000EF1FFF1F011001100110BD17A514A514F4 -:10076000ED160912091209120F1E8003FF1E011057 -:1007700001100110FF1E8002F802080208020802A0 -:10078000F803EF1F291029102910AD17A514A5147F -:10079000BD16811281128112FF1EEF1FEF1F29105B -:1007A00029102910AD17A514A514BD1701100110AB -:1007B0000110FF1FFF1F011001100110FD1F050098 -:1007C00005000D000900090009000F00E01F3F109F -:1007D00001100110BD17A514A514BD1701100110BB -:1007E0003F10E01FFF1F011001100110BD17A514DD -:1007F000A514BD16811281128112FF1EFF01010195 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex deleted file mode 100644 index 94b01ac2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/roms/h.cpu.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C3580285004B1563FBC94F00009C37782D -:10001000F5E5D5C5CDCB043A11223C3211223A295F -:10002000223D322922C264003A15223A2822B7C260 -:100030003600B7CA64003D322822C264003A152255 -:10004000B7C25A0021972235CA53003EBE32282239 -:10005000C364003C329222C36400DB02E604CA643B -:1000600000329122210920DB052F479670CD8800B0 -:10007000222222210C20DB062F479670CD880022F9 -:100080002022C1D1E1F1FBC9B7FA9600FE21FA9D09 -:10009000003E21C39D00FEE0F29D003EE023470E9E -:1000A000007E2F57237E2F5F13EB0906027CB7F2E9 -:1000B000B300371F677D1F6F05C2AD00EB7B8677EE -:1000C0005F2B7E8A77676BC9856FD024C9070707C6 -:1000D000072100201600E6F05F19C9D1E17E472311 -:1000E000E5D5CDCD00220020C9CDDB002A00204E71 -:1000F00021830B79CDC8005E2356EB221121EB231F -:100100005E2356EB220F213E0FCD5002B71F322740 -:1001100022D22201060A11D301CD46013A2722E656 -:1001200010C03A2722060211D301B7C23101118053 -:1001300001CD46012A002023235E2323563E0ACD0B -:100140005002732372C9AFD30278CD5002E607D3B1 -:10015000013A1221217801CDC8006E260019EB2A40 -:100160001121D52DC26201CD26022A11213E2094F3 -:100170004F06002A0F21EBC9463C32281E140A0004 -:100180001AD302DB012FB67713231AD302DB012F18 -:10019000B67713231AD302DB012FB67713231AD3B2 -:1001A00002DB012FB67713231AD302DB012FB677B8 -:1001B00013231AD302DB012FB67713231AD302DBE2 -:1001C000012FB6771323AFD302DB012FB67709AF28 -:1001D000D302C91AD302DB012FAE7713231AD3023D -:1001E000DB012FAE7723131AD302DB012FAE771377 -:1001F000231AD302DB012FAE7713231AD302DB01BC -:100200002FAE7713231AD302DB012FAE7713231AF5 -:10021000D302DB012FAE771323AFD302DB012FAE66 -:100220007709AFD302C978CD50020F0F0FE61F57E1 -:100230002378FE0ACA3802237E0F0F0F47E6E0B28A -:100240005F78E61FC62457C9CDC8007E23666FC9F4 -:100250002A0020CDC8007EC9310024DB02E680C21E -:10026000BC02AF322822329322321522329022323F -:100270008722D3052100200620772305C279023288 -:100280001C2221A0220608772305C287023E4032A5 -:100290008622214009228E22FBC35306000102035D -:1002A0000405060708090A0B0C0D0E0F100F0E0DA2 -:1002B0000C0B0A09080706050403020106011100D8 -:1002C00000210020D304707EA8CACF02CD89032369 -:1002D0007CFE40C2C402D3042B7CFE1FCAF4027E03 -:1002E000A8CAE702CD8903782F77AECAD602CD8996 -:1002F00003C3D602D304237CFE40CA0B03782FAE7F -:10030000CA0603CD8903AF77C3F402780747D2C189 -:10031000027AB3CA3A03EBF911002006002100006B -:10032000390E10AF29DA29032F12133E1812130DBC -:10033000C2230305C21D03C38403310024210C32F0 -:10034000E52100001199033E0A320322010004AFA7 -:1003500086D304230DC2500305C250033CCA6A036E -:100360001AE3EBC5CDA303C1EBE3133A03223DCA65 -:100370007D03FE02C24903210040C34903E17DFE23 -:100380000CCA0000D304C384034F7DE60179C296F2 -:1003900003B257C39803B35FC94848474746464529 -:1003A000454444D5E5EBCDE203CDF103E1D113C9DA -:1003B0002A1622EB3AB1224E2306003DFAC3030966 -:1003C000C3B703EB793DF8F51A13D5FE30C2D60357 -:1003D000CD1507C3DD03CDE203CDF10309D1F1C390 -:1003E000C503EB213E04D64147070780CDC800EB8B -:1003F000C93E05F501E0FF091AAE77F13D09C8F5E0 -:1004000013C3F803EB3D211104CDE803CDF103093B -:10041000C940447E40407252525A4E425A5A5A7E05 -:100420000E08087E004E4A4A32007E4A4A7A00424E -:1004300022120A063C5A5A5A3C040A0A0A7E7814C6 -:100440001614787E4A4A4A343C424242247E424252 -:10045000423C7E525252427E121202023C424252B0 -:10046000747E1010107E42427E424232423E0202B0 -:100470007E181824427E404040407E0408047E7E60 -:100480000418207E3C4242423C7E1212120C3C4236 -:1004900042225C7E1212324C244A5A522402027EBC -:1004A00002023E4040403E06186018063E4078403A -:1004B0003E4224182442060870080662725A4E46CC -:1004C00000000000007060500804952105207E4F58 -:1004D00017DA0E05237EA7CAF204352B3E8FB677B6 -:1004E0003A0820F606320820D3053E24D30F3E20DA -:1004F000D306DB042FE6014779E640CA31054FCD2C -:100500003105B9C8233423343E01321822C9357E5F -:10051000E60FCA2A05FE08C2F2043A0820E6FD32B8 -:100520000820D305AFD306C3F2043E7FA677C3F2FB -:100530000421052078A7C240053E40B677E640C9B1 -:100540003EBFA677C9216009CD41443A1922470E22 -:1005500000CD33442139222200223A1922FE01CA59 -:10056000B30547050E033E12CDC80022042279CD03 -:10057000C800EB79CD1843EBBEFA9E05C291052B5E -:10058000EB2B7E0DF277052A042205C26405C3B366 -:10059000052A04223E07CDC8003601C38705C53AA7 -:1005A000192290470E01CD3344C12A042222002291 -:1005B000C387052139223A1922472281223E07CDDD -:1005C0001B43C2CD05C5CDDA43CD0644C12A8122E5 -:1005D0003E12CDC80005C2BA05218037111E003E6B -:1005E000433600233600233600193DC2E105216061 -:1005F0003F118D07221622CDB30321A0223A882273 -:10060000B7CA070621A4220E0322042279CDC8000E -:10061000EB79CD1843EBBEFA3606C225062BEB2B41 -:100620007E0DF215062A0422EB2A00220E047E1209 -:1006300023130DC22E062A0422CD2942CD1D07CD3B -:100640001D07CD1D07CD10443A88223290223E016D -:10065000321522F33A0820E602320820D305FB21A6 -:10066000BB11DB02E610CA6A0623221322DB02E674 -:1006700003FE03FA77063D32B122AF321822321957 -:1006800022328C22329422D30ED306D3073A15227B -:10069000B7CAE6113A0720B7C2E6117E323022CD42 -:1006A000A506C39D13CD2C07CD430711B707CDB3C6 -:1006B00003CD15073A1922B7CADA063A8C22F60892 -:1006C000328C22D30E116208CDB3033A1922FE04F4 -:1006D000C8110108CDB303CD1507112A08CDB00309 -:1006E0003A3022CD0404114708CDB3033A3022FE3C -:1006F00001CAFA06115C08CDB3033A1922B7C8CD76 -:10070000150711F007CDB3033A19223CCD040411AB -:100710000F08C3B3032A162223221622C9AF3211AF -:1007200022D3043A1122FE60DA2107C9210D33AF2A -:10073000067811D0FF0E1077230DC237071905C2B6 -:100740003507C93A88220601B7CA4E0706003A8C17 -:1007500022E6FEB0328C22D30ECD4F443A1922B796 -:10076000C268073A0720B7C8113B0ACDB303CD15BD -:100770000711FD09CDB30311EB093A8822B7CA84EA -:100780000711B009CDB303CD1507C31507093048CC -:10079000495B53434F52450E4D45494C4C455552CC -:1007A0003053434F524510484F454348305354450A -:1007B000524745424E49530D544F5B535441525496 -:1007C0005B47414D4512504F55525B534F55455273 -:1007D000304150505559455217554D5B4441535B7C -:1007E000535049454C305A555B5354415254454E31 -:1007F00004464F525B05504F55525B0546554552D6 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/BowlingAlley_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf deleted file mode 100644 index f68bb246..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "GunFight" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf deleted file mode 100644 index 03524a57..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.qsf +++ /dev/null @@ -1,178 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 22:12:52 July 17, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# GunFight_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_memory.sv -set_global_assignment -name VHDL_FILE rtl/GunFight_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY GunFight_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# --------------------------- -# start ENTITY(GunFight_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(GunFight_mist) -# ------------------------- - -# -------------------------------- -# start ENTITY(spaceinvaders_mist) - -# end ENTITY(spaceinvaders_mist) -# ------------------------------ -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/GunFight.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/Release/GunFight.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/Release/GunFight.rbf deleted file mode 100644 index a039a136..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/Release/GunFight.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv deleted file mode 100644 index 3e64a989..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_memory.sv +++ /dev/null @@ -1,129 +0,0 @@ - -module GunFight_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; -wire [7:0]rom_data_6; -wire [7:0]rom_data_7; - - -sprom #( - .init_file("./roms/gf-h.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/gf-g.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/gf-f.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/gf-e.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_3) - ); - - sprom #( - .init_file("./roms/gf-d.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_d ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_4) - ); - -sprom #( - .init_file("./roms/gf-c.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_c ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_5) - ); - -sprom #( - .init_file("./roms/gf-b.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_b ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_6) - ); - -sprom #( - .init_file("./roms/gf-a.hex"), - .widthad_a(9), - .width_a(8)) -u_rom_a ( - .clock(Clock), - .Address(Addr[8:0]), - .q(rom_data_7) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin - Rom_out = 8'b00000000; - case (Addr[12:9]) - 4'b0000 : Rom_out = rom_data_0; - 4'b0001 : Rom_out = rom_data_1; - 4'b0010 : Rom_out = rom_data_2; - 4'b0011 : Rom_out = rom_data_3; - - 4'b0100 : Rom_out = rom_data_4; - 4'b0101 : Rom_out = rom_data_5; - 4'b0110 : Rom_out = rom_data_6; - 4'b0111 : Rom_out = rom_data_7; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv deleted file mode 100644 index 220eef32..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_mist.sv +++ /dev/null @@ -1,197 +0,0 @@ -module GunFight_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Gun Fight;;", - "O34,Scanlines,Off,25%,50%,75%;", -// "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_sys), - .ENA(), - .Coin(btn_coin), - .Sel1Player(btn_one_player), - .Fire1(~joystick_0[4]), - .Fire2(~joystick_1[4]), - .GunUp1(gun1_up), - .GunDown1(gun1_dw), - .MoveLeft1(~joystick_0[1]), - .MoveRight1(~joystick_0[0]), - .MoveUp1(~joystick_0[3]), - .MoveDown1(~joystick_0[2]), - .GunUp2(gun2_up), - .GunDown2(gun2_dw), - .MoveLeft2(~joystick_1[1]), - .MoveRight2(~joystick_1[0]), - .MoveUp2(~joystick_1[3]), - .MoveDown2(~joystick_1[2]), -// .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -GunFight_memory GunFight_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B(3'b000), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), - .ce_divider(1), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .c_bits(8)) -dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_coin = 0; - -reg gun1_up = 0; -reg gun1_dw = 0; -reg gun2_up = 0; -reg gun2_dw = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h15: gun1_up <= key_pressed; // Q - 'h35: gun1_dw <= key_pressed; // Y - 'h75: gun2_up <= key_pressed; // Arrow up - 'h72: gun2_dw <= key_pressed; // Arrow down - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd deleted file mode 100644 index 0bbba7ca..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/GunFight_overlay.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity GunFight_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end GunFight_overlay; - -architecture rtl of GunFight_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv deleted file mode 100644 index 507462e5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/gun.sv +++ /dev/null @@ -1,13 +0,0 @@ -module gun( -input clk, -input gun1up, -input gun1dw, -input gun2up, -input gun2dw, -output [2:0] gun1out, -output [2:0] gun2out -); - -//0x06, 0x02, 0x00, 0x04, 0x05, 0x01, 0x03 -wire [6:0]gun[6:0]gun = () -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd deleted file mode 100644 index e29e4774..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,307 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.NUMERIC_STD.ALL; - - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire1 : in std_logic; - Fire2 : in std_logic; - GunUp1 : in std_logic; - GunDown1 : in std_logic; - MoveLeft1 : in std_logic; - MoveRight1 : in std_logic; - MoveUp1 : in std_logic; - MoveDown1 : in std_logic; - GunUp2 : in std_logic; - GunDown2 : in std_logic; - MoveLeft2 : in std_logic; - MoveRight2 : in std_logic; - MoveUp2 : in std_logic; - MoveDown2 : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; - signal gun1 : std_logic_vector(3 downto 0); - signal gun2 : std_logic_vector(3 downto 0); - -signal state1 : unsigned(2 downto 0); -signal state2 : unsigned(2 downto 0); - -type gun_array is array(0 to 6) of std_logic_vector(3 downto 0); -signal gun: gun_array := ( - X"6",X"2",X"0",X"4",X"5",X"1",X"3"); - -begin - -process (Clk, GunUp1, GunUp2, GunDown1, GunDown2) -begin -if Clk = '1' then - if GunUp1 = '1' and not (state1 = 6) then state1 <= state1 + 1; elsif - GunDown1 = '1' and not (state1 = 0) then state1 <= state1 - 1; elsif - GunUp2 = '1' and not (state2 = 6) then state2 <= state2 + 1; elsif - GunDown2 = '1' and not (state2 = 0) then state2 <= state2 - 1; end if; - end if; -end process; - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; --- no Watchdog - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; --- if WD_Cnt = 255 then --- Rst_n_s_i <= '0'; --- end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then --- WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then --- if Sounds(0) = '1' and Old_S0 = '0' then --- WD_Cnt <= WD_Cnt + 1; --- end if; --- if PortWr(6) = '1' then --- WD_Cnt <= (others => '0'); --- end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - -with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - ---GDB <= GDB0 and GDB1 and GDB2 and S;--todo - - GDB0(0) <= not MoveUp1; - GDB0(1) <= not MoveDown1; - GDB0(2) <= not MoveLeft1; - GDB0(3) <= not MoveRight1; - GDB0(4) <= not Gun1(0);--todo - GDB0(5) <= not Gun1(1);--todo - GDB0(6) <= not Gun1(2);--todo - GDB0(7) <= not Fire1; - - GDB1(0) <= not MoveUp2; - GDB1(1) <= not MoveDown2; - GDB1(2) <= not MoveLeft2; - GDB1(3) <= not MoveRight2; - GDB1(4) <= Gun2(0);--todo - GDB1(5) <= Gun2(1);--todo - GDB1(6) <= Gun2(2);--todo - GDB1(7) <= not Fire2; - - GDB2(0) <= '0';--Coinage - GDB2(1) <= '0';--Coinage - GDB2(2) <= '0';--Coinage - GDB2(3) <= '0';--Coinage - GDB2(4) <= '0';--Game_Time - GDB2(5) <= '0';--Game_Time - GDB2(6) <= Coin; - GDB2(7) <= Sel1Player; - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - gun1 <= gun(to_integer(state1)); - gun2 <= gun(to_integer(state2)); - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd deleted file mode 100644 index d65b9f9b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/pll.vhd +++ /dev/null @@ -1,350 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire4_bv(0 DOWNTO 0) <= "0"; - sub_wire4 <= To_stdlogicvector(sub_wire4_bv); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - sub_wire2 <= inclk0; - sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire3, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex deleted file mode 100644 index c83404c4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-a.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:2000000000001902007A0100FC00007E0500FE0380FC0340FE0738F9033EF0FF0FA0FF03F4 -:2000200080FF0080FF00C0FF00E0FF00E0FF0170FF0330FE0730FC0F30FE0F30FE0F30F8C0 -:200040000F20F00700F00700F00700C00700800700000700000300400300800300000F045B -:200060000BA0000000B0010000B0013C00B0017E00F913FF00FF9FFF81F8C7FF9FFCFFFF88 -:20008000FFFEFFFFFF0000FF400000002000031C007E0080FF01E0FF07F0FF0FF0FF0FF810 -:2000A000FF1FF8FF1FF8FF1FF8E71FF0C30FF0810FE08107C0810380C301F0FF0FE0FF07E2 -:2000C000E0FF07F4FF2F843C21048120048120068160F7FFEF0681600400200400200400EE -:2000E000200400204A0D460C870CC40B090D050CC80C86228221C321002145224121042277 -:20010000061AFF08000CFAFE0316FD0201141328740B3336740B1230740B32368C0B1228EB -:200120008C0B0C38740B0C2A740B0D30740B0C2A8C0B0C388C0B0F30740B1111115265990B -:20014000999911111153759999991111115485999999C400747020FFA00AB400008E0E000F -:200160000047414B45404040404D53454F4040404040404040404040404040404040404073 -:200180004040404040404040404040404000002547524C404649474851494C50454F51405C -:2001A000434D494C4040404040404040404040474551404F454144553A3A3A3A3A3A203A19 -:2001C0003A3A3A3A3A4040444F41543B4040474D51404B453B484555404E414F444C454F86 -:2001E0003B2E554D52404841534540434F454449513C00001A4E52504840425251514D4CAF -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex deleted file mode 100644 index e9efe4ee..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-b.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:200000001F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F00C0CE -:200020007F00C01FC0801F7000073C800F0FF8FF03FCFF01CEFF00C61F00C61F00C61F0040 -:20004000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F0088 -:20006000C07F00C01F00801FC0000738800F0CF8FF0FFCFF03CE7F00C61F00C61F00C61F29 -:2000800000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F48 -:2000A00000C07F00C01F00801F00000708800FF0F8FF1FFCFF0FCEFF00C61F00C61F00C678 -:2000C0001F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C028 -:2000E0003F00C07F00C01F00801F00000700800F00F83F00FCFF01CEFF0FC61F7FC61F0016 -:20010000C61F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700E1 -:20012000C03F00C07F00C01F00801F00000700800F00F83F00FCFF00CEFF01C6FF07C61FBC -:200140001EC61F70C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01713 -:2001600000C03F00C07F00C01F00801F00000700800F00F83F00FC7F00CEFF01C6FF03C61F -:200180001F17C61F0EC61F14FA3F20030CF03F00F03F00E03D00C07900C07100C0E100C08F -:2001A000E100E06000707000343400383800F0F000030CF03F00E03F00C01F00C01F00C0AB -:2001C0001F00C01F00001E00001C00000C00000D00000E00003C00030CF03F00F03F00E037 -:2001E0001F00C00F00801F00003E00C07C00E07800703000343400383800F0F00003200421 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex deleted file mode 100644 index 73d416cb..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-c.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:200000007E3C181C1818181818183C3C3C7E66607C3E06067E7E3C7E6660387860667E3CF8 -:20002000666666667E7E606060603E3E06063E7E60667E3C3C3E06063E7E66667E3C7E7E24 -:2000400060703038181C0C0C3C7E66663C7E66667E3C3C7E66667E7C60607C3C10383838A6 -:2000600038383838387CC0C0C0C0C0C00000C0C00000000000000000C0C00000002040FF0D -:2000800040200000F0C0A09008040201000078FCCCE07030300030300000000000000000C1 -:2000A0000000183C7E6666667E7E66663E7E66663E7E66667E3E3C7E6606060606667E3C50 -:2000C0003E7E6666666666667E3E7E7E06063E3E06067E7E7E7E06063E3E060606063C7E62 -:2000E0006606067676667E3C666666667E7E666666663C3C1818181818183C3C06060606BE -:20010000060606067E7EC3C3E7E7FFFFDBC3C3C366666E6E7E7E767666663C7E66666666A7 -:2001200066667E3C3E7E66667E3E060606063E7E66667E3E766666663C7E66063E7C60664B -:200140007E3C7E7E181818181818181866666666666666667E3C66666666667E3C3C18181B -:20016000C3C3C3DBFFFFE7E7C3C366667E3C1818181818180116101818181858781B1A1E49 -:200180001E9898783818181818181818021B000100038003C007C007601D00318007E01F53 -:2001A000F03D383904418003C007E00FF81F3E2907E90001000900050005081F381B3829C6 -:2001C000CC37FE5D0315000500800D00800D00800F00C89F00F8FF00C01780C03F50C07FB8 -:2001E00060C01F30801F3800071C800F0EF8FF07FCFF03CEFF01C61F00C61F00C61F00C6BA -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex deleted file mode 100644 index f5711b67..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-d.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:20000000CE0F3E07C3FB053A0820A7C8218208220020C921C52034C8352A00202B22002086 -:20002000C90413010C610F0A24100F035A0001296D0F0026035A00010B990F143D052A203C -:20004000C30100004000660BAA8B0D4A0D8B0D035A00066320C6035400FE027800C8034B69 -:2000600000010BA40F143D033C00053D20C2FF400060006627A0C7220021C7220340000902 -:2000800021080127D50F012A052A20C30200004000A00BAA8B0D4A0D8B0D0004130F0A019F -:2000A00009AF0F0C2E010CB80FA23E052A20C0010000480066139A8B0D870C8B0D053D20FB -:2000C000C0FFE7A0480066139AC722C321C72206632006000004F800000AC80675200600CB -:2000E0000004F800000AC806872006000004F800000AC806992006000004F800000AC8031B -:200100001E000109C50F0C2E030A072A20073D20000105A40F0E2E14099B080C05202A20B7 -:2001200020FD0D0DC202030F000B2A20105F0E12032D00099B080E6010095D090E6050093E -:200140005D090E6090095D090E7810095D090E9010095D090E9050095D090E90900DB2025E -:200160000917090C02203D20D039230DB202030A000B3D20D09B2311032D00099B08610489 -:200180007304780487042A042A042A04B0048C0499049E04AB043E043E043E0417058407B8 -:2001A0008407840784078407840749056C051308E9053D06490655068D069D067006AD0674 -:2001C0008206BC064907380775078507AB070708E907EF07A305C9031B0936093C09420930 -:2001E00048094E0954095A09630900020000000000000000440000003C7E666666666666C7 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex deleted file mode 100644 index 4372dd3e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-e.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:20000000F21406471C7BE61FC20D06141404C20406C3FC05E5D521F809CA2406010A00097C -:200020003DC21F06EB0120003E0AF51A137709F13DC22A06D1E113F13DC2FB05C92A0020BE -:200040007E23220020320320C92A00207E23220020321520C9F3E10100001100003E1031DD -:200060000F40C513BAC26206AFD301310024FBE92A00205E2356232200201AE6BF1213AFA0 -:2000800012C92A00205E2356EB220020C92A00205E2356230E0FCD7203220020C92A002076 -:2000A0005E2356230E09CD7203220020C92A00205E2356232200201AEE6012C9210E0FAF2C -:2000C000D3023A02203DFAEB06FE02F41907FE05FAD5063E045E235623D55E2356230600CA -:2000E000E3F5CD2D02F1E13DF2D5063A162047E680C2030778F68032162021220F3A052060 -:20010000C3C5063A1620E640C0F6403216203E04D302AF21360FC3D506E5F52150207EE6C4 -:2001200080C22D07EB0E0F21520FCD72033A1620F640321620F1E1C92A00205E235623226E -:2001400000201A3C2712CDA3052A00205E235623F33E801213137E2312131313131AC60867 -:20016000124E234623220020131313EB71237023AF772377C92A00207ED301237E232200FB -:2001800020321420C92A00203A1D205E235623220020922E0267CD5903EBE54B70230DC244 -:2001A0009C07E10E200915C29A07C921002111C40B1AA7C87723134F1A13477723C578064B -:2001C0000009472B1A13D5571E0006087A1F577B175F05C2CC0773D10DC2C307C178060088 -:2001E000094705C2BD07C3B107213F20C3F207212C205E0104000956CD59031B151515219A -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex deleted file mode 100644 index e3ba8b5d..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-f.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:20000000220020C93A0920FE22F4A705C9AEC84F0601790FDA20044F7807471313C3120483 -:2000200078AE77A0EB4E236669E91AE6700F0F0FA7C8321A2021E20E112A20C34F041AE675 -:20004000700F0F0FA7C8321B2021F00E113D204F0600094E2346EB36C0110B00197123706B -:20006000C906FEC268040600212A2036C01105001970C90602C3630406FFC27F0406002113 -:200080002A2036C02370C90601C37A0406FEC293040600213D20C36B040602C38E0406FF07 -:2000A000C2A5040600213D20C382040601C3A004C82163207EE680CAC1042175207EE68021 -:2000C000C01112201AA7C0E5EB11A23E011020CDFA043EE2D301112C2001081A3A1A2021D6 -:2000E000FE0ECD7C03E1F336C623712373232323702372FB3E02321420C90A3C02FE06FA90 -:20010000110577472103207E3611A7CA100536027821A40FC3FB05C82187207EE680CA28CF -:20012000052199207EE680C01113201AA7C0E5EB11B83E011120CDFA043ED2D301113F204F -:2001400001F8F63A1B20C3DF04C83E04321420D301210720343A06204FE603BED036007900 -:200160001F1FE6033C21082086E60777C83A0420A7C03A0820A7C83D32082006603A06202E -:20018000E630CA90054F78C6104779D610C285057832042021C62035210220AF772377232B -:2001A0002377C9AF3203200E04211E201102201A1F1F1F1FE60FC2BB053E10C63077231A2F -:2001C000E60FF63077062B79FE03C2D605062C1AA7C2D6053640132370230DC2AF053E08AD -:2001E000211E20110524C3FB052A00207E235E235623D55E235623220020E1F57E23D63030 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex deleted file mode 100644 index f925841c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-g.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:200000002777C21802C314022115207EA7CA180235C2180221C52035DB0247DB02B8210602 -:2000200020119E09CC0D04F1C1D1E1FBC97AB3C81A134F1A8032BC201A1347C5E51A13D3AC -:2000400004DB0377230DC23D02AFD304DB0377E101200009C105C23B023ABC2047C9E57EE2 -:2000600023CD80025AE3AE771F1FE3232323CD80022B46E1AE77237EB02BC03EBFA677C93D -:20008000E603477E23864F239623DA970296D297022B2B7156AFC92B2B05C2A7022BAF969F -:2000A00077233E10C3BA022B36002305C2B4023E60C3BA0205C294023E4056A7C9AF5E7796 -:2000C00023567723477AB3EBC9E5010F0009444D2F32BD203E60BA21AB20D2E00221B2202D -:2000E00071237023CD5903732372237123E37EEB210B0019EBE3732372EB1717DA14031769 -:20010000DA3E032B562B5E0104003E8009732372E1AE77C9E13E50BDC8E53E2ABD214903AC -:20012000CA26032151033A0920E60C0F856FD23203245E2356E1E5010D00AFC30C03AF7782 -:20014000237723772377E177C98B0DB10DD70DB10DC722ED221323ED227BE6074F0603AF0C -:200160007A1F577B1F5F05C25F03E521002419EBE1C9F37E2312130DC27303C9D55F160084 -:200180001978462356E1865F232323237E8257C93E08210220060070233DC29703CD5506BA -:2001A000212108220020FB2A00203AC620A7CAB403219B085E23220020160021AE0919197F -:2001C0005E2356EB11A603D5E9CD1308DB0047DB00B8211720117E09CC0D04DB0147DB017C -:2001E000B8211820118E09CC0D04211C207EA7CA04043600075F160021D609195E2356EB88 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex deleted file mode 100644 index 45ba5324..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/roms/gf-h.hex +++ /dev/null @@ -1,18 +0,0 @@ -:020000040000FA -:200000000000310024C39003E5D5C5F5C3870077E5D5C5F521B9207E2F77A7FAEA00216F53 -:2000200020E5CDBD02CA38001A1377231A1377780E1F0905A7CA2800E1111200197DFEB727 -:20004000C2210021A220E5CDBD02CA76001A13EB73237223EBD3027E12133E03D304DB038D -:20006000B677237E1213AFD304DB03B677780E1F0905A7CA5700E111EEFF197DFE5AC246AC -:200080000021B220C391003AB920A7FA180221AB20CDBD02D5CAB400CDBD02EBD5CDBD02A8 -:2000A000D1CAB400E54B70230DC2A600E10E200915C2A400E1CDBD02CA18021A13D302D5FE -:2000C000E3CDBD025E235623E322BA200600CD2D02E35E235623E3CD2D022ABA20E30C71B6 -:2000E000237023D1732372C318022163207EA7E5F25101237EA7237EFA0301FE70D2080172 -:20010000C35101FE90D25101110C00197EA7CA510111F8FF197ED610FEC0D25101E1E5363E -:20012000A023237E1F1F1F1FE60F4F232323237E321D20D6101F1FE630B11F5F1600213A48 -:200140000F19791F7ED24C011F1F1F1FE60F321C20E1111200193EABBDC2ED002163207ECF -:20016000A7F283013EFF32C420CD5E027E17F67FA677F28301E501090009CD59037323721C -:200180002371E1011200093EABBDC25F012ABE207DB4C29801212A2022C020AF32BD207EC9 -:2001A000A7F2B101CD5E023ABD20A7CCC90222BE20111300193E63BDC2BE01212A203AC0F1 -:2001C00020BDC29F012114207EA7CAD40135C2D401AFD30121092035F20802362221042060 -:2001E0007EA7CAF601C6992777C2F601EB21C42034C29D03EB342103207EA7CA0802C69922 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf deleted file mode 100644 index 76b4c91f..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "LunarRescue" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf deleted file mode 100644 index 51170b9a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.qsf +++ /dev/null @@ -1,168 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 19:49:43 June 08, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# LunarRescue_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY LunarRescue_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------------ -# start ENTITY(LunarRescue_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(LunarRescue_mist) -# ---------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarRescue_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarRescue_memory.sv -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/LunarRescue_Overlay.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VHDL_FILE rtl/roms/col.vhd -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/LunarRescue.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/Release/LunarRescue.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/Release/LunarRescue.rbf deleted file mode 100644 index b470c9d5..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/Release/LunarRescue.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd deleted file mode 100644 index 8ec20801..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_Overlay.vhd +++ /dev/null @@ -1,366 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - - ---Not Cleaned, iam to lazy for this - - -entity LunarRescue_Overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - CAB : in std_logic_vector(9 downto 0); - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end LunarRescue_Overlay; - -architecture rtl of LunarRescue_Overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_A1 : boolean; - signal Overlay_A1_VCnt : boolean; - signal Overlay_A2 : boolean; - signal Overlay_A3 : boolean; - signal Overlay_A3_VCnt : boolean; - signal Overlay_A4 : boolean; - signal Overlay_A4_VCnt : boolean; - - signal Overlay_R1 : boolean; - signal Overlay_R1_VCnt : boolean; - signal Overlay_R2 : boolean; - signal Overlay_R3 : boolean; - - signal Overlay_Y1 : boolean; - signal Overlay_Y1_VCnt : boolean; - signal Overlay_Y2 : boolean; - signal Overlay_Y3 : boolean; - signal Overlay_Y4 : boolean; - signal Overlay_Y4_VCnt : boolean; - signal Overlay_Y5 : boolean; - signal Overlay_Y5_VCnt : boolean; - - signal Overlay_G1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal Overlay_G2 : boolean; - signal Overlay_G3 : boolean; - signal Overlay_G4 : boolean; - signal Overlay_G4_VCnt : boolean; - - signal Overlay_P1 : boolean; - signal Overlay_P2 : boolean; - signal Overlay_P2_VCnt : boolean; - signal Overlay_P3 : boolean; - signal Overlay_P3_VCnt : boolean; - signal Overlay_P4 : boolean; - signal Overlay_P4_VCnt : boolean; - - signal VideoRGB : std_logic_vector(2 downto 0); - signal COLOR : std_logic_vector(3 downto 0); - -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - - Overlay_G1 <= false; - Overlay_G1_VCnt <= false; - Overlay_G2 <= false; - Overlay_G3 <= false; - Overlay_G4 <= false; - Overlay_G4_VCnt <= false; - - Overlay_A1 <= false; - Overlay_A1_VCnt <= false; - Overlay_A2 <= false; - Overlay_A3 <= false; - Overlay_A3_VCnt <= false; - Overlay_A4 <= false; - Overlay_A4_VCnt <= false; - - Overlay_R1 <= false; - Overlay_R1_VCnt <= false; - Overlay_R2 <= false; - Overlay_R3 <= false; - - Overlay_Y1 <= false; - Overlay_Y1_VCnt <= false; - Overlay_Y2 <= false; - Overlay_Y3 <= false; - Overlay_Y4 <= false; - Overlay_Y4_VCnt <= false; - Overlay_Y5 <= false; - Overlay_Y5_VCnt <= false; - - Overlay_P1 <= false; - Overlay_P3 <= false; - Overlay_P3_VCnt <= false; - Overlay_P4 <= false; - Overlay_P4_VCnt <= false; - - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt >= 0) and (Vcnt <= 99) then - Overlay_A1_VCnt <= true; - else - Overlay_A1_VCnt <= false; - end if; - - if (Vcnt >= 100) and (Vcnt <= 149 ) then - Overlay_R1_VCnt <= true; - else - Overlay_R1_VCnt <= false; - end if; - - if (Vcnt >= 150) and (Vcnt <= 240) then - Overlay_Y1_VCnt <= true; - else - Overlay_Y1_VCnt <= false; - end if; - - if (Vcnt >= 236) and (Vcnt <= 16) then - Overlay_G1_VCnt <= true; - else - Overlay_G1_VCnt <= false; - end if; - - if (Vcnt >= 0) and (Vcnt <= 72) then - Overlay_G4_VCnt <= true; - Overlay_Y5_VCnt <= true; - else - Overlay_G4_VCnt <= false; - Overlay_Y5_VCnt <= false; - end if; - - if (Vcnt >= 73) and (Vcnt <= 200) then - Overlay_P3_VCnt <= true; - else - Overlay_P3_VCnt <= false; - end if; - - if (Vcnt >= 224) and (Vcnt <= 230) then - Overlay_P4_VCnt <= true; - else - Overlay_P4_VCnt <= false; - end if; - - if (Vcnt >= 160) and (Vcnt <= 166 ) then - Overlay_A3_VCnt <= true; - else - Overlay_A3_VCnt <= false; - end if; - - if (Vcnt >= 24 ) and (Vcnt <= 230 ) then - Overlay_A4_VCnt <= true; - else - Overlay_A4_VCnt <= false; - end if; - - if (Vcnt >= 32 ) and (Vcnt <= 222 ) then - Overlay_P2_VCnt <= true; - else - Overlay_P2_VCnt <= false; - end if; - end if; - - if (Vcnt >= 42 ) and (Vcnt <= 216 ) then------------------------------------ - Overlay_Y4_VCnt <= true; - else - Overlay_Y4_VCnt <= false; - end if; - - if (HCnt = 518)then--ok - if Overlay_A1_VCnt then Overlay_A1 <= true; end if; - if Overlay_R1_VCnt then Overlay_R1 <= true; end if; - if Overlay_Y1_VCnt then Overlay_Y1 <= true; end if; - elsif (HCnt >= 540) then - if Overlay_A1_VCnt then Overlay_A1 <= false; end if; - if Overlay_R1_VCnt then Overlay_R1 <= false; end if; - if Overlay_Y1_VCnt then Overlay_Y1 <= false; end if; - end if; - - if (HCnt = 528)then--check - if Overlay_G1_VCnt then Overlay_G1 <= true; end if; - elsif (HCnt >= 540) then - if Overlay_G1_VCnt then Overlay_G1 <= false; end if; - end if; - - if (HCnt = 486) then--ok - Overlay_R2 <= true; - elsif (HCnt = 502) then - Overlay_R2 <= false; - end if; - - if (HCnt = 438) then--ok - Overlay_Y2 <= true; - elsif (HCnt = 470) then - Overlay_Y2 <= false; - end if; - - if (HCnt = 373) then--ok - Overlay_G2 <= true; - elsif (HCnt = 445) then - Overlay_G2 <= false; - end if; - - if (HCnt = 324) then--ok - Overlay_P1 <= true; - elsif (HCnt = 380) then - Overlay_P1 <= false; - end if; - - if (HCnt = 275) then--ok - Overlay_A2 <= true; - elsif (HCnt = 327) then - Overlay_A2 <= false; - end if; - - if (HCnt = 210) then--ok - Overlay_Y3 <= true; - elsif (HCnt = 274) then - Overlay_Y3 <= false; - end if; - - if (HCnt = 166) then--ok - Overlay_R3 <= true; - elsif (HCnt = 214) then - Overlay_R3 <= false; - end if; - - if (HCnt = 70) then--ok - Overlay_G3 <= true; - elsif (HCnt = 170) then - Overlay_G3 <= false; - end if; - - if (HCnt = 70) then--check - if Overlay_P4_VCnt then Overlay_P4 <= true; end if; - elsif (HCnt = 86) then - if Overlay_P4_VCnt then Overlay_P4 <= false; end if; - end if; - - if (HCnt = 0) then--ok - if Overlay_Y5_VCnt then Overlay_Y5 <= true; end if; - if Overlay_P3_VCnt then Overlay_P3 <= true; end if; - elsif (HCnt = 70) then - if Overlay_Y5_VCnt then Overlay_Y5 <= false; end if; - if Overlay_P3_VCnt then Overlay_P3 <= false; end if; - end if; - - if (HCnt = 164) then--check - if Overlay_A3_VCnt then Overlay_A3 <= true; end if; - elsif (HCnt = 172) then - if Overlay_A3_VCnt then Overlay_A3 <= false; end if; - end if; - - if (HCnt = 118) then--check - if Overlay_A4_VCnt then Overlay_A4 <= true; end if; - elsif (HCnt = 134) then - if Overlay_A4_VCnt then Overlay_A4 <= false; end if; - end if; - - if (HCnt = 102) then--check - if Overlay_P2_VCnt then Overlay_P2 <= true; end if; - elsif (HCnt = 118) then - if Overlay_P2_VCnt then Overlay_P2 <= false; end if; - end if; - - if (HCnt = 86) then--check - if Overlay_Y4_VCnt then Overlay_Y4 <= true; end if; - elsif (HCnt = 102) then - if Overlay_Y4_VCnt then Overlay_Y4 <= false; end if; - end if; - - if (HCnt = 486) then--ok - if Overlay_G4_VCnt then Overlay_G4 <= true; end if; - elsif (HCnt = 470) then - if Overlay_G4_VCnt then Overlay_G4 <= false; end if; - end if; - - end if; - end process; - - p_video_out_comb : process(Video) - begin - if (Video = '0') then - VideoRGB <= "000"; - elsif Overlay_R1 or Overlay_R2 or (Overlay_R3 and not Overlay_A3) then--Red - VideoRGB <= "100"; - elsif Overlay_A1 or Overlay_A2 or Overlay_A3 or Overlay_A4 then--Aqua - VideoRGB <= "011"; - elsif (Overlay_Y1 and not Overlay_G1) or Overlay_Y2 or Overlay_Y3 or Overlay_Y4 or Overlay_Y5 then--Yellow - VideoRGB <= "110"; - elsif Overlay_G1 or Overlay_G2 or (Overlay_G3 and not (Overlay_P4 or Overlay_A4 or Overlay_P2 or Overlay_Y4))-- or Overlay_G4 - then - VideoRGB <= "010"; - elsif Overlay_P1 or Overlay_P2 or Overlay_P3 or Overlay_P4 then--Purple - VideoRGB <= "101"; --- elsif not (Overlay_G4) then--white - else - VideoRGB <= "111";-- end if; - end if; - end process; - -colPROM: entity work.col -port map( - clk => Clk, - addr => CAB, --should be Video Counters - data => COLOR -); - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - --- O_VIDEO_R <= COLOR(2); --- O_VIDEO_G <= COLOR(1); --- O_VIDEO_B <= COLOR(0); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv deleted file mode 100644 index 3f7ca5bf..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_memory.sv +++ /dev/null @@ -1,103 +0,0 @@ -module LunarRescue_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - - -sprom #( - .init_file("./roms/lrescue_1.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/lrescue_2.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/lrescue_3.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/lrescue_4.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -sprom #( - .init_file("./roms/lrescue_5.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_i ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_4) - ); - -sprom #( - .init_file("./roms/lrescue_6.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_j ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_5) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4; - 5'b01001 : Rom_out = rom_data_5; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv deleted file mode 100644 index e09110e2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/LunarRescue_mist.sv +++ /dev/null @@ -1,209 +0,0 @@ -module LunarRescue_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Lunar Resc.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [9:0]CAB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_sys), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .CAB(CAB), - .HSync(HSync), - .VSync(VSync) - ); - -LunarRescue_memory LunarRescue_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -LunarRescue_Overlay LunarRescue_Overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_sys), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .CAB(CAB), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(1), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - - - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd deleted file mode 100644 index ed759c73..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,245 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(7 downto 0); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - CAB : out std_logic_vector(9 downto 0); - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - CAB => CAB, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= DIP(7); - GDB0(1) <= DIP(6); - GDB0(2) <= DIP(5); - GDB0(3) <= '1'; - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= DIP(4); - - GDB1(0) <= not Coin; - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1'; - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1'; - - GDB2(0) <= DIP(3); - GDB2(1) <= DIP(2); - GDB2(2) <= '0';--TILT - GDB2(3) <= DIP(1); - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1'; - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd deleted file mode 100644 index 7a8f0d58..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,337 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - CAB : out std_logic_vector(9 downto 0); - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - CAB <= std_logic_vector(CntE7(4 downto 0)) & std_logic_vector(CntE5(4 downto 0)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd deleted file mode 100644 index d65b9f9b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/pll.vhd +++ /dev/null @@ -1,350 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire4_bv(0 DOWNTO 0) <= "0"; - sub_wire4 <= To_stdlogicvector(sub_wire4_bv); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - sub_wire2 <= inclk0; - sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire3, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin deleted file mode 100644 index e65c5a07..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.bin +++ /dev/null @@ -1 +0,0 @@ -                                                                                                             \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd deleted file mode 100644 index f798fd72..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/col.vhd +++ /dev/null @@ -1,86 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity col is -port ( - clk : in std_logic; - addr : in std_logic_vector(9 downto 0); - data : out std_logic_vector(3 downto 0) -); -end entity; - -architecture prom of col is - type rom is array(0 to 1023) of std_logic_vector(3 downto 0); - signal rom_data: rom := ( - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111","1111", - "1101","1101","1100","1100","1100","1100","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1100","1100","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1100","1011","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1101","1101","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1100","1001","1111","1110","1110", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1110","1110", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1110","1110", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1110","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1001","1001", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1011","1011","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1111","1111","1100","1101","1011","1110","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1111","1111","1100","1100","1011","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1111","1111","1011","1100","1100","1110","1111","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1101", - "1111","1111","1100","1100","1100","1100","1100","1100","1001","1001","1001","1101","1101","1101","1101","1110", - "1110","1110","1011","1011","1011","1100","1100","1100","1100","1101","1101","1111","1001","1111","1101","1100"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex deleted file mode 100644 index 5ff2d9cd..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_1.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000000000C34B160000F5C5D5E5C3E70500A9 -:10001000F5C5D5E53E8032BE2021C02035CD4B0A46 -:10002000DB010FDA66003AEA20A7CA42003AEB2069 -:10003000FE09D23E00C6012732EB20CDAC0AAF321A -:10004000EA203AE920A7C260003AEF20A7C2E60EF4 -:100050003AEB20A7C26B003ABF21A7C2E60E000010 -:10006000E1D1C1F1FBC93E01C33F003A5820A7C20C -:1000700060003E01CDDC08310024FBCDA401CDBDE4 -:100080000A21133011501D0E04CD2A05D3063AEB78 -:10009000203DCD974A0E14C28901116A0BCD2A0565 -:1000A000DB01E604CA8E000699AF32EE203AEB205F -:1000B000802732EB20CDAC0ACD184C22F82022FC50 -:1000C00020CDD402CDDF02CDEA02CDC5480620CD39 -:1000D0000049CDA401CD9805CDAC4C21010122E50C -:1000E00020CDB447CD4C4CCD8F02CDE349CDD402C9 -:1000F0000000000000CDF202CDCA01CD6102CD7931 -:1001000002CD4602CDA901CD781F3A2720A7D306FC -:10011000CA0A01CD1210C223013A2820FE02D306DA -:10012000C213012129203600CD30040000002A2D01 -:10013000203A2C20FEFE010014C4850109221D2056 -:10014000CD6D0D2113203601215E207EA7C2304CDB -:100150002114207EA7C2AA04215D207EA7C26203CB -:10016000CD770CD3063A1D20FEB0DC7F023A1D206D -:10017000FEB0D4580D3A1620A7CC9D0DCD054CCD20 -:100180007B48C34801010010C911550BCD2A05DB7E -:10019000010F0FDA9D010FDAA700C38E0006983E0B -:1001A00001C3AA003E01C3AA01AF32E920C9000081 -:1001B00000000000C9C5E51A772B1B0DC2B701E18D -:1001C00001200009C105C2B501C9210224119118FD -:1001D000010318CD1B0C21052401030ACD1B0C21A2 -:1001E000043D11D818010318CDB50121C73E11F601 -:1001F0001801030ACDB5012102270E17113118D5B8 -:10020000C50608CD000AC1D10DC35B1D11EB19C590 -:100210000608CD000AC10DC20C02CD22172E000E19 -:10022000067EE680C43002110500190DC22102C904 -:10023000E5C57EE67F47235E2356234E237E67690E -:10024000CD000AC1E1C9CD22172EACC3CA4B002193 -:100250000127111718C50610CD000AC10DC25202A0 -:10026000C9211C250E0E11F319C5E50605CD000A9E -:10027000E12424C10DC26602C911131AC3A90D3AA3 -:100280001320A7C82126207EA7C03601C36D0DCD3F -:1002900022172EAE4E79A7C8211B3BC5110B1AE5BC -:1002A0000608CD000AE12525C10DC29B02C9000048 -:1002B00000C9000000C9CD8C052311F5201ABE1B12 -:1002C0002B1ACAC902D0C3CB02BED07E1213237E22 -:1002D00012C3004706C011A31A210020C3040B0655 -:1002E000C021002111A31BC3040B06C0210022C39F -:1002F000E402060121292070CD22172E40702E56CF -:1003000070C90600C3F402060121292070CD22170E -:100310002E70702E9070217020702E7C702E887040 -:10032000C90600C30903CDA401CD2103CD020321D9 -:1003300013203600CD9D4ACD14492A1D20010310FB -:10034000CD300C0E0411231AC52A1D20010210CD38 -:10035000180C3E08CDD505C10DC24803CD1949C3BF -:10036000CB05CD26030000C3A54A2EAC3500CAB08C -:1003700004CD424BC3C61E3AEF20A7C83AC620C3DD -:10038000440A00003600CD744CCD224FCD2103C36A -:10039000B91FCD22172EAE34E5CD8F02E12EA07EFF -:1003A000A7CAD4032EAE7EFE06CC0E04CDCB05CD5F -:1003B00022172EA25E2356EBCD0A4FCDA44CCDCBF7 -:1003C00005CDB54CCD22172EAB342EAF342E000602 -:1003D000AACDE402CDCB05C90000211B3D79A7C8F9 -:1003E0000025253DD306C2E103C50610CD340ACD54 -:1003F0004249000000E5CDF549CD0A4F3E10CDD56C -:1004000005E1000000000000C10DC2E903C9C521DB -:10041000142A11AD1E0E10CDB305CD004D00000005 -:100420000000000000215000CD0A4F000000C1C9AB -:10043000CD22172E2D7EFE04210625D44604114A16 -:1004400004060DC3000A21063DC93E083E003E2AAF -:10045000003E02003E2810000000000000000000E6 -:10046000000000000000003600CD020321132036FA -:1004700000CDD20D3AAE20A7C2290621010122A04B -:10048000203AA120A7D306C28104CD8316211320D0 -:100490003601211B203601CD070321162036012A03 -:1004A0009E203A9D2047C3340A00CD6704C35801FB -:1004B000CDB602CDD4020000AF32EE20CDA401CDE6 -:1004C0000203CD210321132D11634B0E0ACDB30579 -:1004D000CD974B3AE320A7C40A47CDC04CCDF84C8A -:1004E000CD864BCDCB05CDA901C37316CD8C05238D -:1004F00011F5201ABE1B2B1ACAC902D0C3CB0200A9 -:1005000000000000000000000000F378D305060A98 -:100510000E000DC2120505C21005FBC94E2346236D -:1005200079867723788677C90E021AD5CD3605D11C -:10053000130DC22A05C9CD9B0B0605D306CD000AB3 -:10054000C5AF770120000977097709C1C9CD8C05AE -:100550003AF120A7C8AF32F120E52AF220EBE17E84 -:100560008327775F237E8A277757237E23666F7AD8 -:10057000CD74057BD5F50F0F0F0FE60FCD8705F175 -:10058000E60FCD8705D1C9C61CC336053AC6200F74 -:1005900021F820D821FC20C92101240E1C06DFE50A -:1005A000C536001120001905C2A105C1E1230DC205 -:1005B0009D05C9D51ACD3605D13E0732C0203AC0B7 -:1005C000203DC2BE05130DC2B305C93E40C3D505CB -:1005D0003E80C3D50532C0203AC020A7D306C2D87A -:1005E00005C900000000003ADC20A7CA8C0EDB0120 -:1005F000E606C41606CD7C03E610060121CB20C218 -:100600000B067EA723C20B062B0600702AD92023D7 -:1006100022D920C360003E0132E120C9210000221E -:10062000CB20C9CD4208C3A0063AEF20A7C8E1C33A -:10063000620300000000003E20C3D5053E05C3D57F -:1006400005015006CD7C03E660CA55060DC244067E -:1006500005C24406C9E1C921CB2011C208061ACD42 -:10066000040B000000000000119A082117270E1744 -:10067000CD2A05211227115B1CCD0407211027CD9F -:100680000407210E270E05CD0607210E331143095D -:100690000628CD000A11B1080E1021062ACD2A0520 -:1006A0003ADC20A7CA78083ADA20FE20D27808CDB2 -:1006B0001607CD7C03E660FE40CC2F07FE20CC85DC -:1006C000073AE120A7C278083ACC20A7C2CF070199 -:1006D0003001CD2607CD1E073ADA20FE1DC2A00646 -:1006E0000605C521062A0620CDEB09CD3C0611B131 -:1006F0000821062A0E04CD2A05CD3C06C105C2E21A -:1007000006C3A0060E0B0605CD000AC5016001094F -:10071000C10DC20607C92ADD203E2AC336052ADDDF -:10072000203E1BC336050DC2260705C22607C9CDCC -:100730004106CD1E072ADD207DFE11CA6007FE0F8F -:10074000CA69077CFE33CA740724247CFE35D25460 -:1007500007C35A07CD1E07210D3622DD20C3160719 -:100760007CFE3BD27907C36F077CFE3BD27F072418 -:1007700024C35A072634C34907210F27C35A072128 -:100780000D27C35A07CD4106CD1E072ADD207DFE69 -:1007900011CAA907FE0FCABA077CFE28DAC307FEF2 -:1007A00034C2AF072633C3AF077CFE28DAB407256F -:1007B00025C35A07211127C35A077CFE28DAC90727 -:1007C000C3AF07210F3BC35A0721113BC35A07018F -:1007D000FF20CD26073ADB20FE0AD25D083ADD2055 -:1007E000FE11CAFD07FE0FCA03083ADE20FE32D210 -:1007F0000B08CD3B08C616CD4208C3A006CD3B086A -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex deleted file mode 100644 index c79ee941..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_2.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C32306CD3B08C60BC32306FE35D27808B2 -:100010003ADB20A7CA31082ADF202522DF203E1B39 -:10002000CD360521DB203521CF203ADB20856F3608 -:100030001BCD1C0600000000C3A0063ADE20D62718 -:100040000FC921CF20F53ADB20856FF1772ADF2019 -:10005000CD360522DF2021DB2034C31C063ADD200B -:10006000FE0DC278083AEE20FE32D27008C378083E -:10007000FE36D27808C31008AF32DC20CD2009CD7F -:100080008D08C398050650211E2DC3EB092ACD20EB -:1000900011CF203ADB204FC32A0507082B12020E8E -:1000A0001104111B1B110406081213110013080E72 -:1000B0000D0D000C041B2E2F2F2F2F2F2F2F2F2F26 -:1000C0002F2E000000001B1B1B1B1B1B1B1B1B1BC5 -:1000D000000000011127073000000000325820AF57 -:1000E00032BF21C93AEF20A7C83AC620C3440A3A12 -:1000F000EF20A7CA9247C36203000000000000007F -:10010000000000E5D5110004193E1CCD3605D1E1F3 -:10011000C36F05CD8C057E23666F292929297CC9EB -:100120003ADB20A7CA3709473E0A90373F1FC62D42 -:10013000672E1E22CD20C9211E2D22CD203E0A323F -:10014000DB20C9001F141609001E01011E001F1527 -:10015000150A000000000000000000001F15151126 -:10016000001F08041F001F11110E003AEF20A7CA3C -:100170007F093A1820A7C2380FCD410AC3380F2A89 -:100180001020CDC009E603C291097DFEB5D4A409B3 -:10019000232210207E0FDAAA0F0FDACB0FAF321C0A -:1001A00020C3480F2EA6C900000002010101000271 -:1001B0000202020202020000000000000000000033 -:1001C0003A12203C321220C9CD2C0AC5E51AD304BC -:1001D000DB03AE772313AFD304DB03AE77E101205B -:1001E0000009C105C2CB09C9CD2C0AC5E5AF7723EB -:1001F0007723E101200009C105C2EB09C9CD2C0A12 -:10020000C51A771301200009C105C2000AC9CD2C07 -:100210000AC5E51AD304DB03772313AFD304DB034A -:1002200077E101200009C105C2110AC97DE607D3A3 -:1002300002C31F0BAFC57701200009C105C2350AF3 -:10024000C9C377030FDB02D0DB01C9DB02E604C8B8 -:100250003A5920A7C03100240604C5CD9805C10530 -:10026000C25A0A3E01325920CDA401FB11571C216C -:1002700016300E04CDB305CDCB05C30B4C00000EDC -:100280001C211E24117F0BC32A0521F820C3960AC6 -:1002900021FC20C3960A5E2356237E23666FC30388 -:1002A000090E0721013511541DC32A053AEB2021FF -:1002B000013CC61CC3360521F420C3960ACD340B7D -:1002C000CD7F0ACD8A0ACD900ACDB70ACD2009CDBF -:1002D0008D08CDA10AC3AC0A21BE20461AE680A82B -:1002E000C037C9322B241C16110D0A080706050455 -:1002F000030201342E27221C181513100E0D0C0BAF -:10030000090705FF1A77231305C2040BC9E5232348 -:100310005E2356234E2346E1D55E2356EBD1C9C555 -:1003200006037C1F677D1F6F05C2220B7CE63FF62C -:100330002067C1C92100243600237CFE40C2370B50 -:10034000C906000C041B0E1504111B1B0F0B001813 -:100350000411261B271D1B0E111B1E0F0B0018045A -:1003600011121B011413130E0D1B0E0D0B181B1D68 -:100370000F0B001804111B1B011413130E0D1B1B74 -:1003800012020E11042B1D1B1B1B1B1B1B1B1B1BFB -:100390001B1B1B12020E11042B1E1B115B1CA7C87A -:1003A000E5210000C5010500093DC2A50B19EBC1FF -:1003B000E1C9CD2C0AC5E51AD304DB032FA67723A8 -:1003C000131AD304DB032FA6772313AFD304DB0365 -:1003D0002FA677E101200009C105C2B50BC9CD2CBC -:1003E0000AC5E51AD304DB03A6CAF10B3E0132505D -:1003F00020DB03AE7723130DC2E30BAFD304DB0383 -:10040000A6CA090C3E01325020DB03AE77E1012081 -:100410000009C105C2E10BC9CD2C0AC5E51A772335 -:10042000130DC21D0CE101200009C105C21B0CC93E -:10043000CD2C0AC5E5AF77230DC2350CE1012000B4 -:1004400009C105C2330CC9010010D3060DC24A0C04 -:1004500005C24A0CC9CD2C0AC5E51AD304DB032F0B -:10046000A6772313AFD304DB032FA677E101200087 -:1004700009C105C2580CC9210C207EA7C83600212D -:100480000000220020CD22172E722256200E087E58 -:10049000A7CA9A0CCD3D0DD2D20CCD450DC28F0C02 -:1004A000CD22172E92CDE74C0E047EA7CAB50CCDF7 -:1004B0003D0DD2C90CCD450DC2AA0C0000002A0684 -:1004C0002001F8FA09C3211F00CD500DDADB0CC35F -:1004D000B50CCD500DDADB0CC39A0C3A072023BEC5 -:1004E000D2E60CC3B50CF53E188647F1B8DAF40C29 -:1004F00000C3B50CC34E1E00CD370DE5CD1E490619 -:100500001311B719CDFD09CDE11DE1E50613CDFDB0 -:1005100009CDE11DC3E51E00E1E57DD6086F061893 -:10052000CD7917E10618CD7917C3004F0000000000 -:1005300000000000000000235E2356EBC9233A06AA -:1005400020C608BEC92A56202323232256200DC9BF -:10055000F53E088647F1B8C90000003A1620A7C842 -:100560002125207EA7C0360121292036003A2C20E3 -:10057000FEFE2A2D20010011C4990D090612CD2C72 -:100580000AC53E01AE770000C31E4801200009C124 -:1005900005C2810DC3804F0DC901000DC9219C20EA -:1005A0007EE610110B1AC47902CD22172E2D4E7E35 -:1005B000A7C8237EA7C4C00D2323230DC2B30DC932 -:1005C000E5C523D5CD380DD1D50608CDFD09D1C15E -:1005D000E1C92A1D207CFE3CDAF50DFED4D2F50DD2 -:1005E0007DFE1BDAF50DFE20DAFB0DFE28DA4C0E3F -:1005F000FE30DA760E21AE203601C97CFE44D204EC -:100600000EC3F50DFE56DA420EFE84D2110EC3F56E -:100610000DFE94DA470EFEC4D21E0EC3F50DFED4B5 -:10062000DA260EC3F50DC32F1E00CD221736002388 -:1006300023CD370D229E2078329D2000000000003F -:1006400000C92E00C3311E2E05C3311E7CFE3CD2D4 -:10065000550EC3F50DFE59DA710EFE7DD2620EC342 -:10066000F50DFE96DA6A0EC3F50D2E140630C33E64 -:100670001E2E0FC36C0E7CFE73D27F0EC3F50DFED3 -:100680009CDA870EC3F50D2E19C3451EAF32BE206E -:10069000219C20342150207EA7C4BF0E3AE920A718 -:1006A000C260003AEF20A7CA2547CDDD12215320B2 -:1006B0007EFE01CC9A11CDF04CCDB64FC360003612 -:1006C000002A1D207DFEB8D20C1FFE30DAD50E2187 -:1006D0005D203601C97CFE3CDACF0EFED4D2CF0EAF -:1006E0002114203601C9215320347EE60377CDDD65 -:1006F00012CD040F3AA020A7C4C510CDAB49CD3A06 -:100700004EC360003A5320A7CA1B0FFE01CA9A11BC -:10071000FE02CA5C13FE03CAC214C93A1320A7C85A -:10072000CDAC12CD364C3A1D20FEBADA350F3A1652 -:1007300020A7CA480FC36B09E6600707DAAA0F07AC -:10074000DACB0F211C203600CD9A0F3A1620A7CA0B -:10075000580FCD5310C3690FCD1210C48B0F3A1D23 -:1007600020FE40DA820FCDE70F211D20CD0D0BC5F5 -:10077000D5CDB20B211B20CD1C052A1D20D1C1C314 -:10078000DE0BCD8249CDED0FC3690FC3CB4C347E58 -:10079000E60123233600C036FFC93A1620A7211BE5 -:1007A00020C2A70F36FEC93601C93A1E20211C20DF -:1007B000FEE0D2C60F3A1620A7C2961D3602C348E5 -:1007C0000F3603C3480F3600C3480F3A1E20211CC2 -:1007D00020FE30DAC60F3A1620A7C2E20F36FEC35B -:1007E000480F36FDC3480FCD1210CA1810CD341073 -:1007F000DA2B10C3ED4ECD4810211A20347EE601CD -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex deleted file mode 100644 index e4e4a765..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_3.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000112C18CC0E102A23200605C3C80911276D -:1000100018C9CD410AE610C92117207EA7C3674938 -:100020002A23200605112C18C3550C211A20CDFDBA -:100030000FC3F60F2117207EA7C241103601CD73E2 -:100040004F2A23207DFE30C92A1D2001F8030922F2 -:100050002320C92117207EA7C25E10CD48100000C2 -:1000600000000000CD2010CD48100000000000006E -:100070000000219820CD1210CA9510E5211B2036D2 -:1000800002E1C3FC0F0000000000000000000000BF -:100090000000009800E523347EE601211B20C2AB5E -:1000A000103601E1347EE604C300103600C3A3100D -:1000B000CD22172EAD7E21FB19A7C4C11022A72087 -:1000C000C921031AC921A2207EA7C2D610CD8B1D3B -:1000D000CDB010CDFB10CDFB10CD22172EAD7EA7DD -:1000E000C229113AA520FE19DC0411211E203AA6CE -:1000F00020BEDA0B1121A320CD1C0521A520CD0D9A -:100100000BC3C8092100FF22A320C921010022A39B -:1001100020211D203AA520BED21E11C3F5102100BA -:100120000022A020AF32A220C921AD207EA7C23C70 -:10013000113AA520FE19DA3C11C3F5103601210051 -:100140000122A320211E203AA620BED25111C3F5C0 -:100150001021010022A320211D203AA520BED26437 -:1001600011C3F510CD22172EAD3600C31E11CD22BE -:10017000172E2D4EE52B2B2B23CD32123600CD37EB -:100180000D22A5200608CDE809E17EA7C8357EFE30 -:1001900003DA9511C92EAD3601C93A1620A7CC173E -:1001A000162129207EA7C44612CDEB48000000216D -:1001B00088207EA7C8237EA7C2001236012A8A2083 -:1001C0004E7DFE37D42112228A20CD22172E72CDE9 -:1001D0003B12C2ED112A8A2023228A20CD22172E1B -:1001E0008C7EFE04C22C12210000C36F1EE52A8AF9 -:1001F0002023228A20E1CD370D01000909228E201B -:10020000218E20CD0D0BCD550C218E207EFE40DAA7 -:100210002412218C20CD1C05218E20CD0D0BC3C8AE -:10022000092E27C92A8E200603CD79172189203669 -:1002300000C9110300190DC23512C979A7CA4312AA -:10024000CD32127EA7C9112E20CDD80AD8212D205B -:10025000CD0D0BCD180C3A2E20FE28DC9C12FEC8CA -:10026000D4A2123A1620A7CC7612212B20CD1C0541 -:100270002127203601C92A2D200100100911F71766 -:10028000010210CD2C0AC5E51AB67723130DC288DA -:1002900012E101200009C105C28612C9212C2036B5 -:1002A00002C9212C2036FE21282034C93A1620A765 -:1002B000C83A1D20FEB8D0CD1210C2CC12210D209C -:1002C0007EA7C2C8123601C9233601C9210E207E7D -:1002D000A7C836002B36002100203601C921002096 -:1002E0007EA7C8237EA7C2F51236012A1D20010869 -:1002F0000509220620110720CDD80AD0210620CDDD -:100300000D0BCD57172106207EFEB8D24D132104C8 -:1003100020CD1C05CD901DCD2C0AC5E51AD304DBDC -:1003200003A6CA2A133E01320C20DB03AE77231347 -:10033000AFD304DB03A6CA3E133E01320C20DB031D -:10034000AE77E101200009C105C21A13C92A0620AF -:100350000603CD7917210000220020C93A1620A7F4 -:10036000CC3316CD22172E407EA7C25D142E707E90 -:10037000A7C8C3271FC5E57EF5E680CABD13F1F502 -:100380000707223420217B19DC4914223A20F1008E -:10039000000000000000002A3420CD370D22382054 -:1003A000213820CD0D0BCDFD092139207EFEE0D472 -:1003B0004D14213620CD1C052A3820EBF5F1E12320 -:1003C00073237223C10DC275132170207EA7C82329 -:1003D0007EA7C21A1436012A72204E7DFE56D45AC8 -:1003E00014227220CD22172E7ECD3B12C207142A72 -:1003F000722023227220CD22172E8A7EFE04C24351 -:1004000014210000C3731EE52A722023227220E10A -:10041000CD370D01000909227620217620CD0D0B64 -:10042000CD550C2176207EFE40DA3B14217420CD80 -:100430001C05217620CD0D0BC3C8092A76200603A2 -:10044000CD79172171203600C9218E19C9E52A38C6 -:10045000200613CDE809E13628C92E47C9CDA514D9 -:1004600022652021F718226920CD22172E414E2324 -:10047000C5E5CD380D226720CD9B1DCDFD09216836 -:10048000207EFEEAD49814216520CD1C052A672021 -:10049000EBC3A11DC27014C9E52A6720060BCDE885 -:1004A00009E13628C9CD22172EAB7EA7210001C84D -:1004B000FE01210001C8C37B1EC900732372230003 -:1004C00000C93A1620A7CC3F16CD22172E567EA77C -:1004D000C2B7152E907EA7C8E5CD5915223620212A -:1004E000A119223A20E1234E23C5E57EA7CA1215A1 -:1004F000CD370D223820213820CD0D0BCDFD09211F -:1005000039207EFE28DC6E15213620CD1C052A38C8 -:1005100020EBC3B31DC2E914217C207EA7C8237E33 -:10052000A7C2971536012A7E204E7DFE47D4561568 -:10053000227E20CD22172E92CD3B12C289152A7E13 -:100540002023227E20CD22172E8B7EFE04C283150F -:10055000210000C3771E2E37C9CD22172EAB7EA7F0 -:100560002100FFC8FE012100FEC8C3621FC9E52AA1 -:1005700038200613CDE809E136E0C92A82200603B7 -:10058000CD7917217D203600C9E52A7E20C3BE1D06 -:1005900001000909228220218220CD0D0BCD550CAE -:1005A0003A8220FE40DA7B15218020CD1C05218275 -:1005B00020CD0D0BC3C809CD0216226520213919A3 -:1005C000226920CD22172E574E23C5E5CD380D22A6 -:1005D0006720216720CD0D0BCDFD092168207EFE0F -:1005E00028DCF515216520CD1C052A6720EBC3AA60 -:1005F0001DC2CA15C9E52A6720060BCDE809E136F8 -:10060000EDC9CD22172EAB7EA72100FFC8FE012128 -:1006100000FEC8C3911EC92111270E05E5219420B3 -:10062000347EA10603C22F16E111DF19C3000AE1CF -:10063000C3340A210F3B0E01E5219520C32016216A -:1006400008360E04E5219620C32016310024AFD3CE -:1006500003D30421002011A31A0600CD040B2100AE -:100660002111A31B06C0D5CD040B210022D106C049 -:10067000CD040BAFD303D305CDA90100000000FBCF -:10068000C3B546CDCB0521F7182263200000002119 -:1006900039192261200606CD22172E414E23C5E5C9 -:1006A000CD380D2267202A6320C3CB1DC29E162A97 -:1006B0006320110B0019226320C5CD470CCD2217F2 -:1006C0002E574E23C5E5CD380D2267202A6120C361 -:1006D000D61DC2C4162A6120110B0019226120C147 -:1006E00005C29716CDD64FCDF11ECD22172E417ED5 -:1006F000FE0AD2F616342E577EFE0BD2FF1634CDEC -:10070000F61DCD0E17210836CD0E17210F3B06031F -:10071000C3340AEB2A6720060BC3FD090000000062 -:1007200000003AC62067C90001020300010203006D -:1007300001020300010203000102030001020300A1 -:100740000102030101020300010203000102030090 -:1007500001020300010203CD2C0AC5E51AD304DB14 -:10076000032FA6772313AFD304DB032FA677E10172 -:10077000200009C105C25A17C9CD2C0AC5E5AFD35F -:1007800004DB03772300AFD304DB0377E101200010 -:1007900009C105C27C17C9000000008001C003E048 -:1007A00047E047F04FF04FF85DF85DFC7FFC5FFEDF -:1007B0005DFF5DFF0FFF0F011C0118013801700183 -:1007C00070017001F001F001F001F00170017001A1 -:1007D0007001300138011CFF0FFF0FFF5DFE5DFC53 -:1007E0005FFC7FF85DF85DF04FF04FE047E047C0F9 -:1007F000038001000000000000000002019E03E2EF -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex deleted file mode 100644 index 871ee3ed..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_4.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000007F806E007FC0EFC0EE007F806E2079E84 -:100010000302010000000000012735785E78DEDE73 -:10002000785E78342701003050885030305CCF5CE7 -:1000300030FF7FFFFF7F3FFF7F83CFFFC1FFFFC503 -:10004000D5D1FFC1DDC1FFF3C1D0D8FAFEFEFFFF5D -:10005000FFFFFFFFE0FFFFE0EEE0FFFFE0EEE0FF6D -:10006000FFFFFEFEFAF8C8800080D0D8FAFEFEFE40 -:10007000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE2AD -:10008000EAE8FFFFE0EEE0FFFFFFFFFFFFFFFFFDFD -:10009000E4FFFFFFFFFFFFFFFFCCFF33BFFFFFEFDA -:1000A000FF3F8FFFFFF9FFE3E7FFEBDCFF1FDBFF05 -:1000B000FFFFFFFFFBFFFFFFFFFFCFFFFFFDFFE3A2 -:1000C0009FFFFB03FFEF00FFD300FFFF00FFFF00D8 -:1000D000FFFF00FFFB00FF7100FFFFFF7FEF1FD955 -:1000E000F9037FFF019B7F00FE1F00FF03003F001D -:1000F00000070000010000000000101C2242224402 -:10010000221C00000000101C3E1E3E1C00000000CF -:100110000000081C0C1C0800000000000000080C77 -:1001200008000000000000000000080000000000BF -:10013000000000000000000000081424221214082F -:100140000000000000081C3C1E1C0800000000000D -:10015000081C1C1C08000000000000081C1C0800F3 -:100160000000000000000008000000000000000087 -:10017000000000000000000000000000000008086F -:100180001C1E37BFBEF6F6BEBF371E1C0808000097 -:10019000000008081C7E6C78EC786C7E1C08080057 -:1001A0000000000000000C1E96BCF4BC961E0C0063 -:1001B0000000000040F040000000040E143A3E1D14 -:1001C0003D3E1D2E0C040000000000880120044E5E -:1001D00014BA381D39BE340C8A2C014012000002BA -:1001E00007020000000000FC023F020001070F01AF -:1001F0000001031028502810000000000001637C5B -:100200001318000018137C6301000000C032DEF8F0 -:10021000DE32C00010096F7C6F0910000E2E241F03 -:10022000070A1B0000000000008001F00FF81FDC2F -:100230003EF81FF00FF01FE017E02728C9E89104EF -:10024000C1080102004450882870CF241DEF3FE20E -:10025000011A123828484C888C0408023201338075 -:10026000014000008443441B24D817800F8A1FB824 -:100270003FF83FD020DE6FC26FA26EB812E41602C4 -:10028000300000000000000000000000000000003E -:10029000000000000000000000000000000000005E -:1002A0000000000000000004000000B41901030079 -:1002B000000000A709000000000000000000FE0090 -:1002C0000000FB17020C000000000000000000FE10 -:1002D000C8909717023000000000000000000001E5 -:1002E000130000000802000025410000C0006070FB -:1002F00000000000000000000000000000000000FE -:100300000000000000000000000000000000010BE1 -:1003100000000000004717FD000000E71901010080 -:10032000003717FD000000E819010300002717FD42 -:10033000000000E8190103000000000000000000B8 -:10034000000000000000FF000000FB190108000091 -:10035000000000000000000000000000000000009D -:10036000000000000000000000210000000000006C -:1003700000001B1B130008130E1B1B1B00000000BA -:1003800011270730000000000000000000000000FE -:100390000100000000000000051D2F00001D2600C8 -:1003A000001D3990391803299039180331903918F4 -:1003B0000339A049180428A049180430A869180571 -:1003C0002F31480D0A094D564909432C3038480D44 -:1003D000060128280120300118380118E00120E822 -:1003E0000128F00005B07058C04050806860784027 -:1003F0008890A85098683870B00005A0E038785010 -:10040000B06890888040D85848409878C04860408C -:1004100048406000088158B08180A081885081A840 -:1004200040C1B0C0C1A070C190B0C1604000000028 -:1004300000000000040170700168C001984001785C -:10044000B000000000800000000000000000000379 -:100450000000000000000013080B131F2444241F99 -:100460007F494949363E414141227F4141413E7FDA -:10047000494949417F484848403E414145477F08F6 -:1004800008087F00417F4100020101017E7F0814BE -:1004900022417F010101017F2018207F7F10080485 -:1004A0007F3E4141413E7F484848303E4145423DC4 -:1004B0007F484C4A31324949492640407F40407E7E -:1004C0000101017E7C0201027C7F020C027F631429 -:1004D00008146360100F1060434549516100000328 -:1004E000030000000000003E4549513E00217F010D -:1004F00000234549493142414959660C14247F047F -:10050000725151514E1E2949494640474850603664 -:10051000494949363149494A3C08142241000041C1 -:10052000221408141414141422147F1422181818F6 -:100530001818080808080820404D502000007900CD -:100540007900000000C04040404040011C3C786001 -:100550000F1412070211040308131BC2FC0121032C -:10056000280E14C30C0221EF203601C921102C0ED5 -:100570000C119D09C32A05CDCB05C3C61E215D20E4 -:1005800036002127203600233600C93601C36E11FC -:10059000210620C30D0B3603C3480F216720C30D6E -:1005A0000BE1CDBA14C10DC39414E1CDBA14C10D41 -:1005B000C3F115E12373237223C10DC31515232243 -:1005C0007E20E1235E2356EBC39015CD1317E12364 -:1005D00023C10DC3AC16CD1317E12323C10DC3D224 -:1005E000163E05C3D505AF321B20C93E01C3E71D2A -:1005F000215E203601C92EAA347EFE06D40E1E21AD -:10060000532036002A5420CD0A4F211127C9360025 -:100610002EA03601C92E0006AACDE4022EAB342E40 -:10062000B03601C3E1000000000000000000002E11 -:100630000AE52115000610225420E1C32A0EE52107 -:100640001000C3371E0630E5210500C3371EE57DC7 -:10065000FE92D2651EFE7ED26A1E2E8C34E12B2BBA -:100660003600C3F80C2E8BC35C1E2E8AC35C1E2280 -:100670008820C9227020C9227C20C9FE02210002E4 -:10068000C8FE03210002C8FE04210002C8210003A5 -:10069000C9FE022100FEC8FE032100FDC8FE0421A0 -:1006A00000FEC8FE052100FDC82100FDC9010E0D98 -:1006B00014121B211C1C1B0F0E080D13120000002E -:1006C000000000000000CD22172EA07EA7CAE10086 -:1006D00036002EAA3600E52EA25E2356EBCD0A4F39 -:1006E000E1C3141F00CDEB1DCD22172E8D34C32680 -:1006F00049CD22172E8D7EFE08D4FD1EC936002E50 -:100700007011131C0630C3040B000000FECBD2CFC7 -:100710000EC3981FE52EAE4E3600CDDA03E1C315A9 -:100720001E010310C3300CE5CD351F223620E12316 -:100730004E23C37513CD22172EAB7EA7210001C80F -:10074000FE01210001C8FE02210002C8FE032100B3 -:1007500002C8210003FE04C8FE05210003C82100D1 -:1007600003C9FE022100FEC8FE032100FDC8FE04ED -:100770002100FEC82100FDC9CD22172EAB7EC60187 -:1007800027E60FC61C21023EC3360500000000000C -:1007900000000000000000003A2E20F5C61A4F7C31 -:1007A000B9D2B01FF1C60B577CBADAB11FC3F01D26 -:1007B000F121C2203601C3E61F21C2207EA7C2C795 -:1007C0001FCDCB05C3920336002EB03AC32067CDB0 -:1007D0002C0A0E0611E01FCDB305C3C24EC39D0304 -:1007E0000000001A1A1A3A1E20FED0D4F41F32C399 -:1007F00020C3F01D3EC0C9000000000000FFFFC084 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex deleted file mode 100644 index 4176ee6a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_5.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C33D4035C036103E013240203A1E20FE2E -:1000100090D227403EFD324820211D203EA8962345 -:1000200086324A20C338403E02324820211D203A01 -:100030001E2086D690324A203EFDC360423A4020C0 -:10004000A7C24A40214120C3034021422035C27C3F -:10005000403602237EA7C29140CDEA402144207E53 -:10006000A7C27340237EFE4DC27C4021442036014E -:10007000C37C40237EFE55C27C4036492143207E0E -:10008000A7C28A40214720CD1C05CDBA40CD0341EF -:10009000C92A452011FCFF192245207DFE25C28A70 -:1000A00040214020360021432036002336002336ED -:1000B0002521492036C02336D0C92A45204E234663 -:1000C000235E2356233A4420A7CAD4403E0132423D -:1000D00020C3DC403A4220FE02C2E6403A4320A759 -:1000E000C2E6402245202A4920C93A4920FE48DA82 -:1000F000FD403A4A20FEE0D2FD40FE2AD0214320B6 -:100100003601C9CD2C0AC5E51AD304DB03772313C6 -:100110000DC20841AFD304DB0377E101200009C120 -:1001200005C20641C9010555410105554101085A5D -:100130004101086241010A6A41010B7441010E7FCD -:100140004102108D410212AD410217CD410218F556 -:1001500041021825420000000000000000040400D5 -:1001600000000000000C0C000000000000081C1C37 -:10017000080000000000000C1E1E1E0E0000000003 -:1001800000004C1C3E3F3E1C0C2000000000000004 -:100190000000008D003C007E00FF00FF007E003E5E -:1001A000000C00C000010000000000000000000082 -:1001B000000000350479057C00FC01FE03FF01FE10 -:1001C00001FE04FC003A04000000000000000000F2 -:1001D0000000006208F808FC03FE07EC0FFF07FFB1 -:1001E0000FBE07BC0FFD07FD03F801F208A80204CB -:1001F00004000000000000000000001220C804E815 -:1002000003F403FC0FFC07780F7A27FF17FE0EF8A4 -:1002100017FC0FE80FFC05FC17B224280120000092 -:100220000000000000000000000000E101FB30FCC5 -:1002300007FC0FFE07FE2EED0EFC1FFE07FE0FFD56 -:100240000FF81FBC0FFC07F803F413811000000027 -:100250000000000000FFFFFFFFFFFFFFFFFFFFFFA9 -:10026000324720214A207EFED0D47542FE30DC7A0F -:1002700042C34A400036D0C900003630C9C9000028 -:10028000CDBD0ACD3246C396423E10CDD5051AC328 -:10029000CF4240CDD5052119281110440E15CD2A85 -:1002A000053E50CDD505CD694321902B0E07CD15C8 -:1002B000433E01CD22433E40CDD505CD8646211695 -:1002C0002E1115451AFEFFCAE842FE5BCAE242E65D -:1002D0003FD5CD3605D1CDA443133E05CDD505C3BD -:1002E000C44221142FC389423E01CD22433E50CD4A -:1002F000D5050E0721902B0610113345CD000A0DB0 -:10030000C2F742211031114345010210CD1B0C3EB2 -:1003100060CDD505C911B5440610CD000A0DC21532 -:1003200043C9F521103111C544010210CD1B0CF158 -:100330003DC8F521903311E5440610CD000AF13D8A -:10034000C8F511F5440610CD000AF13DC8F57CFE54 -:100350003DC2584326312D2D0E01CD1543F1FE1B14 -:10036000DA65433E1BF5C34A43116D4421132D0149 -:100370000408CD1B0C167021122E0600E536800EE7 -:1003800005093601E10E200915C27C43118D442177 -:10039000133C010408CD1B0C11AD44211232060898 -:1003A000CD000AC9C5E5D51AE680CAB34311054593 -:1003B000C3B643110D452190310608CD000AD1E1A5 -:1003C000C1C9CD340BCD32463E04CD2243CD694365 -:1003D000CDA0463E10CDD5050E092115301125447E -:1003E0000608CDA443CD000A3E05CDD5050DC2E0DB -:1003F000433E01CD22433E60CDD505211530112865 -:10040000450E09CD2A053E40CDD505C90F0B001874 -:100410002929291B0B140D00111B1B110412021496 -:10042000041B2929298052387E3852800000101080 -:100430007E101000009244289228449200384438DC -:100440001038443800FE1038543810FE0000000008 -:1004500000000000000018527E52180000001852E0 -:100460007E521800000018527E52180000F0FFFF64 -:100470000F080000100400002002000040020000ED -:1004800040010000800100008001000080010000A8 -:1004900080010000800200004002000040040000D3 -:1004A00020080000103000000CC0FFFF0380808394 -:1004B0004D320408F0307ADDF4F4DD7A30000000CB -:1004C0000000000000E003E603E703FF0F790F7868 -:1004D0000F6C1FEC1FEC1F6C1F780F790FFF0FE7DD -:1004E00003E603E0030E18BE6D3D3C3D6DBE180EE5 -:1004F0000000000000193A6DFAFA6D3A1900000088 -:100500000000000000797C6EE6E66E7C79707878F9 -:10051000F8F87878798F0B840092045B880D920448 -:1005200091131B028E088DFF05080607131B303040 -:10053000301BFF387CECFEB7E5F860340C0000009F -:100540000000001000B800FC05FC0FCC1F9F1FBF6F -:100550000FFD1FC83C9819F03BE07FC03FC41FFC53 -:100560000D3800CDBD0ACD32463E30CDD50521181F -:1005700025117B19010113CD1B0C211829118E198E -:10058000010113CD1B0C21152511A119010113CD5A -:100590001B0C210C27113918010110CD1B0C210F48 -:1005A00026114918010120CD1B0C211225116918B3 -:1005B000010128CD1B0CCD86462E18262C3E1ACDC7 -:1005C00036053E0ACDD5053E018467FE33DABD45CA -:1005D0000E037DFE18C2DE45111C46C30246FE1501 -:1005E000C2E945111F46C30246FE12C2F44511225C -:1005F00046C30246FE0FC2FF45112546C3024611FF -:100600002846CD2A050E07112B46CD2A057DD60397 -:100610006FFE09C2BB453E60C3D505C91B1F1C1B2D -:10062000211C1B211C1D1C1C1D211C1B0F0E080D39 -:1006300013122E07263B116946D51A3CCD3605D13B -:100640001325257DFE09CA56467CFE2AC239462E50 -:10065000092633C339467CFE2FC2394626292E0788 -:10066000117E460608CD000AC90C0D0712FF100DB9 -:100670000E100D011A0D1207FF122422241C3C42F9 -:1006800099A5A581423C21472B01472C11272E1A01 -:10069000D640C00AD644C07ED67FC0AF32ED20C956 -:1006A000262B2E471100027E19861986FE3FC26254 -:1006B00003C9ED20C9CD8042000000CD6345CDCBFC -:1006C00005CDDF02CDD402CDBD0ACDCA01CD781F44 -:1006D000CD6102CD790221BF213601CDF202CDA933 -:1006E000012127207EA7CAE146237EFE01D306C250 -:1006F000EA463A2E20FE70D306DA2F47C3F24600B0 -:10070000CDB70A3AC62032E320C9CDCB05CDBD0A0C -:100710003AE32032C620CD764B000000CD8508009C -:100720000000C357063ABF21A7C2AA0EC36000212A -:10073000292036002A2D203A2C20FEFE010014C468 -:10074000850109221D20CD6D0D2113203601CDEC30 -:10075000470000000000D3062114207EA7C2A14755 -:10076000CDD847215D207EA7C29247CD770CD30616 -:100770003A1D20FEB0DC7F023A1D20FEB0D4580D99 -:100780003A1620A7CC9D0DD306CD054CCD7B48C392 -:100790004E47CD2903CDDF02CDD402CDCB05C373A7 -:1007A00016CD67043AAE20A7C2924721AC092210A9 -:1007B00020C36047CD9805CD22172EB07EA7C8363E -:1007C000002EAB7EFE03CCCF47CD3B4AC39805CD70 -:1007D000C243CDB94DC39805CD7C03E676FE54C027 -:1007E0002EED26207EA7C82B2B3603C93A1620A74C -:1007F000C82100203601C9000000000000000000F0 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex deleted file mode 100644 index 08e0316e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/roms/lrescue_6.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000003A1D20FE48D0215C207EA7C03601210683 -:1000100025060DCD340A21063D060DC3340A3A5D8E -:1000200020A7C230480000003E01CDD505C38B0D8E -:10003000E1215D20C3EF08CD00483A1620A7C8CDC6 -:1000400022172EAB7EFE05D26648FE03D26F48FE15 -:1000500001D2D14B2E8D7EFE07D82EAA7EFE04D86B -:10006000213E203601C92E8D7EFE04D8C360482E65 -:100070008D7EFE05D8C36048000000CD37483A3E6B -:1000800020A7C8CD22172EAB7EFE06D2B648FE05AD -:10009000CABB48FE04CAC04806583A1D20B8D2ACB4 -:1000A00048213F2036012129203600C92140207EE9 -:1000B000A7C02B3600C90688C39A480678C39A4859 -:1000C0000668C39A48DB02E60321AC21F58677F186 -:1000D00021AC228677C900000000003A5C20A7C04E -:1000E0003A9C20E610CA0E48C330043A3F20A7C20B -:1000F0000040C93AEF20A7C83AC420C30349000012 -:10010000C3F348B032C420D303C93AC420A032C4D8 -:1001100020D303C90624C300490620C30A49CDE6FB -:100120001D0628C3004906F7CD0A49C3180D3AC574 -:1001300020B032C520D305C93AC520A032C520D38E -:1001400005C90604CD2E493E05CDD50506FBC338AD -:10015000493A1620A7C83A0020A7CA62490622C316 -:10016000004906FDC30A49CA744936000621CD007C -:1001700049C3201006FECD0A49C90601CD0049C376 -:10018000481006FEC30A493A1620A7C21F4C3A9CE3 -:1001900020E604C21F4C3A1D20FE30C3A34906EFDF -:1001A000C33849DA9E490610C32E493AA020A7C297 -:1001B000B74906FCC338493A9C20E608CACE49062E -:1001C00001CD2E49219B2034E601C0C3B24906026D -:1001D000CD2E49219B2034E601C8C3B249CD8249C6 -:1001E000C348103AEE20A7C0211C390628C3EB09EA -:1001F0000000000000CD22172EAB7EA7210500C80D -:10020000FE01211000C8FE02211500C8213000C9DE -:100210003AC6200FDA224A21122B112D4A0E0EC3A4 -:100220002A05CD174A2112373E1DC336050F0B0094 -:10023000181B0F0B00180411261E27210F2C110B61 -:100240001A0608CD000A115A4A0E0BCD2A05CD65B3 -:100250004A210F2ECD2805C3CB05281B1B1C1B0FC5 -:100260000E080D1312CD22172EAB7EA711804AC89F -:10027000FE0111824AC8FE0211844AC811864AC989 -:100280001B211D1C1D211F1CCDCB0521C620C90013 -:1002900000000000000000211028D306C90620CD70 -:1002A0003849C37D1D3AEE20A7C23C4CCD2217C36E -:1002B0006A0321C6207E0FDAE54A3622CD22172EA8 -:1002C000AC35C2284BCD584B210F393E1ECD3605DB -:1002D000CDB602CD884A3621CD22172EAC7EA7CAD4 -:1002E000B304C38B4BCD22172EAC35C20E4BCD5869 -:1002F0004BCDB602CDCB0521C6203622CD22172EFE -:10030000AC7EA7CAB30421C6203622C38B4BCD4294 -:100310004B21C6203622CD22172EAC7EA7C28B4B96 -:1003200021C6203621C38B4BCD424B21C62036211E -:10033000CD22172EAC7EA7C28B4B21C6203622C3FE -:10034000E1007E3D210127CA504B24243DC24A0BC7 -:100350000610CD340AC3CB05210F2811634B0E13B1 -:10036000C3B30506000C041B0E1504111B0F0B0074 -:10037000180411261D273AC6200FDA864B062021C5 -:10038000C52070C30A050600C37F4BCDBD0ACD76DC -:100390004BCD104AC3B44B0600CD0A4900000021E2 -:1003A000C22011651B0609CD040B21000022E520A7 -:1003B00022EE20C9CD3B4AC3E10021E5203AC62008 -:1003C0000FD823C90000000000007E3DC84FC34F76 -:1003D000022E8D7EFE06D8C3604800CDBA4B7EA7A4 -:1003E000C80630CD1309B8D8CD22172EAC34CD466F -:1003F00002CDBA4B36000610CD00493E20CDD505C2 -:1004000006EFC30A49CDDB4BC3DB48AF325920CDE1 -:10041000974BCDA901C3824CCD661D210000C92197 -:100420003F207EA7CA9E49237EA7CA9E49C3A649EC -:10043000CD8403C3E100CD5149C3004ECD22172E18 -:10044000A07EA7CAB24A3600C3674C00CDBD0ACD14 -:1004500022172EA234211B260E0411634CCD2A052F -:10046000C3154E0514040B2EAC7E3DCAB24ACDA472 -:1004700003C3E14CCDA40121C2207EA7C03600C336 -:10048000AD4D21DC20360021E3203600C3B304004B -:10049000000000000000000000000000000000005C -:1004A00000000000CD22172EB03601C9CD104ACD74 -:1004B0003B4AC3CB05CD22172EAE4E3600C3DA031E -:1004C000AF32E320C9000000000000CD22172EA2A9 -:1004D0007EA7CADB4C211920C38E0F211B2036FEBC -:1004E000C9CD764BC3B24A2256203E01325A20C9AA -:1004F0003AEF20A7C8C3874921C6203621C900008A -:1005000011C04D21C0210606CD040BF3CD114DFBCA -:10051000C92AC0217EA7C8234E5F07DA564DE5CD14 -:100520002B4DE10DC21E4D23C3144DC5D5CD694DD4 -:10053000D1C12AC221530608CD2E49D3062B7CA750 -:10054000C815C23D4D5306F7CD38492B7CA7C815B9 -:10055000C24B4DC3354DE52AC4212B7CA7C25A4D51 -:100560000DC2574DE123C3144DDB0121EC200FDAFE -:10057000754D3600C97EA7C036FF2B7EFE09C3A885 -:100580004D330228022202330228022202330226BD -:10059000021E02330226021E0222021B0216022241 -:1005A000021B021602190600D034C3AC0A11B34D67 -:1005B000C3034DC64DFF0DFF50116D4FC3034D00DA -:1005C000814DFF0DFF5019011B011E012201260163 -:1005D00028012D0133012D012801260122011E01D0 -:1005E0001B011903000000000000000000000000D3 -:1005F00000000000000000000000000000000000FB -:100600003A1620A7C0CD410AE610C821A421347EA5 -:10061000FE02D83600CD22172EA27EA7C8EB2139C4 -:100620004E373E99CE0096EB862777211B2BCD7453 -:1006300005211B2D3E1CC3360501C3D74EAFBEC2DC -:10064000574E342AA82122B82021AA4E22B62021B2 -:10065000B4203618C3834E2AB620EB2AB8200608E9 -:10066000CDC8092AB8207DFE40DAE14E000021B451 -:1006700020AFBECA7A4E35CA954E23BECA834E35C8 -:10068000CAA14E2AB620EB2AB8202B2B0022B82074 -:100690000608C3C80923361021B24E22B620C386ED -:1006A0004E21BA4E22B620C3864E00C031DFFCDF99 -:1006B00031C05D5D2A3E1C3CE40C1090987B3F7B72 -:1006C0008886CDE64E36FFCDA9017EA7D306C2CAE5 -:1006D0004ECD2217C39D0321B220AFBEC823C33E17 -:1006E0004EAF32B220C9CD370621B220C9CD221774 -:1006F0002EA27EA7CA2010CD2010C3F60F00000046 -:100700003A5A20A7210300C41A4F3AEF20A7C82263 -:10071000F22021F1203601C24D05AF325A202105C9 -:1007200000C92A1D2022A821C3D40221B3203601EA -:10073000CDA9012B36017ED306A7C2364FCD221795 -:1007400019041E0216041E0222031E01280226039B -:100750001E03190312060000000422011E012606D2 -:1007600000000000000000000000000000404FFFFB -:1007700011FF50CD22172EA27EA7CADD49C37A49A8 -:100780003A1620A7C82A2D203A2C20A7F2934F7C96 -:10079000C60467CD2C0AAF0160010977012000096A -:1007A00077012000097701200209770120000977ED -:1007B0000120000977C93A1620A7C82A1D20EB2A74 -:1007C0002D207DD60ABBD07CC60CBAD0C612BAD8B2 -:1007D0003E01321820C9CD22172EAB7EFE02D8FE74 -:1007E00006D2F34F16FC2174207221802072218CD6 -:1007F0002072C916FBC3E64F000000000000000095 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf deleted file mode 100644 index 7344eeb5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "OzmaWars" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf deleted file mode 100644 index 567324b3..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.qsf +++ /dev/null @@ -1,178 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 02:57:11 June 09, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# OzmaWars_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name TOP_LEVEL_ENTITY OzmaWars_mist -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# --------------------------- -# start ENTITY(OzmaWars_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(OzmaWars_mist) -# ------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_memory.sv -set_global_assignment -name VHDL_FILE rtl/OzmaWars_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip -set_global_assignment -name VHDL_FILE rtl/roms/mw01.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw02.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw03.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw04.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw05.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw06.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/OzmaWars.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/Release/OzmaWars.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/Release/OzmaWars.rbf deleted file mode 100644 index 06dd508d..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/Release/OzmaWars.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv deleted file mode 100644 index 795f9949..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_memory.sv +++ /dev/null @@ -1,80 +0,0 @@ - -module OzmaWars_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - - -mw01 mw01 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_0) -); - -mw02 mw02 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_1) -); - -mw03 mw03 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_2) -); - -mw04 mw04 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_3) -); - -mw05 mw05 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_4) -); - -mw06 mw06 ( - .clk(Clock), - .addr(Addr[10:0]), - .data(rom_data_5) -); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4; - 5'b01001 : Rom_out = rom_data_5; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv deleted file mode 100644 index bc82fcec..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_mist.sv +++ /dev/null @@ -1,210 +0,0 @@ -module OzmaWars_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Ozma Wars;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .MoveUp(~m_up), - .MoveDown(~m_down), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -OzmaWars_memory OzmaWars_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -OzmaWars_overlay OzmaWars_overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd deleted file mode 100644 index b0188292..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd +++ /dev/null @@ -1,225 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity OzmaWars_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - CAB : in std_logic_vector(7 downto 0); - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end OzmaWars_overlay; - -architecture rtl of OzmaWars_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - - signal Overlay_A1 : boolean; - signal Overlay_A2 : boolean; - signal Overlay_A3 : boolean; - signal Overlay_A3_VCnt : boolean; - - signal Overlay_B1 : boolean; - signal Overlay_B2 : boolean; - signal Overlay_B2_VCnt : boolean; - - signal Overlay_G1 : boolean; - - signal Overlay_P1 : boolean; - - signal Overlay_R1 : boolean; - signal Overlay_R2 : boolean; - - signal Overlay_Y1 : boolean; - signal Overlay_Y2 : boolean; - signal Overlay_Y2_VCnt : boolean; - - signal VideoRGB : std_logic_vector(2 downto 0); - signal col_data : std_logic_vector(3 downto 0); - -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - - Overlay_A1 <= false; - Overlay_A2 <= false; - Overlay_A3 <= false; - Overlay_A3_VCnt <= false; - - Overlay_B1 <= false; - Overlay_B2 <= false; - Overlay_B2_VCnt <= false; - - Overlay_G1 <= false; - - Overlay_P1 <= false; - - Overlay_R1 <= false; - Overlay_R2 <= false; - - Overlay_Y1 <= false; - Overlay_Y2 <= false; - Overlay_Y2_VCnt <= false; - - - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = 0) then - Overlay_A3_VCnt <= true; - elsif (Vcnt = 86) then - Overlay_B2_VCnt <= true; - Overlay_A3_VCnt <= false; - elsif (Vcnt = 168) then - Overlay_Y2_VCnt <= true; - Overlay_B2_VCnt <= false; - elsif (Vcnt = 232) then - Overlay_Y2_VCnt <= false; - end if; - end if; - - if (HCnt = 500) and Overlay_A3_VCnt then - Overlay_A3 <= true; - elsif (HCnt = 540) then - Overlay_A3 <= false; - end if; - - if (HCnt = 486) and Overlay_B2_VCnt then - Overlay_B2 <= true; - elsif (HCnt = 540) then - Overlay_B2 <= false; - end if; - - if (HCnt = 486) and Overlay_Y2_VCnt then - Overlay_Y2 <= true; - elsif (HCnt = 540) then - Overlay_Y2 <= false; - end if; - - if (HCnt = 64) then - Overlay_R2 <= true; - elsif (HCnt = 96) then - Overlay_A2 <= true; - Overlay_R2 <= false; - elsif (HCnt = 120) then - Overlay_A2 <= false; - Overlay_R1 <= true; - elsif (HCnt = 166) then - Overlay_R1 <= false; - Overlay_Y1 <= true; - elsif (HCnt = 228) then - Overlay_Y1 <= false; - Overlay_P1 <= true; - elsif (HCnt = 292) then - Overlay_P1 <= false; - Overlay_A1 <= true; - elsif (HCnt = 358) then - Overlay_G1 <= true; - Overlay_A1 <= false; - elsif (HCnt = 430) then - Overlay_G1 <= false; - Overlay_B1 <= true; - elsif (HCnt = 486) then - Overlay_B1 <= false; --- if Overlay_A3_VCnt then --- Overlay_A2 <= true; --- if Overlay_B2_VCnt then --- Overlay_B2 <= true; --- if Overlay_Y2_VCnt then --- Overlay_Y2 <= true; --- elsif (HCnt = 500) then --- Overlay_A3 <= false; --- elsif (HCnt = 540) then --- Overlay_B2 <= false; --- Overlay_Y2 <= false; - end if; - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA - VideoRGB <= "011"; - elsif Overlay_B1 or Overlay_B2 then--BLUE - VideoRGB <= "001"; - elsif Overlay_G1 then--GREEN - VideoRGB <= "010"; - elsif Overlay_P1 then--PINK - VideoRGB <= "101"; - elsif Overlay_R1 or Overlay_R2 then--RED - VideoRGB <= "100"; - elsif Overlay_Y1 or Overlay_Y2 then--YELLOW - VideoRGB <= "110"; - else - VideoRGB <= "111";--WHITE - end if; - end if; - end process; - --- colPROM: entity work.clr ---port map( --- clk => Clk, --- addr => CAB, --should be Video Counters --- data => col_data ---); - --- O_VIDEO_R <= col_data(2); --- O_VIDEO_G <= col_data(1); --- O_VIDEO_B <= col_data(0); - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd deleted file mode 100644 index db58d70b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/dac.vhd +++ /dev/null @@ -1,48 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity dac is - generic ( - C_bits : integer := 8 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); -end dac; - -architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); -begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; -end rtl; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd deleted file mode 100644 index e35bdc82..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,273 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - MoveUp : in std_logic; - MoveDown : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '1';-- - GDB0(1) <= '1';-- - GDB0(2) <= '1';-- - GDB0(3) <= '1';-- - GDB0(4) <= '1';-- - GDB0(5) <= '1';-- - GDB0(6) <= '1';-- - GDB0(7) <= '1';-- - - GDB1(0) <= Coin; - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1'; - GDB1(4) <= not Fire;--controller - GDB1(5) <= not MoveLeft;--controller - GDB1(6) <= not MoveRight;--controller - GDB1(7) <= '1'; - - GDB2(0) <= '0';--active high - GDB2(1) <= '0';--active high - GDB2(2) <= '0';--active high - GDB2(3) <= '0';--active high - GDB2(4) <= '0';--DIPLOCK --active high - GDB2(5) <= not Sel1Player;--active low - GDB2(6) <= not Coin;--active low - GDB2(7) <= not Sel2Player;--active low - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd deleted file mode 100644 index 1e6a8db4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw01.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw01 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw01 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"F3",X"31",X"7C",X"02",X"C3",X"36",X"02",X"C7",X"F5",X"AF",X"32",X"05",X"20",X"C3",X"49",X"00", - X"F5",X"3E",X"80",X"C3",X"0A",X"00",X"C7",X"C7",X"F3",X"E5",X"D5",X"C5",X"F5",X"C3",X"2B",X"01", - X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"D4",X"01",X"F3",X"CD",X"0F",X"02",X"47",X"C3",X"F3",X"01", - X"F3",X"CD",X"0F",X"02",X"2F",X"C3",X"FB",X"01",X"F3",X"CD",X"0F",X"02",X"79",X"C3",X"04",X"02", - X"AF",X"77",X"23",X"05",X"C2",X"41",X"00",X"C9",X"C7",X"AF",X"32",X"0B",X"20",X"22",X"26",X"20", - X"21",X"00",X"00",X"39",X"22",X"28",X"20",X"F1",X"2A",X"26",X"20",X"E5",X"2A",X"0C",X"20",X"F9", - X"2A",X"28",X"20",X"E5",X"D5",X"C5",X"F5",X"3A",X"06",X"20",X"F5",X"21",X"00",X"00",X"39",X"22", - X"0C",X"20",X"EB",X"2A",X"9E",X"02",X"EB",X"7A",X"2F",X"57",X"7B",X"2F",X"5F",X"19",X"D2",X"BA", - X"00",X"3A",X"0B",X"20",X"A7",X"C2",X"7B",X"01",X"CD",X"B6",X"02",X"21",X"07",X"20",X"7E",X"23", - X"A6",X"CA",X"05",X"01",X"47",X"23",X"4E",X"21",X"1E",X"20",X"16",X"80",X"7A",X"A0",X"CA",X"AC", - X"00",X"35",X"C2",X"AC",X"00",X"A1",X"C2",X"BA",X"00",X"7A",X"B1",X"4F",X"23",X"7A",X"2F",X"A0", - X"47",X"CA",X"BE",X"00",X"7A",X"1F",X"57",X"C3",X"9D",X"00",X"2A",X"A2",X"02",X"E9",X"21",X"09", - X"20",X"71",X"7E",X"2F",X"2B",X"A6",X"77",X"2A",X"0C",X"20",X"F9",X"0E",X"80",X"3A",X"09",X"20", - X"47",X"3A",X"0A",X"20",X"2F",X"A0",X"5F",X"3A",X"07",X"20",X"A3",X"CA",X"05",X"01",X"11",X"0E", - X"20",X"78",X"A1",X"C2",X"EE",X"00",X"79",X"1F",X"4F",X"13",X"13",X"C3",X"E1",X"00",X"2F",X"A0", - X"32",X"09",X"20",X"79",X"32",X"06",X"20",X"1A",X"6F",X"13",X"1A",X"67",X"F9",X"F1",X"C1",X"D1", - X"E1",X"D3",X"06",X"FB",X"C9",X"F3",X"2A",X"0C",X"20",X"F9",X"01",X"0A",X"00",X"09",X"22",X"0C", - X"20",X"F1",X"A7",X"CA",X"1E",X"01",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"05",X"01",X"32",X"06", - X"20",X"F1",X"C1",X"D1",X"E1",X"F9",X"E1",X"D3",X"06",X"FB",X"C9",X"21",X"06",X"20",X"7E",X"47", - X"23",X"A6",X"CA",X"05",X"01",X"23",X"B6",X"77",X"21",X"1E",X"20",X"11",X"0E",X"20",X"78",X"17", - X"DA",X"49",X"01",X"23",X"13",X"13",X"C3",X"3F",X"01",X"44",X"4D",X"21",X"00",X"00",X"39",X"7D", - X"12",X"13",X"7C",X"12",X"11",X"08",X"00",X"19",X"F9",X"E3",X"7E",X"23",X"E3",X"02",X"C3",X"C7", - X"00",X"F3",X"A7",X"CA",X"70",X"01",X"C5",X"47",X"3A",X"07",X"20",X"A0",X"CA",X"72",X"01",X"C1", - X"FB",X"C9",X"78",X"C1",X"F5",X"32",X"0B",X"20",X"C3",X"4D",X"00",X"47",X"21",X"06",X"20",X"77", - X"23",X"B6",X"77",X"31",X"7C",X"02",X"78",X"33",X"33",X"33",X"33",X"17",X"D2",X"87",X"01",X"D1", - X"E1",X"F9",X"EB",X"FB",X"E9",X"F3",X"F5",X"A7",X"C4",X"9E",X"01",X"F1",X"FB",X"C9",X"C5",X"E5", - X"2F",X"47",X"0E",X"03",X"21",X"07",X"20",X"7E",X"A0",X"77",X"23",X"0D",X"C2",X"A7",X"01",X"36", - X"00",X"21",X"2A",X"20",X"78",X"2F",X"23",X"17",X"D2",X"B6",X"01",X"36",X"00",X"E1",X"C1",X"C9", - X"F3",X"3A",X"06",X"20",X"CD",X"9E",X"01",X"C3",X"C7",X"00",X"F1",X"C1",X"D1",X"E1",X"3A",X"00", - X"20",X"FB",X"A7",X"C9",X"CD",X"27",X"02",X"70",X"3E",X"D3",X"32",X"01",X"20",X"EB",X"3E",X"C9", - X"32",X"03",X"20",X"21",X"CC",X"4F",X"CD",X"2A",X"02",X"32",X"02",X"20",X"1A",X"CD",X"01",X"20", - X"C3",X"CA",X"01",X"CD",X"27",X"02",X"B0",X"77",X"C3",X"D8",X"01",X"47",X"CD",X"27",X"02",X"A0", - X"77",X"C3",X"D8",X"01",X"2F",X"4F",X"CD",X"27",X"02",X"B0",X"A1",X"77",X"C3",X"D8",X"01",X"32", - X"00",X"20",X"E3",X"33",X"33",X"EB",X"E3",X"7E",X"23",X"E3",X"3B",X"3B",X"E5",X"C5",X"32",X"04", - X"20",X"3A",X"00",X"20",X"F5",X"D5",X"C9",X"21",X"2A",X"20",X"3A",X"04",X"20",X"85",X"6F",X"7C", - X"CE",X"00",X"67",X"7E",X"A7",X"C9",X"D1",X"E1",X"F9",X"EB",X"CD",X"3E",X"02",X"E9",X"F3",X"F5", - X"C5",X"E5",X"AF",X"06",X"2D",X"21",X"06",X"20",X"CD",X"41",X"00",X"21",X"00",X"24",X"22",X"0C", - X"20",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"F3",X"F5",X"C5",X"E5",X"21",X"00",X"00",X"06", - X"00",X"7E",X"80",X"47",X"23",X"7C",X"FE",X"20",X"C2",X"61",X"02",X"78",X"C6",X"1B",X"C2",X"78", - X"02",X"E1",X"C1",X"F1",X"D3",X"06",X"FB",X"C9",X"2A",X"A0",X"02",X"E9",X"EE",X"02",X"8D",X"21", - X"8E",X"07",X"AD",X"21",X"A3",X"0A",X"C3",X"21",X"30",X"0D",X"DF",X"21",X"B1",X"11",X"F7",X"21", - X"5B",X"13",X"0D",X"22",X"C3",X"13",X"23",X"22",X"A4",X"02",X"24",X"22",X"A7",X"02",X"25",X"22", - X"AE",X"02",X"B2",X"02",X"C3",X"AA",X"02",X"C3",X"AA",X"02",X"F3",X"C3",X"AA",X"02",X"F3",X"C3", - X"AE",X"02",X"F3",X"C3",X"B2",X"02",X"2A",X"59",X"20",X"2B",X"22",X"59",X"20",X"DB",X"01",X"0F", - X"DA",X"C8",X"02",X"AF",X"32",X"47",X"20",X"C9",X"3A",X"46",X"20",X"FE",X"09",X"D0",X"3A",X"47", - X"20",X"A7",X"C0",X"3E",X"01",X"32",X"47",X"20",X"DB",X"02",X"07",X"3A",X"46",X"20",X"D2",X"E3", - X"02",X"C6",X"01",X"C6",X"01",X"27",X"E6",X"0F",X"32",X"46",X"20",X"D3",X"06",X"C9",X"CD",X"A4", - X"04",X"CD",X"16",X"07",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD",X"24",X"07",X"21",X"39",X"20", - X"11",X"6E",X"21",X"CD",X"24",X"07",X"CD",X"16",X"07",X"3E",X"01",X"32",X"58",X"20",X"CD",X"A4", - X"04",X"CD",X"6F",X"03",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"0A",X"06",X"3A",X"46",X"20",X"A7", - X"C2",X"78",X"03",X"3A",X"58",X"20",X"0F",X"DA",X"1C",X"03",X"CD",X"6F",X"03",X"CD",X"EC",X"06", - X"CD",X"0A",X"06",X"3E",X"01",X"32",X"30",X"20",X"3A",X"30",X"20",X"A7",X"C2",X"38",X"03",X"3E", - X"20",X"CD",X"61",X"01",X"3A",X"46",X"20",X"A7",X"C2",X"78",X"03",X"CD",X"0A",X"06",X"3A",X"2E", - X"20",X"A7",X"CA",X"5F",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD",X"61",X"01",X"3A", - X"58",X"20",X"0F",X"D2",X"44",X"03",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"C3",X"11",X"03",X"CD", - X"B2",X"05",X"CD",X"1E",X"05",X"C3",X"DC",X"05",X"CD",X"3E",X"02",X"CD",X"16",X"07",X"AF",X"32", - X"58",X"20",X"32",X"48",X"20",X"CD",X"A4",X"04",X"3E",X"04",X"CD",X"61",X"01",X"CD",X"DC",X"05", - X"CD",X"0A",X"06",X"DB",X"01",X"E6",X"06",X"CA",X"90",X"03",X"EE",X"04",X"CA",X"AE",X"04",X"EE", - X"06",X"C2",X"90",X"03",X"3A",X"46",X"20",X"3D",X"CA",X"90",X"03",X"3D",X"32",X"46",X"20",X"3E", - X"81",X"32",X"48",X"20",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40",X"20",X"CD",X"75", - X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40",X"20",X"CD",X"0A", - X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"E9",X"03",X"3E",X"80",X"CD",X"95",X"01",X"3E",X"80",X"CD", - X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E2",X"03",X"3A",X"2A",X"20",X"0F",X"D2",X"CE",X"03", - X"0F",X"DA",X"48",X"04",X"CD",X"EE",X"1F",X"CD",X"3E",X"02",X"3A",X"48",X"20",X"3C",X"E6",X"81", - X"32",X"48",X"20",X"3A",X"57",X"20",X"A7",X"3E",X"01",X"32",X"57",X"20",X"CA",X"B7",X"03",X"CD", - X"1E",X"05",X"3A",X"3C",X"20",X"A7",X"FA",X"F7",X"03",X"3A",X"29",X"22",X"47",X"3A",X"31",X"22", - X"B0",X"F4",X"75",X"07",X"3E",X"08",X"CD",X"61",X"01",X"CD",X"DC",X"05",X"3E",X"40",X"CD",X"61", - X"01",X"3E",X"01",X"32",X"2D",X"20",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"80",X"CD",X"61",X"01", - X"3E",X"10",X"CD",X"61",X"01",X"C3",X"CE",X"03",X"3A",X"2A",X"20",X"A7",X"F5",X"CD",X"3E",X"02", - X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"3E",X"1F",X"F7",X"0C",X"CD",X"4A",X"07",X"CD",X"0A", - X"06",X"F1",X"F2",X"6B",X"04",X"21",X"DA",X"4F",X"CD",X"F4",X"14",X"21",X"E2",X"1C",X"3A",X"48", - X"20",X"0F",X"DA",X"78",X"04",X"21",X"F9",X"1C",X"CD",X"F4",X"14",X"CD",X"01",X"07",X"3A",X"48", - X"20",X"A7",X"F2",X"93",X"04",X"3A",X"29",X"22",X"A7",X"F2",X"FA",X"03",X"3A",X"31",X"22",X"A7", - X"F2",X"FA",X"03",X"AF",X"32",X"48",X"20",X"CD",X"F6",X"04",X"3A",X"46",X"20",X"A7",X"CA",X"06", - X"03",X"C3",X"78",X"03",X"AF",X"E7",X"09",X"E7",X"0A",X"E7",X"0B",X"E7",X"0C",X"C9",X"3E",X"01", - X"32",X"48",X"20",X"21",X"46",X"20",X"35",X"CD",X"A4",X"05",X"CD",X"1E",X"05",X"AF",X"32",X"40", - X"20",X"CD",X"75",X"07",X"CD",X"EC",X"06",X"3E",X"20",X"CD",X"61",X"01",X"3E",X"08",X"32",X"40", - X"20",X"CD",X"0A",X"06",X"3A",X"2E",X"20",X"A7",X"CA",X"EC",X"04",X"3E",X"80",X"CD",X"95",X"01", - X"3E",X"80",X"CD",X"61",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"E5",X"04",X"3A",X"2A",X"20",X"0F", - X"D2",X"D1",X"04",X"C3",X"48",X"04",X"2A",X"26",X"22",X"EB",X"2A",X"2E",X"22",X"7C",X"BA",X"DA", - X"0B",X"05",X"C2",X"0A",X"05",X"7D",X"BB",X"DA",X"0B",X"05",X"EB",X"2A",X"43",X"20",X"7A",X"BC", - X"D8",X"C2",X"17",X"05",X"7B",X"BD",X"D8",X"EB",X"22",X"43",X"20",X"C3",X"0A",X"06",X"3A",X"48", - X"20",X"0F",X"21",X"39",X"20",X"11",X"26",X"22",X"06",X"08",X"DA",X"30",X"05",X"11",X"2E",X"22", - X"CD",X"34",X"16",X"21",X"68",X"20",X"11",X"36",X"22",X"06",X"D8",X"3A",X"48",X"20",X"0F",X"DA", - X"45",X"05",X"11",X"F6",X"22",X"CD",X"34",X"16",X"CD",X"16",X"07",X"3A",X"48",X"20",X"A7",X"C8", - X"3E",X"20",X"E7",X"0A",X"3A",X"48",X"20",X"0F",X"3E",X"20",X"D2",X"5E",X"05",X"AF",X"E7",X"0C", - X"06",X"10",X"CD",X"D3",X"07",X"7E",X"FE",X"38",X"C2",X"70",X"05",X"3E",X"01",X"EF",X"0A",X"C9", - X"7E",X"FE",X"33",X"C2",X"7B",X"05",X"3E",X"01",X"C3",X"DA",X"07",X"7E",X"FE",X"70",X"C2",X"86", - X"05",X"3E",X"10",X"EF",X"0C",X"C9",X"7E",X"FE",X"50",X"C2",X"95",X"05",X"3E",X"01",X"EF",X"0A", - X"3E",X"1F",X"C3",X"DA",X"07",X"7E",X"FE",X"3F",X"CA",X"90",X"05",X"23",X"23",X"23",X"23",X"05", - X"C2",X"65",X"05",X"C9",X"3E",X"04",X"CD",X"95",X"01",X"21",X"26",X"22",X"11",X"B6",X"23",X"CD", - X"24",X"07",X"DB",X"02",X"E6",X"03",X"87",X"21",X"D4",X"05",X"CD",X"2D",X"02",X"5F",X"23",X"56", - X"EB",X"22",X"28",X"22",X"22",X"30",X"22",X"3E",X"01",X"32",X"2D",X"22",X"32",X"35",X"22",X"AF", - X"32",X"57",X"20",X"C9",X"DC",X"05",X"D0",X"07",X"C4",X"09",X"AC",X"0D",X"21",X"34",X"1D",X"CD", - X"F4",X"14",X"21",X"5D",X"1D",X"CD",X"F4",X"14",X"21",X"68",X"1D",X"CD",X"F4",X"14",X"2A",X"43", - X"20",X"11",X"1D",X"30",X"CD",X"BE",X"06",X"2A",X"26",X"22",X"11",X"1D",X"27",X"CD",X"BE",X"06", - X"2A",X"2E",X"22",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9",X"3A",X"46",X"20",X"21",X"01",X"3D", - X"CD",X"D9",X"06",X"CD",X"7B",X"06",X"60",X"69",X"11",X"01",X"2C",X"CD",X"BE",X"06",X"3A",X"59", - X"20",X"A7",X"CA",X"70",X"06",X"F3",X"2A",X"41",X"20",X"7C",X"B5",X"CA",X"59",X"06",X"EB",X"21", - X"00",X"00",X"22",X"41",X"20",X"2A",X"39",X"20",X"FB",X"7D",X"83",X"27",X"6F",X"7C",X"8A",X"27", - X"67",X"22",X"39",X"20",X"7B",X"21",X"1C",X"33",X"CD",X"D0",X"06",X"CD",X"C9",X"06",X"3E",X"40", - X"32",X"59",X"20",X"21",X"53",X"1D",X"CD",X"F4",X"14",X"FB",X"3A",X"48",X"20",X"A7",X"C8",X"2A", - X"39",X"20",X"0F",X"11",X"1D",X"27",X"DA",X"6C",X"06",X"11",X"1D",X"39",X"CD",X"BE",X"06",X"C9", - X"2A",X"53",X"1D",X"06",X"48",X"CD",X"E1",X"06",X"C3",X"59",X"06",X"2A",X"3B",X"20",X"11",X"A2", - X"06",X"01",X"00",X"00",X"7C",X"A7",X"F8",X"29",X"29",X"29",X"DA",X"95",X"06",X"7C",X"B5",X"C8", - X"13",X"13",X"C3",X"89",X"06",X"1A",X"81",X"27",X"4F",X"13",X"1A",X"88",X"27",X"47",X"13",X"C3", - X"89",X"06",X"92",X"81",X"96",X"40",X"48",X"20",X"24",X"10",X"12",X"05",X"56",X"02",X"28",X"01", - X"64",X"00",X"32",X"00",X"16",X"00",X"08",X"00",X"04",X"00",X"02",X"00",X"01",X"00",X"EB",X"D5", - X"7A",X"CD",X"D0",X"06",X"D1",X"7B",X"CD",X"D0",X"06",X"06",X"00",X"0E",X"08",X"C3",X"3D",X"16", - X"F5",X"0F",X"0F",X"0F",X"0F",X"CD",X"D9",X"06",X"F1",X"E6",X"0F",X"47",X"0E",X"08",X"C3",X"3D", - X"16",X"AF",X"11",X"20",X"00",X"77",X"19",X"05",X"C2",X"E5",X"06",X"C9",X"3E",X"80",X"CD",X"61", - X"01",X"3E",X"40",X"CD",X"61",X"01",X"3E",X"10",X"CD",X"61",X"01",X"3E",X"08",X"CD",X"61",X"01", - X"C9",X"21",X"F4",X"01",X"22",X"59",X"20",X"CD",X"DF",X"07",X"A7",X"F2",X"07",X"07",X"CD",X"E7", - X"07",X"06",X"68",X"C3",X"E1",X"06",X"21",X"00",X"24",X"06",X"00",X"70",X"23",X"7C",X"FE",X"40", - X"DA",X"19",X"07",X"C9",X"06",X"00",X"70",X"23",X"7C",X"BA",X"C2",X"26",X"07",X"7D",X"BB",X"C2", - X"26",X"07",X"C9",X"21",X"62",X"09",X"06",X"1A",X"36",X"00",X"23",X"05",X"C2",X"38",X"07",X"01", - X"06",X"00",X"09",X"7C",X"FE",X"40",X"DA",X"36",X"07",X"C9",X"3A",X"48",X"20",X"0F",X"11",X"39", - X"20",X"21",X"26",X"22",X"06",X"08",X"DA",X"5C",X"07",X"21",X"2E",X"22",X"CD",X"34",X"16",X"21", - X"36",X"22",X"11",X"68",X"20",X"06",X"C0",X"3A",X"48",X"20",X"0F",X"DA",X"71",X"07",X"21",X"F6", - X"22",X"CD",X"34",X"16",X"C9",X"CD",X"DC",X"05",X"CD",X"0A",X"06",X"3A",X"48",X"20",X"0F",X"21", - X"10",X"1D",X"DA",X"88",X"07",X"21",X"22",X"1D",X"CD",X"F4",X"14",X"C3",X"01",X"07",X"3A",X"2E", - X"20",X"E6",X"01",X"C2",X"89",X"09",X"21",X"18",X"8A",X"22",X"49",X"20",X"AF",X"32",X"4F",X"20", - X"21",X"8F",X"1B",X"22",X"4D",X"20",X"21",X"02",X"0F",X"22",X"4B",X"20",X"CD",X"1C",X"0A",X"DF", - X"01",X"2A",X"49",X"20",X"7C",X"C6",X"F8",X"67",X"3A",X"05",X"20",X"AC",X"47",X"3A",X"48",X"20", - X"FE",X"80",X"78",X"07",X"CA",X"CD",X"07",X"D2",X"AF",X"07",X"C3",X"D0",X"07",X"DA",X"AF",X"07", - X"C3",X"EF",X"07",X"CD",X"4F",X"0D",X"21",X"E8",X"20",X"C9",X"E7",X"0B",X"F7",X"0A",X"C9",X"3E", - X"00",X"D3",X"03",X"3A",X"5A",X"20",X"C9",X"3E",X"20",X"EF",X"0A",X"2A",X"10",X"1D",X"C9",X"21", - X"3D",X"20",X"34",X"CD",X"50",X"0A",X"3A",X"3C",X"20",X"A7",X"FA",X"84",X"09",X"3A",X"51",X"20"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd deleted file mode 100644 index ef4b42fa..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw02.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw02 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw02 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"3D",X"32",X"51",X"20",X"F2",X"18",X"08",X"E6",X"0F",X"32",X"51",X"20",X"F3",X"2A",X"3B",X"20", - X"2B",X"22",X"3B",X"20",X"FB",X"C3",X"18",X"08",X"CD",X"79",X"0A",X"E6",X"F0",X"CA",X"4E",X"08", - X"21",X"51",X"20",X"35",X"EE",X"10",X"CA",X"2E",X"08",X"EE",X"30",X"CA",X"3E",X"08",X"2A",X"49", - X"20",X"7C",X"FE",X"28",X"DA",X"4E",X"08",X"25",X"22",X"49",X"20",X"C3",X"4E",X"08",X"2A",X"49", - X"20",X"7C",X"FE",X"E0",X"D2",X"4E",X"08",X"24",X"22",X"49",X"20",X"C3",X"4E",X"08",X"AF",X"32", - X"4F",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3A",X"52",X"20",X"A7",X"CA",X"AF",X"07",X"01",X"00", - X"10",X"21",X"E8",X"20",X"7E",X"A7",X"CA",X"6C",X"08",X"F2",X"78",X"08",X"23",X"23",X"23",X"23", - X"0C",X"05",X"C2",X"64",X"08",X"C3",X"AF",X"07",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20",X"87", - X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"28",X"D2",X"A1",X"08",X"23",X"5E",X"3A",X"4A",X"20", - X"C6",X"02",X"47",X"C6",X"0A",X"BB",X"DA",X"A1",X"08",X"23",X"23",X"7B",X"86",X"B8",X"D2",X"A6", - X"08",X"C1",X"E1",X"C3",X"6C",X"08",X"7A",X"FE",X"40",X"CA",X"98",X"09",X"E6",X"F0",X"87",X"B1", - X"3C",X"32",X"2C",X"20",X"3E",X"3F",X"32",X"0A",X"20",X"7A",X"FE",X"40",X"C1",X"E1",X"36",X"00", - X"11",X"24",X"FA",X"FA",X"D1",X"08",X"FE",X"70",X"11",X"E0",X"FC",X"DA",X"D1",X"08",X"11",X"30", - X"F8",X"2A",X"3B",X"20",X"19",X"7C",X"A7",X"FA",X"4A",X"09",X"3E",X"04",X"EF",X"0A",X"3E",X"20", - X"EF",X"0B",X"DF",X"03",X"AF",X"32",X"66",X"20",X"D5",X"CD",X"50",X"0A",X"2A",X"49",X"20",X"3A", - X"51",X"20",X"3D",X"32",X"51",X"20",X"0F",X"DA",X"FF",X"08",X"25",X"25",X"C3",X"01",X"09",X"24", - X"24",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"D1",X"2A",X"3B",X"20",X"2B",X"2B",X"2B",X"2B",X"2B", - X"2B",X"00",X"00",X"22",X"3B",X"20",X"13",X"13",X"13",X"13",X"13",X"13",X"00",X"00",X"7A",X"A7", - X"FA",X"E2",X"08",X"06",X"01",X"3E",X"04",X"F7",X"0A",X"3E",X"20",X"F7",X"0B",X"3E",X"01",X"32", - X"30",X"20",X"AF",X"32",X"0A",X"20",X"78",X"E6",X"02",X"C2",X"43",X"09",X"3A",X"48",X"20",X"A7", - X"F2",X"AF",X"07",X"78",X"32",X"2A",X"20",X"CD",X"C0",X"01",X"22",X"3B",X"20",X"3E",X"04",X"EF", - X"0A",X"3E",X"20",X"EF",X"0B",X"2A",X"49",X"20",X"11",X"FE",X"FD",X"19",X"22",X"49",X"20",X"21", - X"05",X"17",X"22",X"4B",X"20",X"21",X"54",X"1C",X"22",X"4D",X"20",X"CD",X"1C",X"0A",X"3E",X"64", - X"32",X"51",X"20",X"21",X"51",X"20",X"35",X"CA",X"7F",X"09",X"DF",X"01",X"C3",X"73",X"09",X"06", - X"03",X"C3",X"25",X"09",X"06",X"83",X"C3",X"25",X"09",X"3E",X"7F",X"32",X"0A",X"20",X"AF",X"32", - X"2E",X"20",X"11",X"18",X"FC",X"C3",X"D1",X"08",X"C1",X"E1",X"CD",X"FC",X"09",X"DF",X"01",X"CD", - X"50",X"0A",X"21",X"18",X"8A",X"22",X"49",X"20",X"CD",X"1C",X"0A",X"DF",X"01",X"3E",X"02",X"32", - X"2D",X"20",X"3E",X"10",X"EF",X"0A",X"11",X"DC",X"05",X"DB",X"02",X"E6",X"08",X"CA",X"C3",X"09", - X"11",X"E8",X"03",X"2A",X"3B",X"20",X"23",X"23",X"23",X"23",X"23",X"23",X"22",X"3B",X"20",X"E5", - X"D5",X"CD",X"1C",X"0A",X"D1",X"E1",X"DF",X"02",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"7A",X"A7", - X"F2",X"C3",X"09",X"3E",X"10",X"F7",X"0A",X"3E",X"80",X"32",X"2D",X"20",X"3C",X"32",X"30",X"20", - X"DF",X"01",X"3A",X"2D",X"20",X"A7",X"C2",X"F0",X"09",X"C3",X"AF",X"07",X"21",X"8F",X"19",X"11", - X"AD",X"1B",X"3A",X"FC",X"1F",X"86",X"23",X"47",X"7D",X"AB",X"C2",X"12",X"0A",X"7C",X"AA",X"CA", - X"16",X"0A",X"78",X"C3",X"05",X"0A",X"78",X"A7",X"C8",X"C3",X"30",X"0A",X"2A",X"49",X"20",X"CD", - X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB",X"AF",X"32",X"52",X"20", - X"E5",X"C5",X"1A",X"A6",X"CA",X"3A",X"0A",X"32",X"52",X"20",X"1A",X"B6",X"77",X"13",X"23",X"0D", - X"C2",X"32",X"0A",X"C1",X"05",X"E1",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"30",X"0A", - X"2A",X"49",X"20",X"CD",X"70",X"15",X"EB",X"2A",X"4B",X"20",X"E5",X"2A",X"4D",X"20",X"C1",X"EB", - X"E5",X"C5",X"00",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"62",X"0A",X"C1",X"E1",X"05",X"C8", - X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"60",X"0A",X"3A",X"48",X"20",X"A7",X"CA",X"9A",X"0A", - X"F2",X"91",X"0A",X"0F",X"DA",X"91",X"0A",X"DB",X"00",X"07",X"07",X"47",X"DB",X"02",X"C3",X"96", - X"0A",X"DB",X"00",X"47",X"DB",X"01",X"0F",X"E6",X"38",X"C9",X"3A",X"5B",X"20",X"C6",X"10",X"07", - X"E6",X"38",X"C9",X"AF",X"32",X"5C",X"20",X"32",X"64",X"20",X"3E",X"64",X"32",X"66",X"20",X"3E", - X"20",X"32",X"65",X"20",X"3E",X"01",X"32",X"5F",X"20",X"3A",X"2C",X"20",X"A7",X"C2",X"8D",X"0C", - X"3A",X"E8",X"20",X"FE",X"40",X"CA",X"9F",X"0C",X"3E",X"0F",X"F7",X"0C",X"3A",X"58",X"20",X"A7", - X"CA",X"FA",X"0A",X"21",X"66",X"20",X"35",X"C2",X"DF",X"0A",X"36",X"64",X"C3",X"14",X"0B",X"CD", - X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"CD",X"79",X"0A",X"E6",X"08",X"C2",X"3E",X"0B",X"3A", - X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"3E",X"0B",X"CD",X"79",X"0A",X"E6",X"08",X"C2", - X"0D",X"0B",X"3A",X"5C",X"20",X"E6",X"01",X"32",X"5C",X"20",X"C3",X"DF",X"0A",X"3A",X"5C",X"20", - X"A7",X"C2",X"DF",X"0A",X"3A",X"0A",X"20",X"E6",X"FF",X"C2",X"DF",X"0A",X"3E",X"03",X"32",X"5C", - X"20",X"3E",X"02",X"EF",X"0A",X"3E",X"08",X"32",X"67",X"20",X"F3",X"2A",X"3B",X"20",X"2B",X"2B", - X"22",X"3B",X"20",X"FB",X"2A",X"49",X"20",X"11",X"10",X"07",X"19",X"C3",X"66",X"0B",X"CD",X"DC", - X"0C",X"DF",X"01",X"11",X"05",X"0D",X"06",X"01",X"2A",X"5D",X"20",X"CD",X"DD",X"15",X"21",X"67", - X"20",X"35",X"C2",X"59",X"0B",X"3E",X"02",X"F7",X"0A",X"2A",X"5D",X"20",X"2C",X"2C",X"2C",X"2C", - X"7D",X"FE",X"D8",X"D2",X"D7",X"0B",X"22",X"5D",X"20",X"11",X"05",X"0D",X"06",X"01",X"CD",X"A0", - X"15",X"DF",X"01",X"79",X"A7",X"CA",X"E7",X"0A",X"01",X"00",X"10",X"21",X"E8",X"20",X"7E",X"A7", - X"CA",X"86",X"0B",X"F2",X"94",X"0B",X"23",X"23",X"23",X"23",X"0C",X"05",X"C2",X"7E",X"0B",X"DF", - X"01",X"C3",X"E7",X"0A",X"FE",X"40",X"CA",X"E7",X"0A",X"E5",X"C5",X"57",X"79",X"21",X"68",X"20", - X"87",X"87",X"87",X"CD",X"2D",X"02",X"D5",X"EB",X"2A",X"5D",X"20",X"EB",X"1C",X"1C",X"1C",X"7B", - X"4E",X"B9",X"DA",X"D1",X"0B",X"23",X"7A",X"46",X"B8",X"DA",X"D1",X"0B",X"23",X"23",X"23",X"7E", - X"87",X"87",X"87",X"81",X"BB",X"DA",X"D1",X"0B",X"23",X"7E",X"E6",X"1F",X"80",X"BA",X"D2",X"E2", - X"0B",X"D1",X"C1",X"E1",X"C3",X"86",X"0B",X"3A",X"5C",X"20",X"E6",X"FE",X"32",X"5C",X"20",X"C3", - X"E2",X"0A",X"D1",X"C1",X"E1",X"7A",X"FE",X"40",X"06",X"00",X"D2",X"F8",X"0B",X"3A",X"3D",X"20", - X"E6",X"07",X"47",X"3A",X"3F",X"20",X"80",X"47",X"7A",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"57", - X"59",X"21",X"08",X"0D",X"CD",X"2D",X"02",X"80",X"4F",X"06",X"00",X"2A",X"41",X"20",X"09",X"22", - X"41",X"20",X"3A",X"64",X"20",X"A7",X"CA",X"26",X"0C",X"D5",X"2A",X"63",X"20",X"44",X"4D",X"2A", - X"5F",X"20",X"CD",X"7F",X"15",X"D1",X"7B",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"36", - X"00",X"7A",X"FE",X"04",X"D2",X"81",X"0C",X"3E",X"08",X"EF",X"0A",X"7B",X"87",X"87",X"87",X"21", - X"68",X"20",X"CD",X"2D",X"02",X"D6",X"02",X"4F",X"23",X"7E",X"D6",X"02",X"47",X"C5",X"7A",X"87", - X"87",X"21",X"10",X"0D",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"4E",X"23",X"46",X"21",X"64", - X"20",X"70",X"2B",X"71",X"2B",X"72",X"2B",X"73",X"E1",X"22",X"5F",X"20",X"3A",X"5C",X"20",X"E6", - X"FE",X"32",X"5C",X"20",X"DF",X"01",X"CD",X"25",X"15",X"3E",X"32",X"32",X"65",X"20",X"C3",X"E2", - X"0A",X"FE",X"05",X"C2",X"3B",X"0C",X"3E",X"17",X"E7",X"0B",X"C3",X"3B",X"0C",X"3D",X"57",X"E6", - X"1F",X"4F",X"7A",X"1F",X"57",X"AF",X"32",X"2C",X"20",X"32",X"66",X"20",X"C3",X"E5",X"0B",X"21", - X"65",X"20",X"35",X"F2",X"D0",X"0C",X"36",X"20",X"3A",X"64",X"20",X"3C",X"FE",X"04",X"C2",X"B3", - X"0C",X"3E",X"00",X"32",X"64",X"20",X"3E",X"0F",X"F7",X"0C",X"3A",X"2D",X"20",X"E6",X"02",X"C2", - X"D0",X"0C",X"21",X"D8",X"0C",X"3A",X"64",X"20",X"3D",X"E6",X"03",X"CD",X"2D",X"02",X"EF",X"0C", - X"CD",X"DC",X"0C",X"DF",X"01",X"C3",X"B9",X"0A",X"01",X"04",X"02",X"08",X"3A",X"64",X"20",X"A7", - X"C8",X"21",X"65",X"20",X"35",X"C0",X"2B",X"46",X"36",X"00",X"2B",X"4E",X"2B",X"2B",X"2B",X"7E", - X"2B",X"6E",X"67",X"CD",X"7F",X"15",X"3E",X"08",X"F7",X"0A",X"3A",X"35",X"20",X"FE",X"17",X"C0", - X"3E",X"1F",X"E7",X"0B",X"C9",X"0F",X"00",X"00",X"10",X"20",X"30",X"40",X"05",X"06",X"00",X"80", - X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13",X"19",X"1C",X"02",X"13", - X"3F",X"1C",X"01",X"0C",X"3F",X"1C",X"01",X"0C",X"4A",X"1C",X"02",X"07",X"02",X"4F",X"05",X"28", - X"21",X"2D",X"20",X"7E",X"A7",X"36",X"00",X"C2",X"5C",X"0E",X"3A",X"48",X"20",X"A7",X"C4",X"37", - X"0F",X"21",X"E8",X"20",X"06",X"40",X"CD",X"40",X"00",X"CD",X"4F",X"0D",X"C3",X"66",X"0D",X"3E", - X"DF",X"F7",X"0A",X"F7",X"0B",X"F7",X"0C",X"3A",X"40",X"20",X"E6",X"07",X"C8",X"FE",X"06",X"F0", - X"3E",X"15",X"C3",X"DA",X"0F",X"0A",X"DF",X"01",X"3A",X"40",X"20",X"87",X"87",X"21",X"7F",X"0D", - X"CD",X"2D",X"02",X"5F",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"E9",X"06",X"06",X"08",X"49", - X"0D",X"49",X"0D",X"03",X"0F",X"58",X"0E",X"19",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"0C", - X"0F",X"58",X"0E",X"30",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", - X"0F",X"6C",X"0E",X"CF",X"0E",X"58",X"0E",X"D8",X"0E",X"58",X"0E",X"DF",X"0E",X"58",X"0E",X"EA", - X"0E",X"58",X"0E",X"F3",X"0E",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", - X"0F",X"6C",X"0E",X"03",X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"10",X"0F",X"58",X"0E",X"19", - X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", - X"0F",X"6C",X"0E",X"29",X"0F",X"58",X"0E",X"20",X"0F",X"58",X"0E",X"EA",X"0E",X"58",X"0E",X"03", - X"0F",X"58",X"0E",X"0C",X"0F",X"58",X"0E",X"FA",X"0E",X"58",X"0E",X"FD",X"0E",X"58",X"0E",X"00", - X"0F",X"6C",X"0E",X"7E",X"3C",X"C8",X"3D",X"23",X"32",X"2A",X"21",X"7E",X"23",X"E5",X"CD",X"43", - X"0F",X"E1",X"C3",X"03",X"0E",X"AF",X"32",X"29",X"21",X"3D",X"32",X"2A",X"21",X"3E",X"06",X"C3", - X"26",X"0E",X"0D",X"CD",X"2D",X"02",X"32",X"28",X"21",X"CD",X"ED",X"0F",X"3A",X"2A",X"21",X"FE", - X"10",X"F0",X"21",X"28",X"21",X"35",X"C2",X"29",X"0E",X"DF",X"01",X"C3",X"1D",X"0E",X"DF",X"01", - X"3A",X"29",X"21",X"A7",X"C0",X"3A",X"40",X"20",X"3C",X"32",X"40",X"20",X"FE",X"21",X"DA",X"56", - X"0E",X"3E",X"01",X"32",X"40",X"20",X"AF",X"C9",X"EB",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"CD", - X"3E",X"0E",X"C2",X"5C",X"0E",X"AF",X"32",X"2D",X"20",X"C3",X"49",X"0D",X"EB",X"3E",X"80",X"32", - X"2B",X"21",X"CD",X"03",X"0E",X"CD",X"15",X"0E",X"3A",X"2D",X"20",X"E6",X"02",X"C2",X"90",X"0E", - X"21",X"2B",X"21",X"35",X"CA",X"BD",X"0E",X"CD",X"3E",X"0E",X"C2",X"75",X"0E",X"C3",X"49",X"0D", - X"DF",X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"AA",X"CD",X"41",X"00",X"DF", - X"01",X"CD",X"15",X"0E",X"21",X"26",X"32",X"06",X"08",X"3E",X"55",X"CD",X"41",X"00",X"3A",X"2D", - X"20",X"A7",X"F2",X"90",X"0E",X"21",X"26",X"32",X"06",X"08",X"CD",X"40",X"00",X"21",X"E9",X"20", - X"06",X"08",X"36",X"00",X"23",X"23",X"23",X"23",X"05",X"C2",X"C2",X"0E",X"C3",X"5C",X"0E",X"00", - X"00",X"01",X"01",X"02",X"02",X"03",X"03",X"FF",X"00",X"04",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", - X"05",X"01",X"06",X"02",X"07",X"03",X"08",X"04",X"09",X"FF",X"00",X"0B",X"01",X"0C",X"FF",X"FF", - X"FF",X"FF",X"FF",X"00",X"0D",X"01",X"0E",X"02",X"0F",X"FF",X"00",X"0A",X"FF",X"00",X"13",X"FF", - X"00",X"12",X"FF",X"00",X"10",X"01",X"11",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"18",X"FF",X"FF", - X"00",X"16",X"01",X"17",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"19",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"14",X"01",X"15",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1A",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"DB",X"17",X"11",X"8F",X"19",X"3A",X"FD",X"1F", - X"C3",X"05",X"0A",X"87",X"21",X"00",X"40",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"3A",X"2A",X"21", - X"21",X"68",X"20",X"87",X"87",X"87",X"CD",X"2D",X"02",X"06",X"06",X"3A",X"40",X"20",X"EE",X"07", - X"4F",X"E6",X"07",X"C2",X"77",X"0F",X"79",X"D6",X"08",X"F2",X"6E",X"0F",X"3E",X"18",X"4F",X"05", - X"1A",X"91",X"91",X"00",X"77",X"13",X"23",X"CD",X"34",X"16",X"21",X"E8",X"20",X"3A",X"2A",X"21", - X"87",X"87",X"CD",X"2D",X"02",X"1A",X"13",X"77",X"47",X"78",X"FE",X"38",X"C2",X"96",X"0F",X"3E", - X"01",X"EF",X"0A",X"C3",X"E3",X"0F",X"78",X"FE",X"33",X"C2",X"A3",X"0F",X"3E",X"01",X"E7",X"0B", - X"C3",X"12",X"4D",X"78",X"FE",X"70",X"C2",X"BC",X"0F",X"3E",X"10",X"EF",X"0C",X"D5",X"E5",X"21", - X"AD",X"1B",X"11",X"E0",X"1F",X"3E",X"A3",X"C3",X"EB",X"4F",X"19",X"4D",X"78",X"FE",X"50",X"C2", - X"CD",X"0F",X"3E",X"01",X"EF",X"0A",X"3E",X"1F",X"E7",X"0B",X"C3",X"E3",X"0F",X"78",X"FE",X"3F", - X"C2",X"E5",X"0F",X"3E",X"1F",X"E7",X"0B",X"C3",X"12",X"4D",X"E7",X"0B",X"3E",X"01",X"EF",X"0A", - X"C9",X"4F",X"4F",X"DF",X"01",X"23",X"36",X"00",X"23",X"73",X"23",X"72",X"C9",X"3A",X"2A",X"21", - X"3C",X"32",X"2A",X"21",X"FE",X"10",X"F0",X"21",X"E8",X"20",X"87",X"87",X"F3",X"CD",X"2D",X"02"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd deleted file mode 100644 index cee80385..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw03.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw03 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw03 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"FB",X"CA",X"ED",X"0F",X"47",X"3A",X"29",X"21",X"3C",X"32",X"29",X"21",X"23",X"7E",X"A7",X"CA", - X"7D",X"10",X"35",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"FE", - X"20",X"DA",X"E2",X"10",X"5E",X"23",X"56",X"78",X"78",X"FE",X"50",X"DA",X"48",X"10",X"DB",X"02", - X"E6",X"04",X"CA",X"36",X"10",X"1D",X"78",X"FE",X"66",X"C2",X"48",X"10",X"3A",X"4A",X"20",X"C6", - X"04",X"92",X"14",X"D2",X"48",X"10",X"15",X"15",X"C5",X"4B",X"42",X"23",X"5E",X"23",X"56",X"1A", - X"2B",X"77",X"23",X"13",X"1A",X"77",X"13",X"D5",X"23",X"5E",X"23",X"56",X"D5",X"E5",X"23",X"7E", - X"23",X"66",X"81",X"6F",X"7C",X"80",X"67",X"EB",X"E1",X"2B",X"2B",X"2B",X"2B",X"72",X"2B",X"73", - X"EB",X"C1",X"D1",X"F1",X"A7",X"F8",X"C3",X"25",X"15",X"13",X"C3",X"81",X"10",X"23",X"5E",X"23", - X"56",X"1A",X"A7",X"CA",X"79",X"10",X"FE",X"CD",X"CA",X"63",X"11",X"FE",X"EB",X"CA",X"9A",X"11", - X"FE",X"01",X"CA",X"2E",X"11",X"FE",X"C3",X"CA",X"23",X"11",X"FE",X"AF",X"CA",X"F0",X"10",X"21", - X"E8",X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"7E",X"FE",X"70",X"01",X"D4",X"FE", - X"CA",X"BC",X"10",X"01",X"F6",X"FF",X"7E",X"FE",X"40",X"D2",X"C7",X"10",X"EB",X"F3",X"2A",X"3B", - X"20",X"09",X"22",X"3B",X"20",X"FB",X"EB",X"36",X"00",X"21",X"68",X"20",X"3A",X"2A",X"21",X"87", - X"87",X"87",X"CD",X"2D",X"02",X"5E",X"23",X"56",X"23",X"23",X"23",X"4E",X"23",X"46",X"EB",X"C3", - X"7F",X"15",X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"C3",X"AA",X"10", - X"3A",X"2A",X"21",X"21",X"E8",X"20",X"87",X"87",X"CD",X"2D",X"02",X"F6",X"80",X"77",X"13",X"1A", - X"4F",X"13",X"1A",X"47",X"13",X"23",X"1A",X"77",X"13",X"23",X"73",X"23",X"72",X"21",X"68",X"20", - X"3A",X"2A",X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70", - X"C3",X"AA",X"10",X"13",X"1A",X"4F",X"13",X"1A",X"47",X"C5",X"D1",X"C3",X"81",X"10",X"21",X"E8", - X"20",X"3A",X"2A",X"21",X"87",X"87",X"CD",X"2D",X"02",X"E6",X"7F",X"77",X"23",X"13",X"1A",X"4F", - X"13",X"1A",X"47",X"13",X"1A",X"13",X"77",X"23",X"73",X"23",X"72",X"21",X"68",X"20",X"3A",X"2A", - X"21",X"87",X"87",X"87",X"CD",X"2D",X"02",X"11",X"06",X"00",X"19",X"71",X"23",X"70",X"06",X"01", - X"C3",X"13",X"10",X"3A",X"2A",X"21",X"F5",X"06",X"10",X"0E",X"00",X"21",X"E8",X"20",X"7E",X"A7", - X"CA",X"83",X"11",X"23",X"23",X"23",X"23",X"0C",X"05",X"C2",X"6E",X"11",X"F1",X"13",X"13",X"13", - X"C3",X"81",X"10",X"79",X"32",X"2A",X"21",X"EB",X"23",X"5E",X"23",X"56",X"23",X"E5",X"CD",X"4D", - X"0F",X"E1",X"F1",X"EB",X"32",X"2A",X"21",X"C3",X"81",X"10",X"21",X"68",X"20",X"3A",X"2A",X"21", - X"87",X"87",X"87",X"CD",X"2D",X"02",X"23",X"23",X"13",X"06",X"04",X"CD",X"77",X"0F",X"C3",X"81", - X"10",X"21",X"2D",X"21",X"06",X"08",X"CD",X"40",X"00",X"3E",X"0F",X"32",X"45",X"21",X"AF",X"32", - X"2C",X"21",X"3A",X"E8",X"20",X"FE",X"40",X"CA",X"10",X"12",X"3A",X"2D",X"21",X"A7",X"F2",X"EC", - X"11",X"2A",X"C7",X"1C",X"06",X"70",X"CD",X"E1",X"06",X"AF",X"32",X"2D",X"21",X"32",X"2E",X"21", - X"DF",X"01",X"2A",X"D8",X"1C",X"06",X"28",X"CD",X"E1",X"06",X"DF",X"01",X"21",X"2D",X"21",X"3A", - X"2C",X"21",X"CD",X"2D",X"02",X"C2",X"C1",X"12",X"11",X"45",X"21",X"1A",X"21",X"E8",X"20",X"87", - X"87",X"CD",X"2D",X"02",X"C2",X"71",X"12",X"EB",X"35",X"EB",X"F2",X"FB",X"11",X"3E",X"0F",X"12", - X"DF",X"01",X"3A",X"E8",X"20",X"FE",X"40",X"C2",X"54",X"12",X"3A",X"2D",X"21",X"A7",X"FA",X"3F", - X"12",X"3E",X"80",X"32",X"2D",X"21",X"21",X"C7",X"1C",X"CD",X"F4",X"14",X"21",X"3E",X"20",X"34", - X"7E",X"E6",X"0F",X"47",X"0E",X"08",X"21",X"1A",X"39",X"CD",X"3D",X"16",X"C3",X"54",X"12",X"3A", - X"EC",X"20",X"FE",X"40",X"C2",X"54",X"12",X"3A",X"2E",X"21",X"A7",X"FA",X"54",X"12",X"21",X"D8", - X"1C",X"CD",X"F4",X"14",X"21",X"2C",X"21",X"34",X"3A",X"40",X"20",X"06",X"04",X"0E",X"04",X"D6", - X"08",X"DA",X"69",X"12",X"04",X"0D",X"C2",X"5F",X"12",X"78",X"BE",X"D2",X"C2",X"11",X"C3",X"BE", - X"11",X"FE",X"40",X"D2",X"07",X"12",X"21",X"3D",X"20",X"35",X"7E",X"E6",X"35",X"C2",X"07",X"12", - X"1A",X"21",X"68",X"20",X"87",X"87",X"87",X"CD",X"2D",X"02",X"D6",X"08",X"5F",X"23",X"56",X"23", - X"23",X"23",X"23",X"7E",X"1F",X"A7",X"82",X"57",X"FE",X"20",X"DA",X"10",X"12",X"3A",X"2C",X"21", - X"21",X"2D",X"21",X"CD",X"2D",X"02",X"36",X"01",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD", - X"2D",X"02",X"73",X"23",X"72",X"EB",X"11",X"58",X"13",X"06",X"03",X"CD",X"A0",X"15",X"C3",X"10", - X"12",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD",X"2D",X"02",X"5E",X"23",X"56",X"DB",X"02", - X"E6",X"04",X"3E",X"FA",X"C2",X"D9",X"12",X"3E",X"FB",X"83",X"2B",X"77",X"E5",X"CD",X"4F",X"13", - X"E1",X"7E",X"FE",X"18",X"DA",X"31",X"13",X"23",X"66",X"6F",X"11",X"58",X"13",X"06",X"03",X"CD", - X"A0",X"15",X"DF",X"01",X"79",X"A7",X"CA",X"10",X"12",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87", - X"CD",X"2D",X"02",X"5F",X"FE",X"20",X"DA",X"10",X"12",X"23",X"56",X"FE",X"28",X"D2",X"31",X"13", - X"3A",X"4A",X"20",X"BA",X"D2",X"31",X"13",X"C6",X"0F",X"BA",X"DA",X"31",X"13",X"CD",X"37",X"13", - X"3E",X"01",X"32",X"2E",X"20",X"DF",X"01",X"3A",X"2E",X"20",X"A7",X"C2",X"25",X"13",X"C3",X"10", - X"12",X"CD",X"37",X"13",X"C3",X"10",X"12",X"3A",X"2C",X"21",X"21",X"2D",X"21",X"CD",X"2D",X"02", - X"36",X"00",X"3A",X"2C",X"21",X"21",X"35",X"21",X"87",X"CD",X"2D",X"02",X"5F",X"23",X"56",X"21", - X"58",X"13",X"06",X"03",X"EB",X"C3",X"DD",X"15",X"0F",X"00",X"0F",X"11",X"14",X"1F",X"21",X"46", - X"21",X"06",X"28",X"CD",X"34",X"16",X"DF",X"01",X"06",X"14",X"21",X"46",X"21",X"C5",X"E5",X"7E", - X"23",X"66",X"6F",X"CD",X"0C",X"16",X"E1",X"C1",X"DF",X"01",X"23",X"23",X"05",X"C2",X"6D",X"13", - X"06",X"14",X"21",X"46",X"21",X"3A",X"3F",X"20",X"C6",X"01",X"4F",X"E5",X"7E",X"23",X"66",X"6F", - X"C5",X"CD",X"2C",X"16",X"C1",X"E1",X"E5",X"5E",X"23",X"56",X"1D",X"7B",X"FE",X"28",X"D2",X"A3", - X"13",X"1E",X"D8",X"2B",X"73",X"EB",X"C5",X"CD",X"0C",X"16",X"C1",X"E1",X"23",X"23",X"05",X"C2", - X"B7",X"13",X"06",X"14",X"21",X"46",X"21",X"0D",X"C2",X"8B",X"13",X"DF",X"01",X"C3",X"85",X"13", - X"01",X"00",X"00",X"3A",X"58",X"20",X"A7",X"CA",X"18",X"14",X"0F",X"D2",X"D7",X"13",X"21",X"A5", - X"1D",X"CD",X"F4",X"14",X"C3",X"E4",X"13",X"DF",X"01",X"3A",X"30",X"20",X"A7",X"CA",X"D7",X"13", - X"AF",X"32",X"30",X"20",X"3A",X"58",X"20",X"3D",X"87",X"21",X"F4",X"13",X"CD",X"2D",X"02",X"5F", - X"23",X"56",X"EB",X"E9",X"4E",X"14",X"94",X"14",X"78",X"14",X"EC",X"14",X"7E",X"14",X"B6",X"14", - X"78",X"14",X"D9",X"14",X"3A",X"58",X"20",X"3C",X"32",X"58",X"20",X"FE",X"09",X"DC",X"C0",X"01", - X"3E",X"01",X"32",X"58",X"20",X"CD",X"C0",X"01",X"21",X"A5",X"1D",X"CD",X"F4",X"14",X"21",X"73", - X"1D",X"CD",X"F4",X"14",X"3A",X"46",X"20",X"3D",X"CA",X"31",X"14",X"21",X"90",X"1D",X"CD",X"F4", - X"14",X"CD",X"37",X"14",X"C3",X"1E",X"14",X"21",X"03",X"24",X"3A",X"FB",X"1F",X"01",X"20",X"00", - X"16",X"D0",X"86",X"5F",X"09",X"15",X"C2",X"42",X"14",X"A7",X"C8",X"C3",X"48",X"15",X"21",X"BF", - X"1D",X"CD",X"F4",X"14",X"21",X"1A",X"24",X"3A",X"FA",X"1F",X"CD",X"3D",X"14",X"21",X"F9",X"1D", - X"CD",X"F4",X"14",X"21",X"F4",X"01",X"DF",X"01",X"2B",X"7C",X"B5",X"C2",X"66",X"14",X"3A",X"58", - X"20",X"3C",X"32",X"58",X"20",X"C3",X"C3",X"13",X"21",X"C7",X"1E",X"C3",X"60",X"14",X"21",X"BF", - X"1D",X"CD",X"F4",X"14",X"21",X"38",X"1E",X"DB",X"02",X"E6",X"08",X"CA",X"60",X"14",X"21",X"60", - X"1E",X"C3",X"60",X"14",X"3E",X"01",X"32",X"40",X"20",X"DF",X"02",X"78",X"E6",X"3F",X"47",X"03", - X"0A",X"32",X"5B",X"20",X"3A",X"30",X"20",X"A7",X"C2",X"04",X"14",X"2A",X"3B",X"20",X"7C",X"A7", - X"FA",X"04",X"14",X"C3",X"99",X"14",X"3E",X"08",X"32",X"40",X"20",X"21",X"90",X"01",X"22",X"3B", - X"20",X"01",X"00",X"10",X"3E",X"30",X"32",X"5B",X"20",X"DF",X"02",X"AF",X"32",X"66",X"20",X"3A", - X"30",X"20",X"A7",X"CA",X"C4",X"14",X"C3",X"04",X"14",X"3E",X"0B",X"32",X"40",X"20",X"3E",X"01", - X"32",X"3F",X"20",X"21",X"F4",X"01",X"22",X"3B",X"20",X"C3",X"99",X"14",X"3E",X"0D",X"32",X"40", - X"20",X"C3",X"99",X"14",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23",X"E5",X"7E",X"C5",X"EB", - X"0E",X"08",X"47",X"CD",X"3D",X"16",X"EB",X"C1",X"E1",X"0D",X"CA",X"1D",X"15",X"78",X"A7",X"CA", - X"FB",X"14",X"C5",X"DF",X"01",X"05",X"C2",X"13",X"15",X"C1",X"C3",X"FB",X"14",X"23",X"7E",X"A7", - X"C8",X"23",X"C3",X"F4",X"14",X"C5",X"CD",X"6C",X"15",X"78",X"C1",X"F5",X"7C",X"FE",X"24",X"DA", - X"62",X"15",X"F1",X"E5",X"36",X"00",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB",X"6F",X"26",X"00", - X"05",X"FA",X"48",X"15",X"29",X"C3",X"40",X"15",X"EB",X"7E",X"B3",X"77",X"23",X"72",X"D1",X"C1", - X"0D",X"C2",X"38",X"15",X"78",X"C1",X"E1",X"05",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3", - X"2B",X"15",X"79",X"3D",X"13",X"C2",X"63",X"15",X"F1",X"C3",X"57",X"15",X"7D",X"E6",X"07",X"47", - X"37",X"0E",X"03",X"7C",X"1F",X"67",X"7D",X"1F",X"6F",X"A7",X"0D",X"C2",X"73",X"15",X"C9",X"C5", - X"CD",X"70",X"15",X"C1",X"11",X"20",X"00",X"AF",X"7C",X"FE",X"24",X"DA",X"9A",X"15",X"AF",X"E5", - X"C5",X"77",X"0D",X"23",X"77",X"C2",X"91",X"15",X"C1",X"E1",X"05",X"C8",X"19",X"C3",X"88",X"15", - X"0E",X"00",X"C5",X"CD",X"6C",X"15",X"78",X"C1",X"E5",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB", - X"6F",X"26",X"00",X"05",X"FA",X"BB",X"15",X"29",X"C3",X"B3",X"15",X"EB",X"7E",X"A3",X"B1",X"4F", - X"7E",X"B3",X"77",X"23",X"7E",X"A2",X"B1",X"4F",X"7E",X"B2",X"77",X"69",X"D1",X"C1",X"78",X"C1", - X"4D",X"E1",X"05",X"C8",X"D5",X"11",X"20",X"00",X"19",X"D1",X"C3",X"A8",X"15",X"C5",X"CD",X"6C", - X"15",X"78",X"C1",X"C5",X"47",X"C5",X"1A",X"13",X"D5",X"EB",X"6F",X"26",X"00",X"05",X"FA",X"F5", - X"15",X"29",X"C3",X"ED",X"15",X"EB",X"7B",X"2F",X"A6",X"77",X"23",X"7A",X"2F",X"A6",X"77",X"11", - X"1F",X"00",X"19",X"D1",X"C1",X"78",X"C1",X"05",X"C2",X"E3",X"15",X"C9",X"CD",X"6C",X"15",X"48", - X"06",X"01",X"11",X"C0",X"13",X"1A",X"13",X"EB",X"6F",X"26",X"00",X"0D",X"FA",X"23",X"16",X"29", - X"C3",X"1B",X"16",X"EB",X"7E",X"B3",X"77",X"23",X"7E",X"B2",X"77",X"C9",X"11",X"C0",X"13",X"06", - X"01",X"C3",X"DD",X"15",X"1A",X"77",X"13",X"23",X"05",X"C2",X"34",X"16",X"C9",X"C5",X"E5",X"21", - X"5B",X"16",X"58",X"16",X"00",X"EB",X"29",X"29",X"29",X"19",X"EB",X"E1",X"1A",X"77",X"13",X"C5", - X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"4C",X"16",X"C1",X"C9",X"00",X"3E",X"45",X"49",X"51", - X"3E",X"00",X"00",X"00",X"00",X"21",X"7F",X"01",X"00",X"00",X"00",X"00",X"23",X"45",X"49",X"49", - X"31",X"00",X"00",X"00",X"42",X"41",X"49",X"59",X"66",X"00",X"00",X"00",X"0C",X"14",X"24",X"7F", - X"04",X"00",X"00",X"00",X"72",X"51",X"51",X"51",X"4E",X"00",X"00",X"00",X"1E",X"29",X"49",X"49", - X"46",X"00",X"00",X"00",X"40",X"47",X"48",X"50",X"60",X"00",X"00",X"00",X"36",X"49",X"49",X"49", - X"36",X"00",X"00",X"00",X"31",X"49",X"49",X"4A",X"3C",X"00",X"00",X"00",X"1F",X"24",X"44",X"24", - X"1F",X"00",X"00",X"00",X"7F",X"49",X"49",X"49",X"36",X"00",X"00",X"00",X"3E",X"41",X"41",X"41", - X"22",X"00",X"00",X"00",X"7F",X"41",X"41",X"41",X"3E",X"00",X"00",X"00",X"7F",X"49",X"49",X"49", - X"41",X"00",X"00",X"00",X"7F",X"48",X"48",X"48",X"40",X"00",X"00",X"00",X"3E",X"41",X"41",X"45", - X"47",X"00",X"00",X"00",X"7F",X"08",X"08",X"08",X"7F",X"00",X"00",X"00",X"00",X"41",X"7F",X"41", - X"00",X"00",X"00",X"00",X"02",X"01",X"01",X"01",X"7E",X"00",X"00",X"00",X"7F",X"08",X"14",X"22", - X"41",X"00",X"00",X"00",X"7F",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"7F",X"20",X"18",X"20", - X"7F",X"00",X"00",X"00",X"7F",X"10",X"08",X"04",X"7F",X"00",X"00",X"00",X"3E",X"41",X"41",X"41", - X"3E",X"00",X"00",X"00",X"7F",X"48",X"48",X"48",X"30",X"00",X"00",X"00",X"3E",X"41",X"45",X"42", - X"3D",X"00",X"00",X"00",X"7F",X"48",X"4C",X"4A",X"31",X"00",X"00",X"00",X"32",X"49",X"49",X"49", - X"26",X"00",X"00",X"00",X"40",X"40",X"7F",X"40",X"40",X"00",X"00",X"00",X"7E",X"01",X"01",X"01", - X"7E",X"00",X"00",X"00",X"7C",X"02",X"01",X"02",X"7C",X"00",X"00",X"00",X"7F",X"02",X"0C",X"02", - X"7F",X"00",X"00",X"00",X"63",X"14",X"08",X"14",X"63",X"00",X"00",X"00",X"60",X"10",X"0F",X"10", - X"60",X"00",X"00",X"00",X"43",X"45",X"49",X"51",X"61",X"00",X"00",X"00",X"08",X"14",X"22",X"41", - X"00",X"00",X"00",X"00",X"00",X"41",X"22",X"14",X"08",X"00",X"00",X"00",X"14",X"14",X"14",X"14", - X"14",X"00",X"00",X"00",X"22",X"14",X"7F",X"14",X"22",X"00",X"00",X"00",X"30",X"40",X"45",X"48", - X"30",X"00",X"00",X"00",X"36",X"49",X"49",X"35",X"02",X"05",X"00",X"00",X"08",X"08",X"3E",X"08", - X"08",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"08",X"00",X"00",X"00",X"04",X"08",X"08",X"08", - X"10",X"00",X"00",X"00",X"00",X"00",X"7B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"40",X"00",X"00",X"00",X"FB",X"17",X"00",X"00",X"B0", - X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"13",X"19",X"4F",X"1E",X"E8",X"02",X"4F",X"1E",X"13", - X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"DB",X"17",X"00",X"00",X"B0"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd deleted file mode 100644 index 3b6861b8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw04.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw04 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw04 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"01",X"B8",X"03",X"5C",X"07",X"EE",X"0E",X"F3",X"19",X"FF",X"1F",X"F8",X"03",X"FF",X"1F",X"F3", - X"19",X"EE",X"0E",X"5C",X"07",X"B8",X"03",X"B0",X"01",X"00",X"00",X"3B",X"18",X"00",X"00",X"80", - X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"67",X"5E",X"7C",X"C7",X"08",X"5E",X"7C",X"F8", - X"67",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"1B",X"18",X"00",X"00",X"80", - X"07",X"80",X"0F",X"C0",X"1D",X"E0",X"3B",X"F8",X"7F",X"5E",X"7C",X"FF",X"08",X"5E",X"7C",X"F8", - X"7F",X"E0",X"3B",X"C0",X"1D",X"80",X"0F",X"80",X"07",X"00",X"00",X"7B",X"18",X"00",X"00",X"F0", - X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"79",X"9E",X"30",X"BF",X"1F",X"9E",X"30",X"38", - X"79",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"5B",X"18",X"00",X"00",X"F0", - X"0F",X"80",X"1F",X"80",X"34",X"E0",X"6F",X"38",X"7F",X"9E",X"36",X"B1",X"1F",X"9E",X"36",X"38", - X"7F",X"E0",X"6F",X"80",X"34",X"80",X"1F",X"F0",X"0F",X"00",X"00",X"BB",X"18",X"00",X"00",X"F0", - X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"58",X"70",X"BF",X"7B",X"70", - X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"9B",X"18",X"00",X"00",X"F0", - X"0F",X"C8",X"13",X"40",X"02",X"E0",X"07",X"70",X"5F",X"BF",X"7B",X"5E",X"7C",X"BF",X"7B",X"70", - X"5F",X"E0",X"07",X"40",X"02",X"C8",X"13",X"F0",X"0F",X"00",X"00",X"FB",X"18",X"00",X"00",X"F0", - X"01",X"F8",X"03",X"0C",X"06",X"06",X"0C",X"E3",X"18",X"BF",X"1F",X"1F",X"1F",X"BF",X"1F",X"E3", - X"18",X"06",X"0C",X"0C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"1B",X"19",X"00",X"00",X"F0", - X"01",X"F8",X"03",X"0C",X"07",X"06",X"0F",X"E3",X"1F",X"B3",X"19",X"13",X"19",X"B3",X"19",X"FF", - X"18",X"1E",X"0C",X"1C",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"3B",X"19",X"00",X"00",X"F0", - X"01",X"F8",X"03",X"EC",X"06",X"E6",X"0C",X"E3",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3", - X"18",X"E6",X"0C",X"EC",X"06",X"F8",X"03",X"F0",X"01",X"00",X"00",X"DB",X"18",X"00",X"00",X"F0", - X"01",X"F8",X"03",X"1C",X"06",X"1E",X"0C",X"FF",X"18",X"B3",X"19",X"13",X"19",X"B3",X"19",X"E3", - X"1F",X"06",X"0F",X"0C",X"07",X"F8",X"03",X"F0",X"01",X"00",X"00",X"68",X"19",X"00",X"1C",X"2A", - X"75",X"6B",X"75",X"3D",X"2F",X"1E",X"0C",X"00",X"75",X"19",X"00",X"0C",X"1E",X"2F",X"3B",X"65", - X"7B",X"7D",X"32",X"1C",X"00",X"82",X"19",X"00",X"18",X"3C",X"7E",X"5A",X"5F",X"6B",X"57",X"2A", - X"1C",X"00",X"5B",X"19",X"00",X"1C",X"26",X"5B",X"6F",X"5D",X"72",X"7E",X"3C",X"18",X"00",X"59", - X"1A",X"03",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00", - X"3E",X"00",X"00",X"00",X"00",X"7C",X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0", - X"01",X"00",X"00",X"00",X"E0",X"03",X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F", - X"00",X"00",X"00",X"00",X"2F",X"00",X"00",X"10",X"00",X"7E",X"00",X"00",X"00",X"00",X"7E",X"00", - X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"00",X"E8",X"03",X"00",X"00",X"00",X"D0",X"0B",X"00", - X"00",X"00",X"F0",X"15",X"00",X"00",X"00",X"A0",X"2B",X"00",X"00",X"00",X"40",X"55",X"00",X"00", - X"00",X"80",X"EA",X"00",X"00",X"00",X"00",X"DD",X"03",X"00",X"00",X"00",X"36",X"05",X"00",X"00", - X"00",X"AA",X"08",X"00",X"00",X"00",X"1C",X"1B",X"00",X"00",X"00",X"58",X"36",X"00",X"00",X"00", - X"A0",X"59",X"00",X"00",X"00",X"40",X"67",X"00",X"00",X"00",X"C0",X"CC",X"01",X"00",X"00",X"80", - X"45",X"01",X"00",X"00",X"00",X"AB",X"03",X"00",X"00",X"00",X"50",X"06",X"00",X"00",X"00",X"A4", - X"0C",X"00",X"00",X"00",X"8C",X"05",X"00",X"00",X"00",X"18",X"09",X"00",X"00",X"00",X"30",X"11", - X"00",X"00",X"00",X"40",X"02",X"00",X"00",X"00",X"80",X"04",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"8F",X"19",X"03",X"00",X"00",X"00",X"00", - X"0F",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00",X"7C", - X"00",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"00",X"F0",X"01",X"00",X"00",X"00",X"E0",X"07", - X"00",X"00",X"00",X"C0",X"0F",X"00",X"00",X"00",X"80",X"1F",X"00",X"00",X"00",X"00",X"2F",X"00", - X"00",X"00",X"00",X"6E",X"00",X"00",X"00",X"00",X"DA",X"00",X"00",X"00",X"00",X"EC",X"01",X"00", - X"00",X"00",X"A8",X"03",X"00",X"00",X"00",X"5C",X"0B",X"00",X"00",X"00",X"E0",X"16",X"00",X"00", - X"00",X"A0",X"2D",X"00",X"00",X"00",X"C0",X"71",X"00",X"00",X"00",X"80",X"E5",X"00",X"00",X"00", - X"00",X"CB",X"01",X"00",X"00",X"00",X"36",X"05",X"00",X"00",X"00",X"68",X"02",X"00",X"00",X"00", - X"94",X"0C",X"00",X"00",X"00",X"48",X"39",X"00",X"00",X"00",X"90",X"52",X"00",X"00",X"00",X"20", - X"A5",X"00",X"00",X"00",X"C0",X"48",X"01",X"00",X"00",X"80",X"05",X"02",X"00",X"00",X"00",X"2B", - X"05",X"00",X"00",X"00",X"54",X"0A",X"00",X"00",X"00",X"A8",X"14",X"00",X"00",X"00",X"94",X"01", - X"00",X"00",X"00",X"08",X"01",X"00",X"00",X"00",X"10",X"02",X"00",X"00",X"00",X"20",X"04",X"00", - X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"23",X"1B",X"00",X"00",X"20",X"00",X"30",X"00",X"30",X"00",X"30",X"00",X"34", - X"00",X"3C",X"00",X"2C",X"00",X"7C",X"00",X"7C",X"00",X"3C",X"00",X"3C",X"00",X"3C",X"00",X"3C", - X"00",X"3C",X"00",X"BC",X"00",X"7C",X"00",X"7C",X"00",X"7C",X"01",X"FE",X"00",X"7E",X"00",X"FE", - X"00",X"FE",X"01",X"7E",X"03",X"FE",X"0F",X"7E",X"0F",X"FC",X"01",X"FC",X"03",X"FC",X"00",X"7C", - X"01",X"7C",X"02",X"7C",X"04",X"3C",X"00",X"38",X"00",X"3C",X"00",X"7A",X"00",X"B8",X"00",X"38", - X"00",X"10",X"00",X"00",X"00",X"75",X"1B",X"40",X"A0",X"00",X"60",X"FF",X"F0",X"FF",X"60",X"00", - X"A0",X"40",X"82",X"1B",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", - X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"38",X"00",X"F7",X"01",X"7F",X"1F",X"1E",X"FE",X"7F", - X"1F",X"F7",X"01",X"38",X"00",X"6C",X"00",X"FE",X"03",X"6C",X"00",X"00",X"00",X"B9",X"1B",X"00", - X"00",X"1C",X"0E",X"3B",X"3B",X"0E",X"1C",X"00",X"00",X"AD",X"1B",X"00",X"00",X"1C",X"0E",X"3F", - X"3F",X"0E",X"1C",X"00",X"00",X"E3",X"1B",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63", - X"C6",X"3E",X"7C",X"00",X"00",X"00",X"00",X"3E",X"7C",X"63",X"C6",X"DD",X"BB",X"DD",X"BB",X"63", - X"C6",X"3E",X"7C",X"C5",X"1B",X"3E",X"7C",X"6B",X"B6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"BE", - X"7D",X"C0",X"03",X"C0",X"03",X"BE",X"7D",X"6B",X"D6",X"D5",X"AB",X"D5",X"AB",X"6B",X"D6",X"3E", - X"7C",X"0D",X"1C",X"00",X"00",X"3C",X"05",X"FF",X"1F",X"3C",X"05",X"00",X"00",X"01",X"1C",X"00", - X"00",X"3C",X"05",X"F7",X"1F",X"3C",X"05",X"00",X"00",X"80",X"00",X"80",X"02",X"50",X"48",X"54", - X"21",X"2A",X"04",X"40",X"0B",X"A8",X"24",X"D2",X"0D",X"E0",X"0A",X"F8",X"C7",X"F0",X"24",X"61", - X"04",X"D8",X"1A",X"54",X"25",X"00",X"02",X"88",X"15",X"A4",X"22",X"00",X"00",X"80",X"00",X"54", - X"2A",X"BB",X"56",X"30",X"E8",X"30",X"56",X"B3",X"2A",X"94",X"80",X"B4",X"28",X"1D",X"80",X"43", - X"52",X"24",X"80",X"5C",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"40",X"20", - X"39",X"12",X"2A",X"80",X"C8",X"46",X"09",X"04",X"10",X"95",X"8F",X"A7",X"02",X"00",X"88",X"F1", - X"5E",X"04",X"00",X"55",X"34",X"29",X"22",X"90",X"B2",X"D2",X"76",X"11",X"24",X"F5",X"6F",X"4B", - X"08",X"40",X"FF",X"FF",X"BB",X"02",X"C0",X"FF",X"FF",X"7F",X"02",X"BB",X"FF",X"FF",X"FF",X"DD", - X"C0",X"FF",X"FF",X"7F",X"00",X"20",X"DF",X"FF",X"1F",X"03",X"00",X"F5",X"EF",X"C9",X"20",X"92", - X"EC",X"52",X"76",X"49",X"48",X"CA",X"7C",X"77",X"10",X"04",X"A5",X"97",X"0D",X"00",X"10",X"52", - X"6A",X"55",X"09",X"08",X"28",X"D5",X"22",X"13",X"00",X"94",X"38",X"05",X"00",X"00",X"04",X"10", - X"08",X"00",X"00",X"20",X"10",X"00",X"00",X"1A",X"2C",X"0C",X"03",X"0D",X"18",X"0C",X"14",X"12", - X"17",X"10",X"2E",X"1D",X"12",X"16",X"0E",X"00",X"18",X"28",X"05",X"03",X"1B",X"0E",X"0A",X"0D", - X"22",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16",X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E", - X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"00",X"10",X"29",X"12",X"00",X"10",X"0A",X"16", - X"0E",X"2E",X"18",X"1F",X"0E",X"1B",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"02",X"00", - X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"24",X"01", - X"25",X"00",X"10",X"2B",X"0D",X"00",X"1D",X"1B",X"22",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B", - X"24",X"02",X"25",X"00",X"1E",X"25",X"1A",X"00",X"1C",X"0C",X"18",X"1B",X"0E",X"24",X"01",X"25", - X"2E",X"11",X"12",X"2B",X"1C",X"0C",X"18",X"1B",X"0E",X"2E",X"1C",X"0C",X"18",X"1B",X"0E",X"24", - X"02",X"25",X"00",X"1C",X"2D",X"05",X"00",X"19",X"18",X"12",X"17",X"1D",X"00",X"01",X"36",X"06", - X"00",X"0C",X"1B",X"0E",X"0D",X"12",X"1D",X"00",X"01",X"25",X"06",X"00",X"0E",X"17",X"0E",X"1B", - X"10",X"22",X"00",X"14",X"30",X"04",X"0F",X"19",X"1E",X"1C",X"11",X"01",X"12",X"2A",X"0F",X"0F", - X"01",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"0B",X"1E",X"1D",X"1D",X"18",X"17",X"00", - X"10",X"2A",X"10",X"0F",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"0B",X"1E", - X"1D",X"1D",X"18",X"17",X"00",X"03",X"27",X"15",X"00",X"27",X"2E",X"1C",X"11",X"12",X"17",X"2E", - X"17",X"12",X"11",X"18",X"17",X"2E",X"14",X"12",X"14",X"0A",X"14",X"1E",X"2E",X"27",X"00",X"1A", - X"2C",X"0A",X"1F",X"18",X"23",X"16",X"0A",X"2E",X"2E",X"20",X"0A",X"1B",X"1C",X"01",X"18",X"2F", - X"05",X"1F",X"15",X"0E",X"1D",X"2F",X"1C",X"01",X"16",X"2B",X"0C",X"1F",X"1D",X"1B",X"0A",X"1F", - X"0E",X"15",X"29",X"0F",X"12",X"10",X"11",X"1D",X"01",X"14",X"2B",X"0B",X"1F",X"1C",X"19",X"0A", - X"0C",X"0E",X"2E",X"20",X"18",X"1B",X"15",X"0D",X"00",X"10",X"2E",X"07",X"00",X"27",X"1C",X"0C", - X"18",X"1B",X"0E",X"27",X"01",X"0E",X"2B",X"0E",X"00",X"1E",X"0F",X"18",X"2E",X"2E",X"2E",X"2E", - X"01",X"00",X"00",X"2C",X"05",X"00",X"00",X"01",X"0C",X"2B",X"0C",X"00",X"16",X"0E",X"1D",X"0E", - X"18",X"2E",X"2E",X"05",X"00",X"2C",X"07",X"00",X"01",X"0A",X"2B",X"0A",X"00",X"0C",X"18",X"16", - X"0E",X"1D",X"2E",X"2E",X"08",X"00",X"00",X"00",X"12",X"2A",X"0F",X"00",X"27",X"0C",X"11",X"0A", - X"1B",X"10",X"0E",X"2E",X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"10",X"2B",X"0F",X"00", - X"0D",X"18",X"0C",X"14",X"12",X"17",X"10",X"2E",X"2E",X"2A",X"01",X"05",X"00",X"00",X"00",X"01", - X"0E",X"29",X"13",X"00",X"27",X"0C",X"1B",X"0A",X"1C",X"11",X"2E",X"15",X"18",X"1C",X"1D",X"2E", - X"0E",X"17",X"0E",X"1B",X"10",X"22",X"27",X"01",X"0C",X"2B",X"0F",X"00",X"1E",X"0F",X"18",X"2E", - X"2E",X"2E",X"2E",X"2E",X"2E",X"2B",X"01",X"05",X"00",X"00",X"00",X"01",X"0A",X"2B",X"0E",X"00", - X"16",X"0E",X"1D",X"0E",X"18",X"2E",X"2E",X"2E",X"2E",X"2B",X"08",X"00",X"00",X"00",X"01",X"08", - X"2B",X"0F",X"00",X"0C",X"18",X"16",X"0E",X"1D",X"2E",X"2E",X"2E",X"2E",X"2B",X"02",X"00",X"00", - X"00",X"00",X"01",X"06",X"2B",X"0F",X"00",X"16",X"12",X"1C",X"1C",X"12",X"15",X"0E",X"2E",X"2E", - X"2B",X"01",X"00",X"00",X"00",X"00",X"00",X"14",X"2D",X"0B",X"00",X"12",X"17",X"1C",X"0E",X"1B", - X"1D",X"2E",X"0C",X"18",X"12",X"17",X"01",X"12",X"2B",X"0E",X"00",X"01",X"2E",X"18",X"1B",X"2E", - X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"01",X"10",X"2B",X"0F",X"00",X"01",X"2E", - X"19",X"15",X"0A",X"22",X"0E",X"1B",X"2E",X"01",X"2E",X"0C",X"18",X"12",X"17",X"01",X"0E",X"2A", - X"11",X"00",X"02",X"2E",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"2E",X"02",X"2E",X"0C",X"18", - X"12",X"17",X"1C",X"00",X"DE",X"88",X"D0",X"B8",X"C2",X"26",X"B6",X"CC",X"B0",X"60",X"A8",X"44", - X"A6",X"9C",X"9A",X"FC",X"8B",X"C8",X"7C",X"90",X"76",X"24",X"7C",X"90",X"68",X"C0",X"60",X"60", - X"4C",X"DC",X"48",X"84",X"3E",X"30",X"34",X"F8",X"2C",X"48",X"18",X"30",X"07",X"07",X"07",X"07", - X"45",X"1F",X"0A",X"15",X"0A",X"40",X"1F",X"15",X"0A",X"15",X"51",X"1F",X"00",X"0A",X"07",X"0A", - X"00",X"58",X"1F",X"00",X"05",X"0E",X"05",X"00",X"5F",X"1F",X"00",X"0A",X"0D",X"0A",X"00",X"4A", - X"1F",X"00",X"05",X"0B",X"05",X"00",X"66",X"1F",X"FF",X"0F",X"6A",X"1F",X"00",X"00",X"80",X"07", - X"E0",X"1B",X"F8",X"77",X"47",X"5C",X"FC",X"77",X"F0",X"3B",X"E0",X"1D",X"C0",X"0F",X"80",X"07", - X"00",X"00",X"A6",X"1F",X"00",X"00",X"00",X"00",X"D8",X"00",X"DC",X"01",X"FE",X"03",X"73",X"06", - X"FD",X"05",X"FF",X"07",X"FF",X"07",X"FF",X"07",X"FD",X"05",X"73",X"06",X"FE",X"03",X"DC",X"01", - X"D8",X"00",X"00",X"00",X"00",X"00",X"CA",X"1F",X"00",X"00",X"00",X"00",X"F8",X"00",X"DC",X"01", - X"DE",X"03",X"53",X"06",X"DD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07",X"FD",X"05",X"73",X"06", - X"FE",X"03",X"FC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"82",X"1F",X"00",X"00",X"00",X"00", - X"F8",X"00",X"FC",X"01",X"FE",X"03",X"73",X"06",X"FD",X"05",X"DF",X"07",X"DF",X"07",X"DF",X"07", - X"DD",X"05",X"53",X"06",X"DE",X"03",X"DC",X"01",X"F8",X"00",X"00",X"00",X"00",X"00",X"3A",X"2A", - X"21",X"FE",X"10",X"E2",X"EE",X"1F",X"C3",X"4A",X"07",X"FF",X"85",X"78",X"E9",X"01",X"6C",X"FF"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd deleted file mode 100644 index 02127e5a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw05.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw05 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw05 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"40",X"40",X"6D",X"40",X"B0",X"40",X"EB",X"40",X"1C",X"41",X"A4",X"41",X"DF",X"41",X"12",X"42", - X"45",X"42",X"78",X"42",X"21",X"46",X"A4",X"42",X"85",X"43",X"62",X"44",X"CA",X"44",X"F6",X"44", - X"22",X"45",X"A3",X"45",X"E4",X"45",X"2D",X"46",X"34",X"49",X"99",X"49",X"FD",X"49",X"27",X"4B", - X"4F",X"4C",X"49",X"4D",X"41",X"4E",X"69",X"4E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"D0",X"70",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"28",X"CD",X"53",X"40",X"01",X"FD", - X"01",X"30",X"76",X"D0",X"70",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"01",X"FE", - X"01",X"00",X"F8",X"00",X"01",X"FE",X"01",X"18",X"01",X"FF",X"FF",X"20",X"76",X"D0",X"30",X"DB", - X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"90",X"40",X"01",X"FE",X"01",X"08",X"01", - X"FE",X"FF",X"08",X"01",X"FD",X"01",X"10",X"AF",X"FE",X"FF",X"06",X"01",X"FE",X"01",X"10",X"76", - X"D0",X"30",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"01",X"18",X"01",X"FE",X"FF",X"10",X"01", - X"FE",X"00",X"10",X"AF",X"FE",X"FF",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"76", - X"D0",X"A0",X"DB",X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"18",X"CD",X"C7",X"40",X"01",X"FD", - X"00",X"08",X"01",X"FD",X"FF",X"18",X"76",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE", - X"00",X"18",X"01",X"FE",X"01",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"00",X"10",X"AF",X"FE", - X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FE",X"FF",X"10",X"76",X"D0",X"D0",X"DB",X"17",X"02", - X"0F",X"20",X"01",X"FE",X"00",X"10",X"CD",X"0E",X"41",X"01",X"FE",X"00",X"10",X"AF",X"FF",X"FF", - X"10",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"01",X"10",X"01",X"FD",X"00",X"18",X"76",X"D0",X"D0", - X"1B",X"18",X"02",X"0F",X"02",X"01",X"FE",X"00",X"20",X"C3",X"5E",X"40",X"D0",X"88",X"5B",X"18", - X"02",X"0F",X"10",X"CD",X"3C",X"41",X"CD",X"51",X"41",X"01",X"FE",X"FF",X"0A",X"AF",X"FE",X"FF", - X"02",X"01",X"FE",X"01",X"0A",X"AF",X"FE",X"01",X"02",X"C3",X"29",X"41",X"D0",X"76",X"5B",X"18", - X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"66",X"41",X"01",X"FF",X"FF",X"10",X"C3",X"29", - X"41",X"D0",X"9A",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00",X"12",X"CD",X"77",X"41",X"01", - X"FF",X"01",X"10",X"C3",X"29",X"41",X"D0",X"5C",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00", - X"12",X"CD",X"88",X"41",X"C3",X"4A",X"41",X"D0",X"B4",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00", - X"00",X"12",X"CD",X"96",X"41",X"C3",X"5F",X"41",X"D0",X"40",X"5B",X"18",X"02",X"0F",X"10",X"AF", - X"00",X"00",X"12",X"C3",X"4A",X"41",X"D0",X"CE",X"5B",X"18",X"02",X"0F",X"10",X"AF",X"00",X"00", - X"12",X"C3",X"5F",X"41",X"D0",X"30",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"B9",X"41",X"01",X"FE", - X"01",X"14",X"01",X"FE",X"FF",X"14",X"C3",X"AE",X"41",X"D0",X"40",X"75",X"19",X"01",X"0B",X"50", - X"AF",X"00",X"00",X"10",X"CD",X"CA",X"41",X"C3",X"AE",X"41",X"D0",X"40",X"68",X"19",X"01",X"0B", - X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"40",X"40",X"C3",X"AE",X"41",X"D0", - X"50",X"82",X"19",X"01",X"0B",X"50",X"CD",X"EC",X"41",X"C3",X"AE",X"41",X"D0",X"60",X"75",X"19", - X"01",X"0B",X"50",X"AF",X"00",X"00",X"18",X"CD",X"FD",X"41",X"C3",X"AE",X"41",X"D0",X"50",X"68", - X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD",X"6D",X"40",X"C3", - X"AE",X"41",X"D0",X"70",X"5B",X"19",X"01",X"0B",X"50",X"CD",X"1F",X"42",X"C3",X"AE",X"41",X"D0", - X"80",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"30",X"42",X"C3",X"AE",X"41", - X"D0",X"70",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE",X"00",X"28",X"CD", - X"B0",X"40",X"C3",X"AE",X"41",X"D0",X"90",X"82",X"19",X"01",X"0B",X"50",X"CD",X"52",X"42",X"C3", - X"AE",X"41",X"D0",X"A0",X"68",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"CD",X"63",X"42", - X"C3",X"AE",X"41",X"D0",X"90",X"75",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10",X"01",X"FE", - X"00",X"20",X"CD",X"EB",X"40",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"CD", - X"85",X"42",X"C3",X"AE",X"41",X"D0",X"C0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00",X"10", - X"CD",X"96",X"42",X"C3",X"AE",X"41",X"D0",X"B0",X"5B",X"19",X"01",X"0B",X"50",X"AF",X"00",X"00", - X"18",X"C3",X"AE",X"41",X"D0",X"80",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"E9",X"42",X"01",X"FF", - X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"1F",X"43",X"01",X"FF",X"00",X"10",X"CD",X"2B",X"43", - X"01",X"FF",X"00",X"10",X"AF",X"FF",X"FF",X"10",X"01",X"FF",X"FF",X"10",X"CD",X"35",X"43",X"01", - X"FF",X"FF",X"10",X"CD",X"3F",X"43",X"01",X"FF",X"FF",X"10",X"CD",X"49",X"43",X"01",X"FF",X"00", - X"10",X"CD",X"53",X"43",X"01",X"FF",X"00",X"30",X"76",X"D0",X"60",X"9B",X"18",X"02",X"0F",X"30", - X"AF",X"00",X"00",X"60",X"01",X"FF",X"FF",X"10",X"01",X"FF",X"01",X"10",X"CD",X"5D",X"43",X"01", - X"FF",X"00",X"10",X"CD",X"67",X"43",X"01",X"FF",X"00",X"20",X"AF",X"FF",X"01",X"10",X"01",X"FF", - X"01",X"10",X"CD",X"71",X"43",X"01",X"FF",X"00",X"10",X"CD",X"7B",X"43",X"C3",X"E4",X"42",X"A0", - X"80",X"01",X"1C",X"02",X"05",X"66",X"01",X"FD",X"00",X"30",X"76",X"90",X"8A",X"01",X"1C",X"02", - X"05",X"66",X"C3",X"26",X"43",X"60",X"60",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50", - X"58",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"40",X"01",X"1C",X"02",X"05",X"66", - X"C3",X"26",X"43",X"30",X"4A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"60",X"01", - X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"90",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26", - X"43",X"50",X"80",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"38",X"70",X"01",X"1C",X"02", - X"05",X"66",X"C3",X"26",X"43",X"D0",X"A0",X"9B",X"18",X"02",X"0F",X"30",X"CD",X"C8",X"43",X"01", - X"FF",X"00",X"10",X"CD",X"FE",X"43",X"01",X"FF",X"00",X"10",X"CD",X"08",X"44",X"01",X"FF",X"00", - X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"CD",X"12",X"44",X"01",X"FF",X"01",X"10", - X"CD",X"1C",X"44",X"01",X"FF",X"01",X"08",X"AF",X"FF",X"01",X"10",X"01",X"FF",X"01",X"08",X"CD", - X"26",X"44",X"CD",X"30",X"44",X"C3",X"E4",X"42",X"D0",X"C0",X"9B",X"18",X"02",X"0F",X"30",X"AF", - X"00",X"00",X"50",X"01",X"FF",X"00",X"10",X"CD",X"3A",X"44",X"01",X"FF",X"00",X"10",X"CD",X"44", - X"44",X"01",X"FF",X"FF",X"10",X"AF",X"FF",X"00",X"10",X"01",X"FF",X"01",X"10",X"01",X"FF",X"FF", - X"10",X"CD",X"4E",X"44",X"01",X"FF",X"FF",X"10",X"CD",X"58",X"44",X"C3",X"E4",X"42",X"A0",X"A0", - X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"26",X"43",X"60",X"C0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"60",X"CA",X"01",X"1C", - X"02",X"05",X"66",X"C3",X"26",X"43",X"40",X"E0",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43", - X"40",X"EA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"A0",X"C0",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"26",X"43",X"A0",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"A0", - X"01",X"1C",X"02",X"05",X"66",X"C3",X"26",X"43",X"50",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"26",X"43",X"D0",X"40",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"AB",X"44",X"01",X"FE",X"00",X"12", - X"01",X"FE",X"01",X"04",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"04",X"01",X"FE", - X"01",X"04",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01", - X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"03",X"01",X"FE",X"01",X"03",X"01",X"FE", - X"00",X"08",X"01",X"FE",X"FF",X"08",X"01",X"FE",X"FE",X"30",X"76",X"D0",X"44",X"1B",X"18",X"02", - X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"BC",X"44",X"C3",X"6C",X"44",X"D0",X"38",X"1B",X"18", - X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"80",X"1B",X"18",X"02",X"0F", - X"02",X"CD",X"D7",X"44",X"C3",X"6C",X"44",X"D0",X"84",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00", - X"00",X"20",X"CD",X"E8",X"44",X"C3",X"6C",X"44",X"D0",X"78",X"1B",X"18",X"02",X"0F",X"02",X"AF", - X"00",X"00",X"20",X"C3",X"6C",X"44",X"D0",X"C0",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"03",X"45", - X"C3",X"6C",X"44",X"D0",X"C4",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"CD",X"14", - X"45",X"C3",X"6C",X"44",X"D0",X"B8",X"1B",X"18",X"02",X"0F",X"02",X"AF",X"00",X"00",X"20",X"C3", - X"6C",X"44",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"79",X"45",X"CD",X"87",X"45",X"CD", - X"95",X"45",X"01",X"FF",X"01",X"10",X"EB",X"AA",X"4E",X"02",X"07",X"20",X"01",X"FF",X"01",X"08", - X"EB",X"BA",X"4E",X"02",X"09",X"20",X"01",X"FE",X"01",X"08",X"EB",X"CE",X"4E",X"02",X"0B",X"20", - X"01",X"FE",X"01",X"04",X"EB",X"E6",X"4E",X"02",X"0D",X"20",X"01",X"FE",X"01",X"02",X"EB",X"DB", - X"17",X"02",X"0F",X"20",X"01",X"FE",X"00",X"08",X"AF",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"08", - X"01",X"FE",X"01",X"10",X"01",X"FD",X"01",X"16",X"76",X"D0",X"50",X"9E",X"4E",X"02",X"05",X"20", - X"01",X"00",X"00",X"08",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00", - X"00",X"10",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"01",X"00",X"00",X"18", - X"C3",X"32",X"45",X"D0",X"30",X"9E",X"4E",X"02",X"05",X"20",X"CD",X"BA",X"45",X"CD",X"C8",X"45", - X"CD",X"D6",X"45",X"AF",X"00",X"00",X"20",X"C3",X"32",X"45",X"D0",X"50",X"9E",X"4E",X"02",X"05", - X"20",X"AF",X"00",X"00",X"28",X"C3",X"32",X"45",X"D0",X"70",X"9E",X"4E",X"02",X"05",X"20",X"AF", - X"00",X"00",X"30",X"C3",X"32",X"45",X"D0",X"90",X"9E",X"4E",X"02",X"05",X"20",X"AF",X"00",X"00", - X"38",X"C3",X"32",X"45",X"C0",X"BD",X"23",X"1B",X"02",X"28",X"40",X"01",X"FF",X"FF",X"41",X"CD", - X"F7",X"45",X"01",X"00",X"00",X"FF",X"76",X"77",X"8C",X"75",X"1B",X"01",X"0B",X"40",X"CD",X"06", - X"46",X"01",X"00",X"00",X"FF",X"76",X"23",X"90",X"82",X"1B",X"0B",X"01",X"40",X"CD",X"15",X"46", - X"01",X"00",X"00",X"FF",X"76",X"23",X"92",X"82",X"1B",X"0B",X"01",X"40",X"01",X"00",X"00",X"FF", - X"76",X"C0",X"F0",X"8F",X"19",X"05",X"28",X"70",X"01",X"FD",X"FD",X"40",X"76",X"80",X"B0",X"82", - X"1F",X"02",X"11",X"38",X"01",X"00",X"00",X"01",X"CD",X"82",X"47",X"CD",X"8E",X"47",X"CD",X"98", - X"47",X"CD",X"A4",X"47",X"CD",X"AE",X"47",X"AF",X"00",X"FE",X"04",X"CD",X"B8",X"47",X"01",X"00", - X"FE",X"04",X"CD",X"C2",X"47",X"01",X"00",X"FE",X"04",X"CD",X"CC",X"47",X"AF",X"00",X"FE",X"04", - X"CD",X"D6",X"47",X"01",X"00",X"FE",X"04",X"CD",X"E0",X"47",X"01",X"00",X"FE",X"04",X"CD",X"EA", - X"47",X"AF",X"00",X"FF",X"08",X"CD",X"F4",X"47",X"01",X"00",X"FE",X"04",X"CD",X"FE",X"47",X"01", - X"00",X"FE",X"04",X"CD",X"08",X"48",X"01",X"00",X"FF",X"08",X"CD",X"12",X"48",X"CD",X"1C",X"48", - X"AF",X"00",X"FE",X"04",X"CD",X"26",X"48",X"01",X"00",X"FE",X"04",X"CD",X"30",X"48",X"01",X"00", - X"FE",X"04",X"CD",X"3A",X"48",X"01",X"00",X"FE",X"04",X"CD",X"44",X"48",X"01",X"00",X"FE",X"04", - X"CD",X"4E",X"48",X"01",X"00",X"FE",X"04",X"CD",X"58",X"48",X"01",X"00",X"FE",X"04",X"CD",X"62", - X"48",X"01",X"00",X"02",X"04",X"CD",X"6C",X"48",X"AF",X"00",X"02",X"04",X"CD",X"76",X"48",X"01", - X"00",X"02",X"04",X"CD",X"80",X"48",X"AF",X"00",X"02",X"04",X"CD",X"30",X"48",X"01",X"00",X"02", - X"04",X"CD",X"8A",X"48",X"01",X"00",X"01",X"08",X"CD",X"94",X"48",X"AF",X"00",X"01",X"08",X"CD", - X"1C",X"48",X"01",X"00",X"02",X"04",X"CD",X"9E",X"48",X"01",X"00",X"02",X"04",X"CD",X"F4",X"47", - X"AF",X"00",X"02",X"04",X"CD",X"A8",X"48",X"01",X"00",X"02",X"04",X"CD",X"B2",X"48",X"01",X"00", - X"02",X"04",X"CD",X"D6",X"47",X"01",X"00",X"02",X"04",X"CD",X"BC",X"48",X"01",X"00",X"02",X"04", - X"CD",X"C6",X"48",X"AF",X"00",X"02",X"04",X"CD",X"D0",X"48",X"01",X"00",X"02",X"04",X"CD",X"8E", - X"47",X"01",X"00",X"02",X"04",X"CD",X"DA",X"48",X"01",X"00",X"02",X"04",X"CD",X"AE",X"47",X"AF", - X"00",X"02",X"04",X"CD",X"E4",X"48",X"01",X"00",X"02",X"04",X"CD",X"EE",X"48",X"01",X"00",X"02", - X"04",X"CD",X"F8",X"48",X"01",X"00",X"01",X"08",X"CD",X"02",X"49",X"01",X"00",X"02",X"08",X"CD", - X"0C",X"49",X"01",X"00",X"FE",X"08",X"CD",X"16",X"49",X"01",X"00",X"FE",X"04",X"CD",X"20",X"49", - X"01",X"00",X"FE",X"04",X"CD",X"2A",X"49",X"AF",X"00",X"FE",X"0C",X"01",X"00",X"FE",X"04",X"C3", - X"34",X"46",X"70",X"AC",X"66",X"1F",X"02",X"01",X"64",X"01",X"FC",X"00",X"18",X"76",X"70",X"B2", - X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"B6",X"01",X"1C",X"02",X"05",X"66",X"01", - X"FD",X"00",X"20",X"76",X"70",X"BE",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"C4", - X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"AA",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"9F",X"47",X"70",X"A2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9A",X"01",X"1C", - X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"94",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47", - X"70",X"8A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"82",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"9F",X"47",X"70",X"7C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"72"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd deleted file mode 100644 index dc5691b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/roms/mw06.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity mw06 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of mw06 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"6A",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"9F",X"47",X"70",X"60",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"6C",X"66",X"1F", - X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"5A",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", - X"70",X"54",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"4A",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"9F",X"47",X"70",X"42",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"3A", - X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"32",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"9F",X"47",X"70",X"2C",X"66",X"1F",X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"3B",X"01",X"1C", - X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"43",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", - X"70",X"4B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"5B",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"9F",X"47",X"70",X"63",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"73", - X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"83",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"9F",X"47",X"70",X"8B",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"9B",X"01",X"1C", - X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"A3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", - X"70",X"AB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BB",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"9F",X"47",X"70",X"CB",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"D3", - X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"DB",X"01",X"1C",X"02",X"05",X"66",X"C3", - X"9F",X"47",X"70",X"E3",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"E8",X"66",X"1F", - X"02",X"01",X"64",X"C3",X"89",X"47",X"70",X"CA",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47", - X"70",X"C2",X"01",X"1C",X"02",X"05",X"66",X"C3",X"9F",X"47",X"70",X"BA",X"01",X"1C",X"02",X"05", - X"66",X"C3",X"9F",X"47",X"D0",X"60",X"1B",X"18",X"02",X"0F",X"02",X"CD",X"62",X"44",X"01",X"FE", - X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A",X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08", - X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02",X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00", - X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30",X"01",X"FE",X"02",X"04",X"01",X"FE",X"01",X"03", - X"CD",X"83",X"49",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FF",X"04",X"CD",X"8F",X"49",X"01",X"FE", - X"FE",X"20",X"76",X"7A",X"78",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"20",X"76",X"62", - X"74",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"A0",X"1B",X"18",X"02",X"0F",X"02", - X"CD",X"CA",X"44",X"CD",X"F6",X"44",X"01",X"FE",X"00",X"10",X"AF",X"00",X"04",X"01",X"EB",X"6A", - X"1F",X"02",X"0B",X"10",X"01",X"FE",X"01",X"08",X"AF",X"00",X"04",X"01",X"EB",X"7E",X"4E",X"02", - X"07",X"20",X"01",X"FE",X"01",X"04",X"AF",X"00",X"04",X"01",X"EB",X"8E",X"4E",X"02",X"07",X"30", - X"01",X"FE",X"02",X"03",X"CD",X"E9",X"49",X"01",X"FE",X"01",X"04",X"01",X"FE",X"00",X"04",X"CD", - X"F3",X"49",X"01",X"FE",X"00",X"04",X"C3",X"A2",X"44",X"82",X"73",X"4A",X"1F",X"01",X"05",X"66", - X"C3",X"8A",X"49",X"72",X"67",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"8A",X"49",X"D0",X"78",X"DB", - X"18",X"02",X"0F",X"33",X"CD",X"61",X"4A",X"01",X"FF",X"00",X"10",X"CD",X"3F",X"4A",X"01",X"FF", - X"00",X"10",X"01",X"FF",X"01",X"11",X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0", - X"FF",X"02",X"01",X"00",X"00",X"04",X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"00",X"00",X"12", - X"CD",X"4B",X"4A",X"CD",X"57",X"4A",X"01",X"FE",X"00",X"10",X"01",X"FD",X"FF",X"10",X"76",X"B8", - X"7F",X"4A",X"1F",X"01",X"05",X"66",X"01",X"FD",X"00",X"40",X"76",X"50",X"7A",X"66",X"1F",X"02", - X"01",X"64",X"01",X"FC",X"00",X"10",X"76",X"50",X"84",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52", - X"4A",X"D0",X"48",X"1B",X"19",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"CD",X"DF",X"4A",X"01", - X"FF",X"00",X"10",X"CD",X"AB",X"4A",X"01",X"FF",X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD", - X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A", - X"01",X"00",X"00",X"06",X"CD",X"B5",X"4A",X"CD",X"C1",X"4A",X"01",X"FE",X"00",X"08",X"CD",X"CB", - X"4A",X"CD",X"D5",X"4A",X"01",X"00",X"00",X"10",X"C3",X"9E",X"4A",X"B8",X"4F",X"4A",X"1F",X"01", - X"05",X"66",X"C3",X"46",X"4A",X"60",X"48",X"40",X"1F",X"01",X"03",X"64",X"01",X"FE",X"00",X"30", - X"76",X"60",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"48",X"40",X"1F",X"01", - X"03",X"64",X"C3",X"BC",X"4A",X"50",X"54",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"D0", - X"78",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF",X"00",X"11",X"01",X"FE", - X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"10",X"01",X"FE", - X"00",X"09",X"01",X"FD",X"00",X"06",X"CD",X"13",X"4B",X"CD",X"1D",X"4B",X"01",X"00",X"00",X"10", - X"C3",X"06",X"4B",X"40",X"79",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"40",X"83",X"66", - X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"CD",X"87", - X"4B",X"01",X"FF",X"00",X"18",X"CD",X"69",X"4B",X"01",X"FF",X"00",X"08",X"01",X"FF",X"01",X"11", - X"01",X"FE",X"FF",X"08",X"01",X"FD",X"FF",X"05",X"AF",X"F0",X"FF",X"02",X"01",X"00",X"00",X"02", - X"CD",X"73",X"4B",X"CD",X"7D",X"4B",X"01",X"00",X"00",X"0E",X"CD",X"73",X"4B",X"CD",X"7D",X"4B", - X"01",X"FE",X"00",X"10",X"01",X"FD",X"01",X"10",X"76",X"B0",X"AF",X"4A",X"1F",X"01",X"05",X"66", - X"C3",X"46",X"4A",X"50",X"AA",X"66",X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"50",X"B4",X"66", - X"1F",X"02",X"01",X"64",X"C3",X"52",X"4A",X"D0",X"D8",X"DB",X"18",X"02",X"0F",X"33",X"AF",X"00", - X"00",X"10",X"CD",X"03",X"4C",X"01",X"FF",X"00",X"18",X"CD",X"D1",X"4B",X"01",X"FF",X"00",X"09", - X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00",X"00",X"04", - X"CD",X"DB",X"4B",X"CD",X"E5",X"4B",X"01",X"00",X"00",X"08",X"CD",X"DB",X"4B",X"CD",X"E5",X"4B", - X"01",X"FE",X"00",X"08",X"CD",X"EF",X"4B",X"CD",X"F9",X"4B",X"01",X"00",X"00",X"10",X"C3",X"C4", - X"4B",X"B0",X"DF",X"4A",X"1F",X"01",X"05",X"66",X"C3",X"46",X"4A",X"60",X"D8",X"40",X"1F",X"01", - X"03",X"64",X"C3",X"BC",X"4A",X"60",X"E4",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50", - X"D8",X"40",X"1F",X"01",X"03",X"64",X"C3",X"BC",X"4A",X"50",X"E4",X"40",X"1F",X"01",X"03",X"64", - X"C3",X"BC",X"4A",X"D0",X"A8",X"FB",X"18",X"02",X"0F",X"33",X"AF",X"00",X"00",X"10",X"01",X"FF", - X"00",X"11",X"01",X"FE",X"00",X"08",X"01",X"FD",X"00",X"05",X"AF",X"F0",X"00",X"02",X"01",X"00", - X"00",X"10",X"01",X"FE",X"00",X"09",X"01",X"FD",X"00",X"06",X"01",X"00",X"00",X"04",X"CD",X"3B", - X"4C",X"CD",X"45",X"4C",X"01",X"00",X"00",X"10",X"C3",X"2A",X"4C",X"40",X"A9",X"66",X"1F",X"02", - X"01",X"64",X"C3",X"52",X"4A",X"40",X"B3",X"66",X"1F",X"03",X"01",X"64",X"C3",X"52",X"4A",X"C0", - X"8C",X"C5",X"1B",X"02",X"0E",X"3F",X"00",X"00",X"00",X"CD",X"6C",X"4C",X"CD",X"88",X"4C",X"CD", - X"9A",X"4C",X"CD",X"B0",X"4C",X"01",X"00",X"00",X"20",X"C3",X"56",X"4C",X"AA",X"8A",X"AD",X"1B", - X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"01",X"FE",X"01",X"10",X"01", - X"FD",X"FE",X"10",X"01",X"FC",X"02",X"10",X"76",X"AA",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01", - X"FE",X"00",X"08",X"01",X"FE",X"00",X"18",X"C3",X"7B",X"4C",X"B4",X"8A",X"AD",X"1B",X"01",X"0A", - X"08",X"01",X"FE",X"00",X"08",X"01",X"FE",X"FE",X"0C",X"01",X"FE",X"01",X"04",X"C3",X"7B",X"4C", - X"B4",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"00",X"08",X"CD",X"D2",X"4C",X"CD",X"E4", - X"4C",X"CD",X"F6",X"4C",X"CD",X"04",X"4D",X"01",X"FE",X"02",X"14",X"01",X"FE",X"00",X"04",X"C3", - X"7B",X"4C",X"AE",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE",X"11",X"01",X"FE",X"01", - X"0E",X"C3",X"7B",X"4C",X"AE",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"18",X"01", - X"FE",X"01",X"08",X"C3",X"7B",X"4C",X"B8",X"8A",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"FE", - X"24",X"C3",X"7B",X"4C",X"B8",X"92",X"AD",X"1B",X"01",X"0A",X"08",X"01",X"FE",X"02",X"24",X"C3", - X"7B",X"4C",X"3E",X"01",X"F7",X"0A",X"C3",X"E3",X"0F",X"E1",X"C3",X"E3",X"0F",X"76",X"1E",X"4D", - X"00",X"00",X"1E",X"0C",X"3F",X"0C",X"1E",X"00",X"00",X"29",X"4D",X"00",X"00",X"00",X"00",X"F0", - X"00",X"60",X"00",X"F8",X"01",X"7E",X"00",X"FC",X"00",X"3F",X"00",X"FC",X"00",X"7E",X"00",X"F8", - X"01",X"60",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"D0",X"48",X"29",X"4D",X"02",X"0F",X"12", - X"CD",X"9C",X"4D",X"CD",X"D3",X"4D",X"CD",X"0A",X"4E",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02", - X"10",X"CD",X"76",X"4D",X"CD",X"80",X"4D",X"CD",X"8E",X"4D",X"76",X"01",X"FE",X"FE",X"10",X"01", - X"FE",X"02",X"10",X"C3",X"6B",X"4D",X"90",X"4B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D", - X"93",X"48",X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"FE",X"10",X"C3",X"6B",X"4D",X"93",X"4E", - X"1E",X"4D",X"01",X"09",X"22",X"01",X"FF",X"02",X"08",X"C3",X"6B",X"4D",X"D0",X"78",X"29",X"4D", - X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE",X"02",X"10",X"CD",X"B5",X"4D",X"CD",X"BF", - X"4D",X"CD",X"C9",X"4D",X"76",X"90",X"7B",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93", - X"78",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"7E",X"1E",X"4D",X"01",X"09",X"22", - X"C3",X"95",X"4D",X"D0",X"B8",X"29",X"4D",X"02",X"0F",X"12",X"01",X"FE",X"FE",X"10",X"01",X"FE", - X"02",X"10",X"CD",X"EC",X"4D",X"CD",X"F6",X"4D",X"CD",X"00",X"4E",X"76",X"90",X"BB",X"1E",X"4D", - X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"B8",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D", - X"93",X"BE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95",X"4D",X"D0",X"E8",X"29",X"4D",X"02",X"0F", - X"12",X"01",X"FE",X"FE",X"10",X"01",X"FF",X"02",X"10",X"CD",X"23",X"4E",X"CD",X"2D",X"4E",X"CD", - X"37",X"4E",X"76",X"90",X"EB",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"6B",X"4D",X"93",X"E8",X"1E", - X"4D",X"01",X"09",X"22",X"C3",X"87",X"4D",X"93",X"EE",X"1E",X"4D",X"01",X"09",X"22",X"C3",X"95", - X"4D",X"D0",X"88",X"DB",X"18",X"02",X"0F",X"33",X"CD",X"49",X"4D",X"AF",X"00",X"00",X"20",X"CD", - X"49",X"4D",X"01",X"00",X"00",X"04",X"AF",X"00",X"04",X"02",X"01",X"00",X"00",X"04",X"AF",X"00", - X"FC",X"02",X"01",X"00",X"00",X"04",X"C3",X"4F",X"4E",X"D0",X"10",X"AD",X"1B",X"01",X"0A",X"08", - X"CD",X"49",X"4D",X"AF",X"00",X"00",X"10",X"CD",X"FD",X"49",X"CD",X"27",X"4B",X"76",X"7E",X"4E", - X"00",X"00",X"E0",X"1F",X"78",X"7C",X"FF",X"7F",X"FC",X"3F",X"F0",X"1F",X"00",X"00",X"8E",X"4E", - X"00",X"00",X"00",X"00",X"C0",X"0F",X"FE",X"7F",X"E0",X"0F",X"00",X"00",X"00",X"00",X"9E",X"4E", - X"00",X"00",X"40",X"00",X"E0",X"00",X"40",X"00",X"00",X"00",X"AA",X"4E",X"00",X"00",X"E0",X"00", - X"F0",X"01",X"B0",X"01",X"F0",X"01",X"E0",X"00",X"00",X"00",X"BA",X"4E",X"00",X"00",X"E0",X"00", - X"50",X"01",X"E8",X"02",X"B8",X"03",X"E8",X"02",X"50",X"01",X"E0",X"00",X"00",X"00",X"CE",X"4E", - X"00",X"00",X"B0",X"01",X"F8",X"03",X"EC",X"06",X"B4",X"05",X"58",X"03",X"B4",X"05",X"EC",X"06", - X"F8",X"03",X"B0",X"01",X"00",X"00",X"E6",X"4E",X"00",X"00",X"B0",X"01",X"F8",X"03",X"5C",X"07", - X"AE",X"0E",X"56",X"0D",X"F8",X"03",X"56",X"0D",X"AE",X"0E",X"5C",X"07",X"F8",X"03",X"B0",X"01", - X"00",X"00",X"C0",X"04",X"00",X"00",X"00",X"10",X"C6",X"00",X"00",X"00",X"6C",X"29",X"10",X"01", - X"00",X"16",X"04",X"06",X"11",X"00",X"6E",X"C9",X"00",X"00",X"00",X"34",X"C2",X"05",X"90",X"00", - X"DF",X"08",X"02",X"00",X"00",X"CC",X"25",X"08",X"02",X"10",X"BA",X"43",X"92",X"80",X"00",X"A1", - X"4C",X"08",X"21",X"02",X"2F",X"2B",X"31",X"04",X"10",X"D0",X"6A",X"04",X"81",X"20",X"0A",X"95", - X"02",X"10",X"02",X"A0",X"A8",X"45",X"01",X"04",X"10",X"51",X"00",X"92",X"00",X"01",X"44",X"06", - X"20",X"01",X"36",X"92",X"44",X"42",X"00",X"C2",X"A0",X"91",X"04",X"00",X"00",X"10",X"03",X"01", - X"02",X"28",X"08",X"0C",X"20",X"00",X"80",X"92",X"02",X"41",X"08",X"04",X"00",X"25",X"90",X"00", - X"50",X"05",X"4A",X"24",X"00",X"00",X"20",X"D4",X"48",X"00",X"8A",X"42",X"80",X"81",X"42",X"02", - X"10",X"00",X"21",X"04",X"40",X"01",X"20",X"02",X"08",X"04",X"48",X"44",X"00",X"00",X"20",X"10", - X"88",X"00",X"00",X"00",X"04",X"10",X"10",X"01",X"10",X"01",X"21",X"00",X"20",X"28",X"08",X"00", - X"40",X"44",X"80",X"00",X"04",X"02",X"00",X"00",X"14",X"00",X"04",X"00",X"20",X"20",X"01",X"09", - X"00",X"00",X"02",X"02",X"00",X"08",X"00",X"01",X"20",X"00",X"00",X"40",X"80",X"00",X"00",X"20", - X"00",X"10",X"80",X"00",X"40",X"00",X"20",X"00",X"00",X"80",X"FF",X"FF",X"07",X"07",X"07",X"07", - X"07",X"07",X"07",X"07",X"07",X"02",X"03",X"04",X"05",X"06",X"12",X"2D",X"0A",X"00",X"0E",X"17", - X"0E",X"1B",X"10",X"22",X"2E",X"18",X"1E",X"1D",X"00",X"3E",X"09",X"CD",X"05",X"0A",X"E1",X"D1", - X"C3",X"12",X"4D",X"3E",X"E1",X"C3",X"EB",X"4F",X"F7",X"0A",X"F7",X"0C",X"AF",X"E7",X"0B",X"C9"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README GunFight.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/GunFight_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README GunFight.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README LunarRescue.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Lunar Rescue_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README LunarRescue.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README OzmaWars.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Ozma Wars_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README OzmaWars.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders2.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceInvaders2.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceLaser.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README SpaceLaser.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README SuperEarthInvasion.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README SuperEarthInvasion.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/README Vortex.txt similarity index 100% rename from Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/README.txt rename to Arcade_MiST/Midway-Taito 8080 Hardware/README Vortex.txt diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt deleted file mode 100644 index 6c0eccf4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Shuffleboard port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- -ToDo: Color Prom - Controls + DIP - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf deleted file mode 100644 index d253de0b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "Shuffleboard" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf deleted file mode 100644 index 03efe657..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.qsf +++ /dev/null @@ -1,173 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 13:57:20 June 05, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# LunarRescue_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Shuffleboard_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Shuffleboard_memory.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Shuffleboard_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------------ -# start ENTITY(LunarRescue_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(LunarRescue_mist) -# ---------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Shuffleboard.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Snapshot/Shuffleboard.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Snapshot/Shuffleboard.rbf deleted file mode 100644 index 4b320709..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/Snapshot/Shuffleboard.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv deleted file mode 100644 index 135c4b18..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_memory.sv +++ /dev/null @@ -1,80 +0,0 @@ -module Shuffleboard_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; - - -sprom #( - .init_file("./roms/shuffle.h.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/shuffle.g.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/shuffle.f.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/shuffle.e.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv deleted file mode 100644 index b88aaae3..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/Shuffleboard_mist.sv +++ /dev/null @@ -1,196 +0,0 @@ -module Shuffleboard_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Shuffleb.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_sys), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -Shuffleboard_memory Shuffleboard_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B({Video,Video,Video}), - .HSync(~hs), - .VSync(~vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(1), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd deleted file mode 100644 index db58d70b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/dac.vhd +++ /dev/null @@ -1,48 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity dac is - generic ( - C_bits : integer := 8 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); -end dac; - -architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); -begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; -end rtl; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd deleted file mode 100644 index f089f1f2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,243 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= DIP(8); -- Unused ? - GDB0(1) <= DIP(7); - GDB0(2) <= DIP(6); -- Unused ? - GDB0(3) <= '1'; -- Unused ? - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= DIP(5); -- Unused ? - - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';-- Unused ? - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1';-- Unused ? - - GDB2(0) <= DIP(4); -- LSB Lives 3-6 - GDB2(1) <= DIP(3); -- MSB Lives 3-6 - GDB2(2) <= '0';-- Tilt ? - GDB2(3) <= '0';--DIP(2); -- Bonus life at 1000 or 1500 - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1';--DIP(1); -- Coin info - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd deleted file mode 100644 index 1d9ad578..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,335 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd deleted file mode 100644 index d65b9f9b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/pll.vhd +++ /dev/null @@ -1,350 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire4_bv(0 DOWNTO 0) <= "0"; - sub_wire4 <= To_stdlogicvector(sub_wire4_bv); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - sub_wire2 <= inclk0; - sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire3, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.bin deleted file mode 100644 index f9447473..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex deleted file mode 100644 index bf312566..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.e.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000B8DAF617AF3212223A2F223DFA1F183211 -:100010002F22C21F183A0920E6C7320920D3053A19 -:1000200030223DFA3618323022C236183A0920E61C -:10003000FD320920D3052120203A03222201222269 -:1000400000203204223E09CD9E1BFAE918CAA618E8 -:100050003E0CCD0A1B3E0ECD0A1B3E0FCD9E1BF55E -:100060003621CDCC002A0122463E05CDA8007E23B4 -:10007000B7FA8D18C280182B360423237EC3981834 -:1000800080BEC298183EFC2B7780C398182380BE90 -:10009000D29818237E2336C12A0122773E0FCDA89D -:1000A000003604C3DF182346234E2A01222323B837 -:1000B000C2BA1823237EB9CAE9183A3622B8DACC74 -:1000C000183A3122B7C2CC183C32312278FE60D2C5 -:1000D000D7183E043225223E0FCD9E1BF53605CDA6 -:1000E000CC003E0FCD9E1BF1773E10CD9E1B3A04F7 -:1000F000223DC23C183A1D22B7CA1A1521402235AA -:10010000C21A153A0322FE06CA1A15C380113A1DF7 -:10011000223DC3831E321722321522CD5D1C3213BD -:10012000223A17224F3A342281F22D19AF3234226B -:100130002180200620CD521A3A15224F3A352281CD -:10014000F24419AF32352206CFCD521A3E40320763 -:1001500022212710CDAB1A21F619E53E40320922A3 -:10016000D304AF321222322D222120203E0622005B -:10017000203204223E05CD2002B7CA84193A092252 -:10018000B7C28E193E0FCD20023621CDCC003E10D5 -:10019000CD20023A04223DC26E19D3043A1222FE47 -:1001A00004DA9A193A07223DFAD619320722C2B761 -:1001B00019CD1F1AC3D6192180202200207EB7CA6C -:1001C000D619CDCC003E02CD2002343E0FCD200208 -:1001D000360523C3BA193A09223DF25D193A1D22A8 -:1001E000B7C26C053A3D22B7FAF5193A0822B73A78 -:1001F0001322CAF210C921D53611F90BCD5A0321A9 -:10020000071AE5AFC35D19CD9407CD9407CD9407C8 -:100210003A0022323F22C32C05213410CDAB1A21E3 -:10022000F53B3A3522CD2E1A2115263A34224F3A83 -:100230001822B9D2391A320822790E00FE0AFA477A -:100240001A0CD60AC33C1ACD75041140FF1979C3A4 -:10025000750479B7F26D1AFEF7F4A51A36A4CD9598 -:100260001A792F3C4FFE0AFA8F1AC37C1ACDA51AB1 -:1002700079FE0AF27C1ACDA51AC38F1A1E247BC6FA -:10028000045F79D60A4FFE0AF27E1A73CD951A7969 -:100290008787C624772323366E232370110B00191A -:1002A000360423360078D60847C975111020060594 -:1002B0007E1223131305C2B01A7E1B1223221C20A8 -:1002C000CDC900013A1220211620863212202323A4 -:1002D0003A1420863214202335C2C01AD3042A1CB3 -:1002E000207EFEFFC2AB1AC9EBCDA8004E21000054 -:1002F0000DFAF81A19C3F01A0E047CB7F2001B3776 -:100300001F677D1F6F0DC2FA1AC9F5CD9E1B4E23C4 -:1003100046F1D60BCD9E1B7E8177237E8877C9F56B -:100320002A0522CDA8005E2356F1FE07C2321B2308 -:100330003600F5CD9E1B935F237E9A57F1FE07C2D0 -:10034000451B2336002100000DFA501B19C3481B22 -:100350003A2D22B7F07C2F677D2F6F23C9320B22F5 -:100360002A01222200200600CDA8005E23567AB77B -:10037000FA781B05792F4F03EB093A3122B7FA8738 -:100380001BCA871B090909EB722B730E02EBCDFA0E -:100390001AEB3A0B22C607CD2002732372C92A0139 -:1003A00022856FD2A71B247EB7C97CB7CABB1BFEB0 -:1003B000FFC07DFEF0D82600C3BF1B7DFE10D02EEF -:1003C000003A04223C320422C9213C2235F0360492 -:1003D0003A0A22EE01320A222A01227E113410FE4C -:1003E00000CAE71B113A102180202200201A77232F -:1003F00023131A772323131A773E0BCDA800360454 -:10040000CDCC002120203A03223DCA321C322D22BD -:100410002200203E05CDA8007EB7C2271C3E0ACD93 -:10042000A8003621CDCC003E10CD20023A2D22C3AB -:10043000091C2A01223A0322C602FE07F2561C3288 -:100440002D223E20CDA800220020CDCC003A2D2226 -:100450002A0020C3381C2A0122220020C921202082 -:100460003A0022B7CA4C1D3EFF3214223216223AFD -:1004700003223DC822012232042206FF7E111422EB -:10048000FE00CA881C1116223E04CDA11BFE3FDAD5 -:10049000A71CFE9AD2A71C2B2B7EFE0BDAA71C1AD8 -:1004A000BEDAA61C7E12043E05CD9E1B703E10CD0A -:1004B0009E1B3A04223DC2741C1114220E003A16EF -:1004C00022471AB8CAD21CDAD31C13130E0447C32E -:1004D000D31C04132120203A03223D32042222019E -:1004E000223E05CD9E1BFA221D2A012223237EB81F -:1004F000D21B1D3242222A01227EB9C2221D3A425B -:100500002221B510BED20D1D2323C3041D231A863C -:10051000123E05CD9E1B3600C3221D3E05CD9E1BFF -:1005200036013E10CD9E1B3A04223DC2DB1C3A141C -:1005300022473A1622B8C2461D3E04B9CA481D4F8A -:10054000111622C3D21C79C93A1322C93A03223D9B -:10055000C822012232042223237EFE72D2E51DFE30 -:100560001DDAAC1D23235E57D618F26E1DAF1F4F48 -:10057000C642BBD2E51D3E9591BBDAE51D060A7A5F -:10058000FE57D2CE1D7BFE6FD2901DFE69D2E51DB7 -:1005900006087AFE51D2E51DFE3AD2CE1DFE34D2B7 -:1005A000E51DFE1DDAE51D0607C3CE1DFE0EDAE5CC -:1005B0001DFE17D2E51D23237EFE42DAE51DFE97C0 -:1005C000D2E51D060A2A01227EEE04C3D21D2A01AD -:1005D000227E111522FE00CADD1D1117221A80127B -:1005E0000600C3E71D06013E05CD9E1B703E10CDE3 -:1005F0009E1B3A04223DC2511D3A1322EE04C9212A -:10060000D83601DFFF3E543600233600093DC207CD -:100610001EC940FC000048FC200020FCF0FF78FCD4 -:10062000EAFF80FC20007BFC0C001EFCC0FF90FC5D -:100630001000E0FCF0FF70FCB0FFA0FCD0FF70FCED -:10064000B0FF50FC2800A8FC200040FC000000FC8B -:10065000B0FF30FC100060FC300038FC60FF48FC4C -:10066000600050FCD0FF28FC000030FC100028FC8B -:10067000600028FC400030FC200028FC90FF48FC73 -:10068000A8FFCBCA5D19AFC31519FE80DA9D1E2ADB -:10069000E705CDEB3622E70521DF05362D2AE705F4 -:1006A000444DCD5B1EC9CDFB0CCDF60C2ADE0344B8 -:1006B0004DCD402F3AE203FEC4C2E91E3AE803FEE4 -:1006C00000CACF1E0E31CD8D2221000022E3033A55 -:1006D000E703E680FE00CADE1E0E4ACD8D222AE325 -:1006E00003444DCD7B1ECDFB0C3E0011E303CD2119 -:1006F00037B5C2011FCDA72DF6014FCDBA2DC316B8 -:100700001FCDD62D3E00CD0037B5CA161FCDA72D63 -:10071000E6FE4FCDBA2D2AE303E5CD992DE5CDD6E2 -:100720002DEBC1CDE52FCDD62DEB21E503CD2F3718 -:10073000D2381F0E4BCD8D22C9CDF60C2ADE0322F6 -:10074000DC03CD0F11C9CDFB0CCDF60C3E0011DC46 -:1007500003CD2137B5C2611F2AE30322DC03C38224 -:100760001F3E0011E303CD2137B5CA821F2AE303E0 -:1007700023E52AE30323444DCD4B30E67F5FC1CD13 -:1007800053302AE503EB2ADE031922DE03CD400DA8 -:10079000C9CD2B2022E905CD2B2022E3033E00CD3D -:1007A0000037B5C2AB1F0E4DCD8D22CDF60C3E00ED -:1007B00011E905CD2137B5D6019FF53E0011E303C0 -:1007C000CD2137B5D6019FC148B1EB11DE032BF522 -:1007D000CD16379FC148B11FD2E71F21000022DC90 -:1007E0000322DE03C3272001E30311DE03CD143708 -:1007F00023EB2B732372EB11E905CD2437D20620AE -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.bin deleted file mode 100644 index ba6856a4..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex deleted file mode 100644 index 4fcca38e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.f.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000012C101E9B02FF2C40222A008602443F36 -:100010002A0086021C5C24008B0214127A00000164 -:10002000181245000001FF08B6BF00011008B61005 -:10003000000110FF50CCC00000014CCC10000001AA -:10004000FF808080808080808008667473728282E6 -:1000500082084766657473737208375666657474F0 -:1000600073082747566665647408283747566665DF -:100070006508283747465666650828273747566576 -:100080006600010205080B0E0F10000306070807A3 -:100090000603000001040910192431405101010137 -:1000A0000202020204194B235A286932780B4B0FC3 -:1000B0005A1269157829011A020F030B0400001D5A -:1000C00021E03F2D3600C2C310D304257CFE23C29D -:1000D000C310C9CDC010CD6406AF323422323522F0 -:1000E000321722323D22CD191AAF3241223E04325C -:1000F000132247782120200E08FE00C200110EBAFC -:100100003E03320422703A0022B7F211113A132250 -:1001100077160023722336E8237223713E0423727C -:100120003DC21E112336011E061936042378EE0443 -:1001300047FE003EB2CA3A113E4E814F3A1322B8F2 -:10014000C2051179C60E4F3A04223DC20211212088 -:10015000203E06320322220020CDCC003E10CD20CE -:10016000023A03223DC253113203223A3D22FE01DC -:10017000C280112F323D2221D53611C70BCD5A0333 -:100180003A0022B7C2CD113A0322FE02F2CD114746 -:100190003A4122B0CACD11324122218020220020D2 -:1001A000361423233612232336B03E0ACD200236DE -:1001B0001223367A3E05328F20CDCC003E18328095 -:1001C00020AF3284203E45328B20CDCC003A032232 -:1001D000472120203C320322FE07CA0E19FE02C22C -:1001E000E21105FAEE113E10CDA800C3E211220083 -:1001F000202201223E0FCDA8003605AF3239222A37 -:100200000020232336F72323366F3A1D22B7C22A54 -:10021000123A21223DC230132A00207EFE00C23055 -:100220001311410C21F934CD5A033EFF3231222102 -:1002300000001138003A1D22B7C26012111C003AAA -:100240003422473A352290FE08F2601278B7C25F36 -:10025000123A1722FE02F25F12114E1EC37E1219CD -:10026000014A1E3A0022B7C26D1201121E3A242220 -:10027000C604BBFA7712AF322422856F09EBAF3286 -:1002800036223E04CD2002366F3A1D22B7CA9F1295 -:100290003A0720B7C22C053E32324022C3E1143E59 -:1002A000013204223E05CD9E1B06041A7723130556 -:1002B000C2AB12AF321222D3043A1222FE04DAB7D2 -:1002C000123E08CD9E1B562B5E3E04CD9E1B462B38 -:1002D0004EEB09EB7323723E06CD9E1B462B4E2A36 -:1002E0000122235E2356EB09EB722B73237AFEF770 -:1002F000DA021336F7CD121321042235CAF014C3E3 -:100300000C13FED8D20C1336D8CD1213CDCC00C3AB -:10031000B3123E05CD9E1B7E2F5F237E2F57237E7B -:100320002F4F237E2F471303702B712B722B73C912 -:100330003A3722323622AF323122CD5D1C2A0020DC -:100340002201223A3922B7CABE13F33A0820F60135 -:10035000320820D306FBCDCC00CDFF1D21D83311B0 -:10036000EA0BCD5A0321D936111D0CCD5A033E0597 -:10037000320422D601C28713F33A0820E6FE32087F -:1003800020D306FBCDFF1D1120003E5A217B2C36C9 -:1003900000193DC28F13321222D3043A1222FE04F6 -:1003A000C2991321A60FCDAB1AAF321222D3043A51 -:1003B0001222FE04C2AD133A04223DC2701311DAB8 -:1003C0000C2A01227EFE00CACD1311B30C21D936AE -:1003D000CD5A032A01222200202A2822CDAA1BAFAF -:1003E000321222320422320A22323C222A2A22CD1E -:1003F000AA1B3A0422D601CA0614D3043A1222B721 -:10040000CAFA13C3D913320922CDCC00AF3212225B -:10041000CDC91BD3043A1222FE02DA13143A092280 -:10042000B7CA44143C320922FE06CA99142A26226D -:100430003A2B22BCFA4414C299143A2A22BDFA4437 -:1004400014C299142A0020234E2346EB2A2A222282 -:100450002622CDAA1B097CEBFE60DA6214FEF7DAD5 -:1004600064143EF677FED8D275143A0922B7C275E5 -:10047000143C3209222B7323234E2346EB2A2822D5 -:10048000CDAA1B09EB723E43BADA8D14773E95BEB6 -:10049000D29414772B73C309143A0A22B7C4D81B19 -:1004A0003A27222100FEBCFAB2143E01323922C39F -:1004B000FF112100F9BCF2BC142226222120203A8F -:1004C00003223DCADE143204223E05CDA8003600C8 -:1004D0003E0ACDA8003600233A0422C3C2141126D6 -:1004E000223E05CD200206041A77132305C2E81424 -:1004F0003E09CD9E1B36003E023225223E06CD200F -:10050000022F3C070707E638473A0920B032092096 -:10051000D3053E02322F22C328153A2E22473A2510 -:1005200022A8322E22CAE0153E02322E222120209D -:10053000AF3208223A03222201223204223E09CDA0 -:100540009E1BCA4E15FAC615320822C3C6153E05B3 -:10055000CD9E1B5F23567AB7F261152F577B2F5F15 -:1005600013234E234678B7F270152F47792F4F0388 -:100570003E05F57AE604C29E1578E604C29E15EBA8 -:1005800029EB606909444DF13DC272153E09CD9ECB -:100590001B3506042B360005C29415C3C615F12180 -:1005A00041107807070782CDA8007EF50F0F0F0FC7 -:1005B000E60F4F3E05CD5D1BF1E60F4F3E07CD5DCB -:1005C0001B3E013208223E10CD9E1B3A04223DC242 -:1005D00037153A0822B7C2E015CDFF1DC38011249C -:1005E0003A2522D3043207222120203A0322220175 -:1005F000223204223E09CD9E1BC26E163E0CCD0A4D -:100600001BFE0CD216163E07CD9E1B4F2346110033 -:10061000FF3E54C333163E0ECD0A1BFE99DA261652 -:10062000010001C32E16FE40D26E160100FF11001C -:10063000FF3E7CF53E033230223A0920F602D30514 -:100640003209203E0CCD9E1B732372237123702A26 -:1006500001224678D1D604CA5C16C60C8211090064 -:100660001936012B702B772BC610772B36003E10D6 -:10067000CD9E1B3A04223DC2EE152120203A0322D2 -:100680003204222201223DCAEF173209223E09CD4F -:100690009E1BE2E3172A0122320822AF320A223ED1 -:1006A00010CDA8002205223A0822473E09CDA11B01 -:1006B000E2D617A0C2D6172A052223234623234EAB -:1006C0002A012223237E9047322C22F2D7162F3C78 -:1006D000473E01320A2278FE09D2D617232356213B -:1006E0009310CDA8005E7A914F322D22F2FB162F87 -:1006F0003C4F3A0A22EE01320A2279FE09D2D6177D -:10070000219310CDA8007E83FE41D2D6173E07CD9F -:100710001F1B221022EB220E22483A2C22322D22BD -:100720003E05CD1F1BEB220C222A1022197CB7CAD2 -:100730003517F2E3173A092067F601D3053E403D2D -:10074000C23F177CD3052A0C2211811078CDE81AFC -:1007500022102278118A102A0E22CDE81AEB3E05CB -:10076000320B223A0A22B7CA71177B2F5F7A2F57B2 -:10077000132A102219221022EB2A05223A0B2222D8 -:100780000020CDA8007E83775F237E8A7757CD8BAC -:100790001B2A1022EB2A01222200203A0B22CD9E96 -:1007A0001B93775F237E9A7757CD8B1B3A0B22FEE4 -:1007B00007CAD6172A0E221181103E0890CDE81ADA -:1007C0002210223E07320B222A0C22118A1078CDE9 -:1007D000E81AEBC363172A05223A09223D3209229F -:1007E000C29B163E10CD9E1B3A04223DC380163A92 -:1007F00007223DC2E515D3043A25220F473A1222BB -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.bin deleted file mode 100644 index d20308fb..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex deleted file mode 100644 index 154a3344..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.g.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000005E5B4A4F55455552530E4F4445525B5E19 -:100010005B535049454C4552055B434F494E065B87 -:100020005049454345075B4D55454E5A45015301DF -:1000300053014E12494E534552545B5D5B4D4F5236 -:10004000455B434F494E154D455454455A5B454E0B -:10005000434F52455B5D5B50494543451F574552F1 -:1000600046454E5B534945305D5B574549544552C3 -:10007000455B4D55454E5A455B45494E0D544F5BCA -:1000800053544152545B47414D4512504F55525BBA -:100090004A4F5545525B415050555945521C4452A8 -:1000A0005545434B454E5B534945305D5B53504985 -:1000B000454C45525B4B4E4F504614505553485B90 -:1000C0005D5B504C415945525B425554544F4E0F65 -:1000D000424F55544F4E5B4A4F554555525B5D1745 -:1000E000554D5B4441535B535049454C5B5A555BFE -:1000F0005354415254454E154F525B494E5345524D -:10010000545B5D5B4D4F52455B434F494E184F5515 -:100110005B4D455454455A5B454E434F52455B5DDC -:100120005B5049454345244F4445525B5745524631 -:10013000454E5B534945305D5B57454954455245F3 -:100140005B4D55454E5A455B45494E164F525B49EE -:100150004E534552545B5E5B4D4F52455B434F4996 -:100160004E53124F555B4D455454455A5B5E5B50A0 -:100170004945434553244F4445525B5745524645F4 -:100180004E5B534945305E5B574549544552455B8C -:100190004D55454E5A455B45494E0D464F525B5EA7 -:1001A0005B504C41594552530D504F55525B5E5B6D -:1001B0004A4F5545525318465545525B5E5B535066 -:1001C00049454C45525B535049454C5B45494E0EA1 -:1001D000544F5B53544152545B47414D455B125061 -:1001E0004F55525B4A4F5545525B4150505559450A -:1001F000520E44525545434B454E5B5349455B5D5A -:100200002C505553485B5D5B504C415945525B4205 -:100210005554544F4E304F525B505553485B5E5BC4 -:10022000504C415945525B425554544F4E14424F25 -:1002300055544F4E5B4A4F554555525B5D5B4F558C -:100240005B5E0E4F4445525B5E5B535049454C45E7 -:10025000521E434F4D50555445525B57494C4C5BD1 -:10026000504C41593057484954455B5055434B53C6 -:100270001E434F4D50555445525B57494C4C5B50B3 -:100280004C41593057484954455B5055434B5327CF -:10029000434F4D50555445525B574952445B4D496D -:1002A00054305745495353454E5B5055434B535B70 -:1002B000535049454C454E1346495253545B53499C -:1002C00044455B544F5B53434F5245155052454D87 -:1002D0004945525B434F54455B44555B53434F5232 -:1002E0004511535049454C45525B4552524549438F -:1002F00048544532504F494E54535B4F5230484951 -:1003000047484553545B53434F524530414654454B -:10031000525B4C4153545B4652414D45305B5B5BF5 -:100320005B5B57494E5339504F494E54535B4F55C1 -:100330003053434F52455B4D4158494D554D304127 -:10034000505245535B4445524E494552455B494DD9 -:10035000414745305B5B5B5B5B4741474E414E54D9 -:100360003C50554E4B54455B4F44455230484F45E9 -:1003700043485354455B50554E4B545A41484C30BA -:100380004E4143485B4C45545A54454D5B5755527A -:1003900046305B5B5B5B474557494E4E540A544FB2 -:1003A0005B53454C4543545B0A544F5B53454C45A6 -:1003B00043545B125B5B5B574145484C455B535074 -:1003C00049454C4152541E0A4C4153545B465241DC -:1003D0004D450A4C4153545B4652414D450C4C45EA -:1003E000545A5445525B5755524604464F554C0497 -:1003F000464F554C04464F554C0B5B5B47414D45B2 -:100400005B4F5645520A5B5B5B5B46494E5B5B5BF1 -:100410000C5B5B5B535049454C454E44450B534880 -:100420004F4F545B414741494E0B53484F4F545B2C -:10043000414741494E0B53484F4F545B4147414957 -:100440004E08434F4D505554455208434F4D50555B -:1004500054455208434F4D50555445520647414D5F -:10046000455B5D0647414D455B5D0647414D455B3C -:100470005D0647414D455B5E0647414D455B5E0667 -:1004800047414D455B5E0E405B50524553535B42C6 -:100490005554544F4E0E405B50524553535B42559A -:1004A00054544F4E0E405B50524553535B4255548B -:1004B000544F4E0C52494748545B504C4159455299 -:1004C0000C52494748545B504C415945520C5249D3 -:1004D0004748545B504C415945520B4C4546545B80 -:1004E000504C415945520B4C4546545B504C415978 -:1004F00045520B4C4546545B504C415945520801FE -:10050000AF0D0801B70D0101AC0D0101AD0D0101E9 -:10051000AE0D1E013F0F31010E0F0C02C10D010285 -:10052000BF0D0602D90D0602E50D0602F10D060209 -:10053000FD0D0602090E0602150E0602210E060228 -:100540002D0E0602390E0602450E1002510E100243 -:10055000710E0801AE0E0801B60E0801BE0E0801AC -:10056000C60E0801CD0E0801D50E0801DD0E0801EA -:10057000E50E0801ED0E0801CD0E0701910E0701F1 -:10058000980E06019F0E0501A50E0401AA0E070193 -:10059000F50E0701FC0E0601030F0501090F04010A -:1005A000AA0E0601A60D18181818181801FF03182E -:1005B0007E7EFFFF7E7E181866669999666618FF34 -:1005C00003FE01FF0303030303FF03FE010000001A -:1005D000000003FF03FF030203FE01FF0303030305 -:1005E00003FF03FE0100000003FF03FF03020300FB -:1005F000001E033F0333033303F703E603EE01FF5B -:10060000033303330387038601FF03FF0330003006 -:10061000003F003F00E001F30333033303BF03BF98 -:1006200001E001F30333033303FF03FE010F003F37 -:1006300000FB00E30383030300EE01FF03330333F6 -:1006400003FF03EE01FE01FF03330333033F031EE9 -:1006500000C003C0033C3C3C3C3C3C3C3CC3C3C3EB -:10066000C3C3C3C3C33C3C3C3C3C3C3C3CC003C058 -:1006700003C003C003FC3FFC3FFC3FFC3FFFFFFF08 -:10068000FFFFFFFFFFFC3FFC3FFC3FFC3FC003C000 -:1006900003001866DBDB661800001866DB661800CE -:1006A000003CC3C33C00003CC33C000000FF1824D6 -:1006B0003C5A5A3C2418102838545438281018181A -:1006C00024242424181808081414140808080808F6 -:1006D0000808080808183C3C7E7E3C3C1810383856 -:1006E0007C7C38381018183C3C3C3C181808081C16 -:1006F0001C1C1C080800187EFFFF7E180000187ED6 -:10070000FF7E1800003CFFFF3C00003CFF3C010165 -:100710003F0101003F100C023F00212125253F0031 -:10072000003F100C023F003F2121213F000705053B -:10073000053F00070505053F00003F2121213F2718 -:10074000150D053F00003F2121213F000101050556 -:100750003F000000003F2121213F00003F3A0800F8 -:100760003200017C080E4200015C080E2B000107DC -:10077000080EAD000107081D4200015C081D2B009A -:100780000107081DAD00010708FF3200017C0C01C4 -:10079000320800200C01AD080020200F4208001E86 -:1007A000200F9D08001E08D84200015CFF082C4362 -:1007B00000015A082C2B000107082CAD000107305E -:1007C000102B0084022C1F2B008402282E2B008467 -:1007D00002FF083A5100013E083A2B000107083A8F -:1007E000AD00010708576000012008572B000107E2 -:1007F0000857AD000107081D6F01003A101E4402A2 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.bin deleted file mode 100644 index cf6b9c11..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex deleted file mode 100644 index 620300a5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/roms/shuffle.h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C328028400301133FBC97100009C3763A0 -:10001000F5E5D5C5CDAB043A12223C3212223A3373 -:10002000223D323322C246003A3222B7CA46003D50 -:10003000323222C246003A3D22B7C22C053C323D44 -:10004000223E1E323222210A20DB05479670CD68FF -:1000500000222A22210D20DB06479670CD6800225F -:100060002822C1D1E1F1FBC9B7FA7600FE21FA7D61 -:10007000003E21C37D00FEE0F27D003EE023470EFE -:10008000007E2F57237E2F5F13EB0906027CB7F209 -:100090009300371F677D1F6F05C28D00EB7B86774E -:1000A0005F2B7E8A77676BC9856FD024C9070707E6 -:1000B000072100201600E6F05F19C9D1E17E472331 -:1000C000E5D5CDAD00220020C9CDBB002A00204ED1 -:1000D00021FE0C79CDA8005E2356EB221221EB23E2 -:1000E0005E2356EB2210213E0FCD2002B71F323B7C -:1000F00022D20201060A11AB01CD26013A3B22E6CB -:1001000010C03A3B22060211AB01B7C211011160C7 -:1001100001CD26012A002023235E2323563E0ACD4B -:100120002002732372C9AFD30278CD2002E607D331 -:10013000013A1321215801CDA8006E260019EB2A9F -:100140001221D52DC24201CDF6012A12213E209462 -:100150004F06002A1021EBC93F362D241B1209003F -:100160001AD302DB01B67713231AD302DB01B67769 -:1001700013231AD302DB01B67713231AD302DB0150 -:10018000B67713231AD302DB01B67713231AD302EF -:10019000DB01B67713231AD302DB01B6771323AF43 -:1001A000D302DB01B67709AFD302C91AD302DB0150 -:1001B000AE7713231AD302DB01AE7723131AD302CF -:1001C000DB01AE7713231AD302DB01AE7713231AB8 -:1001D000D302DB01AE7713231AD302DB01AE771310 -:1001E000231AD302DB01AE771323AFD302DB01AEB8 -:1001F0007709AFD302C978CD20020F0F0FE61F5742 -:100200002378FE0ACA0802237E0F0F0F47E6E0B2EA -:100210005F78E61FC62457C9CDA8007E23666FC944 -:100220002A0020CDA8007EC9310024DB02E680CA66 -:100230007602AF323522323422323222320022327A -:100240003F22D3062100200620772305C24902322F -:100250002422FBC32C05000102030405060708093C -:100260000A0B0C0D0E0F100F0E0D0C0B0A090807D0 -:100270000605040302010601110000210020D30439 -:10028000707EA8CA8902CD3203237CFE40C27E0262 -:10029000D3042B7CFE1FCAAE027EA8CAA102CD32B7 -:1002A00003782F77AECA9002CD3203C39002D304F5 -:1002B000237CFE40CAC502782FAECAC002CD3203ED -:1002C000AF77C3AE02780747D27B027AB3CAF40293 -:1002D000EBF91100200600210000390E10AF29DAD9 -:1002E000E3022F12133E1812130DC2DD0205C2D70E -:1002F00002C32D03310024210C32E52100001142FC -:1003000003010004AF86D304230DC2050305C20513 -:10031000033CCA1F031AE3EBC5CD4A03C1EBE31349 -:100320007CFE20C20103E17DFE0CCA0000D304C3A1 -:100330002D034F7DE60179C23F03B257C34103B39A -:100340005FC94848474746464545D5E5EBCD890353 -:10035000CD9803E1D113C92A1E22EB3A3E224E2347 -:1003600006003DFA6A0309C35E03EB793DF8F51A0E -:1003700013D5FE30C27D03CD8907C38403CD890325 -:10038000CD980309D1F1C36C03EB21B603D64047E6 -:10039000070780CDA800EBC93E05F501E0FF091A6B -:1003A00077F13D09C8F513C39F03EB214204CD8FBC -:1003B00003CD980309C970605008047814161478A6 -:1003C0007E4A4A4A343C424242247E4242423C7E79 -:1003D000525252427E121202023C424252747E102B -:1003E00010107E42427E424232423E02027E181885 -:1003F00024427E404040407E0408047E7E04182053 -:100400007E3C4242423C7E1212120C3C4242225C32 -:100410007E1212324C244A5A522402027E02023EBA -:100420004040403E06186018063E4078403E422458 -:10043000182442060870080662725A4E46000000F0 -:1004400000003C4242423C40447E40407252525A7C -:100450004E425A5A5A7E0E08087E004E4A4A3200D0 -:100460007E4A4A7A004222120A063C5A5A5A3C04F0 -:100470000A0A0A7E36EB21D90DE60F0707470780E7 -:10048000CDA8000606AF121312137E1213237E129C -:1004900023E5211D0019EBE105C285043E08EB119F -:1004A0001F00702370193DC2A204C9217F3D3A0785 -:1004B00020CDAA032105207E4F17DAF804237EA75A -:1004C000CADD04352B3E8FB6773A0920F60432098F -:1004D00020D3053A0820F603320820D306DB04E6D1 -:1004E000014779E640CA18054FCD1805B9C823342D -:1004F00023343E01322022C9357EE60FCA1105D6CB -:1005000008C2DD043A0820E6FC320820D306C3DD29 -:10051000043E7FA677C3DD0421052078A7C2270506 -:100520003E40B677E640C93EBFA677C9F331002406 -:100530003A0820E6FE320820D306AF323222FB32E0 -:100540000920D305323A22323D223C321D22DB0201 -:10055000E630219B102323D610F25505221922DB09 -:1005600002E603FE03FA69053D323E22CDC010CDFE -:10057000191A3A0720B7C297053A0022EE01320055 -:1005800022CD6406CD7A06CD9706CDC4063A072063 -:10059000B7C22C05C3E9103A3F22320022CD6406CF -:1005A000CD7A06CD9706119D0BCD5703115C0C3A01 -:1005B0000022B7CAB90511710CCD5A03CD890711B4 -:1005C000860CCD5703CD8907CD8907AF3220223A5B -:1005D00007202A1922BED2E805113308CD5703CDD2 -:1005E0008907CDC406C32C0623BED21D06477E90C4 -:1005F000F5117C08CD5703CD890711BA08CD5703F3 -:10060000CD890711F708F13DCA0E06114B09CD57E8 -:1006100003CD8907119A09CD5703C32C0611CF09C1 -:10062000CD5703CD890711000ACD5A03D3043A20D0 -:1006300022B7C2A0053A3A2247DB042FE60E323A2F -:10064000224F782FA1CA2C06EE08C2F6063A0022E5 -:10065000EE01320022210F39221E22CDC010CD1909 -:100660001AC39D05215E0FCDAB1A21AD0F3A0022B2 -:10067000B7C2770621D20FC3AB1A210D2411160081 -:1006800006CB0E0A3600230DC284061905C2820667 -:10069000210E39221E22C9218E34115C0C3A00220F -:1006A000B7C2A70611710CCD5A03CD8907CD8907B2 -:1006B000C9F5CDAA03111808CD5A03F13DC8112D73 -:1006C00008C35A032A19227E2A1E22CDB10611A37D -:1006D00007CD5A03CD8907CD89072A19227E23BE6B -:1006E000CAF0067E2A1E22CDB10611C807C35A03DE -:1006F00011EF07C357032A19220E01E604CA0207A5 -:10070000230C3A072096FA2C063207207932212250 -:100710003DC22607CDC010210F39221E2211510AD9 -:10072000CD5A03CD9407CDC01021A5101108003A71 -:100730000022B7CA370719DB02E60CCA4507232394 -:10074000D604C23E077EF53D321822DB02E640CADF -:100750005407237E323222210F3911B70ACD5A03B2 -:10076000F121912FCD2E1A211539221E2211F30AC3 -:10077000CD5A03CD94073E20323722AF321D223EA0 -:1007800004320920D305C3D3102A1E220101000917 -:10079000221E22C9AF321222D3043A1222FEC0DA3C -:1007A0009807C90B5B5B5B5D5B504C415945520B35 -:1007B0005B5B5B5D5B4A4F554555520C5B5B5B5D1C -:1007C0005B535049454C45520C5B5B5B5E5B504C48 -:1007D00041594552530C5B5B5B5E5B4A4F55455537 -:1007E00052530C5B5B5B5E5B535049454C45520C6E -:1007F0004F525B5E5B504C41594552530C4F555B19 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Shuffleboard_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf deleted file mode 100644 index 215a8d81..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "Invaders2" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf deleted file mode 100644 index f7c9eea1..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.qsf +++ /dev/null @@ -1,173 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 13:13:10 June 05, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Invaders_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders2_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Invaders2_mist -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# --------------------------- -# start ENTITY(Invaders_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Invaders_mist) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Invaders2.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Release/Invaders2.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Release/Invaders2.rbf deleted file mode 100644 index a59a290f..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/Release/Invaders2.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv deleted file mode 100644 index 8cf901c0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/Invaders2_mist.sv +++ /dev/null @@ -1,211 +0,0 @@ -module Invaders2_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Space Inv.2;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_sys), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -invaders_memory invaders_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -invaders_video invaders_video ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_sys), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(1), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd deleted file mode 100644 index a509baa4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,271 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '1';--DIP(8); -- Unused ? - GDB0(1) <= '1';--DIP(7); - GDB0(2) <= '1';--DIP(6); -- Unused ? - GDB0(3) <= '1'; -- Unused ? - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= '1';--DIP(5); -- Unused ? - - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';-- Unused ? - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1';-- Unused ? - - GDB2(0) <= '1';--DIP(4); -- LSB Lives 3-6 - GDB2(1) <= '1';--DIP(3); -- MSB Lives 3-6 - GDB2(2) <= '0';-- Tilt ? - GDB2(3) <= '0';--DIP(2); -- Bonus life at 1000 or 1500 - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1';--DIP(1); -- Coin info - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv deleted file mode 100644 index 9ad7fe2a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_memory.sv +++ /dev/null @@ -1,104 +0,0 @@ - -module invaders_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - -sprom #( - .init_file("./roms/invad2ct.h.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/invad2ct.g.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/invad2ct.f.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/invad2ct.e.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -sprom #( - .init_file("./roms/invad2ct.b.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_b ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_4) - ); - -sprom #( - .init_file("./roms/invad2ct.a.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_a ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_5) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - - 5'b01010 : Rom_out = rom_data_4; - 5'b01011 : Rom_out = rom_data_5; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd deleted file mode 100644 index 77ac2478..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/invaders_video.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity invaders_video is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end invaders_video; - -architecture rtl of invaders_video is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= not HSync; - O_VSYNC <= not VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd deleted file mode 100644 index d65b9f9b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/pll.vhd +++ /dev/null @@ -1,350 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire4_bv(0 DOWNTO 0) <= "0"; - sub_wire4 <= To_stdlogicvector(sub_wire4_bv); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - sub_wire2 <= inclk0; - sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire3, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex deleted file mode 100644 index 38fd57d7..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.a.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000E5CDC40020E12323110722EB06047E2B5B -:100010002BE61FFE15CA49581ABEC24958231313AE -:100020001AC606BECA2A58D24358C618BEDA435862 -:10003000233E80B67778C6043203221B1B1B1BC3EA -:100040006058C91B1B23C34B582323232323230599 -:10005000C20E58C9F3BFF3BFF3BFF3BFF3BFFBBF7B -:100060002B2BCD551CC9F3BFF3BFF3BFF3BFFBBFB1 -:10007000000000E5D5C5CD3E1DCD811DC1D1E1C932 -:10008000CA8B187CFE01CC7058C37216F3BFF7BF41 -:100090002B7E12D513131313237E2BE61FFE143E63 -:1000A00000C2A6583EFD12D1C3F215BFF3BFF7BF81 -:1000B0003A0722E61FFE15C29A0A3A0B22E61FFEF5 -:1000C00015C29A0A3A3020FE16C29A0A3A0920C38B -:1000D0002E0AF3BFF3BFF3BFF3BFF3BFF3BFF7BF06 -:1000E0003A0F22E61FFE15C2100B3A1322E61FFE3E -:1000F00015C2100B3A6020FE16C2100B3A0920C33D -:10010000A40AFFFFFFFFFFFFFFFFFFFFFFFFFFFF4F -:10011000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF -:10012000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF1F -:10013000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF0F -:10014000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFFF -:10015000FFEFFFEFFFFFFFFFFFFFFFEFFFFFFFFFDF -:10016000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFDF -:10017000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFCF -:10018000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFBF -:10019000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFAF -:1001A000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF9F -:1001B000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF8F -:1001C000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF7F -:1001D000FFEFFFEFFFFFFFFFFFFFFFEFFFFFFFFF5F -:1001E000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF5F -:1001F000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF4F -:10020000A5EFFFEFFFFFFFFFFFEFFFEFFFFFFFFF98 -:10021000CA610FE5CD5B115EE10A83C3480FFFFFA2 -:100220001B1BAF12131306107DC38C1CFFFFFFFFB7 -:100230003AD821FE21C8210722C3C354FFFFFFFF84 -:10024000AF320B20211D37114F083E09CDA557268F -:10025000FFCD180BC39F57FFFFFFFFEFFFFFFFFF0F -:10026000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFDE -:10027000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFCE -:10028000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFBE -:10029000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFAE -:1002A000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF9E -:1002B000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF8E -:1002C000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF7E -:1002D000FFEFFFEFFFFFFFFFFFFFFFEFFFFFFFFF5E -:1002E000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF5E -:1002F000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF4E -:10030000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF3D -:10031000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF2D -:10032000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF1D -:10033000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF0D -:10034000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFFD -:10035000FFEFFFEFFFFFFFFFFFFFFFEFFFFFFFFFDD -:10036000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFDD -:10037000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFCD -:10038000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFBD -:10039000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFFAD -:1003A000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF9D -:1003B000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF8D -:1003C000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF7D -:1003D000FFEFFFEFFFFFFFFFFFFFFFEFFFFFFFFF5D -:1003E000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF5D -:1003F000FFEFFFEFFFFFFFFFFFEFFFEFFFFFFFFF4D -:10040000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC -:10041000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEC -:10042000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDC -:10043000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC -:10044000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBC -:10045000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAC -:10046000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C -:10047000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8C -:10048000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C -:10049000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6C -:1004A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C -:1004B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4C -:1004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C -:1004D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2C -:1004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C -:1004F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0C -:10050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB -:10051000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEB -:10052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB -:10053000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB -:10054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB -:10055000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAB -:10056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B -:10057000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8B -:10058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B -:10059000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6B -:1005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B -:1005B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4B -:1005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B -:1005D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2B -:1005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B -:1005F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0B -:10060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA -:10061000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA -:10062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA -:10063000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA -:10064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA -:10065000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA -:10066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A -:10067000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A -:10068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A -:10069000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A -:1006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A -:1006B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A -:1006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A -:1006D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A -:1006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A -:1006F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A -:10070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9 -:10071000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9 -:10072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9 -:10073000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9 -:10074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9 -:10075000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA9 -:10076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99 -:10077000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF89 -:10078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79 -:10079000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF69 -:1007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59 -:1007B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF49 -:1007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39 -:1007D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF29 -:1007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19 -:1007F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF09 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex deleted file mode 100644 index ec483fdc..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.b.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000002000000000000000100020000000004E7 -:100010000E0008003E000000FD000E00000000047D -:1000200016000000000000000000160000000004A0 -:1000300004000000000000000100040000000004B3 -:100040000F00F0003E00000000000F000000000460 -:100050001600000000000000000016000000000470 -:100060001500000000000000000015000000001353 -:10007000170000000000000000001700000000044E -:10008000780E781E782E783E784E785E786E787E80 -:10009000788E789E78AE680E681E682E683E684E30 -:1000A000685E686E687E688E689E68AE580E581EE0 -:1000B000582E583E584E585E586E587E588E589E50 -:1000C00058AE80AE809E808E807E806E805E804E38 -:1000D000803E802E801E800E90AE909E908E907EF0 -:1000E000906E905E904E903E902E901E900EA0AE20 -:1000F000A09EA08EA07EA06EA05EA04EA03EA02ED0 -:10010000A01EA00E0E019B520E011F520E01845123 -:100110000E0192510E01A0510E01AE510E01BC51C3 -:100120000E01CA510E01D8510E01E6510B01F351D7 -:100130000B01FE510B0109520B0114521501C35260 -:100140001501D8520F01ED520F01FC5203010C535F -:1001500003010F530601185306019B5228019B52BD -:1001600019021E5319025053210182531F01A35338 -:1001700001010B5301010B530301125303011553EA -:1001800016052D52000080617FD6F4F4D67F618081 -:100190000000000010607FDFF4F4DF7F60100000DB -:1001A000000018DCBC76DEDE76BCDC180000000047 -:1001B00098DCBC76DEDE76BCDC9800000000895B53 -:1001C0003E2C38382C3E5B890000000008183B6D3F -:1001D000B8A87D3B18080000000000F8B8749C9C8B -:1001E00074B8F8000000000080F838749C9C7438E3 -:1001F000F8800000003C7EDDF6DD7E3C0000000063 -:10020000BF7CD5E6D57CBF000000001856BA10BAF6 -:100210005618000000009856BA50BA5698000000D0 -:100220000000221400007700001422000008009152 -:10023000003C0600DA007EFE007C00BBFB003400C0 -:100240006F2F001C00BB2F001C007EFB0034003C05 -:10025000FE007C00000600DA0000080091000000AB -:100260000000000000000000001800000018DC0082 -:10027000F80056BC00B800BA7600740010DE009C8E -:1002800000BADE009C00567600740018BC00B8006E -:1002900000DC00F800001800000000000000000072 -:1002A000000000000000000000000000000000004E -:1002B000000000000000000000000000000000003E -:1002C000000000000000000C0E0E0E3E2CFE2C3E26 -:1002D0000E0E0E0C00000000000000003070707068 -:1002E0007C347F347C707070300000000000002A85 -:1002F00000401A984200280044100000812EC500DA -:10030000B845C243C2422598433085FF44AA112212 -:10031000558844FF1122FF8800AD7E7E7D00FF01DD -:10032000FF03FF07FF0FFF0FFF0FFF0FFF0FFF0F71 -:10033000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F4D -:10034000FF0FFF0FFF0FFF0FFF0FFF07FF03FF015F -:1003500080FFC0FFE0FFF0FFF0FFF0FFF0FFF0FFD5 -:10036000F0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FF15 -:10037000F0FFF0FFF0FFF0FFF0FFF0FFE0FFC0FF45 -:1003800080FF00000000000000101010103078FC0A -:100390009E9EF2F29E9EF2F29E9E7C3810101010ED -:1003A0000000000000000000000001021C9CD2F1CF -:1003B000F3F5D9911191D9F5F3F1D29C1C0201000A -:1003C0000000C3C157C680212C22773A242057FE53 -:1003D00004DAA9543A5420C60ABEDAED5396477A95 -:1003E000B8D2ED53210003222720C30F547AFEC355 -:1003F000D2B2543A5420C60A5FD6E02F3CBEDA0F80 -:10040000547B86477AB8DA0F542100FD2227203A20 -:100410002820A7C218543E01322820D53E023203BC -:1004200022110F221AE61FFE151B1BCA8A5421F93E -:10043000543A47223DCD92001ABECA4054D28A5443 -:100440000F0F0FE61F3D210155CD92003A28204F96 -:10045000A73A2420F25D54C60496C36754C60447E5 -:1004600079A778CA67548647C60E67131AB8DA8A1E -:1004700054BCD28A5479A7F28054210003C3835418 -:100480002100FD22272021E4213421032235CA97AF -:1004900054111322C324543AE421FE02D1C3B854A8 -:1004A000210000222720C3B854210003222720C3A3 -:1004B000B8542100FD2227203A5420CDEA54A7C089 -:1004C000C3305A1124200E60CD96573A0920E68099 -:1004D000C03A2420CDEA54A7003A4622A7C0210FF3 -:1004E000221154200E00CD9657C9D60E5FC627475D -:1004F0007AC60ABBD8B8D0AFC9081018202830383F -:1005000040000306090C0F1215E5D57BFE3B01D117 -:1005100021FA175501DC210AFE02CA2255FE04C247 -:100520007E557BFE3B111E202128223A2420FA3AD8 -:1005300055114E20212A223A5420F51AA7C24B55B4 -:10054000F1FE80DA4C553E0BC34D55F11A87E5217B -:100550008155CD92005E23560B0B0B0B0AC60BFE8A -:1005600012DA66553E1187218155CD92007E832790 -:100570004F237E8A2747E17123702BD1F1C9D1E146 -:10058000C90010000500045004000450030003508B -:10059000020002500100015000000400030002505C -:1005A00001000175003A4522A7CA03563A4422A722 -:1005B000C2DB553A0920E680F5CCC253F1CA035696 -:1005C0003A0920E640F5C4C253F1C20356DB0247A4 -:1005D000E620C2E45578E640C2F555210000222706 -:1005E00020C303563A2420FE04DADB552100FD2205 -:1005F0002720C303563A2420FEC3D2DB5521000333 -:100600002227203A4722A7CA7D563A4622A7C2553A -:10061000563A0920E680C247563A5420473A5820B5 -:10062000A7C229563E02325820FA385678FEC3DA5D -:100630007D562100FEC3415678FE04D27D5621002E -:1006400002225720C37D56DB0147E620C25E567862 -:10065000E640C26F56210000225720C37D563A540F -:1006600020FE04DA55562100FD225720C37D563A5C -:100670005420FEC3D255562100032257203A45226A -:10068000A7CA9156212A2011442206020E0ECDA49B -:10069000563A4722A7C8215A2011462206050E0FB6 -:1006A000CDA456C97EFE16CAFA561AA7CC0C57C856 -:1006B0007EFE103610C2BA5636111A3D12C2F656D8 -:1006C0003616131AFE80C2CB56AF12A7CAD0563DBB -:1006D000121B3E60122B2B3600C5CD9957CD9C576F -:1006E0003A4522473A0920E640CAEE5606003A4704 -:1006F00022B0C1CA405ACD0C57C91AA7C83D12C072 -:10070000131AA7C8713EFA856F3603C9F57832020D -:1007100020CD9800220020CDC40020F1C921102056 -:10072000361F2323368023233690211A20361FCDEF -:10073000C40001AF320B200E10211032E5CDA257BC -:10074000E12323E50E20CDA257E123230E30CDA2D5 -:100750005721102F117E573E06E5D5F5CDA557F14F -:10076000D1E12323E5D5F5CDA557F1D1E12323CD63 -:10077000A557210E391184573E11CDA557C9504FA9 -:10078000494E545353504143455B494E56414445AD -:1007900052535B494946C3D011C3D41DC3EB1DC39B -:1007A0001A09C34305C34D040A09434D5009420DBC -:1007B000FABB573A0920E640C2EF1C7E8127C3E905 -:1007C0001C3A54228787878787473AD82190C3C528 -:1007D00053233E80B6777AC604320322606923E54C -:1007E000CDE51BE1D1C36B0F3A0220F5CDC4000764 -:1007F000F1320220C3261C093B4D4F53430D0A0919 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex deleted file mode 100644 index 84ee5864..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.e.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000078A7C00EAAC93A0220E6010601CA16184E -:10001000CD7A1FC31918CD871FC93A0220E6012ADD -:100020002B20C228182A5B20C97EFE08F23218064F -:1000300000C9FE08C23A180601C91AFE01F24318A7 -:100040000600C97EFE09C24C180604C9FE0AC25445 -:10005000180605C91AFE02F25D180600C97ED60B05 -:1000600087C60347C93A0220CD9800220020C3006A -:100070005820C93A0220E6013E06211B20C28518FD -:100080003E08214B2032E621C3A0183A0220E601A7 -:100090003E0A211B20C29D183E0C214B2032E62136 -:1000A0001ABEFA0517C1C50AFE16C21D193A02206A -:1000B000E601F5CABA18782F3C47F13E80CAC2184B -:1000C0003E78C1C503030203033E0702030303D5C1 -:1000D0001B1B1B1B1AD605FADB18AF2F3C8711130D -:1000E0001ACD3D111A0203131A02D103033A02205A -:1000F000E6013E1ACAF9183E1902C1C50203030AF5 -:10010000CA0919327B20C30C19327C200601CA1798 -:1001100019CD521FC31A19CD5C1FC32E190AFE1028 -:10012000CA2819FE11C22E191A3C77C3FB192323C2 -:10013000237EA7C25C19C5E53A0220E6012A2D20DC -:10014000C246192A5D207EFE0AD24E193E0AD60406 -:10015000F25419AF32E321E1C1C366192BD5562BF6 -:100160005E131AD1232303030303C610D5570ABA1B -:10017000D1DA05177EA7C29F192BD5562B5E3A02FE -:1001800020E601CA8C193A7B20C38F193A7C2012D1 -:10019000133AE32112133AE62112D123C3CD192BCE -:1001A000D5562B5EE5D5E13A0220E601CAB5192302 -:1001B0002323C3B8192B2B2B1A7713231AC61077B6 -:1001C000233AE621772B2BEBE1732372D1D51B1B4E -:1001D0001B1B1A3C123E0ACD3D111A3C12D1237E44 -:1001E0003C77C1C50AFE16CAF0197EFE0BC2051780 -:1001F0002B2B2B1A3C77FE03C20517233A0220E66D -:1002000001118120C20A1A1144217323722336007E -:10021000C3051780028003000480048005FAE5D539 -:10022000C5CD281AC1D1E1C9237EE61FFE14C83E00 -:1002300080B6772B2B7EFE80D2B41A3A4E22070767 -:10024000070747C618BEDAAB1A78C607BEDA541AD3 -:10025000CD481CC9E5CD3B1BE13A0322FE07F03A2D -:100260004422A7C03A2020A7C8233A2420C6FEBEB5 -:10027000D0C613BED83A4522A7C83E043244223E17 -:10028000A0322F223E10322A200604CD521F3E10EB -:100290003235223A0322FE05F8FE07F021472234C8 -:1002A0000610CD5C1F3E20323D22C9E5CD3B1BE14F -:1002B000CD481CC9FE80DA371B3A532207070707CF -:1002C0002F3C47C6E6BED22E1B78C6F9BED2D41A42 -:1002D000CD481CC9E5CD3B1BE13A0322FE05C8FE13 -:1002E00006C83A4622A7C03A5020A7C8233A54204D -:1002F000C6FEBED0C613BED83A4722A7C83E0432B7 -:1003000046223EA03230223E10325A200604CD5CF6 -:100310001F3E10323B223A0322FE05F8FE07F82169 -:100320004522340610CD521F3E20323722C9E5CD7A -:100330003B1BE1CD481CC9CD481CC9AF32ED213A69 -:100340000322FE05F8477EE6F84F78FE07FA541BB5 -:100350003E00814F3E2132E421118320EB060A7ECC -:10036000E61F79C2801B233AE421D60332E42179C7 -:100370002323C25F1B3E2132E42105C879C35F1BE2 -:100380002B2BBE2323CAB71B4F3AE421CD92003E4C -:100390002132E4217905C25F1B3AED21A7C03C322E -:1003A000ED211AE6F84F3A0322FE07F2B21B3E0097 -:1003B000814FEBC3541BC93AE421472B131A96DA39 -:1003C000C71BFE0EDAD11B232323050505C2BD1B67 -:1003D000C9237EE680C07EE61FCAE11BFE01C2E59E -:1003E0001B2BC3C71BC50E10FE06FAF61B0E20FE04 -:1003F0000AFAF61B0E300600CDCD1CC12B2B117056 -:1004000020EB360123231A772323131A772323366D -:1004100000232323233E0113127723232323233690 -:1004200004E5C3E85707E136133A0322FE05F8FE58 -:10043000070608FA3F1CCD521F3E05323822C9CDAF -:100440005C1F3E05323E22C9113020CD551C116083 -:1004500020CD551CC91AFE16C83A0322FE05F81312 -:10046000131AD60247C6094F7EB8D8B9D023131342 -:100470001A3DBED0C621BED83E09CD3D111AA7C037 -:100480003E04121B1B1B3E1012C3205AFE0BF2A48B -:100490001C3E10323622325B22CD701F0601CD7A0F -:1004A0001FC3B11C3E10323C22CD661F0601CD8712 -:1004B0001F2A2622CDED1F7BFE3BF2C31C222B20E0 -:1004C000C3C61C225B204E2346CDCD1CC93A092051 -:1004D000E680C83A0322FE05F8FE07E5F5214B2227 -:1004E000F2E61C215022C3B05777237E882777DBA2 -:1004F00002173E14DAF91C3E19BED2351D237EA721 -:10050000C2351D343A0322FE07214522F2121D2175 -:100510004722347E7DFE450610C22A1DCD521F3E65 -:1005200020323722CDD41DC3351DCD5C1F3E203275 -:100530003D22CDEB1DF1F43E1DFC811DE1C93A09C0 -:1005400020E640C0DB02E608CA621D3E01320B20F5 -:100550003A4C224F21E93ECD43053A4B224FCD4341 -:1005600005C93E02320B203A4B220F0F0F0F4F21CD -:10057000E93ECD43053A4C220F0F0F0F4FCD4305F7 -:10058000C93E01320B203A51224F21F33ECD4305A3 -:100590003A50224FCD4305C9C901320B203A4A22B5 -:1005A0004F21EE3ECD43053A49224FCD4305C92A9E -:1005B0004922EB2A4B22CDC41D2A4922EB2A502284 -:1005C000CDC41DC97ABCDAD01DC07BBDDAD01DC92F -:1005D000224922C9210B203601DB02E608C2E11DB7 -:1005E0003421E23E3A4522CDFA1DC921F93E3E01B1 -:1005F000320B203A4722CDFA1DC947878011311EA0 -:10060000CD3D1106033A0B20FE02CA1C1EC5D51AA9 -:100610004FCD4305D1C11305C20D1EC91313C5D556 -:100620001A0F0F0F0F4FCD4305D1C11B05C21E1E60 -:10063000C90AAAAA1AAAAA2ABAAA3ABBAA4ABBBA39 -:100640005ABBBB6ABBBB7ABBBB8ABBBB9ABBBB10EA -:10065000BBBB3A4422A7C03A0920E640C001CD21E5 -:10066000113922214022CD961EF1A7C8C5060FCD13 -:10067000A11FC1CD701FC93A4622A7C001D82111C0 -:100680003F22214222CD961EF1A7C8C5060FCD9468 -:100690001FC1CD661FC91AA7CA9D1EFE01CAA21E90 -:1006A0002600225922E3E5C00AF52A59224E2346A4 -:1006B0000AFEFFC2BA1E01D11EAF03702B7147F1B3 -:1006C000A787C6024F78A7CACE1E3E0212C979126A -:1006D000C901010101000202020200040404000831 -:1006E0000808FF2A26222323237EFE05C2F21E21AC -:1006F000F81E2B222622C9500000015001000200E2 -:10070000030005213422113A1F0E0CD5CD181F23EA -:10071000D113130DC20B1FC97EA7C8FE01C2381F1B -:10072000EB7E234623EBFE01CA7A1FFE03CA871F16 -:10073000FE05CA941FC3A11F35C901020104071099 -:1007400001100108070F030203040510031003083A -:10075000050F3A3122B0323122D301C93A2522B0F5 -:10076000322522D303C93A3222B0323222D305C90C -:100770003A3322B0323322D307C9782F473A312295 -:10078000A0323122D301C9782F473A2522A0322541 -:1007900022D303C9782F473A3222A0323222D3051E -:1007A000C9782F473A3322A0323322D307C9DB015D -:1007B0002FE631C0AF320B202A5D227DB4CAC41FA0 -:1007C0002B225D22C0219D3F11D11F3E19CD4D042A -:1007D000C942595B4A4F454C5B4B52454745525BBA -:1007E000464F525B4D4944574159C3A555C309551E -:1007F000C31D57414C462D57415920504F494E5427 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex deleted file mode 100644 index cf20ae03..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.f.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C32C0F7EA7C20A103601232334E10B0B49 -:1000100022E421CD4D1122002023230A772323033C -:100020000A7722E621032A00200AE61F77FE01C292 -:100030003C10AFCD42111A3D12C34B100AE601CA63 -:1000400048100A3D02C34B100A3C023E0ACD920002 -:100050000AE61F772AE4212B7EA7CA77102AE62119 -:1000600023233ACC21A73604C26D1036FC3E09CDBD -:1000700092003605C385102AE621232336003E0967 -:10008000CD92003604D5C53ACC21A7F5CC4212F169 -:10009000C47412CDC40020CDC40020C1D10B2AE607 -:1000A000217E022B2B0B7E02032AE4210AFE08D2BA -:1000B000C8102B7EA7C2E010D53E05CD3D113E02F3 -:1000C00012D1CD2511C3E010FECADAE0102B7EA7B5 -:1000D000C2E010D53E05CD3D113EFE12D1CD251119 -:1000E000131AA7C83D12C01313131A3C123ACC219D -:1000F000A73A4E22CAFA103A532287D60A2F3C4713 -:10010000D5131313131AD60BFA10110404C30611D6 -:10011000D11AB8F83ACC213C3C473AF821B032F831 -:1001200021CD440EC9E5212D203ACC21A7CA331197 -:10013000215D20712370E1C9814FD004C9835FD054 -:1001400014C9E5F50AE6E06FF1B502E1C93ACC2140 -:10015000211020A7CA5A11214020C93ACC212118C8 -:1001600020A7CA6811214820C93A0920E640C2A444 -:1001700011DB022FE610CA7F1132F921C3A4113A14 -:10018000F921A7CAA4113A2020FE16CAA4113A45A3 -:1001900022A7CAA411AF32F9212107221124200E6F -:1001A00060CDD011DB012FE610CAB01132FE21C99B -:1001B0003AFE21A7C83A5020FE16C83A4722A7C8DF -:1001C000AF32FE21210F221154200E00CDD011C9D3 -:1001D0007EE61FFE15CAEB11E5CD2C12E13E04CDE3 -:1001E00092007EE61FFE15C0C30012E523232323E1 -:1001F0007EE61FFE15C2FC11E1C30012CD2C12E1F8 -:10020000361B79B6772B1AC60A772B1B1B1A772B4E -:10021000360006027DFE0AF22312CD521F3E08323E -:100220003422C9CD5C1F3E08323A22C92B2B7EFEF8 -:1002300080F579A7CA3C12F1D0F1F1C9F1D8F1F1FA -:10024000C9943A0920E640C03A4522A7C8212F2286 -:100250007EA7CA571235C911FB1321EA21060ECD1C -:10026000F00D11FA212AFC210124203E01327E20CA -:10027000CDA012C93A4722A7C82130227EA7CA833F -:100280001235C911091421EA21060ECDF00D11FF16 -:10029000212A01220154203E01327E20CDA012C924 -:1002A0001AD5FE01D2BB12E52AF6213600237EA71D -:1002B000CAB41235E1C25113C30513E52AEF217EFA -:1002C000E1E61FFE15C2CA12AF123AF221C60B3286 -:1002D000F2213E01327E20131AFE01DAF112E52AE4 -:1002E000EF21232323237EE1E61FFE15C25113AF26 -:1002F00012E52AF6217EA7CAFB1235C20113233666 -:1003000000E1C251132B2B7E2BE61FFE02DA3813BD -:10031000CD3814C5477EC6064F78D604B9D23713F8 -:10032000C611B9DA37131A3C12C1D1473A7E20B848 -:10033000CA5613CD1714C9C1D113137D12137C12E1 -:100340001BEBE5D52AEC21197DB4D1E1EBCC1914D6 -:10035000C9D1CD1714C9EBE5D52AEC21197DB4D14B -:10036000E1EBE5CC1714E1E52AEF21444DE10AE683 -:100370001FFE15CA8013030303030AE61FFE15C000 -:10038000D5C5EB2AEC2119EB2322EC213E210605F1 -:10039000BBCA9713D2A013C62105C29013C3B513CD -:1003A00005CAB5133E21CD92007EFE02DAA01322CB -:1003B000EC21C3A0132AEC212BC1D1C579E604CAD4 -:1003C000C91303030303C3CD130B0B0B0B0AE61F67 -:1003D000FE15CAE6130B0A3CBEDAE613D60EBED2F1 -:1003E000E613C1C3F713C13AF221027EC6060B021F -:1003F0002B3AEE21860B02CD1714C927217EDFF898 -:100400001722003208CD215522CC21D9DE081F2227 -:100410000852F1D82157221313F52AF4213E08CDB2 -:1004200092007E2F4F06FF032AEA21090909EB7388 -:100430002372EB1B1B1BF1C9E52AF4217E2E00FE63 -:1004400002FA54142E03FE0CFA54142E06FE17FA68 -:1004500054142E097D211A15CD92003A4822BEDA95 -:100460009014E12B0B0B0A96F26D142F3CD6080367 -:100470000323D5C5A71F57030303030AA7C282148A -:1004800016000AA77AF28A142F3C57C10A82D1C9F2 -:1004900023BEDA1015E10ABEDAB0143AEE21A7F253 -:1004A000A914CDC5140033DEC9CDC5140180DFC940 -:1004B0003AEE21A7F2BE14CDC51401DBDEC9CDC5CD -:1004C0001400D8DEC9EBE3EBC523444DE51AA7C2FF -:1004D000D814232323C3DB142B2B2BC5131A4F1340 -:1004E0001A471B1BE50978B1E1C1CA04152B2B0B78 -:1004F0000B0A0303BE2323C204157EA7CACD1444EE -:100500004DC3CD140B0AE1C1131313EBE3EB2BC95D -:1005100023BEE1DA18150AC97EC9FFFFFFFF80007C -:100520008020004020003E083203222107227EE680 -:100530001FFE15CAA31532EC21FE14C26A153E1522 -:10054000773A0322472F3C4F78FE05F26415FE03ED -:10055000FA59153E0481C35C153E078101FA21CD8D -:100560003811AF02CDB215C39815FE14F27B15FEFB -:10057000130612CA78150613C38715D61B11391630 -:10058000CD3D111AC61B477EE6E0B077E680CA98DB -:100590001506147EE660B0777EE61FFE15CAA31529 -:1005A000CDB215232323233A03223D320322C22E48 -:1005B00015C9E53A0322117A207EE61F121B1B1B88 -:1005C0001BFE14C2CC15010000C3E915FE15C2D7ED -:1005D00015010000C3E9157EE660070707E5213134 -:1005E0001687CD92004E2346E178121B79121BC369 -:1005F00090581B1B2B7E121B2B7E121B3AEC2112D8 -:1006000013E5D5CDC40007D1E11A7713231A77F586 -:100610001313231A773A7422A7C41E1AF1FE04DAC0 -:100620002A16FEF7D22A16C32F16237EF68077E10C -:10063000C900F800FC000400080100030211D121E8 -:100640000130202A3B203E03CD5B16C911DC21017D -:1006500060202A6B203E06CD5B16C93202201AFEAE -:1006600002F8C5FE02CA7318FE04F26F16C1C9C3B0 -:1006700080587DB4CA8C162B3A0220E601CA861631 -:10068000223B20C38916226B20C305170AFE16C21F -:100690000517C5D53A0220E60121D121114E22C20B -:1006A000A81621DC21115322F5CD291878878787D8 -:1006B00047F1F5CABC163E7890C3BF163E808067EE -:1006C000E6082E10CAC9162EC8F1D1C1F503037C65 -:1006D0000203037D020303037DE608218002CAE4CE -:1006E000162180FD7D02037C020303F13E1ACAF34A -:1006F000163E1902C1C5020601CA0217CD521FC318 -:100700000517CD5C1F3A0220E601213E20C21317D7 -:10071000216E207EA7CA201735C22017C1C36518D5 -:100720002B2B2BC10AFE16C8030303030AFE07DAAC -:100730003A17FED0D23A17C34D173E06CD38113EB8 -:100740001602CD06183600233601C3651823237E12 -:10075000A7CA65183E06CD38110AFE103E11CA63BD -:10076000173E100235C265183E16020B0BAF020B86 -:10077000022B2B36002336013A0220E601213020DD -:10078000013E20C28C17216020016E203E16773E6C -:100790001902220020CDF802210003193A5B22A79A -:1007A000CAAA17DB02E608CACC17AF320B20E5CD88 -:1007B0001A1823CDF417E1CD4305E5CD1A184EE103 -:1007C000CD43050EAACD4305CD0618C9AF325B2235 -:1007D0003EFF320B20E5CD1A187E0F0F0F0F4FE1B1 -:1007E000CD4305E5CD1A1823CDF417790F0F0F0F60 -:1007F0004FC3BF177E4FE6F0C07EE60F47C6A04F3F -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex deleted file mode 100644 index 63b4648e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.g.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000005B504C415945525B425554544F4E494EFA -:10001000534552545B434F494E494E534552545BEE -:100020005C5B4D4F52455B434F494E494E534552E1 -:10003000545B5D5B4D4F52455B434F494E53464FBA -:10004000525B5D5B504C415945525B47414D4547C2 -:10005000414D455B4F5645525C5B4F525B5D5B507B -:100060004C41594552535553455B52494748545B9F -:10007000534944455B434F4E54524F4C535B4D499B -:10008000445741595B4D46475E5B434F5E5BDB0126 -:10009000E606FE0447C5CAB708FE02CAE008C1CD9D -:1000A000AE1F3A0720F5CD6200F1473A072090D302 -:1000B00006CA8E08C3AD063A0820D601C178FA9F59 -:1000C000083A0920F64021F408320920DB02E60351 -:1000D00016005F19463A072080320720D1C3C809AD -:1000E0003A0820D602C1FA9F083A0920E6BF21F853 -:1000F00008C3C908FFFFFEFEFEFFFCFE4F57204667 -:10010000AF3207203E0A320520210000224B222276 -:1001100050222249223E55324822AFD303322522B3 -:10012000D301323122CDAF1D21F71E22262231000C -:10013000243E03324522324722325E22AF3209206A -:10014000324E22210000224E22225322CD300BCDEE -:10015000EA0CCD981DCD300B3E0F32F82121000363 -:100160002260223EFD325820CD6200CDD20ECDA5B8 -:1001700006CD2615CDEA1FCD220BD3063A452247E0 -:100180003A4722B0CA2509CDBE09C268092100013B -:10019000226022CD300BCDEA0C2109203E20B6771B -:1001A000CDA506CDF01FCD6200D306CDBE09C2A0FD -:1001B000092109203EFDA677C32509C368092A60E5 -:1001C000222B2260227CB5C931002406803A092006 -:1001D000B0320920210000224B2222502221F71E9A -:1001E0002226223E03324522324722AF324D2232AE -:1001F0005222325C22324E22325322CD300BCDEAD3 -:100200000CCD300B32F821D306CD6200CD6200CD8B -:10021000D20ECDEA1FCD6911CD2615CD3D16CD4CA0 -:1002200016CD220B3ACD21A7C29A0AC3B058E64098 -:10023000C29A0A3AD121FE02F2690A0100103E0870 -:10024000CDD91C210010222822212822222B203E39 -:1002500003320220325B223E403232203E6E323484 -:1002600020CD78172640CD180B214E227EFE02CAE3 -:10027000730A34237EC6012777CDF10CCD6F0B11A5 -:1002800045221AA7C29A0A215C227EE601C29A0A76 -:1002900034EB3421F8213EFDA6773AD821A7C210CD -:1002A0000BC3E058E640C2DC0A3ADC21FE02F2DC75 -:1002B0000A0100103E06CDD91C210010222A22215D -:1002C0002A22225B203E063202203EC03262203EBD -:1002D0006E326420CD78172640CD180B2153227E34 -:1002E000FE02CAE60A34237EC6012777CD470DCD2C -:1002F000DF0B1147221AA7C2100B215C227EE610E9 -:10030000C2100B3E10B677EB3421F8213EF2A677EF -:10031000D306CDE31EC3090AD306CD620025C8C3A8 -:10032000180BA73A482217D22C0BEE2B324822C9C1 -:10033000CD3A0BCD6F0BCDDF0BC9AF320B2032CCDA -:100340002132032232E32132F821322422322522C3 -:10035000322E22322D2221F71E22262221D11E22C8 -:100360004022224222017020117F20CD1204C901B7 -:10037000F92111FD21CD120401CD2111D721CD127A -:10038000043E40322F220630211020110050CDF0C3 -:100390000D21CD2136213A0920E640CAA00B3600B6 -:1003A00021A220221C20CD4B0CAF32CC21CD980CA9 -:1003B000AF3244223A4E22070707072122208677D0 -:1003C000013422113922CD12043A0920E680CAD81C -:1003D0000B3E20323122D301AFD307323322C90181 -:1003E000FE21110222CD120401D82111E221CD12E9 -:1003F000043E403230220640214020113050CDF0E2 -:100400000D21D8213621216521224C20CD7A0C3EA8 -:100410000B32CC21CD980CAF32CC213246223A534C -:1004200022070707072F3C2152208677013A221125 -:100430003F22CD12043A0920E680CA440C3E203205 -:100440002522D303AFD305323222C921805011C3F4 -:10045000200621CD6E0ECD5A0CC93A0920E6400E79 -:1004600000118320CA700CAF0637CD930EC3730CF6 -:10047000CD7C0ECD9C0ECDAA0EC921C25011682193 -:100480000621CD6E0ECD890CC90E02112821CD7C1E -:100490000ECDA30ECDB70EC9E5D5F511CF2121267E -:1004A0002101D6213ACC21A7CAB40C21CB2111DAE3 -:1004B0002101E121AF020B0B02030A0B0B022F4FAC -:1004C00006FF03090909EB7323723A0920E680CA83 -:1004D000DC0C3ACC21A7CC3D16C44C163ACC21C634 -:1004E00001E607320220F1D1E1C9CDF10CCD470D73 -:1004F000C901002411DF3FCDA60DCDD20D3E04323F -:10050000E4212110201170500610CDF00D3A4E223A -:10051000070707074711330EDB02E608F53E00C266 -:10052000230D3D320B20AF32E6213A4F22C6012780 -:10053000CD9B0DF1C23D0D790F0F0F0F4FCDF90D72 -:10054000CD3E1DCDD41DC901102411DF3FCDA60D18 -:10055000CDDB0D3E0432E421214020117050061005 -:10056000CDF00D2110207EFE18CA730D3E187721A4 -:100570001A2077113B0E3A5322070707072F3C47F3 -:10058000AF320B203C32E6213A5422C60127CD9BE4 -:100590000DCDF90DCD811DCDEB1DC94FE6F0C2A5E6 -:1005A0000D3EA0B14FC97B916F7A986723EB6960CC -:1005B00006107AB3C836001B2305C2B20D06103EE2 -:1005C00010CD92007AB3C87BD6105F7ADE0057C395 -:1005D000B20D2100243E10CDE40DC9211F243E0898 -:1005E000CDE40DC911200006DE771905C2E90DC959 -:1005F0001A77132305C2F00DC92112201A80771330 -:1006000023231A7713D5C5CDC40001C1C53E0132DD -:100610005F22CDF802218001193AE621CD9200CD6A -:100620004305AF325F22C1D13AE4213D32E421C219 -:10063000F90DC91C101C461C7C1CB2DC10DC46DC0D -:100640007CDCB2663AF82147FE02CA550EFE0DCA9E -:10065000640EFE0FC0CD751ACA600E3E8032452270 -:1006600078FE0FC0CDF81AC83E80324722C97E12EC -:1006700023137E1223131305C26E0EC9AF0616CDC7 -:10068000930E3E0681060BCD930E3E02810616CDDB -:10069000930EC91213131305C2930EC921272122E9 -:1006A000FC21C921CC21220122C9210722CDC40E5F -:1006B000211722CDC40EC9210F22CDC40E211F2225 -:1006C000CDC40EC906023E15772323232305C2C8D5 -:1006D0000EC9AF32CC213E0232242221CD213ACCA8 -:1006E00021CD9200E5D12323E52323232322E821F2 -:1006F000E13ACC21C601E6073202203ACC21A7011B -:100700004422CA080F0146220AA7CA130F030AA7E8 -:10071000C2160FCD290F3ACC21EE0B32CC213A2450 -:10072000223D322422C2DB0EC91AA7C8E54E234659 -:100730000B0AFE02FA6B0F0BD521072216047E2B43 -:10074000E61FFE15C3105A0ABECA4F0FD2610FC66C -:100750000EBEDA610F2B0B0ABE0323C2610FC3D199 -:1007600057232323232315C23E0FD12AE8217E3CA1 -:1007700077FE38E1CC980CC2CE0FE53ACC21A7C267 -:10078000A90F3ACD2121D7217721D2217EA747CAAF -:10079000CD0F36003AF821E602C2A20F21CD217E0C -:1007A000237721182070C3CD0F3AD82121E2217779 -:1007B00021DD217EA747CACD0F36003AF821E60C8D -:1007C000C2C90F21D8217E237721482070E1E52A74 -:1007D000E8217E2323BEE1CA2C0F4E23460B0B0BD0 -:1007E000702B7103030AE61FE52AE82123C20310D8 -:1007F0007EA723C2F70F3423237E2BBECA730FE1DB -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex deleted file mode 100644 index 1ffa200a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/roms/invad2ct.h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000003E00327B22C32503F53E01327A22F1C93C -:10001000F53E02327A223A8E223C328E22F1C327FA -:1000200000F1CD7800FBC9228C22E1E5E5F5E1E3A2 -:10003000D5C5116EFF197CA7F5CD031FCD521ECD7E -:10004000771ECD3B06F1FA5100C1D1F12A8C22FB7B -:10005000C9C1D1F12A8C22C321003E01327B22C3C7 -:1000600088003A8E22FE02DA6F00AF328E22C9AFCC -:10007000328E223E02C35C003A7B22FE00CA8C0014 -:10008000473A7A22B8CA8C00FBC388003E00327B14 -:1000900022C9856FD024C9BA070707075F2100204E -:1000A000E60F577BE6F05F19C9D1E17E4723E5D51E -:1000B000E6E0CAB9003A02204778320220CD980023 -:1000C000220020C9CDA9002A00207E87874F210465 -:1000D0005179CD920056235EEB227522EB235E23ED -:1000E000563E0FCD1D03320320EB2270223A8B22A5 -:1000F000FE01CA2601AF3274223A0320E601CA107B -:100100000106063A0320E602CA0D010604CD6A0183 -:100110003E0ACD1D032A00204EB9CA2A0177218B41 -:10012000223601C3C700AF328B223A0320E640C219 -:100130005201210000392277222A002023F3F9C13D -:10014000D1E109444DE1193B3B3B3BE5C52A772210 -:10015000F9FB06023A03204FE604C2660179060065 -:10016000E610C26601C9CD6A01C9AFD3042A0020D6 -:1001700023237EE607D3027821AB01CD1503EB786C -:1001800007072A75228521B301CD92006E2600193A -:10019000545D2A7522D525C29501CDF8022A752213 -:1001A0003E20954F06002A7022EBC9D301540275F8 -:1001B00002C8026C5A4836241200001C1814100C95 -:1001C000080400463C32281E140A002A241E181275 -:1001D0000C06001AD304DB03A6CADF01327422DB4B -:1001E00003AE7723131AD304DB03A6CAF1013274DA -:1001F00022DB03AE7723131AD304DB03A6CA030260 -:10020000327422DB03AE7723131AD304DB03A6CAAE -:100210001502327422DB03AE7723131AD304DB03F7 -:10022000A6CA2702327422DB03AE7723131AD30443 -:10023000DB03A6CA3902327422DB03B6772313AF7D -:10024000D304DB03A6CA4B02327422DB03AE770968 -:10025000AFD304C91A7713231A7713231A771323FA -:100260001A7713231A7713231A7713231A77132372 -:10027000AFB67709C9CD6F00C30C04A67713231A54 -:10028000D304DB032FA67723231AD304DB032FA683 -:100290007713231AD304DB032FA67713231AD3046F -:1002A000DB032FA67713231AD304DB032FA67713C0 -:1002B000231AD304DB032FA6771323AFD304DB0366 -:1002C0002FA67709AFD304C91A2FA67713231A2FA5 -:1002D000A67713231A2FA67713231A2FA677132393 -:1002E0001A2FA67713231A2FA67713231A2FA67770 -:1002F0001323AF2FA67709C93E02CD1D030F0F0FA1 -:10030000E61F5723237E0F0F0F47E6E0B25F78E624 -:100310001FC62457C9CD92007E23666FC92A0020CC -:10032000CD92007EC9310024DB00E601CA5203C32E -:100330000009000102030405060708090A0B0C0D59 -:100340000E0F100F0E0D0C0B0A090807060504030B -:1003500002010601110000210020D306707EA8CA08 -:100360006503CD2404237CFE40C25A03D3062B7CB4 -:10037000FE1FCA8A037EA8CA7D03CD2404782F7786 -:10038000AECA6C03CD2404C36C03D306237CFE40A9 -:10039000CAA103782FAECA9C03CD2404AF77C38AC9 -:1003A00003780747D257037AB3CAD203F3EBF911A4 -:1003B00000200600210000390E10AF29DAC0032FFB -:1003C00012133E1812130DC2BA0305C2B403FBC3C5 -:1003D0000D04F3310024210C32E521000011340416 -:1003E000010008AF86D306230DC2E40305C2E4036F -:1003F0003CCAFE031AE3EBC5CD4004C1EBE3137C1A -:10040000FE60C2E003E17DFE0CCA0000FBD306C320 -:1004100075027B914F7A984703EB36000B2B78B12E -:10042000C21A04C94F7DE60179C23104B257C33301 -:1004300004B35FC9484746455B5B5B5B5B5B42411E -:10044000D5E5EBCD7704CD8704E1D113C9F51A13B7 -:10045000D5CD77043A0B20E601CC87043A0B20E691 -:1004600001C4990409D1F13DCA6E04C34D043A0B8D -:1004700020E6FE320B20C9E521AD04D6414717170F -:1004800080CD9200EBE1C93E05F501E0FF091A7746 -:10049000F13D09C8F513C38E043E0501E0FFF51ACE -:1004A0007713F1093DC29E042301A000C9781416F8 -:1004B00014787E4A4A4A343C424242247E424242B6 -:1004C0003C7E525252427E121202023C424252740E -:1004D0007E1010107E42427E424232423E02027E36 -:1004E000181824427E404040407E0408047E7E046A -:1004F00018207E3C4242423C7E1212120C3C424288 -:10050000225C7E1212324C244A5A522402027E028B -:10051000023E4040403E06186018063E4078403E8D -:100520004224182442060870080662725A4E460099 -:100530000000000040447E40407452524A4C00008B -:1005400000C0C0790F0F0F0FE5CD72053A0B20FEEA -:1005500001110100F25A051100FFE11979E5CD7290 -:10056000053A0B20FE01110100F26F051100FFE1B9 -:1005700019C9EB21D3050608E60F070707CD92003E -:100580003A0B20A7CAB605FE01CAB605D53E07CD6F -:10059000920011EA210608C506000E087E1FF578B4 -:1005A0001747F10DC29D057812132BC105C297059F -:1005B00021EA21D106083A5F22A7F5F1F57ECAC4E7 -:1005C00005EBAEEB1223E521200019EBE105C2BBE0 -:1005D00005F1C9003E414141413E000000407F42DB -:1005E000000000004245495162400000364949413F -:1005F00041220000007F090A0C08000031494949E6 -:100600004F00000031494949523C000001030509EF -:100610001163000036494949493600000E1929493D -:100620000600000000000000000000001038383E06 -:100630003838103C42A5A5A599423C2105207E4FA3 -:1006400017DA7306237EA7CA5706352B3E82B67784 -:100650003A2522F604D3002105207E17D8DB01E6D7 -:10066000014779E640CA91064FCD9106B9C82334B7 -:100670002334C9357EE60FCA8A061E08BBC2570658 -:100680003A2522E6FBD300C357063E7FA677C35721 -:100690000621052078A7CAA0063E40B677E640C9E5 -:1006A0003EBFA677C93A0720A7CA6507D101002433 -:1006B00011DF3FCD1204CD3E1DCD981DCD811DAF64 -:1006C000320B20DB0247E601CADC0678E602CA3FAD -:1006D000073A0720FE02FA2D07C33F0778E6023AE1 -:1006E0000720CAF706D604F23F07FEFFF2FC06FE1B -:1006F000FEF2A307C32D07FE02F23F0721E33611E6 -:10070000D4073E0DCD4D0421E43911E1073E15CD4E -:100710004D0421C5381119083E12CD4D042166380B -:10072000113E083E11CD4D043E01C3390721C538A5 -:100730001119083E12CD4D04AF320820C38E082196 -:10074000E33611D4073E0DCD4D0421E43911E10704 -:100750003E15CD4D0421053B11F6073E18CD4D0445 -:100760003E02C33907AF320B203A0920E620C821E8 -:100770002536110E083E0BCD4D04AF320B200EACCA -:1007800021C73CCD430521C73B117D083E11CD4D0E -:1007900004AF320B200E1921072CCD43050E80CD5E -:1007A0004305C921E33611D4073E0DCD4D0421E4A4 -:1007B0003911E1073E15CD4D0421C538112B083EF6 -:1007C00013CD4D04216638113E083E11CD4D043E37 -:1007D00001C33907544F5B53544152545B47414D59 -:1007E0004550524553535B5C5B504C415945525BFD -:1007F000425554544F4E4F525B50524553535B5DDC -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/Release/SpaceInvaders.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/Release/SpaceInvaders.rbf deleted file mode 100644 index 81d6dac1..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/Release/SpaceInvaders.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf deleted file mode 100644 index 4195da4c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "SpaceInvaders" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf deleted file mode 100644 index 6c2d87d6..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.qsf +++ /dev/null @@ -1,173 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 19:10:47 June 08, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# SpaceInvaders_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/spaceinvaders_memory.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spaceinvaders_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY spaceinvaders_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# -------------------------------- -# start ENTITY(spaceinvaders_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(spaceinvaders_mist) -# ------------------------------ \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/SpaceInvaders.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd deleted file mode 100644 index db58d70b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/dac.vhd +++ /dev/null @@ -1,48 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity dac is - generic ( - C_bits : integer := 8 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); -end dac; - -architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); -begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; -end rtl; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd deleted file mode 100644 index 21326c26..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,271 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= DIP(8); -- Unused ? - GDB0(1) <= DIP(7); - GDB0(2) <= DIP(6); -- Unused ? - GDB0(3) <= '1'; -- Unused ? - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= DIP(5); -- Unused ? - - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';-- Unused ? - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1';-- Unused ? - - GDB2(0) <= DIP(4); -- LSB Lives 3-6 - GDB2(1) <= DIP(3); -- MSB Lives 3-6 - GDB2(2) <= '0';-- Tilt ? - GDB2(3) <= '0';--DIP(2); -- Bonus life at 1000 or 1500 - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1';--DIP(1); -- Coin info - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd deleted file mode 100644 index d65b9f9b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/pll.vhd +++ /dev/null @@ -1,350 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire4_bv(0 DOWNTO 0) <= "0"; - sub_wire4 <= To_stdlogicvector(sub_wire4_bv); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - sub_wire2 <= inclk0; - sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire3, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex deleted file mode 100644 index 5ff2818c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_e.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000020C3C9162184207EA7CA0707237EA7C064 -:100010000601C3FA1821102811A31C0E15CDF308F0 -:100020003E0A326C2001BE1DCD5618DA3718CD4479 -:1000300018C32818CDB10A01CF1DCD5618D8CD4C04 -:1000400018C33A18C50610CD3914C1C9C53A6C2079 -:100050004FCD930AC1C90AFEFF37C86F030A670371 -:100060000A5F030A5703A7C921C22034234ECDD902 -:1000700001473ACA20B8CA98183AC220E6042ACCE6 -:1000800020C288181130001922C72021C520CD3B7D -:100090001AEBC3D3150000003E0132CB20C921501A -:1000A0002011C01B0610CD321A3E023280203EFFC6 -:1000B000327E203E0432C1203A5520E601CAB818EB -:1000C0003A5520E601C2C0182111333E2600CDFF6B -:1000D00008C3B60A3100240600CDE601CD56193E0C -:1000E0000832CF20C3EA0A3A672021E7200FD02345 -:1000F000C906023A82203DC004C93A9420B0329425 -:1001000020D303C9210022C3C301CDD814C397153E -:1001100021E7203A67200FD823C90E1C211E241185 -:10012000E41AC3F30821F820C3311921FC20C3319C -:10013000195E2356237E23666FC3AD090E07210186 -:100140003511A91FC3F3083AEB2021013CC3B209C2 -:1001500021F420C33119CD5C1ACD1A19CD2519CD42 -:100160002B19CD5019CD3C19C34719CDDC19C371DA -:10017000163E01326D20C3E616CDD719CD4719C3FF -:100180003C1932C120C98B19C3D60921032811BEDD -:10019000190E13C3F308000000003A1E20A7C2ACDA -:1001A00019DB01E676D672C03C321E20DB01E67612 -:1001B000FE34C0211B2E11F70B0E09C3F3082813C0 -:1001C0000008130E26020E110F0E110013080E0D5B -:1001D000283E0132E920C9AFC3D319003A9420A0C8 -:1001E000329420D303C9210127CAFA1911601C06D1 -:1001F000104FCD3914793DC2EC190610CDCB147CCB -:10020000FE35C2FA19C9217220461AE680A8C03705 -:10021000C9322B241C16110D0A0807060504030217 -:1002200001342E27221C181513100E0D0C0B090774 -:1002300005FF1A77231305C2321AC95E2356237E9F -:10024000234E2346616FC9C506037C1F677D1F6F60 -:1002500005C24A1A7CE63FF62067C1C92100243650 -:1002600000237CFE40C25F1AC9C5E51AB677132386 -:100270000DC26B1AE101200009C105C2691AC9CD7E -:100280002E09A7C8F53D77CDE619F1210125E60F26 -:10029000C3C50900000000FFB8FE201C109E00200E -:1002A0001C30100B080706000C04260E150411263E -:1002B000260F0B001804112426251B260E11261CC0 -:1002C0000F0B001804111226011413130E0D260E25 -:1002D0000D0B18261B0F0B001804112626011413F2 -:1002E000130E0D262612020E1104241B25260708C4 -:1002F0003F12020E11042612020E1104241C2526A0 -:100300000100001000000000027838783800F80082 -:100310000080008E02FF050C601C203010010000E0 -:10032000000000BB030010901C2830010400FFFFF8 -:100330000000027604000000000004EE1C00000330 -:10034000000000B604000001001D04E21C000003D0 -:100350000000008206000001061D04D01C000003FE -:10036000FF00C01C0000102101003000120000003E -:100370000F0B0018260F0B00180411241B25FC007E -:1003800001FFFF00000020641DD0291802541D0049 -:100390000800060000014000010000109E00201C23 -:1003A000000304781413081A3D68FCFC683D1A0029 -:1003B000000001B898A01B10FF00A01B0000000067 -:1003C0000010000E05000000000007D01CC89B03B1 -:1003D0000000030478140B193A6DFAFA6D3A19000B -:1003E00000000000000000000001000001741F0078 -:1003F0008000000000001C2F00001C2700001C399A -:10040000000039797A6EECFAFAEC6E7A79390000EC -:10041000000000781DBE6C3C3C3C6CBE1D780000AA -:1004200000000000193A6DFAFA6D3A190000000058 -:100430000000387A7F6DECFAFAEC6D7F7A380000B4 -:100440000000000E18BE6D3D3C3D6DBE180E000054 -:10045000000000001A3D68FCFC683D1A0000000026 -:1004600000000F1F1F1F1F7FFF7F1F1F1F1F0F0079 -:10047000000401130307B30F2F032F4904030001E6 -:10048000400805A30A035B0F27270B4B4084114844 -:100490000F993C7E3DBC3E7C99271B1A260F0E0807 -:1004A0000D13122812020E110426000315000D026E -:1004B00004261300010B04280210203013080B132C -:1004C0000008492214814200428114224908000098 -:1004D00044AA1088542210AA442254884A15BE3FC8 -:1004E0005E2504FC0410FC1020FC2080FC8000FE33 -:1004F0000024FE1200FE0048FE900F0B00290000B1 -:100500000107010101040B01060301010B090208A7 -:10051000020B04070A050205040607080A060A0377 -:10052000FF0FFF1FFF3FFF7FFFFFFCFFF8FFF0FF04 -:10053000F0FFF0FFF0FFF0FFF0FFF0FFF8FFFCFF2F -:10054000FFFFFFFFFF7FFF3FFF1FFF0F051015306D -:1005500094979A9D10050510151010053010101075 -:100560000515100500000000040C1E373E7C747E4B -:100570007E747C3E371E0C0400000000002200A5A3 -:100580004008983DB63C361D104862B61D9808429A -:1005900090080000261F1A1B1A1A1B1F1A1D1A1A70 -:1005A00010203060504848484040400F0B0018125F -:1005B0000F0002042626080D1500030411120E2C4C -:1005C000681D0C2C201C0A2C401C082C001CFF0E43 -:1005D0002EE01D0C2EEA1D0A2EF41D082E991CFF7C -:1005E0002738260C181213041118271D1A260F0E6F -:1005F000080D1312271C1A260F0E080D13120000E7 -:10060000001F2444241F0000007F49494936000090 -:10061000003E414141220000007F4141413E000037 -:10062000007F494949410000007F48484840000098 -:10063000003E414145470000007F0808087F000058 -:100640000000417F4100000000020101017E000026 -:10065000007F081422410000007F01010101000019 -:10066000007F2018207F0000007F1008047F00001A -:10067000003E4141413E0000007F484848300000B4 -:10068000003E4145423D0000007F484C4A31000099 -:1006900000324949492600000040407F40400000A8 -:1006A000007E0101017E0000007C0201027C00004E -:1006B000007F020C027F0000006314081463000036 -:1006C0000060100F106000000043454951610000B8 -:1006D000003E4549513E00000000217F010000001E -:1006E0000023454949310000004241495966000054 -:1006F000000C14247F04000000725151514E000080 -:10070000001E29494946000000404748506000004B -:100710000036494949360000003149494A3C000049 -:1007200000081422410000000000412214080000CB -:100730000000000000000000001414141414000055 -:100740000022147F14220000000304780403000038 -:10075000241B260E11261C260F0B0018041112252F -:100760002626281B260F0B0018041126261B2602FE -:100770000E080D2601010000010002010002010027 -:1007800060100F106030181A3D68FCFC683D1A00BC -:10079000080D120411132626020E080D0D2A501FF3 -:1007A0000A2A621F072AE11FFF0211040308132609 -:1007B0000060100F106038193A6DFAFA6D3A19009E -:1007C0000020404D50200000000000FFB8FF801FB7 -:1007D000109700801F000001D022201C10940020E0 -:1007E0001C281C260F0B0018041112261C26020EB2 -:1007F000080D120F14120726000808080808000048 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex deleted file mode 100644 index 4f7acccc..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_f.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000000000000000000000000000000000000F0 -:1000100000000000000000000000000000000000E0 -:1000200000000000000000000000000000000000D0 -:1000300000000000000000000000000000000000C0 -:1000400000000000000000000000000000000000B0 -:1000500000000000000000000000000000000000A0 -:100060000000000000000000000000000000000090 -:100070000000000000000000000000000000000080 -:100080000000000000000000000000000000000070 -:100090000000000000000000000000000000000060 -:1000A0000000000000000000000000000000000050 -:1000B0000000000000000000000000000000000040 -:1000C0000000000000000000000000000000000030 -:1000D0000000000000000000000000000000000020 -:1000E0000000000000000000000000000000000010 -:1000F0000000000000000000000000000000000000 -:1001000000000000000000000000000000000000EF -:1001100000000000000000000000000000000000DF -:1001200000000000000000000000000000000000CF -:1001300000000000000000000000000000000000BF -:1001400000000000000000000000000000000000AF -:10015000000000000000000000000000000000009F -:10016000000000000000000000000000000000008F -:10017000000000000000000000000000000000007F -:10018000000000000000000000000000000000006F -:10019000000000000000000000000000000000005F -:1001A000000000000000000000000000000000004F -:1001B000000000000000000000000000000000003F -:1001C000000000000000000000000000000000002F -:1001D000000000000000000000000000000000001F -:1001E000000000000000000000000000000000000F -:1001F00000000000000000000000000000000000FF -:1002000000000000000000000000000000000000EE -:1002100000000000000000000000000000000000DE -:1002200000000000000000000000000000000000CE -:1002300000000000000000000000000000000000BE -:1002400000000000000000000000000000000000AE -:10025000000000000000000000000000000000009E -:10026000000000000000000000000000000000008E -:10027000000000000000000000000000000000007E -:10028000000000000000000000000000000000006E -:10029000000000000000000000000000000000005E -:1002A000000000000000000000000000000000004E -:1002B000000000000000000000000000000000003E -:1002C000000000000000000000000000000000002E -:1002D000000000000000000000000000000000001E -:1002E000000000000000000000000000000000000E -:1002F00000000000000000000000000000000000FE -:1003000000000000000000000000000000000000ED -:1003100000000000000000000000000000000000DD -:1003200000000000000000000000000000000000CD -:1003300000000000000000000000000000000000BD -:1003400000000000000000000000000000000000AD -:10035000000000000000000000000000000000009D -:10036000000000000000000000000000000000008D -:10037000000000000000000000000000000000007D -:10038000000000000000000000000000000000006D -:10039000000000000000000000000000000000005D -:1003A000000000000000000000000000000000004D -:1003B000000000000000000000000000000000003D -:1003C000000000000000000000000000000000002D -:1003D000000000000000000000000000000000001D -:1003E000000000000000000000000000000000000D -:1003F00000000000000000000000000000000000FD -:1004000000CD741400C5E51AD304DB03B6772313BB -:10041000AFD304DB03B677E101200009C105C205B3 -:1004200014C90000CD7414C5E5AF77237723E1012B -:10043000200009C105C22714C9C51A77130120007D -:1004400009C105C23914C900000000000000000005 -:100450000000CD7414C5E51AD304DB032FA677235F -:1004600013AFD304DB032FA677E101200009C105F8 -:10047000C25514C97DE607D302C3471AC5E57E12EB -:1004800013230DC27E14E101200009C105C27C14B2 -:10049000C9CD7414AF326120C5E51AD304DB03F56E -:1004A000A6CAA9143E01326120F1B6772313AFD357 -:1004B00004DB03F5A6CABD143E01326120F1B67714 -:1004C000E101200009C105C29814C9AFC577012018 -:1004D0000009C105C2CC14C93A2520FE05C8FE0298 -:1004E000C03A2920FED847D230153A0220A7C87852 -:1004F000FECED27915C606473A0920FE90D20415E1 -:10050000B8D2301568CD62153A2A2067CD6F152212 -:1005100064203E05322520CD81157EA7CA301536D0 -:1005200000CD5F0ACD3B1ACDD3153E10320320C952 -:100530003E03322520C34A1521032035C02A6420FA -:100540000610CD24143E04322520AF32022006F7D7 -:10055000C3DC19000E00BCD49015BCD0C6100CC36F -:100560005A153A092065CD54154105DE106FC93A78 -:100570000A20CD5415DE1067C93E01328520C345DF -:100580001578070707808080813D6F3A672067C92B -:100590000CC610FA9015C93A0D20A7C2B71521A4B0 -:1005A0003ECDC515D006FE3E01320D207832082022 -:1005B0003A0E20320720C9212425CDC515D0CDF112 -:1005C00018AFC3A91506177EA7C26B162305C2C7AD -:1005D00015C900CD7414E5C5E51AD304DB037723F0 -:1005E00013AFD304DB0377E101200009C105C2D7B3 -:1005F00015E1C9CD11160100377EA7CAFF150C23DE -:1006000005C2F91579328220FE01C0216B20360126 -:10061000C92E003A672067C93A1520FEFFC0211095 -:10062000207E2346B0C03A2520A7C03AEF20A7CAB3 -:1006300052163A2D20A7C24816CDC017E610C83E64 -:1006400001322520322D20C9CDC017E610C0322D31 -:1006500020C921252036012AED20237DFE7EDA6384 -:10066000162E7422ED207E321D20C937C9AFCD8BE6 -:100670001ACD10193600CDCA092311F5201ABE1B58 -:100680002B1ACA8B16D29816C38F16BED298167E16 -:100690001213237E12CD50193ACE20A7CAC91621B3 -:1006A000032811A61A0E14CD930A2525061B3A67B6 -:1006B000200FDAB716061C78CDFF08CDB10ACDE7BA -:1006C000187EA7CAC916C3ED0221182D11A61A0E4D -:1006D0000ACD930ACDB60ACDD609AF32EF20D305A5 -:1006E000CDD119C3890B310024FBAF321520CDD8F1 -:1006F000140604CDFA18CD590AC2EE16CDD7192129 -:100700000127CDFA19AFCD8B1A06FBC36B19CDCAE1 -:1007100009237E11B81C21A11A0E04471AB8D2274A -:100720001723130DC21C177E32CF20C93A2520FE95 -:1007300000C2391706FDC3DC190602C3FA1800000F -:10074000219B2035CC6D173A6820A7CA6D172196DA -:100750002035C02198207ED3053A8220A7CA6D1784 -:100760002B7E2B772B36013E04329B20C93A9820F2 -:10077000E630D305C93A9520A7CAAA1721111A1144 -:10078000211A3A8220BED28E172313C385171A323C -:1007900097202198207EE630477EE60F07FE10C2A4 -:1007A000A4173E01B077AF32952021992035C006BD -:1007B000EFC3DC1906EF2198207EA077D305C9008E -:1007C0003A67200FD2CA17DB01C9DB02C9DB02E698 -:1007D00004C83A9A20A7C03100240604CDD60905E2 -:1007E000C2DC173E01329A20CDD719FB11BC1C2167 -:1007F00016300E04CD930ACDB10AAF329A2032934F -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_g.hex deleted file mode 100644 index 44ccade4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_g.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000AF32C120CDCF013A67200FDA7208CD138D -:1000100002CDCF01CDB100CDD1190620CDFA18CD3A -:100020001816CD0A19CDF315CD88093A8220A7CA32 -:10003000EF09CD0E17CD3509CDD808CD2C17CD59E8 -:100040000ACA49080604CDFA18CD7517D306CD049F -:1000500018C31F0800000011BA1ACDF3080698DB78 -:10006000010F0FDA6D080FDA9807C37F073E01C34F -:100070009B07CD1A02C314083A0820472A0920EB2F -:10008000C386080000003A6720672EFCC921112BA7 -:1000900011701B0E0ECDF3083A67200F3E1C211184 -:1000A00037D4FF083EB032C0203AC020A7C8E604CB -:1000B000C2BC08CDCA09CD3119C3A9080620211C2C -:1000C000273A67200FDACB08211C39CDCB14C3A9FE -:1000D00008DB02E603C603C93A8220FE09D03EFBD4 -:1000E000327E20C93ACE20A7C0211C390620C3CBBE -:1000F000140E031AD5CDFF08D1130DC2F308C91190 -:10010000001EE526006F29292919EBE10608D30610 -:10011000C339143A0920FE78D02A91207DB4C2292F -:10012000092100063E013283202B229120C9CD11E6 -:10013000162EFF7EC9CD10192B2B7EA7C80615DB06 -:1001400002E608CA48090610CDCA09237EB8D8CDF0 -:100150002E09347EF521012524243DC258090610BC -:1001600011601CCD3914F13CCD8B1ACD10192B2BFD -:1001700036003EFF3299200610C3FA1821A01DFE5A -:1001800002D823FE04D823C9CDCA093AF120A7C852 -:10019000AF32F120E52AF220EBE17E8327775F235F -:1001A0007E8A277757237E23666FC3AD097ACDB247 -:1001B000097BD5F50F0F0F0FE60FCDC509F1E60F3F -:1001C000CDC509D1C9C61AC3FF083A67200F21F867 -:1001D00020D821FC20C92102243600237DE61FFE01 -:1001E0001CDAE809110600197CFE40DAD909C9CDEC -:1001F0003C0AAF32E920CDD6093A6720F5CDE401BB -:10020000F13267203A672067E52EFE7EE6073C77ED -:1002100021A21D233DC2130A7EE12EFC772336382E -:100220007C0FDA330A3E21329820CDF501CD041936 -:10023000C30408CDEF01CDC001C30408CD590AC2E3 -:10024000520A3E3032C0203AC020A7C8CD590ACA4F -:10025000470ACD590AC2520AC93A1520FEFFC93AC7 -:10026000EF20A7CA7C0A480608CDFA184178CD7C51 -:10027000097E21F32036002B772B3601216220C91D -:100280003E0232C120D3063ACB20A7CA850AAF323C -:10029000C120C9D51ACDFF08D13E0732C0203AC0CF -:1002A000203DC29E0A130DC2930AC9215020C34BA0 -:1002B000023E40C3D70A3E80C3D70AE1C372003A68 -:1002C000C1200FDABB0A0FDA68180FDAAB0AC921AE -:1002D000142B0E0FC3930A32C0203AC020A7C2DAF3 -:1002E0000AC921C220060CC3321AAFD303D305CDED -:1002F0008219FBCDB10A3AEC20A72117300E04C2B7 -:10030000E80B11FA1CCD930A11AF1DCDCF0ACDB168 -:100310000ACD1518CDB60A3AEC20A7C24A0B1195A2 -:100320001ACDE20ACD800A11B01BCDE20ACD800AB7 -:10033000CDB10A11C91FCDE20ACD800ACDB10A2183 -:10034000B733060ACDCB14CDB60ACDD6093AFF2174 -:10035000A7C25D0BCDD10832FF21CD7F1ACDE401BC -:10036000CDC001CDEF01CD1A023E0132C120CDCF6B -:1003700001CD1816CDF10BD306CD590ACA710BAFBA -:10038000322520CD590AC2830BAF32C120CDB10A2C -:10039000CD88190E0C21112C11901FCDF3083AECC9 -:1003A00020FE00C2AE0B2111333E02CDFF08019C9E -:1003B0001FCD5618CD4C18DB0207DAC30B01A01F66 -:1003C000CD3A18CDB60A3AEC20FE00C2DA0B11D5B0 -:1003D0001FCDE20ACD800ACD9E1821EC207E3CE69E -:1003E0000177CDD609C3DF1811AB1DCD930AC30B1E -:1003F0000BCD0A19C39A19130008130E26020E0F0B -:1004000000000000000000000000000000000000EC -:1004100000000000000000000000000000000000DC -:1004200000000000000000000000000000000000CC -:1004300000000000000000000000000000000000BC -:1004400000000000000000000000000000000000AC -:10045000000000000000000000000000000000009C -:10046000000000000000000000000000000000008C -:10047000000000000000000000000000000000007C -:10048000000000000000000000000000000000006C -:10049000000000000000000000000000000000005C -:1004A000000000000000000000000000000000004C -:1004B000000000000000000000000000000000003C -:1004C000000000000000000000000000000000002C -:1004D000000000000000000000000000000000001C -:1004E000000000000000000000000000000000000C -:1004F00000000000000000000000000000000000FC -:1005000000000000000000000000000000000000EB -:1005100000000000000000000000000000000000DB -:1005200000000000000000000000000000000000CB -:1005300000000000000000000000000000000000BB -:1005400000000000000000000000000000000000AB -:10055000000000000000000000000000000000009B -:10056000000000000000000000000000000000008B -:10057000000000000000000000000000000000007B -:10058000000000000000000000000000000000006B -:10059000000000000000000000000000000000005B -:1005A000000000000000000000000000000000004B -:1005B000000000000000000000000000000000003B -:1005C000000000000000000000000000000000002B -:1005D000000000000000000000000000000000001B -:1005E000000000000000000000000000000000000B -:1005F00000000000000000000000000000000000FB -:1006000000000000000000000000000000000000EA -:1006100000000000000000000000000000000000DA -:1006200000000000000000000000000000000000CA -:1006300000000000000000000000000000000000BA -:1006400000000000000000000000000000000000AA -:10065000000000000000000000000000000000009A -:10066000000000000000000000000000000000008A -:10067000000000000000000000000000000000007A -:10068000000000000000000000000000000000006A -:10069000000000000000000000000000000000005A -:1006A000000000000000000000000000000000004A -:1006B000000000000000000000000000000000003A -:1006C000000000000000000000000000000000002A -:1006D000000000000000000000000000000000001A -:1006E000000000000000000000000000000000000A -:1006F00000000000000000000000000000000000FA -:1007000000000000000000000000000000000000E9 -:1007100000000000000000000000000000000000D9 -:1007200000000000000000000000000000000000C9 -:1007300000000000000000000000000000000000B9 -:1007400000000000000000000000000000000000A9 -:100750000000000000000000000000000000000099 -:100760000000000000000000000000000000000089 -:100770000000000000000000000000000000000079 -:100780000000000000000000000000000000000069 -:100790000000000000000000000000000000000059 -:1007A0000000000000000000000000000000000049 -:1007B0000000000000000000000000000000000039 -:1007C0000000000000000000000000000000000029 -:1007D0000000000000000000000000000000000019 -:1007E0000000000000000000000000000000000009 -:1007F00000000000000000000000000000000000F9 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_h.hex deleted file mode 100644 index 60810bae..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/roms/invaders_h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000000000C3D4180000F5C5D5E5C38C00007E -:10001000F5C5D5E53E8032722021C02035CDCD1703 -:10002000DB010FDA67003AEA20A7CA42003AEB2068 -:10003000FE99CA3E00C6012732EB20CD4719AF32E8 -:10004000EA203AE920A7CA82003AEF20A7C26F004F -:100050003AEB20A7C25D00CDBF0AC382003A9320CD -:10006000A7C28200C365073E0132EA20C33F00CD2C -:1000700040173A3220328020CD0001CD4802CD1306 -:100080000900E1D1C1F1FBC900000000AF327220CC -:100090003AE920A7CA82003AEF20A7C2A5003AC1D8 -:1000A000200FD28200212020CD4B02CD4101C382FE -:1000B00000CD8608E57E23666F220920220B20E111 -:1000C0002B7EFE03C2C8003D320820FEFE3E00C269 -:1000D000D3003C320D20C93E0232FB2132FB22C349 -:1000E000E408000000000000000000000000000024 -:1000F0000000000000000000000000000000000000 -:100100002102207EA7C23815E53A06206F3A672003 -:10011000677EA7E1CA360123237E2346E6FE070752 -:10012000075F160021001C19EB78A7C43B012A0BBE -:10013000200610CDD315AF320020C921300019EBB5 -:10014000C93A6820A7C83A0020A7C03A6720673A92 -:10015000062016023CFE37CCA1016F4605C25401B1 -:10016000320620CD7A0161220B207DFE28DA71193A -:100170007A3204203E01320020C916007D21092078 -:1001800046234EFE0BFA9401DE0B5F78C610477BC8 -:1001900014C3830168A7C85F79C6104F7B3DC39520 -:1001A0000115CACD012106203600234E3600CDD9D7 -:1001B000012105207E3CE60177AF21672066C9005A -:1001C000210021063736012305C2C501C9E1C93E18 -:1001D0000106E0210224C3CC142346237986772329 -:1001E000788677C906C011001B210020C3321A216E -:1001F0004221C3F8012142220E0411201DD5062CF4 -:10020000CD321AD10DC2FD01C93E01C31B023E0110 -:10021000C31402AF114222C31E02AF114221328128 -:10022000200102162106283E04F5C53A8120A7C206 -:100230004202CD691AC1F13DC8D511E00219D1C3FE -:100240002902CD7C14C335022110207EFEFFC8FE9A -:10025000FECA810223464FB079C27702237EA7C22D -:100260008802235E2356E5EBE5216F02E3D5E9E141 -:10027000110C0019C34B020504C27D023D05702B11 -:100280007711100019C34B02352B2BC38102E123D8 -:100290007EFEFFCA3B032335C047AF326820326978 -:1002A000203E30326A207836052335C29B032A1A55 -:1002B000200610CD241421102011101B0610CD3261 -:1002C0001A0600CDDC193A6D20A7C03AEF20A7C866 -:1002D000310024FBCDD719CD2E09A7CA6D16CDE765 -:1002E000187EA7CA2C033ACE20A7CA2C033A67204F -:1002F000F50FDA3203CD0E02CD78087323722B2B63 -:100300007000CDE401F10F3E210600D21203062059 -:100310003E22326720CDB60AAF32112078D3053C99 -:10032000329820CDD609CD7F1AC3F907CD7F1AC3E5 -:100330001708CD0902C3F802000000216820360129 -:10034000237EA7C3B003002B36013A1B20473AEFA8 -:1003500020A7C263033A1D200FDA81030FDA8E0350 -:10036000C36F03CDC0170707DA810307DA8E0321B5 -:100370001820CD3B1ACD471ACD39143E0032122039 -:10038000C978FED9CA6F033C321B20C36F0378FEC5 -:1003900030CA6F033D321B20C36F033CE6013215A8 -:1003A000200707070721701C856F221820C36F03E1 -:1003B000C24A032335C24A03C34603112A20CD068D -:1003C0001AE1D0237EA7C8FE01CAFA03FE02CA0AB8 -:1003D0000423FE03C22A0435CA36047EFE0FC0E59C -:1003E000CD3004CD5214E123342323353523353564 -:1003F00035233608CD3004C300143C773A1B20C6A1 -:1004000008322A20CD3004C30014CD3004D5E5C510 -:10041000CD5214C1E1D13A2C20856F322920CD91E3 -:10042000143A6120A7C8320220C9FE05C8C33604A9 -:10043000212720C33B1ACD3004CD52142125201191 -:10044000251B0607CD321A2A8D202C7DFE63DA5338 -:10045000042E54228D202A8F202C228F203A842093 -:10046000A7C07EE601012902C26E0401E0FE218AD6 -:100470002071232370C9E13A321B3232202A3820FE -:100480007DB4C28A042B223820C91135203EF9CD13 -:1004900050053A46203270203A5620327120CD6302 -:1004A000053A7820A7213520C25B0511301B213089 -:1004B000200610C3321AE13A6E20A7C03A8020FE0F -:1004C00001C01145203EEDCD50053A362032702056 -:1004D0003A5620327120CD63053A7620FE10DAE7D5 -:1004E000043A481B3276203A7820A7214520C25B87 -:1004F0000511401B2140200610CD321A3A82203DC2 -:10050000C208053E01326E202A7620C37E06E11124 -:1005100055203EDBCD50053A46203270203A362039 -:10052000327120CD63053A7620FE15DA34053A584B -:100530001B3276203A7820A7215520C25B05115046 -:100540001B2150200610CD321A2A7620225820C9AD -:10055000327F20217320060BC3321A117320060B41 -:10056000C3321A2173207EE680C2C1053AC120FE43 -:10057000043A6920CAB705A7C82336003A7020A7F5 -:10058000CA8905473ACF20B8D03A7120A7CA960544 -:10059000473ACF20B8D0237EA7CA1B062A76204E22 -:1005A0002300227620CD2F06D0CD7A0179C60767A9 -:1005B0007DD60A6F227B202173207EF6807723343C -:1005C000C9117C20CD061AD0237EE601C244062341 -:1005D00034CD75063A7920C603217F20BEDAE205C4 -:1005E000D60C3279203A7B20473A7E2080327B201D -:1005F000CD6C063A7B20FE15DA12063A6120A7C8B8 -:100600003A7B20FE1EDA1206FE2700D2120697322F -:1006100015203A7320F601327320C93A1B20C60810 -:1006200067CD6F1579FE0CDAA5050E0BC3A5050D78 -:100630003A6720676916057EA737C07DC60B6F1520 -:10064000C23706C9217820357EFE03C26706CD7504 -:100650000621DC1C227920217C2035352B35353EC6 -:1006600006327D20C36C06A7C0C37506217920CD54 -:100670003B1AC39114217920CD3B1AC3521422484E -:1006800020C9E13A8020FE02C02183207EA7CA0F44 -:10069000053A5620A7C20F05237EA7C2AB063A82B1 -:1006A00020FE08DA0F053601CD3C07118A20CD0661 -:1006B0001AD02185207EA7C2D606218A207E232338 -:1006C00086328A20CD3C07218A207EFE28DAF90670 -:1006D000FEE1D2F906C906FECDDC1923357EFE1FE8 -:1006E000CA4B07FE18CA0C07A7C006EF2198207E48 -:1006F000A077E620D305000000CD4207CDCB142122 -:100700008320060ACD5F0706FEC3DC193E0132F1E5 -:10071000202A8D20460E0421501D114C1D1AB8CAE6 -:10072000280723130DC21D077E3287202600682963 -:1007300029292922F220CD4207C3F108CD4207C35F -:100740003914218720CD3B1AC3471A06102198205F -:100750007EB077CD7017217C1D228720C33C071106 -:10076000831BC3321A3E01329320310024FBCD7922 -:1007700019CDD60921133011F31F0E04CDF3083A19 -:10078000EB203D2110280E14C2570811CF1ACDF3CB -:1007900008DB01E604CA7F070699AF32CE203AEBA8 -:1007A00020802732EB20CD471921000022F820229B -:1007B000FC20CD2519CD2B19CDD7192101017C3273 -:1007C000EF2022E72022E520CD5619CDEF01CDF50F -:1007D00001CDD10832FF2132FF22CDD700AF32FE4A -:1007E0002132FE22CDC001CD041921783822FC210E -:1007F00022FC22CDE401CD7F1ACD8D08CDD6090093 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv deleted file mode 100644 index cb74d5cf..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_memory.sv +++ /dev/null @@ -1,82 +0,0 @@ - -module spaceinvaders_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; - - - -sprom #( - .init_file("./roms/invaders_h.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/invaders_g.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/invaders_f.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/invaders_e.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin - Rom_out = 8'b00000000; - case (Addr[13:11]) - 3'b000 : Rom_out = rom_data_0; - 3'b001 : Rom_out = rom_data_1; - 3'b010 : Rom_out = rom_data_2; - 3'b011 : Rom_out = rom_data_3; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv deleted file mode 100644 index ad18ca58..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_mist.sv +++ /dev/null @@ -1,211 +0,0 @@ -module spaceinvaders_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Space Inv.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_sys), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), -// .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -spaceinvaders_memory spaceinvaders_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -spaceinvaders_overlay spaceinvaders_overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_sys), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .ce_divider(1), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd deleted file mode 100644 index 5188f6f0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spaceinvaders_overlay.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity spaceinvaders_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end spaceinvaders_overlay; - -architecture rtl of spaceinvaders_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/Release/SpaceLaser.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/Release/SpaceLaser.rbf deleted file mode 100644 index 39c51e51..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/Release/SpaceLaser.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf deleted file mode 100644 index 2dd6eff6..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "SpaceLaser" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf deleted file mode 100644 index 97a90f38..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.qsf +++ /dev/null @@ -1,173 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 13:58:36 June 09, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# SpaceLaser_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_mist.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/spacelaser_memory.sv -set_global_assignment -name VHDL_FILE rtl/spacelaser_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/roms/clr.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY SpaceLaser_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ----------------------------- -# start ENTITY(SpaceLaser_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SpaceLaser_mist) -# --------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.srf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.srf deleted file mode 100644 index 8a69edda..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/SpaceLaser.srf +++ /dev/null @@ -1,11 +0,0 @@ -{ "" "" "" "Verilog HDL or VHDL warning at T8080se.vhd(105): object \"BUSRQ_n\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net is missing source, defaulting to GND" { } { } 0 12011 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Output pins are stuck at VCC or GND" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at invaders_audio.vhd(59): object \"Clk240_ena\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Using initial value X (don't care) for net \"IHitTri\[0\]\" at invaders_audio.vhd(86)" { } { } 0 10873 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd deleted file mode 100644 index d37537f9..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,245 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - CAB : out std_logic_vector(7 downto 0); - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - CAB => CAB, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '1';--unknown - GDB0(1) <= '1';--unknown - GDB0(2) <= '1';--unknown - GDB0(3) <= '1';--unknown - GDB0(4) <= '1';--unknown - GDB0(5) <= '1';--unknown - GDB0(6) <= '1';--unknown - GDB0(7) <= '1';--unknown - - GDB1(0) <= not Coin; - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';--unknown - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1';--unknown - - GDB2(0) <= '0';--unknown - GDB2(1) <= '0';--unknown - GDB2(2) <= '0';--unknown - GDB2(3) <= '0';--unknown - GDB2(4) <= not Fire;--player2 - GDB2(5) <= not MoveLeft;--player2 - GDB2(6) <= not MoveRight;--player2 - GDB2(7) <= '1';-- Coinage - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd deleted file mode 100644 index 536bb064..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - CAB : out std_logic_vector(7 downto 0); - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - CAB <= std_logic_vector(CntE7(3 downto 0)) & std_logic_vector(CntE5(3 downto 0)); - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd deleted file mode 100644 index 1ebf53de..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/clr.vhd +++ /dev/null @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity clr is -port ( - clk : in std_logic; - addr : in std_logic_vector(7 downto 0); - data : out std_logic_vector(3 downto 0) -); -end entity; - -architecture prom of clr is - type rom is array(0 to 255) of std_logic_vector(3 downto 0); - signal rom_data: rom := ( - "0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010", - "0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010", - "0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010", - "0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010", - "0101","0111","0001","0011","0100","0110","0110","0010","0010","0101","0101","0010","0010","0001","0011","0010", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0110","0110","0001","0011","0010", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110", - "0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110", - "0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110", - "0010","0010","0001","0011","0100","0110","0110","0010","0010","0101","0101","0011","0011","0001","0011","0110", - "0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110", - "0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110", - "0110","0110","0001","0011","0100","0110","0110","0010","0010","0101","0101","0101","0101","0001","0011","0110"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex deleted file mode 100644 index 761aac36..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la01.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C34000414B412045FBC9203135353848BC -:10001000D306C380003020434E414B4120454F550D -:100020002031353538480D013932383020434E41C2 -:100030004B4120454F552031353538480D01393277 -:100040002100203600237CFE40C2430031C022CD77 -:100050005A01CD6F01CD0004CD401CAF325020328B -:100060005120325A203252203E0932592032582033 -:1000700000FBC37000454F552031353538480D0120 -:10008000CD990FC3BC00211E20347E0FDA9800CD1D -:10009000D700CDE100C39E00CDE100CDD700CDD289 -:1000A00006CDEE0BCD0903CD7F01CDF80A3A5020E5 -:1000B000A7CC340ACD5907CD8007FBC92147207E44 -:1000C000A7CA001435CACB00C30014214E207EE617 -:1000D000EF77D303C30014CD1104CD1406CD65060C -:1000E000C9CDA707CD8809CDD90900C9487802E054 -:1000F00002504802B002583002A002606002C802FA -:100100006828029802704802E8027820027802808B -:10011000A802B8028840028802905802B80298905B -:1001200002E802A07002B802A85002E002B0300259 -:100130009002007E183C66663C187E000018181875 -:100140003C247E7E180000925428C6285492000059 -:100150000000000000000000000021002111EC0060 -:100160001A7713237DFE47C26001AF32C021C92137 -:1001700000212281213E07328A21AF328B21C93AE8 -:10018000C021A7CA9E013DCA900132C021C39E0171 -:10019000AF32C0213A4E20E6F7D303324E202A81F7 -:1001A000217E328321232284217E328621232287CD -:1001B000217E328921218B21343A8321A7C2E0019B -:1001C0001105002A8121197DFE46C2D0012100219E -:1001D0002281213A8A21218B21BEC29E01AF77C99B -:1001E0003A8321E60F328E21AF328C21328D213AB3 -:1001F0008621A7C22F02218D2134218C21347EFE3D -:1002000002C214023A8D21FE02C211022A8121AFDC -:1002100077C3C0012A842123237E328621228421B0 -:100220002A872123237E328921228721C3EF013AA5 -:100230008921FE01CA3D02DA5502C35E0221460150 -:10024000228F213A4E20F608D303324E203E0A3246 -:10025000C021C37402215001228F21C374023A8E3F -:1002600021A7C26E02213201228F21C37402213CD8 -:1002700001228F21AF3291213A8E21A7C28502CD72 -:100280008B02C3BB02CD8B02C3EA023A83210F0F5C -:100290000FE61F4F06203A86216F260029292929BB -:1002A0002909EB2A8F21EB0120001A7713093A91D3 -:1002B000213C329121FE0AC2AA02C93A8921FE01DB -:1002C000CADA02DAE2022A84217EFEFFC2D5023EA9 -:1002D0001877C3FA013C77C3FA012A8721AF77C3A5 -:1002E000FA012A8421AF77C3FA013A8921FE01CAB3 -:1002F000DA02DAE2022A84217EFE16C204033EFFFD -:1003000077C3FA013D77C3FA013A0D20A7C218035B -:100310003A2C20A7C22F03C921062022A0212107A1 -:100320002022A221CD3E03AF320D20322C20C92144 -:10033000292022A021212A2022A221C324032AA08D -:10034000217E3CE6F8472100211105000E0E0D7EAE -:10035000B8CA5B031979A7C24E03C901140222A4CB -:10036000212AA2217ED60A2AA42123BECA7D0323E4 -:100370002305C26B0306023C0DC26703C93E01237D -:1003800077C9C3BB02CD8B02C3EA023A83210F0FA8 -:100390000FE61F4F06203A86216F260029292929BA -:1003A0002909EB2A8F21EB0120001A7713093A91D2 -:1003B000213C329121FE0AC2AA02C93A8921FE01DA -:1003C000CADA02DAE2022A84217EFEFFC2D5023EA8 -:1003D0001877C3FA013C77C3FA012A8721AF77C3A4 -:1003E000FA012A8421AF77C3FA013A8921FE01CAB2 -:1003F000DA02DAE2022A84217EFE16C204033EFFFC -:10040000065021002011700E1A77132305C208042C -:10041000C93A0C20A7C03A0020A7C265053A0220BD -:10042000A7C207053A0120A7C270043A5020A7CA04 -:10043000D9043A1420A7C0DB01E610CA03053A3BF1 -:1004400020A7C207052F323B20AF323820CD040C45 -:100450003A0820FE05DA07053E01320120CDFF06ED -:100460003A0A20C6073207203E00320520323320E8 -:100470003A05203C320520CD200ACD5A052A062017 -:10048000EBCDAD063A30204F160F3A05205F3A0803 -:1004900020BBDAF6043E26BBDAF6047AA6C249058A -:1004A000E5C5012000097EA7C2CF0401C0FF097E77 -:1004B000A7C2CF04C1E17AB6770DCA5A05CD200A8A -:1004C0003A05203C3205200FD2D40423C38804C14E -:1004D000E1C3490516F0C38A043E013236202138B3 -:1004E000207EA7C249042139207EFE0100CA2B05C7 -:1004F000D23A05C319053A05203D320520CD2A0A16 -:10050000C34F05AF323B203A5020A7CAE604DB01B7 -:100510000707DA2B0507DA3A052A0920EBCDAD06E5 -:10052000EB2A1520EB060FCDC406C93A0A20FEE0DF -:10053000CA19053C320A20C319053A0A20FE30CAFE -:1005400019053D320A20C319057AB677320B203ED1 -:1005500001320C203A32203219203A05208787C612 -:1005600037320620C93A03203D320320A7C03E059A -:10057000320320CD43073A04203D320420A7CAA00D -:10058000053A10203CE601321020070707072A151C -:1005900020856FEB2A0920EBE5CDAD06D1C32505FB -:1005A0003A5020A7CAE105CD4E073A1A203D321A2B -:1005B00020F5CD0711F1CACF053A5020A7CAE105B1 -:1005C000CD740ACD5A01CD581531C022C370002F09 -:1005D000321D203257203E12325820CDB60ACD832C -:1005E000132150203600233600CD4E07AF320122B2 -:1005F000C3C0053A5020A7C82A20203A24208527C6 -:100600006F3A25208C2767222420210000222020F9 -:10061000CD5510C93A0B20A7C83A0520FE25DA416E -:10062000063E013214203E0A3203203E16320420D8 -:1006300021300E2217203E01321020322120C35ECD -:1006400006320D2001070921500E3A0520B8DA5A6A -:100650000623040404040DC24D067E322020AF326E -:100660000B20C3F3053A0C20A7C83A19203D3219D4 -:1006700020A7C02A0620EBCDAD06AF3A0520471FC4 -:10068000CE0036002B3DC28206320C20320120CD36 -:1006900038073A082090320820AF320F203A332032 -:1006A0002FC69B473A0E208027320E20C926006AAB -:1006B0002929292929010020097B0F0F0FE61F0690 -:1006C000004F09C91A7713C501200009C105C2C42A -:1006D00006C93A2D203D322D20C03A3120322D203E -:1006E0003A0820FE64CA12073C3208203A0E20C69F -:1006F0000127320E20DA0A07AF320F20C30F073A64 -:100700004E20F601324E20D303C93E01320F20CDD8 -:10071000BF0F3A2B20FE64C83C322B203A2E20C655 -:100720000127322E20DA2F07AF322F20C334073EA5 -:1007300001322F20000000C93A4E20E6FE324E2042 -:10074000D303C93A4E20F604324E20D303C93A4EA1 -:1007500020E6FB324E20D303C93A4520A7C03A25F4 -:1007600020FE05D8211A2034CD07113A4E20F6106C -:10077000324E20D3033E803247203E01324520C90D -:100780003A4620A7C03A2720FE05D8211B2034CDA9 -:100790001A113A4E20F610324E20D3033E803247D3 -:1007A000203E01324620C93A2820A7C03A1420A78B -:1007B000C205093A0120A7C294083A0220A7C20341 -:1007C000083A0020A7C03A3620A7C27908DB02E623 -:1007D00010CA90083A3C20A7C294082F323C20AFA0 -:1007E000324B223A2B20FE05DA94083E01320220D9 -:1007F000CDFF063A1320C607322A203E00320520DC -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex deleted file mode 100644 index 37b1d86a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la02.hex +++ /dev/null @@ -1,129 +0,0 @@ -:100000003233203A05203C320520CD200ACDF708B6 -:100010002A2920EBCDAD063A30204F16F03A0520C4 -:100020005F3A2B20BBDA6C083E26BBDA6C087AA656 -:10003000C2E608E5C5012000097EA7C2620801C02A -:10004000FF097EA7C26208C1E17AB6770DCAF70838 -:10005000CD200A3A05203C3205200FD267082BC379 -:100060001B08C1E1C3E608160FC31D083A05203D71 -:10007000320520CD2A0AC3EC08214B227EA7C2DF1D -:10008000073A4C22FE0100CAB808D2CF08C3A6081E -:10009000AF323C203A3620A7C28108DB020707DADC -:1000A000CF0807DAB8082A1220EBCDAD06EB2A17E5 -:1000B00020EB060FCDC406C93A1320FEE0CAC708DC -:1000C0003C321320C3A6083EFF324C22C3A6083A96 -:1000D0001320FE30CADE083D321320C3A6083E01BD -:1000E000324C22C3A6087AB677321F203E0132284E -:1000F000203A32203219203A052087872FC601C6C0 -:10010000C8322920C93A03203D320320A7C03E054A -:10011000320320CD43073A04203D320420A7CA40D1 -:10012000093A10203CE601321020070707072A177A -:1001300020856FEB2A1220EBE5CDAD06D1C3B208C6 -:100140003A3620A7C25909CD4E073A1B203D321B33 -:1001500020F5CD1A11F1CA5F09CD4E07C3B905C309 -:10016000CF053A5020A7C83A3620A7C02A22203A05 -:10017000262085276F3A27208C27672226202100FA -:1001800000222220CDAE10C93A1F20A7C83A052070 -:10019000FE25DAB5093E013200203E0A3203203E38 -:1001A0001632042021100E2215203E01321020327A -:1001B0002320C3D209322C2001070921500E3A0511 -:1001C00020B8DACE0923040404040DC2C1097E322A -:1001D0002220AF321F20C362093A2820A7C83A194B -:1001E000203D321920C02A2920EBCDAD06AF3A05BB -:1001F00020471FCE003600233DC2F50932282032A9 -:100200000220CD38073A2B2090322B203A33202F72 -:10021000C69B473A2E208027322E20AF322F20C98E -:100220003A3320C60127323320C93A3320C69927F2 -:10023000323320C93A0820C34B0A21372035C03653 -:10024000200FDA590A21392036FFC93A0820FE3832 -:10025000DA3A0A3E01323820C92139203601C92153 -:1002600000002224202226202245203A8A0E321A1B -:1002700020321B2021002011700E1A7713237DFEDF -:100280001ACAA10AFE24CAA80AFE34CAAF0A7DFE11 -:1002900040C27A0A3A3620A7CAA00A3E24321B205E -:1002A000C92E1C1E8CC37A0A2E281E98C37A0A2EC9 -:1002B000371EA7C37A0A3E0232A0212A2420E5C1B4 -:1002C0002A26207CB8CACE0ADAD60AC3DB0A7DB950 -:1002D000DAD60AC3DB0AC5D1C3DD0AE5D13AA021CB -:1002E0003D32A021CAEF0A2A3420424BC3C30A7A06 -:1002F0003235207B323420C93A4D22E601C2820BCE -:10030000CD610C3A3422A7CA630B3A3222A7CA6ED7 -:100310000B3A4A22A7C2380B213C227EA7C27E0B91 -:100320003A4322210A2086E67F323C220FDA5A0B1A -:100330003A5E0C2F3C324C223A3622A7214A227ECA -:10034000CA490BF60177C3F70CE6FE773A4122E67D -:100350000F323622C3F70CC3450B3A5E0C324C22E7 -:10036000C3380B3A2B20FE30D27C0CC3180B3A401A -:1003700022E60F3232223E01324B22C3F70C35C344 -:10038000F70C213C2235C2970B34214D227EE6FE2C -:10039000772BAF77C3000B21332235C2AB0B360866 -:1003A000CD240C21322235F2AB0B3421352235C25B -:1003B000BF0B3607CD240C21342235F2BF0B34217C -:1003C000372235C2D30B3608CD240C21362235F224 -:1003D000D30B3421312235C2E90B3607CD240C2151 -:1003E000302235C2E90BC3140D214F2234C9060750 -:1003F0002147227E172B7E177705C2F50B21472256 -:100400007E1777C9060821590C1147227E122B1B33 -:1004100005C20C0C3E023233223E053235223E012B -:10042000323622C93A2520FE01DA510C35FE02DAB5 -:10043000510C35FE04DA510C35FE10DA510C35FE44 -:1004400020DA510C35FE40DA510C35FE80DA510CC1 -:1004500035C9D44B8CADB5195DE60205010001002C -:10046000023A0A2021132096213F22DA730C772BBF -:10047000AF77C92F3C772B3EFFC3710CDB01E64001 -:10048000C2900CDB01E620C29B0CCDD00CC3E20C69 -:100490003A3E22E680C2DF0CC3A60C3A3E22E6803A -:1004A000C2A60CC3DF0C3A3F22A7CAEC0C3A3E228C -:1004B000E680C2CB0C3E01324C22214C2277CDD0BB -:1004C0000C3A3F22BEDAEC0CC3F70C3EFFC3B70C6C -:1004D000213D2236003A4F22E60786323D22C9CD21 -:1004E000D00C3A3F22213D2296D2A60C3A4122E678 -:1004F0000F323422C3760B214922360FCD240C3A19 -:100500004F22E60FBE00DA970B2101207EA7C21F03 -:100510000DC3970B3A4422E60F323022C3E90B2178 -:100520003F227EFE09D2970B2B7EA7214C2236015B -:10053000C2350D36FF214D227EF601773A4522E67F -:100540000FC60A323C22C3970B0685050B094D5591 -:100550004003060C8F2D511189041512450DC50459 -:10056000A340A14E2008E21925160D192606040500 -:10057000A209515BC5098D05250540449A04010374 -:10058000870B712114002503A79D0309C209633657 -:10059000E102C40D809003840D87880955512E0017 -:1005A000821098C84904260C078BCC0860130709F1 -:1005B000898239435B0530029D808F4283180C4D40 -:1005C00055186048000E938D869480CA70188A046E -:1005D000C90052603E00C84A8982FF80481C8AAC2C -:1005E0004D028804410BDC0B06126DA0800E4F08F3 -:1005F00081001ACACD121D8A62C81C082501454D0A -:10060000001F070F0E153FE53F150E0F071F004A8D -:100610001184404B0B27270F5B030AA305084000FA -:10062000000401130307A30F2F032F4904030C0831 -:1006300000C02092F4C0F4F0CDE0C0C880200000DB -:100640000210A0C550C0DAF0E4E4D0D2022188152F -:1006500001020304050607010011E0170423202905 -:1006600000F8E0F070A8FCA7FCA870F0E0F80082A9 -:10067000000000000000000000303000000000001A -:100680000000C8E000000E600E0005050500000037 -:10069000000000000000000000C8E00000060000AC -:1006A0000403080000000000000025092AC8081CF7 -:1006B000640414041C000000E70546703F4000027B -:1006C0008D086000169064650E210500892E410D8D -:1006D000860F27078B0B2A297C010D03040005498F -:1006E0003C0810414400960B4512470910082C04A1 -:1006F0006A004723690185003F08892BCF04021255 -:10070000AF320122C30C0FAF3C320122AF02CD4405 -:100710000F02CD440F02CD440F210022868686862B -:10072000866F26003A01221E00BBC2330F112D1125 -:10073000C3360F11FF111916057E0223CD440F1584 -:10074000C2390FC9E521200009444DE1C9D11A473A -:10075000131A4F131A13D516FFBACA760F1630BAEA -:10076000C26C0F21000109444DC3720F320022CD2B -:100770000C0FD1C3540FE1E93A0222E60F320022F6 -:10078000011E3DCD000F3A0222E6F00F0F0F0F328F -:100790000022011E3CCD000FC9DB01E601CABA0FE1 -:1007A0003A032247AFB8C2B90F3A02223C273202BD -:1007B00022CD780FAF3C320322C9AF320322C93AAF -:1007C0000E20E60F320022011C37CD000F01032C52 -:1007D000CD070F3A0E20E6F00F0F0F0F3200220167 -:1007E0001C36CD000F01032DCD070F3A0F20FE0060 -:1007F000CAF80F3E01C3FA0F3E24320022011C3515 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex deleted file mode 100644 index 3d5b3e4a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la03.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000CD000F01032ECD070FC93A2E20E60F3287 -:100010000022011B37CD000F01042CCD070F3A2E13 -:1000200020E6F00F0F0F0F320022011B36CD000F1C -:1000300001042DCD070F3A2F20FE00CA43103E01C8 -:10004000C345103E24320022011B35CD000F0104B0 -:100050002ECD070FC93A2520E6F00F0F0F0F320003 -:1000600022011C2ECD000F010335CD070F3A2520AC -:10007000E60F320022011C2FCD000F010334CD0703 -:100080000F3A2420E6F00F0F0F0F320022011C3030 -:10009000CD000F010333CD070F3A2420E60F3200C5 -:1000A00022011C31CD000F010332CD070FC93A27C1 -:1000B00020E6F00F0F0F0F320022011B2ECD000F94 -:1000C000010435CD070F3A2720E60F320022011B2D -:1000D0002FCD000F010434CD070F3A2620E6F00F94 -:1000E0000F0F0F320022011B30CD000F010433CD62 -:1000F000070F3A2620E60F320022011B31CD000FF8 -:10010000010432CD070FC9011C3C3A1A20320022EB -:10011000CD000F010327CD070FC9011B3C3A1B205F -:10012000320022CD000F010427CD070FC93E414107 -:10013000413E00217F010031434549312241494977 -:10014000360C14247F0479494949463E49494926D9 -:1001500040474850303649494936304949493E1FA1 -:100160002444241F7F494949363E414141227F4171 -:1001700041221C7F494949417F484848403E414906 -:10018000492F7F0808087F00417F41000201417E1E -:10019000403F081422417F010101017F2018207F88 -:1001A0007F1008047F3E4141413E7F484848303E31 -:1001B0004145423D7F484C4A3132494949264040F9 -:1001C0007F40407E0101017E7C0201027C7E0106AF -:1001D000017E631408146360100F10604345495199 -:1001E0006100000000000408040800081422410017 -:1001F000004122140822147F142214141414140031 -:1002000000000000000000000000000000000000EE -:1002100000000000000000000000000000000000DE -:1002200000000000000000000000000000000000CE -:10023000001F2444241F7F494949363E4141412241 -:100240007F4141221C7F494949417F484848403EFF -:100250004149492F7F0808087F00417F4100020182 -:10026000417E403F081422417F010101017F201897 -:10027000207F7F1008047F3E4141413E7F4848482F -:10028000303E4145423D7F484C4A3132494949263A -:1002900040407F40407E0101017E7C0201027C7E65 -:1002A0000106017E22147F142260100F10600000EE -:1002B00003030000000000003E00320122CD4D0F7C -:1002C000261E11121C0C181B0E30000000000030FE -:1002D000300C1B0E0D121D300000FFCD4D0F2E1DDA -:1002E0001C0C181B0E300F1E0E15301C111219FF9E -:1002F000CD4D0F261C2619150A220E1B27000000C3 -:10030000000030303000003030303000FFCD4D0F75 -:10031000261B3030303030303030303030303030FC -:10032000303030303030303030FF3E01320122CDBD -:100330004D0F2E0230211D0A121D18300C181B19EA -:10034000232130FFCD4D0F27033030303030303097 -:10035000303030303030303030303030303030309D -:10036000FFCD4D0F27043030303030303030211C7D -:10037000190A0C0E30150A1C0E1B213030FFAF324B -:100380000122C93A3520E6F00F0F0F0F320022018B -:100390001E2ECD000F3A3520E60F320022011E2F0F -:1003A000CD000F3A3420E6F00F0F0F0F320022017C -:1003B0001E30CD000F3A3420E60F320022011E31EC -:1003C000CD000FC90D1231363536202053484C442C -:1003D0002032314134480D123136363020204C481D -:1003E0004C442032314132480D0F31363634202012 -:1003F0004D4F5620412C4D0D0F31363638202053AD -:100400003A5720A7C27B153A5020E601C286003A2F -:100410000222E6FFC232143A5120FE00CA09163AFF -:100420005120FE02C28600CD62153E03325120C328 -:100430008600DB02E680C2BE143A5520E601C249BE -:1004400014CD17153E01325520DB01E604CA6614AF -:100450003A022206998027320222AF321B203E0147 -:10046000323620C38B14DB01E602C8DB02E680C211 -:100470007A143A02220699C382143A02223DC83CF9 -:1004800006988027320222AF323620AF3252203215 -:100490005C2032552032CC213C325020325B20CDC2 -:1004A0004B15CD481CCD5F0ACD8313CD780FCD07FA -:1004B00011CD1A113E20324E20D303C386003A5587 -:1004C00020A7C2D014CDEB143E01325520C34914ED -:1004D0003A0222FE01CA49143A5520FE01C24914CB -:1004E000CD17153E02325520C34914CD6215AF32E7 -:1004F0000122CD4D0F3014191E1C11FFCD4D0F28B8 -:1005000011303030281C1D0A1B1D300B1E1D1D18FC -:100510001728303030FFC9AF320122DB02E680C23B -:100520002F15CD6215CD4D0F3014191E1C11FFCDA6 -:100530004D0F281124242424281C1D0A1B1D240BC4 -:100540001E1D1D181728242424FFC93E4021002405 -:10055000360023BCC25015C93A1A20A7C83A1B203E -:10056000A7C8110B002106243600237DE61FFE1BC1 -:10057000C26815197CFE40C26815C93A58203D3240 -:100580005820C03A5A20FE01C29D15AF325A20327F -:100590005120324E20D303C620325820C9FE00C25B -:1005A000BE153A5920A7CABE153A59203D325920E6 -:1005B000C2C8153E01325A203E30325820C9AF32EF -:1005C00057203E09325920C93D4787805F160021D8 -:1005D000F115197E2332002246230E08E5CD000FC7 -:1005E000E1460E170000003E09325820AF320122CA -:1005F000C91B362D0E352E1F342F1833300E3033D5 -:10060000162F340A2E35102D363A5220FE00CA78A5 -:10061000183A5B203D325B20C03A5220FE01C239BD -:1006200016CD6215CD4D0F301619150A22FF3E204A -:10063000325B203E02325220C9FE02C25616CD8CD9 -:1006400017A7CA4B163E09325B20C93E20325B20F9 -:100650003E03325220C9FE03C2AE16CD4D0F280F05 -:10066000281C0C181B0E300A0D1F0A170C0E301D0B -:100670000A0B150E28FF3E0A325F20113201010CD1 -:100680002ACD64183E0F325F2011000E01CA29CD19 -:100690006418010C2C3E29320022CD000F010A2CD7 -:1006A000CD000F3E20325B203E04325220C9FE04B2 -:1006B000C2CB16CD8C17A7C2C5163E20325B203E9A -:1006C00005325220C93E09325B20C9FE05C2E81638 -:1006D000CD8C17A7C2E2163E60325B203E06325236 -:1006E00020C93E09325B20C9FE06C20C17CD621537 -:1006F000CD4D0F2C1512171C0E1B1D300C18121788 -:10070000FF3E60325B203E07325220C9FE07C229FD -:1007100017CD8C17A7C223173E20325B203E08322C -:100720005220C93E09325B20C9FE08C24617CD8C53 -:1007300017A7C240173E20325B203E09325220C923 -:100740003E09325B20C9FE09C27C17CD8C17A7C2B7 -:1007500076173A5C20A7CA6B17DB02E680C27617D1 -:100760003A5C20C60B325C20C376173E40325B20D9 -:100770003E0A325220C93E09325B20C9AF325220B4 -:10078000325C203E02325120325B20C921ED171627 -:10079000003A5C205F197EFEFFCAEA17FEFECAAC73 -:1007A00017473A5C203C325C20C3C017237E325E80 -:1007B00020237E325D2023463A5C20C604325C2032 -:1007C000783200222A5D20444D24225D20CD000F86 -:1007D00021ED1716003A5C205F197EFEFECAE8176D -:1007E000FEFFCAEA173EFFC9AFC9C3501CFE2C1357 -:1007F0001C190A0C0E24150A1C0E1BFE2E0C0100DF -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex deleted file mode 100644 index acef86ea..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/roms/la04.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000025070024191812171D1CFE2E0A010000D6 -:10001000002424191812171D1CFE2A112618171562 -:100020002224012419150A220E1B2724FE290E283A -:1000300028282828240109080024282828282824DA -:10004000FE290B281D0A121D18240C181B19181B39 -:100050000A1D121817282424FFFE340B01240C1843 -:10006000121724FF1A023A5F203DC8325F20132185 -:10007000200009444DC364183ACC21A7CA88183D12 -:10008000CA76193DCA7619C9110B0021062436001B -:10009000237DE61FFE1BC28E18197CFE40C28E18FF -:1000A0003E0132CC213E5432B0213EC832B121AFA4 -:1000B00032BF21C3C8183E5532B0213EC932B121EA -:1000C000AF32BF21C3C818C921D81922B2212AB220 -:1000D000217EFE00CAC61BFE07CAB01932B5212A0E -:1000E000B2212322B2217E32B6213AB621A7CACE4E -:1000F000193D32B6213AB52121B021FE00CA23199B -:10010000FE01CA2919FE02CA2F19FE03CA3319FEBD -:1001100004CA3719FE05CA3C19FE09CA4119FE0A6C -:10012000CA4719342334C34D19352335C34D193407 -:10013000C34D1935C34D192334C34D192335C34D50 -:1001400019352334C34D19342335C34D193ACC2105 -:10015000FE02CA6419003ABF21FE02C26F19AF3213 -:10016000BF21FBC93ABF21FE60C26F19C35E193CB3 -:1001700032BF21C376193AB0216F260029292929D7 -:1001800029010020093AB1210F0F0F57E61F060081 -:100190004F097AE6E00F0F0F0F0F4FA7CAA9193EBC -:1001A00001070DC2A119C3AB193E01B677C3EA1806 -:1001B0002AB221237E4F237E572322B2213AB02137 -:1001C0008132B0213AB1218232B121C3CE182AB294 -:1001D000212322B221C3CE180028021C00100308DC -:1001E0000108030C0020030807FCD80220001803B4 -:1001F00008011003180108071414020C0004030C72 -:100200000104070C0C020C0004030C01040710008D -:1002100002040008030401080708000204000803A0 -:1002200004010807F8E002080008020401040204BF -:10023000000803080004030801040308010402087D -:100240000108071800021800100308010C03100130 -:100250000407080802040008030401080708000254 -:10026000040008030401080710F802100028032006 -:10027000011002080008021001180308010807987D -:10028000E005040204051402040414020404040337 -:100290000C070CF80510020A040303060403020607 -:1002A00004040306040302060403030A070D000501 -:1002B00010020804030304040D030407D0E0030242 -:1002C000010405040A0402020904040400040704EA -:1002D000040514020C0414030C0704FC050C0204AE -:1002E000040C0304070C040514020C040C0308049A -:1002F0000402080404030C0704F4050402040404C3 -:100300000304070C080A04050401040202000404A3 -:100310000409040302070C080504020C0506030C7B -:100320000504020C0506030C050402100418031052 -:1003300007140005180210041803100704FC051028 -:10034000020804100308071004050C020C0508033A -:100350000C050402100410030C0404020C04040332 -:10036000100714F60504020404040304070C0A0130 -:10037000040504000405140204041803040708001B -:100380000504020C0506030C0504020C0506030C0B -:1003900005040210041803100714000504020C05DC -:1003A00006030C0504020C0506030C0504021004E8 -:1003B00018031007180001040504000405140204C2 -:1003C0000418030408083ACC21FE02CAD61B3E02D8 -:1003D00032CC21C3B6183E0032CC213E013252202D -:1003E0003E40325B20FBC9F51C352334C3F51C3479 -:1003F0002335C3F51C3ACC21FE02CA0C1D003ABFBE -:10040000F5C5D5E500210524060036BA0023047899 -:10041000FE20C20D1C7CFE40C2081CE1D1C1F1C906 -:1004200000FF00FF00FF00FF00FF00FF00FF00FFD4 -:1004300000FF00FF00FF00FF00FF00FF00FF00FFC4 -:10044000CD001CCDB812C9FFCD001CCDB812C9FF1C -:10045000AF325C20C9FF00FF00FF00FF00FF00FF7C -:1004600000FF00FF00FF00FF00FF00FF00FF00FF94 -:1004700000FF00FF00FF00FF00FF00FF00FF00FF84 -:10048000000000000000000000000000000000006C -:10049000000000000000000000000000000000005C -:1004A0007777336655666666661111555522224484 -:1004B00044222255551111555555555566227777C9 -:1004C0007777336655666666661111555522224464 -:1004D00044222255551111555555555566227777A9 -:1004E0007777336655666666661111555522224444 -:1004F0004422225555111155555555556622777789 -:100500007777336655666666661111555522224423 -:100510004422225555111155555555556622777768 -:100520007777336655666666661111555522224403 -:100530004422225555111155555555556622777748 -:1005400077773366556666666611115555222244E3 -:100550004422225555111155555555556622777728 -:1005600077773366556666666611115555222244C3 -:100570004422225555111155555555556622777708 -:1005800077771166556666666611115555222244C5 -:1005900044222255551111555555555566227777E8 -:1005A00077771166556666666611115555222244A5 -:1005B00044222255551111555555555566227777C8 -:1005C0007777116655666666661111555522224485 -:1005D00044222255551111555555555566227777A8 -:1005E0007777116655666666661111555522224465 -:1005F0004422225555111155555555556622777788 -:100600007777116655666666661111555522224444 -:100610004422225555111155555555556622777767 -:100620007777226655666666661111555522224413 -:100630004422225555111155555555556622777747 -:1006400077772266556666666611115555222244F3 -:100650004422225555111155555555556622777727 -:1006600077772266556666666611115555222244D3 -:100670004422225555111155555555556611777718 -:1006800077772266556666666611115555222244B3 -:1006900044222255551111555555555566117777F8 -:1006A0007777226655666666661111555522224493 -:1006B00044222255551111555555555566117777D8 -:1006C0007777226655666666661111555522224473 -:1006D00044222255551111555555555566117777B8 -:1006E0007777226655666666661111555522224453 -:1006F0004422225555111155555555556611777798 -:100700007777226655666666661111555522224432 -:100710004422225555111155555555556633777755 -:100720007777226655666666661111555522224412 -:100730004422225555111155555555556633777735 -:1007400077772266556666666611115555222244F2 -:100750004422225555111155555555556633777715 -:1007600077772266556666666611115555222244D2 -:1007700044222255551111555555555566337777F5 -:1007800077772266556666666611115555222244B2 -:1007900044222255551111555555555566337777D5 -:1007A0007777226655666666661111555522224492 -:1007B00044222255551111555555555566337777B5 -:1007C0007777226655666666661111555522224472 -:1007D0004422225555111155555555556633777795 -:1007E0000000000000000000000000000000000009 -:1007F00000000000000000000000000000FFFF00FB -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv deleted file mode 100644 index eb503e87..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_memory.sv +++ /dev/null @@ -1,81 +0,0 @@ -module spacelaser_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - - -sprom #( - .init_file("./roms/la01.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/la02.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/la03.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/la04.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv deleted file mode 100644 index 2f80be68..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_mist.sv +++ /dev/null @@ -1,208 +0,0 @@ -module SpaceLaser_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "SpaceLaser;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]CAB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .CAB(CAB), - .HSync(HSync), - .VSync(VSync) - ); - -spacelaser_memory spacelaser_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -spacelaser_overlay spacelaser_overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .CAB(CAB), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - - -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd deleted file mode 100644 index 05c20798..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spacelaser_overlay.vhd +++ /dev/null @@ -1,228 +0,0 @@ --- 2019 by Gehstock --- needs some cleanup i´m to Lazy for this -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity spacelaser_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - CAB : in std_logic_vector(7 downto 0); - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end spacelaser_overlay; - -architecture rtl of spacelaser_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - - signal Overlay_A1 : boolean; - signal Overlay_A2 : boolean; - signal Overlay_A3 : boolean; - signal Overlay_A3_VCnt : boolean; - - signal Overlay_B1 : boolean; - signal Overlay_B2 : boolean; - signal Overlay_B2_VCnt : boolean; - - signal Overlay_G1 : boolean; - - signal Overlay_P1 : boolean; - - signal Overlay_R1 : boolean; - signal Overlay_R2 : boolean; - - signal Overlay_Y1 : boolean; - signal Overlay_Y2 : boolean; - signal Overlay_Y2_VCnt : boolean; - - signal VideoRGB : std_logic_vector(2 downto 0); - signal col_data : std_logic_vector(3 downto 0); - -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - - Overlay_A1 <= false; - Overlay_A2 <= false; - Overlay_A3 <= false; - Overlay_A3_VCnt <= false; - - Overlay_B1 <= false; - Overlay_B2 <= false; - Overlay_B2_VCnt <= false; - - Overlay_G1 <= false; - - Overlay_P1 <= false; - - Overlay_R1 <= false; - Overlay_R2 <= false; - - Overlay_Y1 <= false; - Overlay_Y2 <= false; - Overlay_Y2_VCnt <= false; - - - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = 0) then - Overlay_A3_VCnt <= true; - elsif (Vcnt = 98) then - Overlay_B2_VCnt <= true; - Overlay_A3_VCnt <= false; - elsif (Vcnt = 140) then - Overlay_Y2_VCnt <= true; - Overlay_B2_VCnt <= false; - elsif (Vcnt = 232) then - Overlay_Y2_VCnt <= false; - end if; - end if; - - if (HCnt = 500) and Overlay_A3_VCnt then - Overlay_A3 <= true; - elsif (HCnt = 540) then - Overlay_A3 <= false; - end if; - - if (HCnt = 486) and Overlay_B2_VCnt then - Overlay_B2 <= true; - elsif (HCnt = 540) then - Overlay_B2 <= false; - end if; - - if (HCnt = 486) and Overlay_Y2_VCnt then - Overlay_Y2 <= true; - elsif (HCnt = 540) then - Overlay_Y2 <= false; - end if; - - if (HCnt = 64) then - Overlay_R2 <= true; - elsif (HCnt = 96) then - Overlay_A2 <= true; - Overlay_R2 <= false; - elsif (HCnt = 120) then - Overlay_A2 <= false; - Overlay_R1 <= true; - elsif (HCnt = 166) then - Overlay_R1 <= false; - Overlay_Y1 <= true; - elsif (HCnt = 228) then - Overlay_Y1 <= false; - Overlay_P1 <= true; - elsif (HCnt = 292) then - Overlay_P1 <= false; - Overlay_A1 <= true; - elsif (HCnt = 358) then - Overlay_G1 <= true; - Overlay_A1 <= false; - elsif (HCnt = 430) then - Overlay_G1 <= false; - Overlay_B1 <= true; - elsif (HCnt = 486) then - Overlay_B1 <= false; --- if Overlay_A3_VCnt then --- Overlay_A2 <= true; --- if Overlay_B2_VCnt then --- Overlay_B2 <= true; --- if Overlay_Y2_VCnt then --- Overlay_Y2 <= true; --- elsif (HCnt = 500) then --- Overlay_A3 <= false; --- elsif (HCnt = 540) then --- Overlay_B2 <= false; --- Overlay_Y2 <= false; - end if; - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA - VideoRGB <= "011"; - elsif Overlay_B1 or Overlay_B2 then--BLUE - VideoRGB <= "001"; - elsif Overlay_G1 then--GREEN - VideoRGB <= "010"; - elsif Overlay_P1 then--PINK - VideoRGB <= "101"; - elsif Overlay_R1 or Overlay_R2 then--RED - VideoRGB <= "100"; - elsif Overlay_Y1 or Overlay_Y2 then--YELLOW - VideoRGB <= "110"; - else - VideoRGB <= "111";--WHITE - end if; - end if; - end process; - - colPROM: entity work.clr -port map( - clk => Clk, - addr => CAB, --should be Video Counters - data => col_data -); - --- O_VIDEO_R <= col_data(2); --- O_VIDEO_G <= col_data(1); --- O_VIDEO_B <= col_data(0); - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceLaser_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt deleted file mode 100644 index ffd0e157..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Space Walk port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- -ToDo: Color Prom - Controls + DIP - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf deleted file mode 100644 index 31bfde3e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "SpaceWalk" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf deleted file mode 100644 index 224648a1..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.qsf +++ /dev/null @@ -1,172 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 20:00:37 August 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# SpaceWalk_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Spacewalk_memory.sv -set_global_assignment -name VHDL_FILE rtl/Spacewalk_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ----------------------- -# start ENTITY(SpaceWalk) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SpaceWalk) -# --------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/SpaceWalk.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv deleted file mode 100644 index 708187bd..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/SpaceWalk.sv +++ /dev/null @@ -1,187 +0,0 @@ -module SpaceWalk( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Spacewalk;;", - "O34,Scanlines,Off,25%,50%,75%;", -// "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaders invaders( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(btn_one_player), - .Fire(~joystick_0[4]), - .MoveLeft(~joystick_0[1]), - .MoveRight(~joystick_0[0]), -// .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -Spacewalk_memory Spacewalk_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B({Video,Video,Video}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), - .ce_divider(0), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .c_bits(8)) -dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_coin = 0; - -reg gun1_up = 0; -reg gun1_dw = 0; -reg gun2_up = 0; -reg gun2_dw = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h15: gun1_up <= key_pressed; // Q - 'h35: gun1_dw <= key_pressed; // Y - 'h75: gun2_up <= key_pressed; // Arrow up - 'h72: gun2_dw <= key_pressed; // Arrow down - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv deleted file mode 100644 index 0d77837a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_memory.sv +++ /dev/null @@ -1,132 +0,0 @@ - -module Spacewalk_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; -wire [7:0]rom_data_6; -wire [7:0]rom_data_7; - - -sprom #( - .init_file("./roms/sw.h.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/sw.g.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/sw.f.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/sw.e.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_3) - ); - - - - - sprom #( - .init_file("./roms/sw.d.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_d ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_4) - ); - -sprom #( - .init_file("./roms/sw.c.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_c ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_5) - ); - -sprom #( - .init_file("./roms/sw.b.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_b ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_6) - ); - -sprom #( - .init_file("./roms/sw.a.hex"), - .widthad_a(10), - .width_a(8)) -u_rom_a ( - .clock(Clock), - .Address(Addr[9:0]), - .q(rom_data_7) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin - Rom_out = 8'b00000000; - case (Addr[13:10]) - 4'b0000 : Rom_out = rom_data_0; - 4'b0001 : Rom_out = rom_data_1;// 0100 0000 0000 - 4'b0010 : Rom_out = rom_data_2;// 1000 0000 0000 - 4'b0011 : Rom_out = rom_data_3; - - 4'b0100 : Rom_out = rom_data_4; - 4'b0101 : Rom_out = rom_data_5; - 4'b0110 : Rom_out = rom_data_6; - 4'b0111 : Rom_out = rom_data_7; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd deleted file mode 100644 index c45739e0..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/Spacewalk_overlay.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity Spacewalk_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end Spacewalk_overlay; - -architecture rtl of Spacewalk_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= not HSync; - O_VSYNC <= not VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd deleted file mode 100644 index 5c95d579..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaders is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl4 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - SoundCtrl6 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaders; - -architecture rtl of invaders is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(7 downto 0); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '0';-- - GDB0(1) <= '0';-- - GDB0(2) <= '0';-- - GDB0(3) <= '0';-- - GDB0(4) <= '0';-- - GDB0(5) <= '0';-- - GDB0(6) <= '0';-- - GDB0(7) <= '0';-- - - GDB1(0) <= '1';-- Unused ? - GDB1(1) <= '1';-- Unused ? - GDB1(2) <= '1';-- Unused ? - GDB1(2) <= '1';-- Unused ? - GDB1(4) <= not Sel2Player; - GDB1(5) <= not Sel1Player; - GDB1(6) <= not Coin; - GDB1(7) <= '1';-- Unused ? - - GDB2(0) <= '0';--Game_Time - GDB2(1) <= '0';--Game_Time - GDB2(2) <= '0';--Coinage - GDB2(3) <= '0';--Coinage - GDB2(4) <= '0';--Extended Time At - GDB2(5) <= '0';--Extended Time At - GDB2(6) <= '0';--Springboard Alignment - GDB2(7) <= '0';--unused - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl4 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - SoundCtrl6 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0);--audio_1_w - end if; - --if PortWr(4) = '1' and OldSample = '0' then - --D5(15 downto 8) <= DB; - --D5(7 downto 0) <= D5(15 downto 8); - --end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0);--tone_generator_lo_w - end if; - if PortWr(6) = '1' then - SoundCtrl6 <= DB(5 downto 0);--midway_tone_generator_hi_w - end if; - if PortWr(7) = '1' then - SoundCtrl4 <= DB(5 downto 0);--audio_2_w - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.bin deleted file mode 100644 index bd675dec..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex deleted file mode 100644 index c3bcceac..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.a.hex +++ /dev/null @@ -1,65 +0,0 @@ -:10000000494E40414E445052455353405448454058 -:100010004F4E4540504C4159455240425554544F23 -:100020004E4F524445504F53495440324E44404342 -:100030004F494E40414E4450524553534054484519 -:100040004054574F40504C415945524042555454EA -:100050004F4E455854454E4445444D495353494FDE -:100060004E50524556494F555340484947484053D2 -:10007000434F5245434F4D42494E454440494E53EC -:1000800045525440434F494E353600FFFFFFFFFFB6 -:10009000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF70 -:1000A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60 -:1000B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50 -:1000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40 -:1000D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF30 -:1000E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20 -:1000F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF10 -:10010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -:10011000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF -:10012000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF -:10013000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCF -:10014000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF -:10015000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF -:10016000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9F -:10017000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F -:10018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F -:10019000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6F -:1001A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F -:1001B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4F -:1001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F -:1001D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F -:1001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F -:1001F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F -:10020000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE -:10021000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE -:10022000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDE -:10023000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCE -:10024000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE -:10025000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAE -:10026000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9E -:10027000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8E -:10028000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7E -:10029000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6E -:1002A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5E -:1002B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4E -:1002C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E -:1002D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2E -:1002E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1E -:1002F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0E -:10030000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD -:10031000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED -:10032000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD -:10033000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCD -:10034000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBD -:10035000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAD -:10036000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9D -:10037000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8D -:10038000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D -:10039000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6D -:1003A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5D -:1003B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4D -:1003C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D -:1003D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2D -:1003E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1D -:1003F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0D -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin deleted file mode 100644 index 5d164292..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex deleted file mode 100644 index 93134886..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.b.hex +++ /dev/null @@ -1,65 +0,0 @@ -:1000000000040BCD1B0A35061E000AF317160C2040 -:10001000571810F8080F9E170C011A211A162060A5 -:100020003E1A18207B3E0C8041210C8837210E2A75 -:100030000147200C01462018B81A18EE0D18241B91 -:100040000C1E4B200E030224210C0826210E010158 -:100050004C200C0A4F2000060F0010FE0C01062059 -:10006000189A1A041B061C022C0402211C0F3004CF -:1000700014231C0632041B371C02340C010D2118FA -:10008000611B060500160B21741916212194181402 -:100090000C208218160C2168190414CD1B06320A94 -:1000A0008218041B061C02280402211C0F2C041BAE -:1000B000371C02300C0121210A7B180410231C0874 -:1000C0002818611B160C20A2180605000AC418186F -:1000D000611B0412F41B0726041B061C02280402E1 -:1000E000211C0F2C0413BA1B0630041B371C0232D0 -:1000F000060500140C20F01818611B0C010D2104DA -:1001000012CD1B072604012B1C0E30060500160B12 -:10011000215519160C2025191403210B19160C2131 -:1001200070190A0B1916102140190401FC1B0E301E -:100130000405C91B14300C01102118611B0A0B198E -:100140001603211D190412CD1B06300C01032118C2 -:10015000611B0A0B191410217419185C1B1403215C -:100160007419185C1B0A7419162121701918611B67 -:100170000C02062018EA1A10F80E2A0147200C017A -:1001800046200E000016200E0000182018EE0D0C60 -:10019000014D2018F71A10F8146020A41918EE0D5C -:1001A0000C0060200CC837210CC041211A162060B9 -:1001B0003E1A18207B3E18B81A0409E11B0C3506BC -:1001C0003C000409CD1B0C351202EA1B0C35061E3F -:1001D000001202CD1B0C3518241B0C1E4B200E03E5 -:1001E0000224210C0B26210C014C20000C01622062 -:1001F0000604001A1620603E1A18207B3E0413CD18 -:100200001B863E063C000A96190CC837210CC041DB -:1002100021187B1A0E341216200E907818201A1608 -:1002200020603E0402881C8F3E1A18207B3E0C0280 -:1002300006200C010D21140C20471A0404841C0E06 -:100240002618611B0A4D1A0404CD1B0E26140B211F -:100250005B1A0411101C07290A611A0411CD1B072F -:1002600029140C216F1A0411411C072C0A751A0459 -:1002700011CD1B072C0605000A361A210024CD904B -:100280001A06DD111F0036011936802305C2861AB1 -:1002900001FF20712305C2931AC9DB021F1FE60369 -:1002A0004F060021B01A09095E2356EB220020C92F -:1002B0006318A218BB18CF1811322121E51ACDD22C -:1002C0001AB612C911362121E91ACDD21AF604B68E -:1002D00012C906037E2B121B05C2D41ACDBB0DE634 -:1002E00003C9807F0600807B0620AFD305D307219A -:1002F0000E207EE60177C9210E207EF604773A06AD -:10030000203D211B1BCA0B1B211F1BDB02E6032305 -:100310003DF20F1B7E320320326220C970605040D4 -:10032000907560453A1620473A1820B8C2331BCD65 -:10033000BB0D1F114A1BD23C1B11531B21B82006B9 -:10034000091A13772305C2411BC9C080FF007980B9 -:10035000FD00ACC08000007980FD00AC210C203491 -:10036000C9210C2035C92A1820CDA61B3A06203DEC -:10037000C27F1B2A1C20CDB41BD8EB221C20C92A0B -:1003800016207C8227577D8B275F2A1E20CDB41B29 -:10039000DAA31BEB221E202A16202220202A182056 -:1003A0002222202A1620EB2A1A20CDB41BD8EB22B9 -:1003B0001A20EBC97BBDC07ABCC94445504F534994 -:1003C00054403340434F494E5340414E44404040D7 -:1003D000404040404040404040404040404040401D -:1003E00040474554405245414459474F47414D4588 -:1003F0004F5645524445504F534954403140434F66 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.bin deleted file mode 100644 index 1cfd2e87..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex deleted file mode 100644 index 88bf7240..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.c.hex +++ /dev/null @@ -1,65 +0,0 @@ -:1000000023732372233A6020773E02325220C93E86 -:100010001E324920210E21354E06002125140909E2 -:100020007E23666FE9A214881475146B1449143189 -:1000300014213F14110B323E0A326220C31E0143C9 -:100040004F554E5440444F574E21CD1B110B323E5D -:100050000ACD1E012163207EA7CA6114AF773262E8 -:10006000203E19CDE4060633C37C143E1FCDE406C2 -:100070000632C37C143E19CDE406063121062170F8 -:10008000110E343E01C36C0121A80E221420219CC4 -:10009000141104343E06321320C36C014C41554EFA -:1000A0004348AF32492032622021CD1B1104343E37 -:1000B00006CD6C012137217EE640CAC014214121C2 -:1000C0007EEE04E6FD77E60423237ECAD714C61F1E -:1000D000FEF3DAD7143EF3D603D2DD14AF32BC20E0 -:1000E000237ED61632C02021000022B92021000034 -:1000F00022BD203A0620A7C83EC832B8203E04D30D -:10010000073E1E324520324B203E01324D20321632 -:1001100021C9CDBB0DF61FE67F3247202166200E98 -:10012000F8C33315CDBB0DF61FE67F324820216F93 -:10013000200E0011030006027EA7FA4A1523712B38 -:100140000C3E80F248153EA077C91905C23815C982 -:100150003E3C3246203A0221A7C0CDBB0DF5CD650D -:1001600015F11F1F1FE60F217420232323233DF2C7 -:100170006A157EA7F0E640C07EF62077235E235600 -:10018000CDB201237EA7C8EB0E2070093DC28A15AF -:10019000C93A0920A7C02A002023220020C9AFD3D2 -:1001A00007C92142207EA7C836001FF5DCD615F10D -:1001B0001FF5DCFA15F11FF5DC4C16F11FF5DC0814 -:1001C00017F11F1FF5DC1017F11FF5DC2017F11FC9 -:1001D000F5DC4617F1C93A1320A7C021122135CA10 -:1001E000F4153E04325320CDBB0DD618D2EA15C605 -:1001F00019C3E406AFD305D306C9212721CD0316C1 -:10020000212B217EA7C835235E235623CA25163EFF -:100210001E3252207EA72145163E03CA22162148CF -:10022000163CC31E017EA721CD1B3E03CA30163CDF -:10023000CD1E013A6020A7CAB81A2100217EA7C2AC -:10024000B81A34C9C9353030313030302104213545 -:10025000CAB5167E3DCA61162222213E5A3251206D -:10026000C921CD1B1106323E05CD6C01110E363E63 -:1002700004CD1E013E5A32512021F5161109323E9D -:100280000DCD1E012102171104343E06326020CD2F -:100290006C0121CD1BE511863E3E03CD1E0121FDE3 -:1002A000163E05CD1E01131313133E06CD1E01E1AC -:1002B0003E01C31E0121CD1B1109323E0DCD1E0191 -:1002C0001104343E06CD6C01322321320521326205 -:1002D00020676F3ABC20FE0DD2DD162E40FEE4DA18 -:1002E000E51621C0FF22B92021A0FD22BD20210456 -:1002F0000B222521C9544152474554534053434F83 -:100300005245444F55424C45210E207EE6F777C9B1 -:10031000210E207E1FD07EE6FE773E0A324E20C997 -:1003200021B8203A1621A73E1ECA2E173E06324D8E -:1003300020C24017CDBB0DE607477EE6F8B077C96F -:100340007E3CE6F977C93A2621324C203A1121A7A2 -:10035000C02ABD203A1621A7018000CA601706FFF7 -:100360000922BD20C90018661B0C000620060200E9 -:100370000C011B210413CD1B863E1A1620603E1A69 -:1003800018207B3E0402CD1B8F3E18EA1A08059EFA -:10039000171204EC1B08311204F01B083500160C70 -:1003A00020571810FE080F0D180413611C06241A9C -:1003B0001A200D26040D611C0129040C0F1C0E29A6 -:1003C0000404EC1B1A291A1C200D2B0409611C05BE -:1003D0002E0409741C0E2E04046A1C172E040C40F3 -:1003E0001C08300404EC1B14301A202009321A2295 -:1003F000201232160C200718040B7D1C0A35063C0F -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin deleted file mode 100644 index 3bd482c3..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex deleted file mode 100644 index d7cdf5e2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.d.hex +++ /dev/null @@ -1,65 +0,0 @@ -:100000003910CD2610110500C36212EB7EF6407741 -:10001000E620110101CA1A1016FFCD3910CD2610A5 -:10002000111000C362123E04321221325320C92B38 -:100030007EF620773E10324A2021BA207E82773A1F -:10004000BE20A72160FEF257101DF25A102ABD20D3 -:100050007C2F677D2F6F2322BD2021B8207EE6F7FD -:1000600077AF321621C921B8207EE6BF77326320F0 -:100070003A0620A7CA97103E20D3073E0A324520F1 -:10008000216420347EFE05DA9110AF320320C3973D -:100090001021EC19C29A10216617220020C93A4B90 -:1000A00020A7C02120FE22BD202AB9207CB5C2C2D3 -:1000B000103ABC20C607218000FABE1026FF22B9E4 -:1000C00020C97CFE02D8FE102602DABE10FEFED049 -:1000D00026FEC3BE10003A4B20A7C0326420EBCDF1 -:1000E0003412C03217213A1C21FE181606DAF2101B -:1000F00016027EE6B9B277E608320D20F5213721E7 -:10010000CA06112141217EF6407721B8207EE6BF44 -:1001100077F1CA1F113A06203DC21F1132BC203EA2 -:1001200008D3073E0A3245203E06324920320E21CE -:100130002160207EA7C8360021CD1B11863E3E13CC -:10014000CD1E013200212133217EF640773A2F2146 -:10015000A7F4B81AC3EE0D3A4B20A7C0EBCD34126A -:10016000C03217217EE6041E1CCA6E111EFC23231A -:1001700046237ED61532C0202B2B2B7EE604171784 -:1001800017F605AE774F23360A21B8207EF6107792 -:100190007883FEFCDA9811AFFEF0DA9F113EF03260 -:1001A000BC203A1C215778FE04D2B71179E608CA60 -:1001B000C411161BC3C411FED4DAC41179E608C2F7 -:1001C000C41116007A1F1FE607D603C2D71111000B -:1001D00000CD5212C3EC11DAE011CD3D12C3EC1187 -:1001E0002F3CCD3D127A2F577B2F5F1322BD20EB82 -:1001F00022B92021242135C207123602237E3CFE7B -:1002000006D207127723353E0A324B203A0620A742 -:10021000CA1C123E10D3073E0A324520110100CD00 -:1002200062123A06203DC0CDBB0DE6033CFE03C082 -:10023000321721C97EE608C83A1721A7C957AFC6A9 -:100240004015C23F125F3A2521210000193DC24CE2 -:1002500012EB01C0FE3A2521210000093DC25B12CC -:10026000C9003A0620A7C83A6020A7CA75127B8346 -:10027000275F7A8A573A0D20A701172021603EC2D6 -:10028000861203032E7B0A8327020B0A8A27025F4A -:100290003A06203DC29E123A0D20A7C2FA12DB0296 -:1002A0001F1F1F1FE603CAFA12C604577BBADAFAE9 -:1002B000121161201AA7C2FA123C12E5C53A0620B3 -:1002C0003D213A13CACA12213E13DB02E603233D45 -:1002D000F2CE121103201A86271221521C11863EDB -:1002E0003E08CD1E01131313133E07CD1E01219AA4 -:1002F0000E2214203C321320C1E1E5210621E5CD78 -:100300002013CD20133630E1D13E05326520477EE3 -:10031000FE3078C21E0123133DC20E13326520C980 -:100320000ACD2E1377230A03CD32137723C90F0F7B -:100330000F0FE60FC69027CE4027C9353025204540 -:10034000353020002140207EA7C836001FF5DC8410 -:1003500013F11FF5DC5913F1C93A0E21A7C271132D -:100360003A6020A7CA7613210F21347EFE07D27689 -:100370001321032034C921B8207EE6BF77216617F8 -:10038000220020C93A0A20A7C03C3209202A0420B2 -:10039000220020C92141207EA7C836001F1FF5DC9E -:1003A000C813F11FF5DC0F14F11FF5DC2415F11F44 -:1003B000F5DC1215F11FF5DC5015F11FF5DC9E156B -:1003C000F11FF5DC9115F1C9212F21CDD113213376 -:1003D000217EA7F0E620C87EE610C2E7137EF61065 -:1003E000773E10324A20C97EF64077235E2323569B -:1003F000CDB2012127217EA7CAFE13212B2136026F -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin deleted file mode 100644 index efcc5800..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex deleted file mode 100644 index 107eddf5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.e.hex +++ /dev/null @@ -1,65 +0,0 @@ -:1000000000003F0000000000001800000080FF0119 -:100010000000F8001F00F00F00F00F1F000000F8B4 -:10002000FFFFFFFFFF0000180000000018000000A5 -:1000300080FF010000F8FF1F00F0FFFFFF0FFFFF30 -:10004000FFFFFFFFFFFFFFFF00001800000F384415 -:1000500028387CFEBABABA383828286C6C071038B1 -:1000600038BAFE828200AFD303D305D307CDBD0ECD -:10007000DB02E64021091AC27D0C2166172200200E -:1000800021800CE5FBD3042A00207EA7CAA10CF333 -:1000900023220020EB21DB0E4F0600097E23666F32 -:1000A000E9CD4413CDA60FCD9413CDA60FCDA21547 -:1000B000CD6E0DCDA60FCDA50DCDE60CCDD70DCDBA -:1000C000A60F211E217E3CFE10DACD0CAF772174E5 -:1000D00020232323233DF2D10C7EA7F0E640C07EEF -:1000E000E6DF77C30B0E3A6020A7C006002174201C -:1000F000232323237EA7F0E640CAFD0C047EE610EE -:10010000CAF00C78FE0CD8320221FE0FC03A06204D -:10011000A7CAEE0D2105217EA7C0342B36033E0170 -:100120003200213E013251203262203211212165FC -:100130000D1106323E05CD6C0121000022BD2021AB -:10014000C0207EFE41DA4A0D3641216A0D110E367D -:100150003E04CD1E0121800E2214203C32132011BA -:100160000001C36212424F4E5553313030303A4E87 -:1001700020A7C0210720DB012FE64047AEC87078DA -:10018000A7C8210E207EF601773E0A324E20210CB0 -:1001900020343A0620A7C03C320920320A202157D9 -:1001A00018220020C93A0D21A7C8210B21DB012FFD -:1001B000E6207723DB012FE61077C9E52108200E22 -:1001C000007EA7C2C70D3D47E61DEACF0D0E807821 -:1001D0000FE67F8177E1C90103200AA7C821062124 -:1001E000E5CD2013E1118F3E3E02C31E01002178B0 -:1001F0002011520E1A137723E6101A1377231A13BD -:10020000772323CAF40DAF320221C97EE6034F23C0 -:100210005E2356CDB201D5E521330E09095E235682 -:10022000E11A23774FE1131A77790E20094F0DC297 -:10023000260EC9390E420E490E08183C66C3C36625 -:100240003C180642183C3C1842083C7EFFFDF9620F -:1002500034188000308122308244308066308188BA -:100260003082AA3080CC3081EE3082104080324023 -:1002700081544082764080984081BA4092DC4000B0 -:10028000850100010C020F010C010D020F0100019C -:100290000C020F010C010D030F00830208020D0276 -:1002A000110414021104140081012201220122010F -:1002B00022012201220122012204250000F3E10192 -:1002C0000000310040C5C5C5C5C5C5C5C5C5C5C546 -:1002D000C5C5C5C5C53DC2C50E310024E9240F06FC -:1002E0000F170F250F370F400F450FF70E000F5256 -:1002F0000F5D0F7F0F850FEB7E23220020C3BD0E05 -:10030000216C01C3090F211E01E5EB7E235E2356FC -:1003100023D5CD770FE1C9AF320920EB7E324420DF -:1003200023220020C9AF320A20EB7E32432023CDA6 -:10033000770FEB220420C9EB5E2356EB220020C985 -:10034000CD740F12C9EB4E234623CD770FEB7023EC -:1003500071C9CD680FC2590FEB220020C9CD680FBB -:10036000CA640FEB220020C9EB5E2356231A5E23DA -:100370005623A7C9EB7E235E235623220020C9EB18 -:10038000CD770FEBE9EB4E234623E5210621CD2067 -:1003900013CD20133630E1CD770F2106213E0532F3 -:1003A0006520C30E13001115211AA7C82A13214F67 -:1003B000AF12EB4721BC0F09097E23666FE9CC0F12 -:1003C000F40F0B10D610571166109E10EB7EE6044A -:1003D000110001CAD80F16FFCD2F103A0620A7CA68 -:1003E000EE0F210E207EF608773E3C325020115051 -:1003F00000C36212EB7EF64077CD7C15110000CD74 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin deleted file mode 100644 index 07a82f8c..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex deleted file mode 100644 index 7339ab28..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.f.hex +++ /dev/null @@ -1,65 +0,0 @@ -:1000000023702370093DC2FF07C94E237E5FD301D1 -:10001000232356CDB20179E61021B908CA2208215E -:10002000C808C3A407350846085708660877088833 -:10003000089908A808080000C07FFAC3C07F000123 -:1000400080007E000000080000FE070002A8FFA854 -:10005000FF0002FE070000070000C007F83FBEFADD -:10006000F83FC0070000080000E28F2288FEFF2250 -:1000700088E28F02800000080000FE03C35FFE03D9 -:1000800080000001007E0000080000E07F4000FFCB -:1000900015FF154000E07F0000070000E003FC1F93 -:1000A0005F7DFC1FE0030000080000F1471144FFE2 -:1000B0007F1144F147014000000710046003600312 -:1000C0008000600360031004080870313EF81F18B8 -:1000D000393CFC7C3D9E0F0798003A1521A7C021B2 -:1000E000B8207EA7F03ABC204F3AC020573AC32030 -:1000F000825F3A3221C602BADA0209BB212F21DC23 -:1001000010093A3621C602BADA3209BBD0213321AE -:100110007EA7F0E620C0237E91C610FE20D02323C8 -:100120007E92C608FE17D02B2B2213213E013215DA -:1001300021C93E32BADA4209BBD02178201E08C359 -:100140004F093E42BADA7409BBD02198201E077EBF -:10015000A7F26B09E640C26B09237E2B91FE10D2F9 -:100160006B092213213E02321521C9232323231DAB -:10017000C24F09C93E52BADA8209BBD0216620C3F8 -:100180008D093E62BADAAB09BBD0216F20CD93094D -:10019000D823237EA7F0E640C0237E91C608FE1731 -:1001A000D02B2213213E03321521C93EAEBADA15F7 -:1001B0000ABBD021372179FE6BDACA09214121FE21 -:1001C00087D2CA093E07321521C97EA7F022132122 -:1001D0007EE640CAF009232379C60C96FE30D03261 -:1001E0001C21237E92C607FE16D03E04321521C97B -:1001F0007EE6040600CAFA09061423237990C60C89 -:1002000096FE1CD0321C21237E92C607FE16D03EDD -:1002100005321521C93EC4BAD8BBD021412179FE8F -:100220006BDACA09213721FE87DAC409C3CA09007B -:100230003A1B21A7C03A0E20E602213721CA430A01 -:100240002141213A0620A7C2500ACD520BC35A0AB7 -:100250003DC25A0A7EE608C4520B7EA7F01FD26B3D -:100260000A23352BC26B0A7EE6DE77E5CD700BE103 -:100270004EC53A1921FEAFDA7C0A3EAFFE58DA834A -:100280000AC62847792323E60811B3C9CA920A117E -:10029000C9B3787723FE6CDA9B0A5372235FD301CC -:1002A000CDB20173237223791FD2BC0AE6103E0936 -:1002B00001DA0BC2C90A01AD0BC3C90AE6043E0745 -:1002C00001070CC2C90A012A0C77E5EB11DBFFF527 -:1002D0000A03D302DB0377230A03D302DB0377236A -:1002E0000A03D302DB0377230A03D302DB0377235A -:1002F0000A03D302DB037723AFD302DB037719F1C1 -:100300003DC2CF0AD1C179E640C0791F0120FFDA92 -:10031000150B0160FE1FD21C0B0160FF1FDA240BBE -:100320000C0C0C0C09EB2373237217015D0CDA34EF -:100330000B014D0C0A032377EB111F00F50A03D3C1 -:1003400002DB037723AFD302DB037719F13DC23C15 -:100350000BC97EE604CA5A0B3E0CC604473ABC20C1 -:1003600090D2650BAFFE58DA6C0BD628321921C932 -:10037000232323235E2356237EA7C84F3600E5EBB5 -:1003800011DBFFAF77237723772377237723771941 -:100390000DC2840BE1235E2356237EA7C83600EBF3 -:1003A0003D011F00702370093DC2A40BC9FFFF1F50 -:1003B0000000F0FF3F000000FFFF000000F0FF071B -:1003C000000000FF1F000000F8FF00000018FC07FD -:1003D000000000C01F00000000FC0000F8FFFF004C -:1003E00000FCFF0F0000FFFF0000E0FF0F0000F81F -:1003F000FF000000FF1F0000E03F180000F80300AE -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin deleted file mode 100644 index 6f921f66..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex deleted file mode 100644 index 65a5a680..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.g.hex +++ /dev/null @@ -1,65 +0,0 @@ -:100000001AA7C0470E08CD0B0412C97EA7CA150453 -:1000100035C2150437781747230DC20B04C90011E8 -:10002000FF500EFFC32C0411F9600E017E17D0178C -:10003000DA3B04237986BBC240042B3600C372042A -:10004000775FD301CDB20123798677E6032182045D -:100050000E06093DF252040E06EB1A13D302DB031F -:100060007723AFD302DB0377790E1F094F0DC25AF6 -:1000700004C9237E5FD301CDB2013E080E1FEB7091 -:100080002370093DC27F04C9187E18187E185020BD -:10009000500A040A24247E7E24240A040A50205094 -:1000A000003AB820A7F0CD700521B8207EE640C206 -:1000B000B40477C97EF62077E60F3218217EE61069 -:1000C000CAD204AE77232323235E2323232356C3DC -:1000D00023052AB920444D2ABB20097CFEF1DAEA27 -:1000E00004CD680522B920C3D5045FD30122BB200B -:1000F0002ABD20444D2ABF20097CFEF0DA130521D9 -:10010000B8207EE6F777AF321621CD680522BD20F4 -:10011000C3F3045722BF207AFED0DA23053E06320D -:100120001521C9CDB201EB22C120E53A18214F219A -:10013000870509095E23561A1332C3204F21020096 -:1001400039221F21E1311E001A13D302DB0377236A -:100150001A13D302DB037723AFD302DB0377390D06 -:10016000C248052A1F21F9C9782F67792F6F23C943 -:10017000E620C82AC1203AC320111E007223722330 -:1001800072193DC27C05C99B05BA05D705F4051156 -:10019000062E063F06BA055E0673060F800340046E -:1001A00080028003C007E00FA00BA00BA00B800310 -:1001B000800380028002C006C0060E8003400488CF -:1001C000228823F83FF01F800380038003C007E0EC -:1001D0000E600C383818300E800340048802880303 -:1001E000F807F01F803380238203FE1FFE1F0018D4 -:1001F000003800300E8003400480228023C03FF08E -:100200001F980388038083F0FFF0FF300038001848 -:10021000000E18303838600CE00EC00780038003F1 -:100220008003F01FF83F882388224004800308C021 -:1002300007C007E0EFFFFFFFAF0363800180000FFF -:10024000C001C002C0038000C001F001F003F0074C -:10025000F00DC001C00180018001800380030A000D -:100260000180038003A00BE00F2008A00A0001001A -:100270000000020A000180038003A00BE00F2008A9 -:100280002008000100008000003A1320A7C82110B8 -:10029000207EA7CA980635C9237EA7CAA506352B96 -:1002A0003A0F2077C9237EA7CAB00635AFD305C958 -:1002B0002A14207EA7C2BC06321320C9F2C606E665 -:1002C0007F320F20237E321120233A0F20477EA752 -:1002D000FAD9063E0132122005783210207E232200 -:1002E0001420E67F4F060021F50609097ED3052379 -:1002F0007ED306C90000003F131D1633183F1A05B0 -:100300001D011F392027221124352513272B283FB3 -:10031000290F2B192C1F2D212E212F1D30153109AE -:10032000323B32293317343F3427350D36313611FD -:100330003731370F382B3805391D3935390B3A210C -:100340003A00211D21347E1F212F21DA510721334C -:10035000217E17D017DAF00717DA0A087EE6074F72 -:10036000E6043E01CA69073EFF2386775FD301FE9C -:1003700020CA7907FEE0C27F072B7EEE0477232395 -:1003800035C2860736062356C298077A32012114F1 -:100390007BA7FA9707151572CDB201212508090927 -:1003A0007E23666FEB1A134F1A13D302DB037723F6 -:1003B0001A13D302DB037723AFD302DB0377790E63 -:1003C0001E094F0DC2A8072100217EA7C83A0121AE -:1003D0003DC2DA07CDE307C3C71AFE1FC0CDE3074E -:1003E000C3BB1A713A1D211F113221D0113621C908 -:1003F0003600235E232356CDB201EB3E080E1E705D -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.bin b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.bin deleted file mode 100644 index 4172f1bc..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.bin and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex deleted file mode 100644 index 18ba68e5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/roms/sw.h.hex +++ /dev/null @@ -1,65 +0,0 @@ -:100000000000310024C31700FBC9000000000000FD -:10001000F5C5D5E5C34C03DB0217DA2000C3660C37 -:100020000601110000210020D304707EA8CA3F0001 -:100030004F7DE60179C23D00B257C33F00B35F2355 -:100040007CFE40C22800D3042B7CFE1FCA7C007EAD -:10005000A8CA63004F7DE60179C26100B257C3634D -:1000600000B35F782F77AECA46004F7DE60179C2B4 -:100070007700B257C37900B35FC34600D304237C33 -:10008000FE40CA9F00782FAECA9A004F7DE60179E4 -:10009000C29800B257C39A00B35FAF77C37C0078B1 -:1000A0000747D225007AB3CACE00EBF9110020062B -:1000B00000210000390E10AF29DABD002F12133EC7 -:1000C0001812130DC2B70005C2B100C308013100F8 -:1000D00024210C36E5210000110D010100041A1342 -:1000E00086D304230DC2E00005C2E0003CCAFA003A -:1000F000E3EB3E01CD1E01EBE31B137CFE20C2DBD4 -:1001000000E17DFE0CCA0000D304C30801004828AA -:10011000477A460F456244BB43F242514137F57E70 -:1001200023D630F2370147137BE61FC23001141487 -:1001300004C22701C31F01E5D5CDC4010E203A65D5 -:1001400020D601F5DA490136FF09F13E0AF51A1306 -:10015000DA54012F7709F13DC24D01DA600136FF13 -:10016000D1E113F13DC21E01326520C9F57ED630C2 -:1001700023E5CDC4013E0AE5F51A13CD9C01CD9CC3 -:1001800001CD9C01CD9C01F1E10E40093DC27701FA -:100190000184FD09EBE1F13DC26C01C91F0E00D2E3 -:1001A000A4010E0F1FF53E00D2AD013EF0B1772342 -:1001B000F1C90603AF7A1F577B1F5F05C2B4017AEE -:1001C000C62457C93CFE0BFACC01D60621CF01014B -:1001D0000A00093DC2D201EBC93C7E6666666666CE -:1001E000667E3C181C1818181818183C3C3C7E6693 -:1001F000607C3E06067E7E3C7E6660387860667E69 -:100200003C666666667E7E606060603E3E06063ED8 -:100210007E60667E3C3C3E06063E7E66667E3C7E9A -:100220007E60703038181C0C0C3C7E66663C7E6626 -:10023000667E3C3C7E66667E7C60607C3C000000A6 -:1002400000000000000000183C7E6666667E7E6648 -:10025000663E7E66663E7E66667E3E3C7E66060640 -:100260000606667E3C3E7E6666666666667E3E7E08 -:100270007E06063E3E06067E7E7E7E06063E3E06E6 -:100280000606063C7E6606067676667E3C666666F2 -:10029000667E7E666666663C3C1818181818183C20 -:1002A0003C60606060606060667E3C6666763E1EB4 -:1002B0001E3E76666606060606060606067E7EC3B1 -:1002C000C3E7E7FFFFDBC3C3C366666E6E7E7E7661 -:1002D0007666663C7E6666666666667E3C3E7E66E2 -:1002E000667E3E06060606081C1C1C1C1C1C1C0800 -:1002F0001C3E7E66667E3E766666663C7E66063E92 -:100300007C60667E3C7E7E181818181818181866CF -:10031000666666666666667E3C66666666667E3CA1 -:100320003C1818C3C3C3DBFFFFE7E7C3C366667EA1 -:100330003C18183C7E666666667E3C1818181818CD -:1003400018181818181899FF7E3C18003A1A21A797 -:10035000C25803DB00321921210E207EEE0277D332 -:10036000033A2221A7C283033AC020FE90DA7D031C -:1003700021B8207EE608C27D037EE6F877CDA10491 -:10038000CDDA08CD300ACD4207216620CD1F0421E9 -:100390006920CD1F04216F20CD2704217220CD2795 -:1003A00004CDBD03CDED03CD89063A2321A7C2B705 -:1003B00003322221321121E1D1C1F1FBC9114020C8 -:1003C0001AA7C04721022035C0363C3A6220A7C296 -:1003D000E3032103207EA7CAE303C6992777C2E37C -:1003E0000306010E01214320CD0B0412C921442034 -:1003F0001141201AA7C0470E08CD0B04121142204C -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/SpaceWalk_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/Release/SuperEarthInvasion.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/Release/SuperEarthInvasion.rbf deleted file mode 100644 index e9124245..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/Release/SuperEarthInvasion.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf deleted file mode 100644 index 8c553b65..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:27:39 November 20, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:27:39 November 20, 2017" - -# Revisions - -PROJECT_REVISION = "SuperEarthInvasion" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf deleted file mode 100644 index 0ebe06ab..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.qsf +++ /dev/null @@ -1,172 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 19:20:51 August 08, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# SuperEarthInvasion_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperEarthInvasion_memory.sv -set_global_assignment -name VHDL_FILE rtl/SuperEarthInvasion_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY SuperEarthInvasion_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------------------- -# start ENTITY(SuperEarthInvasion_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SuperEarthInvasion_mist) -# ----------------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/SuperEarthInvasion.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv deleted file mode 100644 index 04687a33..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_memory.sv +++ /dev/null @@ -1,81 +0,0 @@ -module SuperEarthInvasion_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; - - -sprom #( - .init_file("./roms/earthinv_h.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/earthinv_g.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/earthinv_f.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/earthinv_e.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv deleted file mode 100644 index 0c0853d6..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_mist.sv +++ /dev/null @@ -1,212 +0,0 @@ -module SuperEarthInvasion_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "SEarthInv.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -SuperEarthInvasion_memory SuperEarthInvasion_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -SuperEarthInvasion_overlay SuperEarthInvasion_overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_core), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ce_divider(0), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd deleted file mode 100644 index adbf653b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/SuperEarthInvasion_overlay.vhd +++ /dev/null @@ -1,128 +0,0 @@ ---2019 by Gehstock -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity SuperEarthInvasion_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end SuperEarthInvasion_overlay; - -architecture rtl of SuperEarthInvasion_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd deleted file mode 100644 index db58d70b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/dac.vhd +++ /dev/null @@ -1,48 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity dac is - generic ( - C_bits : integer := 8 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(C_bits-1 downto 0); - dac_o : out std_logic - ); -end dac; - -architecture rtl of dac is - signal sig_in: unsigned(C_bits downto 0); -begin - seq: process(clk_i, res_n_i) - begin - if res_n_i = '0' then - sig_in <= to_unsigned(2**C_bits, sig_in'length); - dac_o <= '0'; - elsif rising_edge(clk_i) then - -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i - --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); - sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); - dac_o <= sig_in(C_bits); - end if; - end process seq; -end rtl; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd deleted file mode 100644 index f089f1f2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,243 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: entity work.mw8080 - port map( - Rst_n => Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= DIP(8); -- Unused ? - GDB0(1) <= DIP(7); - GDB0(2) <= DIP(6); -- Unused ? - GDB0(3) <= '1'; -- Unused ? - GDB0(4) <= not Fire; - GDB0(5) <= not MoveLeft; - GDB0(6) <= not MoveRight; - GDB0(7) <= DIP(5); -- Unused ? - - GDB1(0) <= not Coin;-- Active High ! - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1';-- Unused ? - GDB1(4) <= not Fire; - GDB1(5) <= not MoveLeft; - GDB1(6) <= not MoveRight; - GDB1(7) <= '1';-- Unused ? - - GDB2(0) <= DIP(4); -- LSB Lives 3-6 - GDB2(1) <= DIP(3); -- MSB Lives 3-6 - GDB2(2) <= '0';-- Tilt ? - GDB2(3) <= '0';--DIP(2); -- Bonus life at 1000 or 1500 - GDB2(4) <= not Fire; - GDB2(5) <= not MoveLeft; - GDB2(6) <= not MoveRight; - GDB2(7) <= '1';--DIP(1); -- Coin info - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd deleted file mode 100644 index 1d9ad578..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,335 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd deleted file mode 100644 index f8d0b139..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex deleted file mode 100644 index 9d3a7323..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_e.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000FE6EC8002184207EA7CA0707237EA7C0F2 -:100010000601C3FA18F5CDD609F121A21D06072362 -:1000200005C83DC21F18C91631001C1131401C0CF7 -:1000300031201C0731681DFF0000CD5618D8CD4C6B -:1000400018C33A18C50610CD3914C1C9C50E12CD52 -:10005000930AC1C900000AFEFF37C86F030A67038D -:100060000A5F030A5703A7C921C22034234ECDD902 -:1000700001473ACA20B8CA98183AC220E6042ACCE6 -:1000800020C288181130001922C72021C520CD3B7D -:100090001AEBC369140000003E0132CB20C9215085 -:1000A0002011C01B0610CD321A3E023280203EFFC6 -:1000B000327E203E0432C1203A5520E601CAB818EB -:1000C0003A5520E601C2C0182111333E2600CDFF6B -:1000D00008C3B60A3100240600CDE601CD991C3EC6 -:1000E0000832CF20C3EA0A3A672021E7200FD02345 -:1000F000C906023A82203DC004C93A9420B0329425 -:1001000020D303C9210022C3C301CDD814C397153E -:1001100021E7203A67200FD823C90E1C211E241185 -:10012000E41AC3F30821F820C3311921FC20C3319C -:10013000195E2356237E23666FC3CE130E0721015B -:100140003511A91FC3F3083AEB2021013CC3B209C2 -:1001500021F420C33119CD5C1ACD630CCD2519CD06 -:100160002B19CD5019CD3C19C34719CDDC19C371DA -:10017000163E01326D20C3E616CDD719CD4719C3FF -:100180003C1932C120C92AA51F7EFECD3E40CAD7E8 -:100190000A0000000000000000003A1E20A7C2ACC8 -:1001A00019DB01E676D672C03C321E20DB01E67612 -:1001B000FE34C9F5E53E31D303CDEC1001DA17CD9D -:1001C0003A18CDB10AAFD303D306E1F1C90000005C -:1001D000003E0132E920C9AFC3D319003A9420A0F0 -:1001E000329420D303C9210127CAFA1911601C06D1 -:1001F000104FCD3914793DC2EC190610CDCB147CCB -:10020000FE35C2FA19C9217220461AE680A8C03705 -:10021000C9322B241C16110D0A0807060504030217 -:1002200001342E27221C181513100E0D0C0B090774 -:1002300005FF1A77231305C30011005E2356237EA2 -:10024000234E2346616FC9C506037C1F677D1F6F60 -:1002500005C24A1A7CE63FF62067C1C92100243650 -:1002600000237CFE40C25F1AC9C5E51AB677132386 -:100270000DC26B1AE101200009C105C2691AC9CD7E -:100280002E09A7C8F53D77CDE619F1210125E60F26 -:10029000C3C50900000000FFB8FE201C109E00200E -:1002A0001C30100B080706000C04260E150411263E -:1002B000260F0B001804112426251B260E11261CC0 -:1002C0000F0B001804111226011413130E0D260E25 -:1002D0000D0B18261B0F0B001804112626011413F2 -:1002E000130E0D262612020E1104241B25260708C4 -:1002F0003F12020E11042612020E1104241C2526A0 -:100300000100001000000000027838783800F80082 -:100310000080008E02FF050C601C203010010000E0 -:10032000000000BB030010901C2830010400FFFFF8 -:100330000000027604000000000004EE1C00000330 -:10034000000000B604000001001D04E21C000003D0 -:100350000000008206000001061D04D01C000003FE -:10036000FF00C01C0000102101003000120000003E -:100370000F0B0018260F0B00180411241B25FC007E -:1003800001FFFF00000020641DD0291802541D0049 -:100390000800060000014000010000109E00201C23 -:1003A0000003047814130821217E5C7E21C1000023 -:1003B000000001B898A01B10FF00A01B0000000067 -:1003C0000010000E05000000000007D01CC89B03B1 -:1003D0000000030478140B202344B8A8B844330069 -:1003E00000000000000000000001000001741F0078 -:1003F0008000000000001C2F00001C2600001C389C -:100400000000030458E1B6E8E8B6E1580403000030 -:1004100000000030481A2DB8FCB82D1A48300000F2 -:1004200000000000003344B8A8B8443300000000C6 -:100430000000E01051A3B4E8E8B4A35110E00000BC -:100440000000000C10193F94FE943F19100C00009E -:100450000000000000C1217E5C7E21C10000000080 -:1004600000000F1F1F1F1F7FFF7F1F1F1F1F0F0079 -:10047000000401130307B30F2F032F4904030001E6 -:10048000400805A30A035B0F27270B4B4084114844 -:1004900007993C7E3DBC3E7C992139230647C3DE4B -:1004A000122626040011130726080D150012080E47 -:1004B0000D2626C43FC400000210203000000000BA -:1004C0000008492214814200428114224908000098 -:1004D00044AA1A88542210AA442254884A15BE3FBE -:1004E0005E2504FC0410FC1020FC2080FC8000FE33 -:1004F0000024FE1200FE0048FE900F0B00290000B1 -:100500000107010101040B01060301010B090208A7 -:10051000020B04070A050205040607080A060A0377 -:10052000000000008000FF01FF03FF07330F330FBF -:10053000330F330FFF0FFF0FFF0FF00FE03FF03FC0 -:100540003F4F3F8FFF07FF03FF01800005020110AF -:1005500094979A9D01020101020101100102050216 -:10056000010501010000000000040E5BF55B0E1C9C -:100570001C0E5BF55B0E0400000000002008021852 -:1005800048E1461B151B0C14620003163D96030040 -:100590000802512019000F0F0E1601000C0E0E0557 -:1005A00001020360504848484040400F0B001809C2 -:1005B0002612130E0F0F080D0626130704261B1212 -:1005C000132626001104260E0D26130704081126F3 -:1005D00016001826115E1F2108310E02CD930A2144 -:1005E0000629115C0F0E12CD930AC3B60A262626E1 -:1005F00026261600110D080D06382626262626006A -:10060000001F2444241F0000007F49494936000090 -:10061000003E414141220000007F4141413E000037 -:10062000007F494949410000007F48484840000098 -:10063000003E414145470000007F0808087F000058 -:100640000000417F4100000000020101017E000026 -:10065000007F081422410000007F01010101000019 -:10066000007F2018207F0000007F1008047F00001A -:10067000003E4141413E0000007F484848300000B4 -:10068000003E4145423D0000007F484C4A31000099 -:1006900000324949492600000040407F40400000A8 -:1006A000007E0101017E0000007C0201027C00004E -:1006B000007F020C027F0000006314081463000036 -:1006C0000060100F106000000043454951610000B8 -:1006D000003E4549513E00000000217F010000001E -:1006E0000023454949310000004241495966000054 -:1006F000000C14247F04000000725151514E000080 -:10070000001E29494946000000404748506000004B -:100710000036494949360000003149494A3C000049 -:1007200000081422410000000000412214080000CB -:100730000000000000000000001414141414000055 -:100740000022147F14220000000304780403000038 -:10075000210A290E1211EE00CD930AC3D41D0118EF -:10076000020E0D06110013140B0013080E0D1226B5 -:100770000E0DD31D01010000010002010002010065 -:1007800060100F1060202344B8A8B8443300000064 -:10079000080D120411132626020E080D11F81ECDA5 -:1007A0003914C32E0FB10B4F1F0211040308132677 -:1007B0000060100F106021217E5C7E21C1000000CE -:1007C00000007D7D00000000000000FFB8FF801FDA -:1007D000109700801F000001D022201C10940020E0 -:1007E0001C020E0C0F041308130815042626150806 -:1007F00003040E05110E0C0000080808080800008C -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex deleted file mode 100644 index a6308ac3..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_f.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000131226050E112626262612020E1104268C -:100010001D1A1A260F0E080D131226050E1126267C -:1000200012020E110426000D2604171311002601DA -:100030000E0D141226050E111214020204121205DE -:10004000140B2626000213080E0D26000600080DCC -:10005000121326080D150003041112262608122675 -:100060001104160011030403261608130726000DB9 -:10007000260417131100260B001904112606140D6F -:1000800026050E11261D1A1A1A1A260F0E080D1310 -:100090001226DB02E604C2D4103A213EE60FFE0F20 -:1000A000C03AEB20F5DB0207DACE10F1C6032732A7 -:1000B000EB20CD4719AF32213EC91F1A0F26020E81 -:1000C000080D2627261D2602110403081312F1C667 -:1000D00005C3AE103E0F32213EC912140F041108A1 -:1000E0000E112626080D15000304111201CD17CD9F -:1000F000EC11CD5618D8C50E12CDF308C1C3F210BD -:10010000C2321AC5D5E53A6720672EFE3A7E1B96A5 -:10011000FEF7D217113EF8327E20E1D1C1D306C9D5 -:1001200000003A4023A7CA0001FA84113A9420EE55 -:1001300008329420D3032A44230603CD24142A44EE -:100140002311FCFF19224423CD471A7DE61FFE042C -:10015000C27B11112000197EA7CAFF113E01321582 -:1001600020210000224623AF3240233241233A941B -:1001700020E6F7329420D303C30001FE03C2FF112F -:10018000AF3241233A4623A7C29A112F324023238C -:10019000224423112000192246230608CDFA18AF65 -:1001A0002A4623772A442377214023357EE607CA4F -:1001B00061111120002A4623192246232A442311C3 -:1001C000E0FF19224423EB3A1B20FE30CADF112A3C -:1001D0001A20CD471A01E00109CD3000CA5C112A6E -:1001E000442336FF2A462336FFC30001C50E1A2AD0 -:1001F000A71F237EFEC9CC5F070DC2F211C1C92A19 -:100200004423CD501411B31C0603CD3914C300018F -:100210003A4323A7C230123241233A8C20A7FA2650 -:10022000123E01C328123EFF3248233E01324323CF -:100230003DC25512CD7212CA82123A41233C32415C -:1002400023FE04C23C073E02324323AF3242233234 -:100250004123C33C07CD7212CA8912AF3241233AFF -:1002600042233C324223FE04C23C07AF324223C346 -:100270003C072A8920CD471A7DD6116F0610CDC7BD -:1002800015C9AF324123C33C07AF3242233A412361 -:100290003C324123D607C23C073241233A4023A7D0 -:1002A000C23C073A6520B72A892011F70219224477 -:1002B000233E01324023C33C07C50E0F2A721FC3E1 -:1002C000F2112A8D202C7DFE63DACE122E54228D5F -:1002D00020C9AF324323C342072140230640AF77F2 -:1002E0002305C2DF12C35619C53A8220FE01CA9FF8 -:1002F000134FE5CDCA097EE1814F3A642081B7E210 -:100300009F13E53A6720672EFE7EFE04FA11133E26 -:1003100003074F060021A313094E2346C52A642074 -:10032000CD471A7CC1E1B9FA9F13B8F29F137DA79C -:10033000FA9F13FE37F29F132BF5FE00CA6C13FED3 -:100340000BCA6C13FE16CA6C13FE21CA6C13FE2C6A -:10035000CA6C137E3601FE00C26C13E52A642011BC -:1003600000F01911AB130610CD6914E1F12323FE3F -:100370000ACA9F13FE15CA9F13FE20CA9F13FE2BA5 -:10038000CA9F13FE36CA9F137E3601FE00C29F131A -:100390002A64201100101911AB130610CD6914C185 -:1003A000C35F0A33312C372A39283B000000000094 -:1003B000000972DC72090000000000CDC113C313F4 -:1003C00017CDCA097E23666F292929297CC9E5D55D -:1003D000110004193E1ACDFF08D1E1C3AD09EB6E3F -:1003E000260079B7CAEC13293DC2E713EBC9CD50FB -:1003F0001479F50E00F1F5D5C54FCDDE13C17BA6FE -:10040000CA05140E017BB677237AA6CA10140E0112 -:100410007AB677111F0019D11305C2F513F179329D -:100420006120C900CD5014C5E5AF77237723E101E2 -:10043000200009C105C22714C9C51A77130120007D -:1004400009C105C23914C9CDB60ACDD609C3DF1812 -:100450007DE6074FC506037C1F677D1F6F05C257EA -:10046000147CE63FF62067C1C9CD5414C5011F00B6 -:100470001A7723137009C105C26C14C9C5E57E1231 -:1004800013230DC27E14E101200009C105C27C14B2 -:10049000C9CD5014D5CDDE137BB677237AB677114C -:1004A0001F0019D11305C29414C9CD5014D5CDDE47 -:1004B000137B2FA677237A2FA677111F0019D1134C -:1004C00005C2AD14C9000000000000AFC5770120CF -:1004D0000009C105C2CC14C93A2520FE05C8FE0298 -:1004E000C03A2920FED847D230153A0220A7C87852 -:1004F000FECED27915C606473A0920FE90D20415E1 -:10050000B8D2301568CD62153A2A2067CD6F152212 -:1005100064203E05322520CD81157EA7CA301536D0 -:1005200000CDE812CD3B1ACD69143E10320320C92C -:100530003E03322520C34A1521032035C02A6420FA -:100540000610CD24143E04322520AF32022006F7D7 -:10055000C3DC19000E00BCD49015BCD0C6100CC36F -:100560005A153A092065CD54154105DE106FC93A78 -:100570000A20CD5415DE1067C93E01328520C345DF -:100580001578070707808080813D6F3A672067C92B -:100590000CC610FA9015C93A0D20A7C2B71521A4B0 -:1005A0003ECDC515D006FE3E01320D207832082022 -:1005B0003A0E20320720C9212425CDC515D0CDF112 -:1005C00018AFC3A91506177EA7C26B162305C2C7AD -:1005D00015C900000000000000000000000000003D -:1005E000000000000000000000000000000000000B -:1005F000000000CD11160100377EA7CAFF150C239D -:1006000005C2F91579328220FE01C0216B20360126 -:10061000C92E003A672067C93A1520FEFFC0211095 -:10062000207E2346B0C03A2520A7C03AEF20A7CAB3 -:1006300052163A2D20A7C24816CDC017E610C83E64 -:1006400001322520322D20C9CDC017E610C0322D31 -:1006500020C921252036012AED20237DFE7EDA6384 -:10066000162E7422ED207E321D20C937C9AFCD8BE6 -:100670001ACD10193600CDCA092311F5201ABE1B58 -:100680002B1ACA8B16D29816C38F16BED298167E16 -:100690001213237E12CD50193ACE20A7CAC91621B3 -:1006A000032811A61A0E14CD930A2525061B3A67B6 -:1006B000200FDAB716061C78CDFF08CDB10ACDE7BA -:1006C000187EA7CAC916C3ED0221182D11A61A0E4D -:1006D0000ACD930ACDB60ACDD609AF32EF20D305A5 -:1006E000CDD119C3890B310024FBAF321520CDD8F1 -:1006F000140604CDFA18CD590AC2EE16CDD7192129 -:100700000127CDFA19AFCD8B1A06FBC36B19CDCAE1 -:1007100009237E11B81C21A11A0E04471AB8D2274A -:100720001723130DC21C177E32CF20C93A2520FE95 -:1007300000C2391706FDC3DC190602C3FA1800000F -:10074000219B2035CC6D173A6820A7CA6D172196DA -:100750002035C02198207ED3053A8220A7CA6D1784 -:100760002B7E2B772B36013E04329B20C93A9820F2 -:10077000E630D305C93A9520A7CAAA1721111A1144 -:10078000211A3A8220BED28E172313C385171A323C -:1007900097202198207EE630477EE60F07FE10C2A4 -:1007A000A4173E01B077AF32952021992035C006BD -:1007B000EFC3DC1906EF2198207EA077D305C9008E -:1007C0003A67200FD2CA17DB01C9DB02C9182960BA -:1007D0001F1629B01D1429A11CFF0E29ED1D0C297F -:1007E000DA100A29C21DFFC602F5DB0207DAF41788 -:1007F000F1C602C9F1C9AF32E02132E022C3D60905 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex deleted file mode 100644 index cf7f462f..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_g.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000AF32C120CDCF013A67200FDA7208CD138D -:1000100002CDCF01CDB100CDD1190620CDFA18CD3A -:100020001816CD0A19CDF315CD88093A8220A7CA32 -:10003000EF09CDBB13CD3509CDD808CD2C17CD593F -:100040000ACA49080604CDFA18CD7517D306CD049F -:1000500018C31F0800000011BA1ACDF3080698DB78 -:10006000010F0FDA6D080FDA9807C37F073E01C34F -:100070009B07CD1A02C314083A0820472A0920EB2F -:10008000C386080000003A6720672EFCC921112BA7 -:1000900011701B0E0ECDF3083A67200F3E1C211184 -:1000A00037D4FF083EB032C0203AC020A7C8E604CB -:1000B000C2BC08CDCA09CD3119C3BD0B0630211C05 -:1000C000263A67200FDACB08211C38CDCB14C3A900 -:1000D00008DB02E601C3E7173A8220FE0CD03EF9A6 -:1000E000327E20C93ACE20A7C0211C380630C3CBAF -:1000F000140E031AD5CDFF08D1130DC2F308C91190 -:10010000001EE526006F29292919EBE10608D30610 -:10011000C339143A0920FE78D02A91207DB4C2292F -:10012000092100063E013283202B229120C9CD11E6 -:10013000162EFF7EC9CD10192B2B7EA7C80650DBCB -:10014000020700D248090630CDC1130000B8D8CD4F -:100150002E09347EF521012524243DC258090610BC -:1001600011601CCD3914F13CCD8B1ACD10192B2BFD -:1001700036003EFF3299200610C3FA1821A01DFE5A -:1001800002D823FE04D823C9CDCA093AF120A7C852 -:10019000AF32F120E52AF220EBE17E8327775F235F -:1001A0007E8A277757237E23666FC3AD097ACDB247 -:1001B000097BD5F50F0F0F0FE60FCDC509F1E60F3F -:1001C000CDC509D1C9C61AC3FF083A67200F21F867 -:1001D00020D821FC20C92102243600237DE61FFE01 -:1001E0001CDAE809110600197CFE40DAD909C9CDEC -:1001F0003C0AAF32E920CDD6093A6720F5CDE401BB -:10020000F13267203A672067E52EFE7E3C77FE01DB -:10021000CCB319CD151800007EE12EFC77233638BB -:100220007C0FDA330A3E21329820CDF501CD041936 -:10023000C30408CDEF01CDC001C30408CD590AC2E3 -:10024000520A3E3032C0203AC020A7C8CD590ACA4F -:10025000470ACD590AC2520AC93A1520FEFFC93AC7 -:10026000EF20A7CA7C0A480608CDFA184178CD7C51 -:10027000097E21F32036002B772B3601216220C91D -:100280003E0232C120D3063ACB20A7CA850AAF323C -:10029000C120C9D51ACDFF08D13E0732C0203AC0CF -:1002A000203DC29E0A130DC2930AC9215020C34BA0 -:1002B000023E40C386193E80C3D70AE1C372003AAA -:1002C000C1200FDABB0A0FDA68180FDAAB0AC900CF -:1002D0000000000000000032C0203AC020A7C2DAAF -:1002E0000AC921C220060CC3321AAFD303D305CDED -:1002F0008219FBCDB10A3AEC20A72117300E04C2B7 -:10030000E80B11FA1CCD930ACDB10ACD7F0C3A90BF -:100310001FCD640E0000003AEC20A7C24A0B1195D5 -:100320001ACDE20ACD800A11B01BCDE20ACD800AB7 -:10033000CDB10A11C91FCDE20ACD800ACDB10A2183 -:10034000B733060ACDCB14CDB60ACDDD0E3AFF2168 -:10035000A7C25D0BCDD10832FF21CD7F1ACDE401BC -:10036000CDC001CDEF01CD1A023E0132C120CDCF6B -:1003700001CD1816CDF10BD306CD590ACA710BAFBA -:10038000322520CD590AC2830BAF32C120CDB10A2C -:10039000CDD6090E0C21112C11901FCDF3083AEC8B -:1003A00020FE00C2AE0B2111333E02CDFF08CD2C42 -:1003B0000CCD501FC3C60BC5CDF308C1C9CD630C0E -:1003C000CDE408C3A9083AEC20FE00C2DA0B11D52F -:1003D0001FCDE20ACD800ACD9E1821EC207E3CE69E -:1003E0000177CDD609C3340F11AB1DCD930AC308D5 -:1003F0000BCD0A19C39A193EC0C3D70A01183AEBAC -:1004000020FE99CA3E00F5DB0207D2140CF1C601AA -:1004100027C338003A013EFE07C2230CAF32013E2B -:10042000C30D0C3E0732013EF1C33E00DB0207D292 -:10043000380C116E0FC33B0C117E0F210F2A0E10CA -:10044000CDF308DB020F0FD8210D2811BA100E14BE -:10045000CDF308DB0207D0210D3311F81E0608C3C7 -:10046000391498CD1A19211C3DCD750C211C34CDA1 -:10047000750C211C2B11D01E0608D306C33914118C -:10048000F80C21152E0640CD3914D30611380D2154 -:10049000142E0640CD3914CDB10A11780D21122E3B -:1004A0000640CD391411B80D21112E0640CD391456 -:1004B000CDB10A11FA0D210F2B066ACD3914D306DE -:1004C00011730E210E2B066ACD3914CDB10A11F32A -:1004D0001F210B300E04CD930A21092911E11F0EB3 -:1004E00012CD930AC3B60A1826D80F1326F00F0EA2 -:1004F00026081009262010FF003C7EC3C3C3C3C3D7 -:10050000C37130000000FFFF000000000000FFFF8B -:10051000000000FFFFC3C3C3C3C3C37E3C00000091 -:10052000FFFFC3C3C3C3C3C3C0C0000000FFFFC3FA -:10053000C3C3C3C3C37E3C000030380C0C0C0C0C8E -:100540000CF8F0000000F0F81C0C0C0C0C1CF8F07F -:10055000000000FCFC0000000000000000000000A3 -:10056000FCFC0C0C0C0C0C0C0C0C000000FCFC003B -:1005700000C0C030300C0C0000FFFFC3C3C3C3C3B6 -:10058000C3C0C0000000071F3870C0C070381F070C -:10059000000000FFFFC3C3C3C3C3C37E3C00000011 -:1005A000C0C0C0C0FFFFC0C0C0C0000000FFFF034C -:1005B0000303030303FFFF0000FCFC0C0C0C0C0CFA -:1005C0000C0C0C000000FCFCC0C0C0C0C0C0FCFC97 -:1005D000000000FCFC0000C0C030300C0C0000002B -:1005E00000000000FCFC00000000000000FCFC001B -:1005F0000000000000FCFC005E0F0000000000C0D6 -:10060000C0C0C0FFFFC0C0C0C0000000FFFF0C0C96 -:1006100003030000FFFF000000FFFF0000000000D8 -:1006200000FFFF000000071F3870C0C070381F07B0 -:100630000000003C7EC3C3C3C3C3C37130000000CD -:10064000C0C0C0C0FFFFC0C0C0C00000003F7FC02E -:10065000C0C0C0C0C07F3F000000FFFF0C0C030300 -:100660000000FFFF1E0A2AF80D4E1DCA0018812344 -:10067000C3690E00000000000C0C0C0CFCFC0C0C00 -:100680000C0C000000FCFC00000000C0C0FCFC00E2 -:100690000000C0C030300C0C3030C0C0000000FC86 -:1006A000FCC0C0C0C0C0C0FCFC00000030380C0C56 -:1006B0000C0C0C0CF8F00000000C0C0C0CFCFC0CEE -:1006C0000C0C0C000000F0F80C0C0C0C0C0CF8F0EE -:1006D000000000FCFC00000000C0C0FCFCCDD609FE -:1006E0002116280E14118E0FCD560F0E122114292B -:1006F000CD560F211229CD560F211029CD560F218D -:100700000D291138100E12CDB70B210B29CDB70BC7 -:10071000210929CDB70B210729CDB70B210529CDFB -:10072000B70B21052E0608DB020700D29C1FCDF770 -:100730000BC3D609012718CD5618DA430FCD44183C -:10074000C3370F01E70CCD5618DA4714C50E18CD84 -:10075000930AC1C3460FC5CD930AC1C9020E0C0F3F -:10076000041308130815042626150803040E1B2677 -:10077000020E080D26261B260211040308131C0274 -:100780000E080D122627261B02110403081313005E -:100790000A04260E15041126020E0C0C000D032669 -:1007A0000E050400111307260100120426000D0394 -:1007B00026141204180E141126120A080B0B261305 -:1007C0000E2612130E0F130704260400111307261A -:1007D000080D150012080E0D262612020E11042611 -:1007E0001B1A1A260F0E080D131226050E112626A7 -:1007F000262612020E1104261C1A1A260F0E080DA8 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex deleted file mode 100644 index d334786f..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/roms/earthinv_h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000000C3D4180F141207F5C5D5E5C38C000042 -:10001000F5C5D5E53E8032722021C02035CD921045 -:10002000DB010FDA67003AEA20A7CA4200C3FE0BE1 -:100030007CBAC07DBBC9000032EB20CD4719AF327E -:10004000EA203AE920A7CA82003AEF20A7C26F004F -:100050003AEB20A7C25D00CDBF0AC382003A9320CD -:10006000A7C28200C365073E0132EA20C33F00CD2C -:1000700040173A3220328020CD2211CD4802CD13D4 -:100080000900CDC212E1D1C1F1FBC900AF3272202B -:100090003AE920A7CA82003AEF20A7C2A5003AC1D8 -:1000A000200FD28200212020CD4B02CD4101C382FE -:1000B00000CD8608E57E23666F220920220B20E111 -:1000C0002B7EFE03C2C8003D320820FEFE3E00C269 -:1000D000D3003C320D20C93E0232FB2132FB22C349 -:1000E000E4082A132011651B2319EBC3321A0308F5 -:1000F000120F0B00182626020E0F18110806071300 -:100100002102207EA7C23815E53A06206F3A672003 -:10011000677EA7E1CA360123237E2346E6FE070752 -:10012000075F160021001C19EB78A7C43B012A0BBE -:10013000200610CD6914AF320020C921300019EB20 -:10014000C93A6820A7C83A0020A7C03A6720673A92 -:10015000062016023CFE37CCA1016F4605C25401B1 -:10016000320620CD7A0161220B207DFE28DA71193A -:100170007A3204203E01320020C916007D21092078 -:1001800046234EFE0BFA9401DE0B5F78C610477BC8 -:1001900014C3830168A7C85F79C6104F7B3DC39520 -:1001A0000115CACD012106203600234E3600CDD9D7 -:1001B000012105207E3CE60177AF21672066C9005A -:1001C000210021063736012305C2C501C9E1C93E18 -:1001D0000106E0210224C3CC142346237986772329 -:1001E000788677C906C011001B210020C3321A216E -:1001F0004221C3F8012142220E0411201DD5062CF4 -:10020000CD321AD10DC2FD01C93E01C31B023E0110 -:10021000C31402AF114222C31E02AF114221328128 -:10022000200102162106283E04F5C53A8120A7C206 -:100230004202CD691AC1F13DC8D511E00219D1C3FE -:100240002902CD7C14C335022110207EFEFFC8FE9A -:10025000FECA810223464FB079C27702237EA7C22D -:100260008802235E2356E5EBE5216F02E3D5E9E141 -:10027000110C0019C34B020504C27D023D05702B11 -:100280007711100019C34B02352B2BC38102E123D8 -:100290007EFEFFCA3B032335C047AF326820326978 -:1002A000203E30326A207836052335C29B032A1A55 -:1002B000200610CD241421102011101B0610CD3261 -:1002C0001A0600CDDC193A6D20A7C03AEF20A7C866 -:1002D000310024FBCDD719CD2E09A7CA6D16CDE765 -:1002E000187EA7CA2C033ACE20A7CA2C033A67204F -:1002F000F50FDA3203CD0E02CD78087323722B2B63 -:100300007000CDE401F10F3E210600D21203062059 -:100310003E22326720CDB60AAF32112078D3053C99 -:10032000329820CDD609CD7F1AC3F907CD7F1AC3E5 -:100330001708CD0902C3F802000000216820360129 -:10034000237EA7C3B003002B36013A1B20473AEFA8 -:1003500020A7C263033A1D200FDA81030FDA8E0350 -:10036000C36F03CDC0170707DA810307DA8E0321B5 -:100370001820CD3B1ACD471ACD39143E0032122039 -:10038000C978FED9CA6F033C321B20C36F0378FEC5 -:1003900030CA6F033D321B20C36F033CE6013215A8 -:1003A000200707070721701C856F221820C36F03E1 -:1003B000C24A032335C24A03C34603112A20CD068D -:1003C0001AE1D0237EA7C8FE01CAFA03FE02CA0AB8 -:1003D0000423FE03C22A0435CA36047EFE0FC0E59C -:1003E000CD3004CDAA14E12334232335352335350C -:1003F00035233608CD3004C391143C773A1B20C610 -:1004000008322A20CD3004C39114CD3004D5E5C57F -:10041000CDAA14C1E1D13A2C20856F322920CDEE2E -:10042000133A6120A7C8320220C9FE05C8C33604AA -:10043000212720C33B1ACD3004CDAA142125201139 -:10044000251B0607CD321A00000000000000000046 -:100450000000000000002A8F202C228F203A8420E8 -:10046000A7C07EE601012902C26E0401E0FE218AD6 -:100470002071232370C9E13A321B3232202A3820FE -:100480007DB4C28A042B223820C91135203EF9CD13 -:1004900050053A46203270203A5620327120CD6302 -:1004A000053A7820A7213520C25B0511301B213089 -:1004B000200610C3321AE13A6E20A7C03A8020FE0F -:1004C00001C01145203EEDCD50053A362032702056 -:1004D0003A5620327120CD63053A7620FE10DAE7D5 -:1004E000043A481B3276203A7820A7214520C25B87 -:1004F0000511401B2140200610CD321A3A82203DC2 -:10050000C208053E01326E202A7620C37E06E11124 -:1005100055203EDBCD50053A46203270203A362039 -:10052000327120CD63053A7620FE15DA34053A584B -:100530001B3276203A7820A7215520C25B05115046 -:100540001B2150200610CD321A2A7620225820C9AD -:10055000327F20217320060BC3321A117320060B41 -:10056000C3321A2173207EE680C2C1053AC120FE43 -:10057000043A6920CAB705A7C82336003A7020A7F5 -:10058000CA8905473ACF20B8D03A7120A7CA960544 -:10059000473ACF20B8D0237EA7CA1B062A76204E22 -:1005A0002300227620CD2F06D0CD7A0179C60767A9 -:1005B0007DD60A6F227B202173207EF6807723343C -:1005C000C9117C20CD061AD0237EE601C244062341 -:1005D00034CD75063A7920C603217F20BEDAE205C4 -:1005E000D60C3279203A7B20473A7E2080327B201D -:1005F000CD6C063A7B20FE15DA12063A6120A7C8B8 -:100600003A7B20FE1EDA1206FE2700D2120697322F -:1006100015203A7320F601327320C93A1B20C60810 -:1006200067CD6F1579FE0CDAA5050E0BC3A5050D78 -:100630003A6720676916057EA737C07DC60B6F1520 -:10064000C23706C9217820357EFE03C26706CD7504 -:100650000621DC1C227920217C2035352B35353EC6 -:1006600006327D20C36C06A7C0C37506217920CD54 -:100670003B1AC3EE13217920CD3B1AC3AA1422489A -:1006800020C9E13A8020FE02C02183207EA7CA0F44 -:10069000053A5620A7C20F05237EA7C2AB063A82B1 -:1006A00020FE02DA0F053601CD3C07118A20CD0667 -:1006B0001AD02185207EA7C2D606218A207E232338 -:1006C00086328A20CD1012218A207EFE28DAF90691 -:1006D000FEE1D2F906C906FECDDC1923357EFE1FE8 -:1006E000CA4B07FE18CA0C07A7C006EF2198207E48 -:1006F000A077E620D305000000CDD212CDCB142187 -:100700008320060ACD5F0706FEC3DC193E0132F1E5 -:10071000202A8D20460E0421501D114C1D1AB8CAE6 -:10072000280723130DC21D077E3287202600682963 -:1007300029292922F220CDD212C3F108CD4207C3C4 -:100740003914218720CD3B1AC3471A06102198205F -:100750007EB077CD7017217C1D228720C33C071106 -:10076000831BC3321A3E01329320310024FBCD7922 -:1007700019CDF6172113301104000E04CDF3083AF9 -:10078000EB203D2110280E14C2570811CF1ACDF3CB -:1007900008DB01E604CA7F070699AF32CE203AEBA8 -:1007A00020802732EB20CD471921000022F820229B -:1007B000FC20CD2519CD2B19CDD7192101017C3273 -:1007C000EF2022E72022E520CDD912CDEF01CDF593 -:1007D00001CDD10832FF2132FF22CDD700AF32FE4A -:1007E0002132FE22CDC001CD041921783822FC210E -:1007F00022FC22CDE401CD7F1ACD8D08CDD6090093 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Super Earth Invasion_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt deleted file mode 100644 index 04cbfbca..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Vortex port to MiST by Gehstock --- 08 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- - -ToDo Sound - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Release/Vortex.rbf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Release/Vortex.rbf deleted file mode 100644 index dee3424e..00000000 Binary files a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Release/Vortex.rbf and /dev/null differ diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf deleted file mode 100644 index 8bec1592..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:15:41 June 05, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "16:15:41 June 05, 2019" - -# Revisions - -PROJECT_REVISION = "Vortex" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf deleted file mode 100644 index b86690cb..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/Vortex.qsf +++ /dev/null @@ -1,176 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:00:39 August 08, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Vortex_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Vortex_memory.sv -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VHDL_FILE rtl/roms/1.t36.vhd -set_global_assignment -name VHDL_FILE rtl/roms/2.t35.vhd -set_global_assignment -name VHDL_FILE rtl/roms/3.t34.vhd -set_global_assignment -name VHDL_FILE rtl/roms/4.t33.vhd -set_global_assignment -name VHDL_FILE rtl/roms/5.t32.vhd -set_global_assignment -name VHDL_FILE rtl/roms/6.t31.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY Vortex_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------- -# start ENTITY(Vortex_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Vortex_mist) -# ----------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat deleted file mode 100644 index ac9bf0a8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/clean.bat +++ /dev/null @@ -1,16 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s build_id.v -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv deleted file mode 100644 index 46ef1be8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_memory.sv +++ /dev/null @@ -1,80 +0,0 @@ - -module Vortex_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; -wire [7:0]rom_data_5; -wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]}; - -rom1t36 rom1t36 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_0) -); - -rom2t35 rom2t35 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_1) -); - -rom3t34 rom3t34 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_2) -); - -rom4t33 rom4t33 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_3) -); - -rom5t32 rom5t32 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_4) -); - -rom6t31 rom6t31 ( - .clk(Clock), - .addr(rom_addr), - .data(rom_data_5) -); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4; - 5'b01001 : Rom_out = rom_data_5; - default : Rom_out = 8'b00000000; - endcase -end - -spram #( - .addr_width_g(13), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[12:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv deleted file mode 100644 index a2b52c05..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/Vortex_mist.sv +++ /dev/null @@ -1,191 +0,0 @@ -module Vortex_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Vortex;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hs, vs; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft(~m_left), - .MoveRight(~m_right), - .MoveUp(~m_up), - .MoveDown(~m_down), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(hs), - .VSync(vs) - ); - -Vortex_memory Vortex_memory ( - .Clock(clk_core), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_core), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({Video,Video,Video}), - .G({Video,Video,Video}), - .B({Video,Video,Video}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .ce_divider(0), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd deleted file mode 100644 index 40003ea4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,283 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft : in std_logic; - MoveRight : in std_logic; - MoveUp : in std_logic; - MoveDown : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; - signal GDB_A : unsigned(1 downto 0); -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - --- with AD_i(9 downto 8) select --- GDB <= GDB0 when "00", --- GDB1 when "01", --- GDB2 when "10", --- S when others; - - GDB_A <= not AD_i(9) & AD_i(8); - - with GDB_A select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - - GDB0(0) <= '1';--IPT_UNKNOWN - GDB0(1) <= '1';--IPT_UNKNOWN - GDB0(2) <= '1';--IPT_UNKNOWN - GDB0(3) <= '1';--IPT_UNKNOWN - GDB0(4) <= '1';--IPT_UNKNOWN - GDB0(5) <= '1';--IPT_UNKNOWN - GDB0(6) <= '1';--IPT_UNKNOWN - GDB0(7) <= '1';--IPT_UNKNOWN - - GDB1(0) <= Coin; - GDB1(1) <= not Sel2Player; - GDB1(2) <= not Sel1Player; - GDB1(3) <= '1'; - GDB1(4) <= not Fire;--controller - GDB1(5) <= not MoveLeft;--controller - GDB1(6) <= not MoveRight;--controller - GDB1(7) <= '1'; - - GDB2(0) <= '0';--active high - GDB2(1) <= '0';--active high - GDB2(2) <= '0';--active high - GDB2(3) <= '0';--active high - GDB2(4) <= not Fire;--controller 2 - GDB2(5) <= not MoveLeft;--controller 2 - GDB2(6) <= not MoveRight;--controller 2 - GDB2(7) <= '0';--active low - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd deleted file mode 100644 index 97a42db7..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd deleted file mode 100644 index 5cd19142..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/1.t36.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom1t36 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom1t36 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"C2",X"27",X"19",X"2A",X"A7",X"7D",X"2A",X"C2",X"41",X"CD",X"C3",X"40",X"01",X"81",X"FE",X"7C", - X"13",X"20",X"44",X"23",X"E1",X"4D",X"00",X"C9",X"C3",X"19",X"1B",X"C6",X"01",X"3E",X"D6",X"32", - X"23",X"13",X"C2",X"0D",X"02",X"22",X"F3",X"C9",X"00",X"00",X"47",X"7E",X"77",X"1A",X"12",X"78", - X"20",X"F5",X"CA",X"A7",X"17",X"E4",X"A6",X"C3",X"CA",X"76",X"03",X"3D",X"93",X"C3",X"3A",X"02", - X"ED",X"C2",X"CD",X"1E",X"1F",X"92",X"1E",X"C3",X"C2",X"40",X"1F",X"54",X"92",X"CD",X"C9",X"1F", - X"20",X"E6",X"32",X"3C",X"20",X"E6",X"51",X"C3",X"CD",X"1F",X"15",X"D2",X"D2",X"C3",X"3A",X"1D", - X"51",X"C3",X"3A",X"02",X"20",X"E4",X"32",X"3C",X"3A",X"02",X"20",X"E5",X"32",X"3C",X"20",X"E5", - X"32",X"3C",X"20",X"E3",X"51",X"C3",X"21",X"02",X"20",X"E4",X"51",X"C3",X"3A",X"02",X"20",X"E3", - X"E4",X"32",X"21",X"20",X"21",X"C0",X"00",X"C9",X"21",X"00",X"32",X"97",X"20",X"E3",X"97",X"C9", - X"E5",X"20",X"CD",X"D5",X"15",X"B4",X"E1",X"D1",X"00",X"00",X"11",X"00",X"20",X"B0",X"D3",X"2A", - X"15",X"96",X"DE",X"C3",X"3A",X"15",X"20",X"E1",X"D6",X"3A",X"A7",X"20",X"D9",X"C2",X"CD",X"03", - X"20",X"E0",X"CA",X"A7",X"04",X"EE",X"CC",X"C3",X"CA",X"A7",X"04",X"EE",X"A1",X"C3",X"3A",X"01", - X"11",X"06",X"14",X"00",X"06",X"CD",X"11",X"15",X"3A",X"01",X"20",X"F6",X"0A",X"FE",X"D6",X"DA", - X"B4",X"CD",X"3A",X"15",X"20",X"D6",X"01",X"FE",X"20",X"B0",X"F0",X"21",X"22",X"32",X"20",X"D3", - X"15",X"96",X"32",X"97",X"20",X"D1",X"DA",X"32",X"1C",X"CA",X"C3",X"03",X"03",X"78",X"CD",X"00", - X"20",X"E8",X"02",X"3E",X"32",X"00",X"20",X"F5",X"32",X"20",X"20",X"D7",X"D9",X"32",X"32",X"20", - X"20",X"D2",X"02",X"3E",X"DD",X"32",X"32",X"20",X"05",X"3E",X"00",X"32",X"3E",X"20",X"32",X"10", - X"32",X"01",X"20",X"D8",X"32",X"97",X"20",X"D6",X"20",X"CF",X"10",X"3E",X"D5",X"32",X"3E",X"20", - X"97",X"13",X"F6",X"32",X"C3",X"20",X"08",X"EE",X"D0",X"32",X"00",X"20",X"00",X"00",X"66",X"C3", - X"03",X"1C",X"9E",X"C3",X"D5",X"03",X"C3",X"C5",X"12",X"FE",X"94",X"C2",X"78",X"03",X"C2",X"A7", - X"4E",X"CA",X"3E",X"03",X"47",X"20",X"E8",X"3A",X"02",X"C1",X"00",X"06",X"03",X"DB",X"08",X"E6", - X"3E",X"20",X"C3",X"22",X"03",X"60",X"20",X"3E",X"A7",X"20",X"5E",X"CA",X"3D",X"03",X"E8",X"32", - X"00",X"20",X"02",X"3E",X"E8",X"32",X"21",X"20",X"D3",X"B0",X"C3",X"01",X"05",X"89",X"DA",X"32", - X"60",X"01",X"C3",X"00",X"03",X"8E",X"48",X"CD",X"20",X"EA",X"C3",X"34",X"16",X"41",X"00",X"00", - X"D3",X"20",X"C3",X"01",X"00",X"C3",X"8D",X"21",X"C3",X"0B",X"00",X"F7",X"33",X"CA",X"3E",X"13", - X"E6",X"7D",X"C3",X"1F",X"03",X"30",X"09",X"EB",X"5D",X"31",X"46",X"54",X"7E",X"23",X"47",X"B0", - X"11",X"32",X"20",X"B0",X"E7",X"C3",X"21",X"02",X"FE",X"7C",X"C2",X"34",X"03",X"91",X"F0",X"21", - X"0C",X"11",X"21",X"01",X"22",X"C0",X"0C",X"06",X"00",X"00",X"EB",X"22",X"22",X"20",X"20",X"DB", - X"00",X"21",X"36",X"24",X"23",X"00",X"FE",X"7C",X"97",X"EF",X"CE",X"32",X"C9",X"22",X"04",X"D3", - X"3E",X"00",X"D3",X"24",X"3A",X"01",X"20",X"AF",X"C2",X"40",X"03",X"CB",X"00",X"C9",X"00",X"00", - X"C3",X"20",X"13",X"AE",X"32",X"97",X"20",X"AF",X"FF",X"FE",X"96",X"CA",X"3C",X"13",X"AF",X"32", - X"E6",X"7B",X"5F",X"E0",X"C3",X"19",X"17",X"B3",X"00",X"3E",X"01",X"D3",X"50",X"C3",X"57",X"4A", - X"C5",X"F3",X"E5",X"D5",X"C3",X"F5",X"02",X"37",X"31",X"F3",X"20",X"A0",X"C3",X"97",X"48",X"00", - X"06",X"C5",X"0E",X"A0",X"0D",X"A0",X"1D",X"C2",X"1F",X"C3",X"C2",X"40",X"00",X"28",X"00",X"C9", - X"77",X"1A",X"23",X"13",X"C3",X"05",X"00",X"13",X"05",X"00",X"04",X"D3",X"C5",X"C3",X"00",X"47", - X"06",X"20",X"21",X"0C",X"20",X"A4",X"00",X"11",X"A1",X"32",X"32",X"20",X"20",X"A2",X"A3",X"32", - X"CD",X"FB",X"09",X"43",X"00",X"00",X"D0",X"C3",X"EF",X"01",X"50",X"C3",X"CD",X"01",X"09",X"CB", - X"21",X"40",X"08",X"06",X"21",X"EF",X"21",X"80",X"11",X"06",X"01",X"18",X"08",X"06",X"21",X"EF", - X"06",X"EF",X"21",X"05",X"20",X"F6",X"21",X"EF",X"08",X"06",X"21",X"EF",X"21",X"C0",X"08",X"06", - X"22",X"00",X"01",X"21",X"36",X"20",X"23",X"00",X"00",X"00",X"ED",X"22",X"3E",X"20",X"32",X"05", - X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"FE",X"7D",X"DA",X"24",X"00",X"7D",X"C6",X"CD", - X"04",X"D3",X"AE",X"CD",X"3A",X"1E",X"20",X"F5",X"00",X"00",X"27",X"21",X"22",X"00",X"20",X"03", - X"C2",X"02",X"00",X"98",X"39",X"C3",X"32",X"00",X"C2",X"A7",X"03",X"42",X"EF",X"3A",X"FE",X"20", - X"C3",X"20",X"00",X"30",X"F5",X"3A",X"A7",X"20",X"20",X"E8",X"B9",X"C3",X"00",X"06",X"F5",X"32", - X"A7",X"20",X"D3",X"C2",X"2A",X"00",X"20",X"A5",X"84",X"C3",X"C5",X"03",X"E5",X"D5",X"E2",X"3A", - X"00",X"20",X"11",X"FE",X"EA",X"D2",X"01",X"00",X"D6",X"C3",X"2A",X"00",X"20",X"A9",X"01",X"78", - X"01",X"00",X"2A",X"CD",X"A7",X"13",X"4A",X"C2",X"00",X"50",X"0E",X"FE",X"EA",X"D2",X"01",X"00", - X"C1",X"D1",X"28",X"3E",X"31",X"C3",X"00",X"13",X"22",X"01",X"20",X"A5",X"40",X"CD",X"E1",X"0B", - X"00",X"38",X"00",X"00",X"30",X"5D",X"18",X"00",X"00",X"2F",X"00",X"00",X"00",X"25",X"00",X"00", - X"3E",X"82",X"13",X"00",X"2F",X"87",X"13",X"00",X"27",X"41",X"1A",X"00",X"35",X"01",X"1A",X"00", - X"3E",X"FC",X"12",X"00",X"2F",X"95",X"12",X"00",X"28",X"FC",X"12",X"00",X"36",X"92",X"12",X"00", - X"08",X"00",X"88",X"48",X"00",X"C8",X"01",X"00",X"28",X"F9",X"11",X"00",X"2F",X"92",X"11",X"00", - X"C9",X"C1",X"A9",X"22",X"C3",X"20",X"03",X"7E",X"00",X"FE",X"FF",X"00",X"C2",X"FF",X"00",X"1B", - X"C3",X"EF",X"00",X"45",X"75",X"21",X"C3",X"00",X"ED",X"21",X"11",X"20",X"01",X"3D",X"08",X"06", - X"FE",X"20",X"C2",X"01",X"01",X"FF",X"E0",X"3A",X"09",X"03",X"00",X"00",X"00",X"00",X"F1",X"3A", - X"3E",X"20",X"32",X"01",X"20",X"F5",X"C9",X"E1",X"A7",X"20",X"0C",X"CA",X"3D",X"06",X"E0",X"32", - X"E0",X"3A",X"A7",X"20",X"95",X"C2",X"CD",X"01",X"3A",X"00",X"20",X"E2",X"C2",X"A7",X"01",X"B2", - X"C3",X"20",X"01",X"A1",X"03",X"3E",X"8F",X"C3",X"05",X"DE",X"A1",X"C3",X"3D",X"01",X"E0",X"32", - X"11",X"40",X"0B",X"98",X"17",X"21",X"C3",X"2F",X"3E",X"04",X"32",X"01",X"20",X"E2",X"08",X"CD", - X"A7",X"20",X"F8",X"C2",X"CD",X"01",X"05",X"EC",X"01",X"D5",X"32",X"97",X"20",X"E2",X"E1",X"3A", - X"02",X"AD",X"00",X"00",X"0D",X"CD",X"11",X"40",X"E0",X"3A",X"A7",X"20",X"CC",X"C2",X"C3",X"01", - X"09",X"F1",X"73",X"CD",X"11",X"04",X"22",X"ED",X"0B",X"90",X"17",X"21",X"0E",X"2F",X"CD",X"08", - X"08",X"11",X"0E",X"23",X"CD",X"F7",X"05",X"CF",X"50",X"0E",X"22",X"CD",X"21",X"02",X"21",X"08", - X"32",X"3D",X"20",X"E1",X"CC",X"C3",X"00",X"01",X"01",X"3E",X"F5",X"32",X"C3",X"20",X"03",X"29", - X"15",X"0E",X"11",X"04",X"DE",X"CD",X"C3",X"05",X"06",X"18",X"06",X"C9",X"0C",X"00",X"26",X"04", - X"F1",X"CD",X"06",X"09",X"DF",X"06",X"C2",X"05",X"04",X"EE",X"00",X"21",X"C3",X"21",X"00",X"51", - X"15",X"21",X"0E",X"2A",X"C3",X"0F",X"05",X"44",X"06",X"1D",X"0E",X"C9",X"C3",X"15",X"05",X"44", - X"32",X"97",X"20",X"F5",X"53",X"C3",X"C2",X"05",X"01",X"3E",X"F5",X"32",X"C3",X"20",X"08",X"3F", - X"C3",X"06",X"05",X"27",X"41",X"CD",X"D3",X"40",X"05",X"1E",X"AD",X"3A",X"A7",X"20",X"38",X"CA", - X"40",X"CD",X"CD",X"0B",X"0B",X"48",X"22",X"C9",X"00",X"01",X"00",X"00",X"CD",X"00",X"0B",X"20", - X"3E",X"20",X"32",X"01",X"20",X"CD",X"C9",X"E1",X"20",X"D3",X"CE",X"3A",X"3C",X"20",X"CE",X"32", - X"06",X"12",X"CD",X"3A",X"A7",X"20",X"87",X"C2",X"32",X"00",X"22",X"CE",X"CD",X"32",X"C3",X"20", - X"E6",X"01",X"CA",X"80",X"06",X"6E",X"32",X"97",X"3A",X"06",X"20",X"CE",X"61",X"C3",X"DB",X"05", - X"77",X"FC",X"A5",X"C3",X"BC",X"18",X"B1",X"D2",X"20",X"CD",X"6E",X"C3",X"EB",X"06",X"E6",X"7E", - X"B5",X"D2",X"2F",X"06",X"85",X"3C",X"E0",X"FE",X"2F",X"06",X"84",X"3C",X"02",X"FE",X"BD",X"C9", - X"11",X"06",X"01",X"0C",X"C0",X"21",X"06",X"20",X"94",X"C9",X"A4",X"C3",X"95",X"06",X"AE",X"C3", - X"E6",X"20",X"A7",X"01",X"C3",X"C0",X"19",X"5C",X"EF",X"0C",X"C8",X"C3",X"3D",X"05",X"EE",X"32", - X"8F",X"CD",X"67",X"04",X"8D",X"CD",X"84",X"04",X"CB",X"CD",X"C3",X"09",X"04",X"BB",X"23",X"3E", - X"3F",X"C3",X"00",X"08",X"1C",X"00",X"FF",X"38",X"C3",X"67",X"0C",X"AA",X"CD",X"0A",X"09",X"CB", - X"FF",X"46",X"00",X"00",X"20",X"04",X"FF",X"FF",X"00",X"00",X"49",X"92",X"00",X"FF",X"62",X"00", - X"07",X"A0",X"07",X"B0",X"07",X"C0",X"07",X"D0",X"07",X"60",X"07",X"76",X"07",X"80",X"07",X"90", - X"40",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"40",X"01",X"00",X"40",X"FF",X"FF",X"40", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"50",X"88",X"FF",X"FF",X"50",X"88",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7C",X"10",X"10",X"FF",X"FF",X"10",X"10",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"08",X"14",X"22",X"FF",X"FF",X"14",X"22",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",X"04",X"04",X"FF",X"FF",X"04",X"04",X"00", - X"04",X"FF",X"FF",X"04",X"04",X"04",X"04",X"FF",X"0E",X"1F",X"0E",X"FF",X"FF",X"0E",X"04",X"0E", - X"1C",X"FF",X"FF",X"08",X"00",X"08",X"FF",X"FF",X"FF",X"04",X"00",X"04",X"FF",X"FF",X"1C",X"3E", - X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"38",X"7C",X"38",X"FF",X"FF",X"10",X"00",X"10", - X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"70",X"F8",X"70",X"FF",X"FF",X"20",X"00",X"20", - X"00",X"40",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"E0",X"FC",X"00",X"07",X"E0",X"FF",X"FF",X"40", - X"FF",X"00",X"00",X"80",X"FF",X"FF",X"FF",X"FF",X"E0",X"FE",X"03",X"3F",X"E0",X"FF",X"03",X"80", - X"FF",X"01",X"00",X"00",X"00",X"01",X"FF",X"FF",X"80",X"F0",X"03",X"1F",X"80",X"FF",X"03",X"00", - X"FF",X"02",X"00",X"00",X"00",X"02",X"FF",X"FF",X"00",X"80",X"07",X"0F",X"00",X"FF",X"07",X"00", - X"FF",X"12",X"20",X"20",X"11",X"12",X"40",X"FF",X"80",X"40",X"0B",X"07",X"20",X"FF",X"01",X"00", - X"86",X"CD",X"C3",X"0C",X"13",X"17",X"00",X"00",X"0C",X"C0",X"FF",X"08",X"11",X"FF",X"1C",X"B9", - X"14",X"CD",X"3C",X"48",X"F6",X"32",X"C9",X"20",X"48",X"CD",X"C3",X"0B",X"00",X"F7",X"A0",X"FE", - X"20",X"3E",X"EA",X"32",X"CD",X"20",X"40",X"3C",X"EA",X"3A",X"FE",X"20",X"DA",X"10",X"04",X"24", - X"04",X"0B",X"45",X"CD",X"00",X"40",X"00",X"00",X"CD",X"00",X"48",X"14",X"F6",X"3A",X"C3",X"20", - X"A7",X"20",X"40",X"CA",X"2A",X"04",X"20",X"A9",X"C8",X"C3",X"3A",X"18",X"20",X"E2",X"A5",X"2A", - X"4E",X"D2",X"01",X"04",X"03",X"00",X"EB",X"CD",X"EF",X"3A",X"01",X"20",X"02",X"00",X"01",X"FE", - X"A5",X"22",X"CD",X"20",X"0B",X"40",X"67",X"C3",X"3A",X"0B",X"20",X"E2",X"C2",X"A7",X"04",X"61", - X"01",X"0C",X"0C",X"06",X"C0",X"21",X"EF",X"20",X"22",X"04",X"20",X"A9",X"48",X"CD",X"11",X"0B", - X"04",X"75",X"C0",X"21",X"11",X"20",X"22",X"C0",X"C8",X"C3",X"06",X"18",X"DF",X"06",X"C2",X"05", - X"D3",X"C9",X"DB",X"00",X"3E",X"01",X"6F",X"12",X"10",X"0E",X"22",X"CD",X"21",X"02",X"20",X"ED", - X"D5",X"E5",X"80",X"11",X"19",X"00",X"D1",X"7E",X"30",X"E6",X"0F",X"0F",X"E6",X"B5",X"C9",X"0F", - X"20",X"3E",X"01",X"D3",X"41",X"CD",X"C3",X"40",X"A7",X"E1",X"2A",X"C2",X"C3",X"19",X"1B",X"C6", - X"38",X"C3",X"97",X"0B",X"EA",X"32",X"C3",X"20",X"00",X"4E",X"7E",X"23",X"00",X"BA",X"00",X"00", - X"46",X"CD",X"00",X"40",X"3E",X"00",X"32",X"05",X"00",X"AF",X"ED",X"32",X"32",X"20",X"20",X"EE", - X"88",X"CD",X"26",X"17",X"3A",X"20",X"22",X"00",X"22",X"00",X"3E",X"C9",X"32",X"01",X"20",X"DF", - X"88",X"CD",X"C3",X"17",X"01",X"62",X"40",X"C3",X"CD",X"6F",X"18",X"8D",X"32",X"97",X"20",X"DF", - X"46",X"41",X"CD",X"1A",X"41",X"3A",X"1A",X"46",X"11",X"48",X"20",X"A3",X"1A",X"46",X"3A",X"CD", - X"46",X"20",X"CD",X"1A",X"41",X"4A",X"1A",X"46",X"3A",X"CD",X"21",X"41",X"20",X"AB",X"A3",X"11", - X"4C",X"CD",X"CD",X"06",X"03",X"C6",X"06",X"3F",X"4A",X"CD",X"46",X"41",X"CD",X"1A",X"41",X"4A", - X"21",X"04",X"30",X"17",X"70",X"11",X"CD",X"0B",X"00",X"00",X"00",X"00",X"3F",X"C3",X"0E",X"06", - X"05",X"4A",X"CA",X"A7",X"06",X"38",X"2D",X"11",X"09",X"F1",X"AD",X"3A",X"FE",X"20",X"D2",X"02", - X"06",X"30",X"74",X"11",X"21",X"0B",X"28",X"13",X"C3",X"09",X"06",X"28",X"F1",X"CD",X"C3",X"09", - X"22",X"00",X"20",X"9F",X"C9",X"00",X"7A",X"C3",X"23",X"C3",X"31",X"06",X"20",X"9F",X"42",X"21", - X"80",X"E6",X"6E",X"C2",X"11",X"06",X"20",X"B0",X"FE",X"06",X"D2",X"04",X"06",X"6E",X"FF",X"3E", - X"FE",X"20",X"CA",X"01",X"05",X"BC",X"02",X"FE",X"D3",X"2A",X"CD",X"20",X"15",X"B4",X"CE",X"3A", - X"3A",X"06",X"20",X"E3",X"3A",X"47",X"20",X"E4",X"C2",X"CA",X"21",X"05",X"29",X"9A",X"5F",X"C3", - X"20",X"E6",X"A7",X"B0",X"A8",X"CA",X"C3",X"04",X"47",X"B0",X"E5",X"3A",X"B0",X"20",X"3A",X"47", - X"C9",X"21",X"32",X"97",X"20",X"E6",X"80",X"21",X"00",X"98",X"32",X"97",X"20",X"E5",X"40",X"21", - X"08",X"06",X"C9",X"EF",X"42",X"21",X"C3",X"3A",X"C9",X"21",X"A5",X"21",X"11",X"20",X"01",X"01", - X"32",X"97",X"20",X"CE",X"71",X"C3",X"CD",X"06",X"05",X"86",X"83",X"21",X"C3",X"2B",X"05",X"86", - X"01",X"0E",X"22",X"CD",X"C9",X"02",X"17",X"21",X"02",X"22",X"CE",X"21",X"11",X"20",X"22",X"CE", - X"C3",X"09",X"05",X"F7",X"17",X"21",X"11",X"2F",X"11",X"2F",X"0B",X"90",X"08",X"0E",X"F1",X"CD", - X"2E",X"15",X"03",X"11",X"0E",X"06",X"C3",X"09",X"0B",X"98",X"08",X"0E",X"F1",X"CD",X"21",X"09"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd deleted file mode 100644 index 4b813941..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/2.t35.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom2t35 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom2t35 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"49",X"7F",X"49",X"49",X"00",X"36",X"00",X"00",X"24",X"1F",X"24",X"44",X"00",X"1F",X"00",X"00", - X"41",X"7F",X"41",X"41",X"00",X"3E",X"00",X"00",X"41",X"3E",X"41",X"41",X"00",X"22",X"00",X"00", - X"70",X"C3",X"FF",X"4A",X"FF",X"FF",X"01",X"FF",X"49",X"7F",X"49",X"49",X"00",X"41",X"00",X"00", - X"08",X"7F",X"08",X"08",X"00",X"7F",X"00",X"00",X"41",X"3E",X"45",X"41",X"00",X"47",X"00",X"00", - X"9C",X"CD",X"57",X"01",X"3D",X"84",X"67",X"3D",X"41",X"00",X"41",X"7F",X"00",X"00",X"00",X"00", - X"01",X"7F",X"01",X"01",X"00",X"01",X"00",X"00",X"3D",X"3D",X"87",X"5F",X"C3",X"87",X"1D",X"FC", - X"10",X"7F",X"04",X"08",X"00",X"7F",X"00",X"00",X"20",X"7F",X"20",X"18",X"00",X"7F",X"00",X"00", - X"48",X"7F",X"48",X"48",X"00",X"30",X"00",X"00",X"41",X"3E",X"41",X"41",X"00",X"3E",X"00",X"00", - X"48",X"7F",X"4A",X"4C",X"00",X"31",X"00",X"00",X"07",X"00",X"7E",X"1E",X"07",X"1E",X"00",X"00", - X"40",X"40",X"40",X"7F",X"00",X"40",X"00",X"00",X"49",X"32",X"49",X"49",X"00",X"26",X"00",X"00", - X"06",X"78",X"06",X"01",X"00",X"78",X"00",X"00",X"01",X"7E",X"01",X"01",X"00",X"7E",X"00",X"00", - X"14",X"63",X"14",X"08",X"00",X"63",X"00",X"00",X"F1",X"CD",X"CD",X"09",X"09",X"CE",X"14",X"C9", - X"45",X"43",X"51",X"49",X"00",X"61",X"00",X"00",X"10",X"60",X"10",X"0F",X"00",X"60",X"00",X"00", - X"00",X"00",X"7F",X"21",X"00",X"01",X"00",X"00",X"3E",X"00",X"49",X"45",X"3E",X"51",X"00",X"00", - X"42",X"00",X"49",X"41",X"66",X"59",X"00",X"00",X"23",X"00",X"49",X"45",X"31",X"49",X"00",X"00", - X"72",X"00",X"51",X"51",X"4E",X"51",X"00",X"00",X"0C",X"00",X"24",X"14",X"04",X"7F",X"00",X"00", - X"40",X"00",X"48",X"47",X"60",X"50",X"00",X"00",X"1E",X"00",X"49",X"29",X"46",X"49",X"00",X"00", - X"31",X"00",X"49",X"49",X"3C",X"4A",X"00",X"00",X"36",X"00",X"49",X"49",X"36",X"49",X"00",X"00", - X"5F",X"20",X"01",X"21",X"C3",X"3C",X"0B",X"D2",X"A1",X"21",X"C3",X"20",X"40",X"FE",X"AD",X"3A", - X"7E",X"23",X"00",X"BB",X"00",X"00",X"E9",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"A9",X"21",X"C3",X"20",X"40",X"FE",X"00",X"00",X"A5",X"21",X"C3",X"20",X"40",X"FE",X"00",X"00", - X"26",X"26",X"08",X"07",X"12",X"26",X"0E",X"02",X"12",X"26",X"0E",X"02",X"04",X"11",X"1B",X"26", - X"26",X"04",X"26",X"1C",X"0B",X"0F",X"18",X"00",X"04",X"11",X"26",X"26",X"02",X"12",X"11",X"0E", - X"1C",X"26",X"0F",X"26",X"00",X"0B",X"04",X"18",X"14",X"0F",X"07",X"12",X"26",X"1B",X"11",X"0E", - X"02",X"0D",X"04",X"11",X"08",X"03",X"26",X"13",X"12",X"11",X"01",X"26",X"13",X"14",X"0E",X"13", - X"0B",X"0F",X"18",X"00",X"11",X"04",X"1C",X"26",X"0B",X"0F",X"18",X"00",X"11",X"04",X"1B",X"26", - X"0A",X"00",X"26",X"E5",X"6F",X"00",X"29",X"29",X"0F",X"26",X"08",X"0E",X"13",X"0D",X"11",X"12", - X"1A",X"C5",X"13",X"77",X"20",X"01",X"09",X"00",X"19",X"29",X"E1",X"EB",X"08",X"06",X"04",X"D3", - X"23",X"56",X"23",X"7E",X"6F",X"66",X"CD",X"7A",X"05",X"C1",X"B8",X"C2",X"C9",X"0B",X"23",X"5E", - X"E6",X"0F",X"CD",X"0F",X"0B",X"E6",X"E6",X"F1",X"0B",X"D3",X"D5",X"7B",X"0F",X"F5",X"0F",X"0F", - X"3C",X"C3",X"AF",X"09",X"81",X"7D",X"6F",X"27",X"CD",X"0F",X"0B",X"E6",X"C9",X"D1",X"1A",X"C6", - X"11",X"0E",X"04",X"13",X"26",X"17",X"76",X"F3",X"88",X"7C",X"C3",X"27",X"41",X"1B",X"15",X"26", - X"30",X"17",X"70",X"11",X"CD",X"0B",X"0A",X"B0",X"3F",X"FE",X"F8",X"C2",X"0E",X"17",X"21",X"04", - X"01",X"06",X"05",X"FB",X"1A",X"C2",X"CD",X"08",X"0F",X"0E",X"15",X"21",X"C3",X"2A",X"09",X"0D", - X"20",X"AD",X"0E",X"6F",X"CD",X"01",X"0B",X"EB",X"0A",X"28",X"18",X"C2",X"26",X"08",X"3A",X"00", - X"20",X"AD",X"99",X"FE",X"53",X"D2",X"CD",X"08",X"32",X"7D",X"20",X"AD",X"26",X"CD",X"3A",X"0B", - X"0B",X"74",X"13",X"21",X"CD",X"28",X"09",X"F1",X"0A",X"28",X"53",X"CA",X"0E",X"08",X"11",X"15", - X"62",X"DA",X"DB",X"08",X"E6",X"03",X"C2",X"02",X"18",X"C3",X"3A",X"08",X"20",X"AD",X"02",X"FE", - X"3E",X"09",X"C3",X"01",X"08",X"7B",X"16",X"CD",X"08",X"6E",X"03",X"DB",X"04",X"E6",X"08",X"CA", - X"3E",X"20",X"32",X"02",X"20",X"F1",X"16",X"CD",X"DB",X"09",X"E6",X"02",X"3C",X"03",X"E1",X"32", - X"32",X"3C",X"20",X"E0",X"C6",X"CD",X"00",X"03",X"CD",X"09",X"0B",X"26",X"02",X"DB",X"03",X"E6", - X"08",X"0E",X"17",X"21",X"11",X"2F",X"0B",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"7D",X"E5",X"DD",X"C6",X"24",X"6F",X"B8",X"7E",X"F1",X"CD",X"C3",X"09",X"08",X"BC",X"44",X"4D", - X"FE",X"81",X"C9",X"81",X"AF",X"CD",X"21",X"03",X"7E",X"23",X"C3",X"B9",X"04",X"B2",X"E6",X"F3", - X"08",X"06",X"21",X"EF",X"23",X"80",X"08",X"06",X"23",X"00",X"08",X"06",X"21",X"EF",X"23",X"40", - X"DF",X"09",X"C2",X"05",X"08",X"D9",X"F6",X"21",X"21",X"EF",X"23",X"C0",X"08",X"06",X"06",X"EF", - X"EF",X"22",X"CD",X"97",X"1C",X"00",X"9F",X"31",X"06",X"22",X"EF",X"05",X"08",X"06",X"ED",X"21", - X"B4",X"7D",X"B2",X"B3",X"C2",X"A7",X"01",X"5C",X"2A",X"20",X"20",X"A5",X"2A",X"EB",X"20",X"A9", - X"04",X"D3",X"37",X"C3",X"11",X"08",X"09",X"2D",X"4E",X"21",X"22",X"00",X"20",X"9F",X"C9",X"FB", - X"3D",X"20",X"E6",X"47",X"FE",X"0F",X"C2",X"0F",X"F1",X"CD",X"C3",X"09",X"08",X"18",X"AD",X"3A", - X"32",X"78",X"20",X"AD",X"1B",X"C9",X"0F",X"26",X"09",X"28",X"E6",X"78",X"F6",X"F0",X"47",X"09", - X"13",X"13",X"0D",X"0E",X"CD",X"00",X"0B",X"A7",X"00",X"0B",X"04",X"18",X"26",X"11",X"14",X"01", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CD",X"C9",X"4A",X"C4",X"00",X"00", - X"DF",X"00",X"21",X"DF",X"28",X"10",X"F7",X"CD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"D2",X"CD",X"DF",X"0B",X"10",X"21",X"0E",X"35",X"DF",X"0C",X"10",X"21",X"1E",X"33",X"00",X"20", - X"28",X"0C",X"F5",X"CD",X"DF",X"10",X"0C",X"21",X"11",X"07",X"0B",X"A0",X"BB",X"CD",X"21",X"09", - X"00",X"00",X"0C",X"21",X"0E",X"35",X"11",X"07",X"1E",X"33",X"00",X"50",X"D2",X"CD",X"DF",X"0B", - X"F5",X"CD",X"DF",X"07",X"08",X"21",X"11",X"31",X"0B",X"A0",X"BB",X"CD",X"21",X"09",X"28",X"08", - X"08",X"21",X"0E",X"35",X"11",X"07",X"0B",X"A0",X"C1",X"00",X"CE",X"CD",X"DF",X"0B",X"00",X"00", - X"FF",X"FF",X"1A",X"FF",X"00",X"D5",X"A7",X"CD",X"BB",X"CD",X"CD",X"09",X"40",X"4C",X"FF",X"C9", - X"09",X"BB",X"CD",X"C9",X"1C",X"F3",X"1C",X"0E",X"00",X"0B",X"DF",X"D1",X"00",X"13",X"C2",X"0D", - X"CD",X"09",X"0B",X"40",X"20",X"CD",X"CD",X"0B",X"1E",X"21",X"11",X"24",X"0B",X"50",X"F1",X"CD", - X"0B",X"89",X"F1",X"CD",X"C3",X"09",X"0D",X"DB",X"0B",X"48",X"07",X"0E",X"01",X"21",X"11",X"35", - X"00",X"D1",X"0D",X"13",X"F1",X"C2",X"C9",X"09",X"1A",X"C9",X"00",X"D5",X"A7",X"CD",X"00",X"0B", - X"0C",X"E2",X"0D",X"10",X"0D",X"25",X"0D",X"3A",X"0C",X"8E",X"0C",X"A3",X"0C",X"B8",X"0C",X"CD", - X"FF",X"7F",X"80",X"00",X"E3",X"7F",X"80",X"FF",X"00",X"00",X"3E",X"3E",X"00",X"FF",X"3E",X"00", - X"80",X"C1",X"01",X"01",X"C0",X"FF",X"80",X"20",X"E3",X"C0",X"00",X"C1",X"FF",X"01",X"C0",X"C0", - X"00",X"02",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"02",X"00",X"20",X"00",X"00", - X"00",X"FF",X"38",X"00",X"FF",X"7C",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"01",X"C6",X"01",X"00",X"00",X"FF",X"EE",X"7C",X"00",X"FF",X"EE",X"00",X"FF",X"C6", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"01",X"00",X"FF",X"00",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"FF",X"F8",X"00",X"FF",X"F8",X"00",X"00",X"FF",X"FF",X"00",X"00",X"F8",X"FC",X"00",X"01", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F8",X"00",X"FF",X"20",X"00",X"FF",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"00",X"FF",X"FC",X"00",X"07",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"FF",X"F0",X"00",X"01",X"40",X"FF",X"00",X"FF",X"01",X"00",X"00",X"F0",X"F0",X"01",X"01", - X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"40",X"40",X"00",X"FF",X"40",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"0C",X"86",X"10",X"21",X"C3",X"2E",X"0F",X"F5",X"FF",X"FF",X"FF",X"FF",X"A6",X"11",X"CD",X"10", - X"0C",X"3A",X"0C",X"4F",X"0C",X"64",X"0C",X"79",X"06",X"EB",X"0C",X"10",X"0C",X"25",X"07",X"E0", - X"DC",X"00",X"0F",X"F4",X"FF",X"0F",X"00",X"00",X"00",X"00",X"EC",X"EC",X"0F",X"0F",X"00",X"FF", - X"12",X"F2",X"FF",X"03",X"00",X"00",X"E3",X"E0",X"FA",X"38",X"07",X"17",X"00",X"FF",X"F0",X"00", - X"FF",X"00",X"00",X"00",X"07",X"00",X"00",X"38",X"01",X"31",X"00",X"FF",X"00",X"00",X"3E",X"1F", - X"00",X"FF",X"EE",X"00",X"06",X"FA",X"FF",X"07",X"FF",X"FF",X"00",X"00",X"F6",X"F6",X"05",X"05", - X"78",X"00",X"09",X"F9",X"FF",X"01",X"80",X"00",X"00",X"00",X"FD",X"9C",X"03",X"0B",X"00",X"FF", - X"1F",X"0F",X"FF",X"00",X"80",X"00",X"03",X"00",X"F1",X"F0",X"00",X"18",X"00",X"FF",X"00",X"80", - X"02",X"02",X"00",X"FF",X"37",X"00",X"03",X"3D",X"00",X"1C",X"FF",X"FF",X"00",X"00",X"1B",X"1B", - X"00",X"FF",X"BC",X"80",X"04",X"FC",X"FF",X"00",X"FF",X"03",X"80",X"00",X"FE",X"CE",X"01",X"05", - X"80",X"C0",X"0F",X"07",X"FF",X"00",X"C0",X"00",X"C0",X"00",X"78",X"78",X"00",X"0C",X"00",X"FF", - X"05",X"0D",X"01",X"01",X"80",X"FF",X"9B",X"80",X"01",X"00",X"00",X"0E",X"FF",X"FF",X"80",X"80", - X"00",X"02",X"00",X"FF",X"5E",X"40",X"02",X"7E",X"01",X"86",X"FF",X"01",X"40",X"00",X"CF",X"E7", - X"00",X"FF",X"C0",X"E0",X"07",X"03",X"FF",X"00",X"FF",X"00",X"60",X"00",X"3C",X"3C",X"00",X"06", - X"80",X"80",X"3F",X"2F",X"80",X"FF",X"3F",X"80",X"E0",X"00",X"00",X"00",X"00",X"07",X"FF",X"FF", - X"0D",X"00",X"FF",X"07",X"00",X"00",X"02",X"07",X"FF",X"0D",X"80",X"80",X"0F",X"0F",X"80",X"FF", - X"86",X"CD",X"C9",X"0C",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"11",X"FF",X"11",X"10", - X"07",X"20",X"07",X"30",X"07",X"40",X"07",X"50",X"1E",X"7A",X"1E",X"8A",X"1E",X"9A",X"07",X"10", - X"FF",X"09",X"00",X"00",X"10",X"02",X"00",X"FF",X"80",X"80",X"4E",X"5C",X"00",X"FF",X"24",X"00", - X"FF",X"27",X"00",X"40",X"24",X"02",X"00",X"FF",X"0C",X"00",X"FF",X"0C",X"40",X"FF",X"1E",X"80", - X"FF",X"FF",X"80",X"C0",X"03",X"01",X"20",X"FF",X"02",X"00",X"FF",X"04",X"00",X"00",X"03",X"0C", - X"40",X"FF",X"00",X"00",X"FF",X"02",X"C8",X"FF",X"09",X"90",X"FF",X"04",X"60",X"20",X"04",X"06", - X"20",X"FF",X"00",X"00",X"FF",X"01",X"C0",X"C0",X"05",X"E8",X"FF",X"04",X"90",X"40",X"00",X"02", - X"12",X"FF",X"00",X"20",X"FF",X"01",X"20",X"10",X"FF",X"FF",X"FF",X"FF",X"3C",X"F2",X"01",X"00", - X"3A",X"FF",X"FF",X"5C",X"90",X"09",X"91",X"FF",X"60",X"FF",X"FF",X"18",X"FF",X"FF",X"FF",X"FF", - X"DF",X"1D",X"C9",X"DF",X"FF",X"FF",X"30",X"30",X"FF",X"89",X"46",X"62",X"FF",X"FF",X"AA",X"CD", - X"C3",X"F1",X"00",X"08",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"3E",X"F5",X"32",X"AA",X"22",X"48", - X"FF",X"FF",X"EB",X"CD",X"84",X"19",X"C3",X"67",X"FF",X"FF",X"F0",X"FF",X"FF",X"F0",X"60",X"60", - X"F0",X"F0",X"03",X"03",X"E0",X"FF",X"01",X"E0",X"0A",X"48",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"0F",X"F0",X"FF",X"01",X"C0",X"C0",X"FF",X"FF",X"FF",X"FF", - X"07",X"E0",X"FF",X"07",X"C0",X"C0",X"03",X"03",X"FF",X"0F",X"F0",X"F0",X"0F",X"0F",X"E0",X"FF", - X"1F",X"E0",X"FF",X"1F",X"C0",X"C0",X"0F",X"0F",X"FF",X"FF",X"E0",X"E0",X"1F",X"1F",X"E0",X"FF", - X"1E",X"41",X"86",X"CD",X"C3",X"0C",X"0D",X"FA",X"80",X"FF",X"07",X"80",X"FF",X"07",X"11",X"FF", - X"1D",X"21",X"1D",X"31",X"1D",X"41",X"1E",X"31",X"1C",X"B9",X"1C",X"C9",X"1C",X"D9",X"1D",X"11", - X"FF",X"0F",X"00",X"00",X"06",X"06",X"FF",X"FF",X"80",X"80",X"1F",X"1F",X"00",X"FF",X"0F",X"00", - X"FF",X"1E",X"00",X"00",X"0C",X"0C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"1E",X"00", - X"FF",X"FF",X"00",X"00",X"18",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"C0",X"FF",X"07",X"00",X"00",X"01",X"FF",X"00",X"1F",X"C0",X"FF",X"07",X"C0",X"C0",X"07",X"07", - X"FF",X"00",X"D2",X"FF",X"08",X"53",X"C5",X"F5",X"00",X"00",X"01",X"01",X"00",X"FF",X"01",X"00", - X"86",X"41",X"47",X"23",X"A7",X"7D",X"9D",X"CA",X"26",X"E5",X"2E",X"0B",X"6E",X"DE",X"F3",X"3A", - X"80",X"C0",X"0F",X"1F",X"80",X"FF",X"0F",X"80",X"78",X"0D",X"79",X"C3",X"FF",X"0D",X"FF",X"FF", - X"02",X"00",X"FF",X"00",X"78",X"FF",X"C0",X"A7",X"FF",X"0F",X"00",X"80",X"02",X"0F",X"00",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C1",X"E1",X"C3",X"F1",X"08",X"3F",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"AA",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"3B",X"1F",X"80",X"FF",X"3B",X"80",X"FF",X"31",X"00",X"FF",X"0E",X"00",X"FF",X"1F",X"80",X"00", - X"FF",X"00",X"CD",X"FF",X"0B",X"26",X"03",X"0E",X"40",X"80",X"40",X"31",X"40",X"FF",X"40",X"00", - X"C9",X"48",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"9C",X"21",X"11",X"30",X"22",X"51",X"2C",X"CD", - X"FF",X"FF",X"10",X"21",X"C3",X"2B",X"0E",X"F4",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd deleted file mode 100644 index 40698213..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/3.t34.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom3t34 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom3t34 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"10",X"10",X"10",X"42",X"10",X"74",X"10",X"A6",X"0F",X"10",X"0F",X"42",X"0F",X"74",X"0F",X"A6", - X"E3",X"F0",X"07",X"E3",X"FF",X"07",X"E0",X"E0",X"30",X"30",X"7F",X"7F",X"06",X"06",X"F0",X"FF", - X"70",X"2A",X"3E",X"12",X"86",X"00",X"CA",X"A7",X"C1",X"C1",X"03",X"03",X"FF",X"FF",X"E5",X"F5", - X"C2",X"C3",X"16",X"41",X"F1",X"E1",X"DC",X"C3",X"12",X"36",X"C3",X"23",X"12",X"2D",X"FE",X"7D", - X"00",X"FF",X"1F",X"00",X"00",X"E0",X"FF",X"03",X"FF",X"13",X"00",X"00",X"F0",X"1E",X"01",X"00", - X"19",X"00",X"00",X"60",X"FF",X"06",X"00",X"00",X"00",X"80",X"60",X"19",X"06",X"00",X"80",X"FF", - X"00",X"80",X"FF",X"01",X"FF",X"FF",X"FF",X"FF",X"C0",X"0F",X"03",X"00",X"00",X"FF",X"06",X"00", - X"00",X"FF",X"18",X"00",X"FF",X"3C",X"00",X"00",X"40",X"8E",X"FF",X"FF",X"00",X"00",X"18",X"18", - X"00",X"00",X"66",X"66",X"00",X"FF",X"66",X"00",X"7E",X"3C",X"00",X"FF",X"7E",X"00",X"FF",X"66", - X"3C",X"00",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"00",X"00",X"3C",X"7E",X"00",X"FF", - X"3E",X"F0",X"00",X"01",X"00",X"FF",X"E0",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00", - X"00",X"06",X"00",X"FF",X"60",X"80",X"06",X"19",X"03",X"1F",X"FF",X"00",X"80",X"00",X"19",X"60", - X"00",X"FF",X"80",X"00",X"01",X"06",X"FF",X"00",X"FF",X"00",X"00",X"00",X"0F",X"C0",X"00",X"03", - X"E0",X"60",X"0F",X"0B",X"E0",X"FF",X"0F",X"60",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"03",X"C0",X"FF",X"01",X"80",X"C0",X"00",X"01",X"FF",X"03",X"E0",X"60",X"03",X"03",X"E0",X"FF", - X"0B",X"21",X"C3",X"2E",X"13",X"10",X"00",X"00",X"80",X"FF",X"FF",X"00",X"CD",X"FF",X"0C",X"86", - X"0E",X"10",X"0E",X"49",X"0E",X"82",X"0E",X"BB",X"1E",X"41",X"0D",X"4F",X"0D",X"88",X"0D",X"C1", - X"2B",X"08",X"50",X"11",X"CD",X"07",X"0C",X"86",X"10",X"11",X"CD",X"0D",X"0C",X"86",X"21",X"C9", - X"C9",X"0C",X"EB",X"CD",X"3A",X"0B",X"20",X"E2",X"08",X"21",X"11",X"2E",X"07",X"60",X"86",X"CD", - X"97",X"23",X"C3",X"77",X"19",X"67",X"FE",X"78",X"D3",X"C9",X"05",X"01",X"05",X"05",X"C9",X"78", - X"CD",X"20",X"19",X"72",X"77",X"78",X"FE",X"3D",X"C3",X"40",X"11",X"61",X"FF",X"FF",X"FA",X"3A", - X"7B",X"23",X"FA",X"32",X"C3",X"20",X"1F",X"41",X"C2",X"0B",X"13",X"56",X"07",X"3E",X"13",X"12", - X"11",X"26",X"13",X"86",X"E2",X"3A",X"A7",X"20",X"97",X"23",X"C3",X"77",X"1F",X"3E",X"01",X"21", - X"3A",X"12",X"20",X"E0",X"DC",X"C3",X"CD",X"13",X"79",X"CA",X"3A",X"13",X"20",X"E1",X"26",X"C3", - X"10",X"10",X"10",X"10",X"26",X"10",X"26",X"26",X"09",X"F1",X"D1",X"C1",X"C9",X"E1",X"10",X"10", - X"2A",X"13",X"20",X"D3",X"CD",X"2B",X"1D",X"58",X"26",X"26",X"26",X"26",X"26",X"26",X"C7",X"11", - X"F1",X"CD",X"C3",X"09",X"03",X"EC",X"01",X"E6",X"01",X"21",X"0E",X"26",X"11",X"09",X"13",X"8D", - X"C1",X"CA",X"CD",X"13",X"1D",X"58",X"7D",X"C3",X"D3",X"2A",X"2B",X"20",X"C7",X"11",X"A7",X"13", - X"15",X"AA",X"FF",X"2B",X"B4",X"54",X"56",X"6B",X"CD",X"16",X"1D",X"AA",X"7D",X"C3",X"D8",X"16", - X"04",X"01",X"FF",X"FF",X"CA",X"A7",X"13",X"82",X"A8",X"FF",X"14",X"28",X"FF",X"09",X"80",X"10", - X"3E",X"13",X"C3",X"02",X"1F",X"71",X"E2",X"CA",X"A7",X"00",X"82",X"CA",X"4F",X"13",X"7F",X"C3", - X"A7",X"20",X"E2",X"CA",X"C3",X"18",X"04",X"33",X"FE",X"18",X"C2",X"02",X"18",X"57",X"F5",X"3A", - X"1C",X"65",X"1C",X"7A",X"1C",X"8F",X"1C",X"A4",X"1C",X"11",X"1C",X"26",X"1C",X"3B",X"1C",X"50", - X"FF",X"C1",X"A0",X"80",X"61",X"73",X"00",X"01",X"C0",X"C0",X"82",X"86",X"C0",X"FF",X"CD",X"40", - X"30",X"00",X"1E",X"1E",X"00",X"03",X"00",X"FF",X"00",X"FF",X"2F",X"20",X"01",X"33",X"FF",X"00", - X"00",X"80",X"00",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"F0",X"03",X"01",X"FF",X"00",X"70",X"00", - X"7E",X"A0",X"FF",X"60",X"D0",X"C0",X"30",X"B9",X"FF",X"FF",X"60",X"60",X"61",X"73",X"E0",X"FF", - X"0F",X"8F",X"00",X"01",X"00",X"FF",X"F0",X"F8",X"80",X"FF",X"97",X"90",X"FF",X"19",X"18",X"00", - X"00",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"FF",X"00",X"38",X"00",X"00",X"C0", - X"70",X"FF",X"3F",X"50",X"FF",X"3C",X"68",X"E0",X"FF",X"FF",X"FF",X"FF",X"B0",X"B0",X"3E",X"3F", - X"8C",X"80",X"07",X"C7",X"00",X"FF",X"F8",X"7C",X"18",X"5C",X"C0",X"FF",X"4B",X"C8",X"FF",X"0C", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1C",X"00",X"00",X"E0",X"FF",X"FF", - X"1F",X"1F",X"B8",X"FF",X"1F",X"E8",X"FF",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"D8",X"D8", - X"FF",X"06",X"C6",X"C0",X"03",X"63",X"00",X"FF",X"B4",X"70",X"0F",X"2E",X"E0",X"FF",X"25",X"64", - X"FF",X"FF",X"E0",X"07",X"FF",X"00",X"FF",X"FF",X"7C",X"3E",X"FF",X"00",X"0E",X"00",X"00",X"70", - X"C0",X"C0",X"1F",X"17",X"C0",X"FF",X"1E",X"C0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"07",X"80",X"FF",X"03",X"00",X"80",X"01",X"03",X"FF",X"07",X"C0",X"C0",X"06",X"07",X"C0",X"FF", - X"86",X"CD",X"C3",X"0C",X"11",X"F6",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"11",X"FF",X"1C",X"11", - X"12",X"10",X"12",X"42",X"12",X"74",X"12",X"A6",X"11",X"10",X"11",X"42",X"11",X"74",X"11",X"A6", - X"FF",X"7E",X"1E",X"1E",X"3C",X"3C",X"FF",X"FF",X"F3",X"F3",X"67",X"67",X"3F",X"FF",X"7E",X"3F", - X"32",X"3D",X"22",X"43",X"C3",X"F1",X"03",X"66",X"3A",X"F5",X"22",X"43",X"CA",X"A7",X"11",X"2C", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"FF",X"1F",X"00",X"CC",X"33",X"00",X"FF",X"FF",X"80",X"F0",X"0F",X"01",X"F8",X"FF", - X"1E",X"00",X"30",X"FF",X"00",X"00",X"FF",X"0C",X"CC",X"FF",X"00",X"00",X"FF",X"33",X"00",X"78", - X"FE",X"00",X"DA",X"0C",X"13",X"60",X"46",X"C3",X"DA",X"FF",X"11",X"66",X"0C",X"06",X"BC",X"CD", - X"00",X"FF",X"06",X"00",X"FF",X"0F",X"80",X"00",X"FF",X"13",X"FF",X"FF",X"00",X"00",X"06",X"06", - X"80",X"80",X"19",X"19",X"80",X"FF",X"19",X"80",X"1F",X"0F",X"80",X"FF",X"1F",X"80",X"FF",X"19", - X"0F",X"00",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",X"00",X"80",X"0F",X"1F",X"00",X"FF", - X"0F",X"7C",X"00",X"FF",X"F8",X"C0",X"FF",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"80",X"00", - X"98",X"60",X"01",X"06",X"FF",X"00",X"C0",X"00",X"60",X"00",X"06",X"98",X"00",X"01",X"00",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"F0",X"00",X"FF",X"60",X"80",X"FF",X"01", - X"00",X"00",X"7B",X"5F",X"00",X"FF",X"7F",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"1F",X"00",X"FF",X"0E",X"00",X"00",X"04",X"0E",X"FF",X"1F",X"00",X"00",X"1F",X"1B",X"00",X"FF", - X"11",X"2B",X"0C",X"79",X"F5",X"C3",X"00",X"12",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"0C",X"21", - X"E6",X"3D",X"32",X"1F",X"20",X"D1",X"01",X"3E",X"32",X"10",X"20",X"D0",X"D1",X"3A",X"3D",X"20", - X"E5",X"20",X"CD",X"D5",X"15",X"B4",X"00",X"CD",X"D8",X"32",X"11",X"20",X"20",X"B0",X"D3",X"2A", - X"00",X"00",X"96",X"CD",X"3A",X"15",X"20",X"DA",X"D1",X"15",X"3A",X"E1",X"20",X"D6",X"00",X"A7", - X"CA",X"A7",X"16",X"7D",X"03",X"3E",X"20",X"C3",X"C2",X"A7",X"16",X"87",X"ED",X"CD",X"00",X"40", - X"16",X"5F",X"1A",X"17",X"02",X"32",X"13",X"20",X"97",X"11",X"05",X"32",X"3A",X"20",X"20",X"D1", - X"03",X"32",X"7D",X"20",X"04",X"32",X"CD",X"20",X"32",X"1A",X"20",X"01",X"D3",X"2A",X"7C",X"20", - X"32",X"97",X"20",X"DF",X"00",X"3A",X"6F",X"22",X"17",X"88",X"20",X"26",X"DF",X"3A",X"F5",X"20", - X"17",X"88",X"5E",X"C3",X"3A",X"05",X"20",X"CF",X"8D",X"CD",X"F1",X"18",X"DF",X"32",X"CD",X"20", - X"40",X"ED",X"A7",X"00",X"7D",X"C2",X"21",X"16",X"C2",X"A7",X"1B",X"87",X"12",X"C3",X"CD",X"1B", - X"16",X"AA",X"D0",X"3A",X"C6",X"20",X"32",X"10",X"20",X"DA",X"C3",X"35",X"16",X"7D",X"D2",X"07", - X"16",X"09",X"DD",X"3A",X"47",X"20",X"D5",X"3A",X"20",X"D0",X"D1",X"3A",X"3C",X"20",X"C3",X"3C", - X"20",X"D5",X"ED",X"CD",X"00",X"40",X"C3",X"A7",X"90",X"20",X"96",X"D2",X"3E",X"1B",X"32",X"50", - X"3A",X"17",X"20",X"DD",X"50",X"FE",X"D5",X"D2",X"42",X"20",X"D8",X"3A",X"A7",X"20",X"6F",X"C2", - X"D3",X"2A",X"E5",X"20",X"B4",X"CD",X"00",X"15",X"3C",X"16",X"DD",X"32",X"11",X"20",X"20",X"B0", - X"20",X"D9",X"16",X"5F",X"1A",X"17",X"B7",X"4F",X"33",X"C3",X"00",X"18",X"00",X"00",X"3A",X"E1", - X"17",X"17",X"5F",X"17",X"C3",X"9F",X"03",X"F7",X"13",X"17",X"CE",X"1A",X"B7",X"00",X"17",X"17", - X"FF",X"FE",X"00",X"FE",X"00",X"FF",X"01",X"FF",X"FF",X"00",X"FD",X"FF",X"FE",X"FF",X"FE",X"FE", - X"00",X"02",X"FF",X"02",X"FF",X"01",X"FE",X"01",X"01",X"00",X"02",X"01",X"01",X"01",X"01",X"02", - X"DA",X"03",X"17",X"49",X"3C",X"2F",X"A7",X"4F",X"7B",X"57",X"E0",X"E6",X"3E",X"26",X"FE",X"79", - X"3C",X"20",X"07",X"E6",X"D7",X"32",X"3E",X"20",X"63",X"CA",X"CD",X"17",X"1B",X"9C",X"D7",X"3A", - X"A7",X"17",X"63",X"CA",X"CD",X"17",X"15",X"14",X"32",X"01",X"20",X"D2",X"79",X"0D",X"2F",X"C3", - X"3E",X"20",X"32",X"01",X"20",X"D2",X"79",X"0D",X"D7",X"3A",X"3C",X"20",X"07",X"E6",X"D7",X"32", - X"CD",X"20",X"15",X"96",X"7D",X"C3",X"3A",X"1B",X"49",X"C3",X"22",X"17",X"20",X"D3",X"B0",X"11", - X"D2",X"C3",X"3A",X"16",X"20",X"D7",X"C2",X"A7",X"20",X"DD",X"03",X"FE",X"7B",X"C3",X"3D",X"17", - X"00",X"3A",X"47",X"22",X"00",X"3A",X"32",X"20",X"16",X"D5",X"D1",X"3A",X"C3",X"20",X"1B",X"73", - X"EB",X"20",X"DB",X"2A",X"22",X"20",X"20",X"EB",X"22",X"00",X"32",X"78",X"20",X"00",X"EB",X"2A", - X"AE",X"3A",X"32",X"20",X"20",X"EE",X"32",X"78",X"22",X"EB",X"20",X"DB",X"EE",X"3A",X"47",X"20", - X"7C",X"19",X"25",X"FE",X"24",X"DA",X"FE",X"17",X"20",X"AE",X"79",X"C9",X"C2",X"A7",X"17",X"B9", - X"C3",X"27",X"17",X"26",X"21",X"E5",X"20",X"B1",X"DA",X"3E",X"17",X"26",X"26",X"CA",X"26",X"17", - X"13",X"13",X"23",X"23",X"FE",X"7D",X"C2",X"C1",X"B0",X"11",X"1A",X"20",X"7E",X"47",X"70",X"12", - X"17",X"F0",X"E1",X"F1",X"C1",X"D1",X"C9",X"FB",X"17",X"D3",X"C9",X"E1",X"F0",X"C3",X"C2",X"1A", - X"00",X"00",X"00",X"00",X"05",X"C3",X"00",X"08",X"01",X"3E",X"F5",X"32",X"CD",X"20",X"03",X"C6", - X"C0",X"07",X"00",X"01",X"40",X"04",X"00",X"01",X"80",X"03",X"80",X"03",X"C0",X"07",X"80",X"03", - X"C0",X"00",X"C0",X"00",X"40",X"00",X"40",X"00",X"C0",X"07",X"C0",X"03",X"C0",X"0F",X"C0",X"01", - X"80",X"01",X"60",X"00",X"00",X"01",X"00",X"00",X"C0",X"0F",X"C0",X"07",X"80",X"01",X"E0",X"01", - X"00",X"03",X"00",X"00",X"00",X"02",X"00",X"00",X"C0",X"03",X"E0",X"07",X"80",X"03",X"F0",X"0F", - X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"03",X"E0",X"03",X"E0",X"03",X"00",X"07", - X"F8",X"07",X"00",X"01",X"00",X"00",X"00",X"00",X"E0",X"01",X"C0",X"01",X"F0",X"03",X"80",X"01", - X"F0",X"00",X"80",X"00",X"30",X"00",X"00",X"00",X"E0",X"07",X"C0",X"00",X"E0",X"03",X"C0",X"00", - X"60",X"00",X"60",X"00",X"20",X"00",X"20",X"00",X"E0",X"01",X"E0",X"03",X"E0",X"00",X"E0",X"07", - X"80",X"00",X"E0",X"03",X"80",X"00",X"20",X"02",X"C0",X"01",X"C0",X"01",X"C0",X"01",X"E0",X"03", - X"00",X"03",X"00",X"03",X"00",X"02",X"00",X"02",X"C0",X"03",X"E0",X"03",X"80",X"03",X"F0",X"03", - X"00",X"06",X"80",X"01",X"00",X"00",X"80",X"00",X"E0",X"03",X"F0",X"03",X"80",X"07",X"80",X"01", - X"00",X"00",X"C0",X"00",X"00",X"00",X"40",X"00",X"E0",X"07",X"C0",X"03",X"F0",X"0F",X"C0",X"01", - X"00",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"C0",X"07",X"C0",X"1F",X"E0",X"00",X"C0",X"07", - X"20",X"00",X"F8",X"07",X"00",X"00",X"00",X"00",X"E0",X"00",X"E0",X"01",X"60",X"00",X"F0",X"03", - X"40",X"00",X"C0",X"03",X"00",X"00",X"00",X"03",X"C0",X"00",X"F8",X"01",X"C0",X"00",X"F0",X"01", - X"00",X"03",X"00",X"03",X"00",X"02",X"00",X"02",X"E0",X"03",X"C0",X"03",X"F0",X"03",X"80",X"03", - X"1A",X"20",X"7D",X"77",X"BF",X"FE",X"13",X"C8",X"D0",X"3A",X"5F",X"20",X"14",X"16",X"B0",X"21", - X"20",X"B1",X"1A",X"B7",X"12",X"17",X"1B",X"4F",X"C3",X"23",X"15",X"09",X"06",X"C5",X"11",X"00", - X"CA",X"BE",X"15",X"32",X"13",X"13",X"C3",X"13",X"17",X"1A",X"79",X"12",X"47",X"B0",X"FE",X"7B", - X"17",X"CC",X"00",X"00",X"B6",X"1A",X"13",X"77",X"15",X"1A",X"C1",X"78",X"C0",X"A7",X"C3",X"23", - X"69",X"60",X"77",X"B6",X"2B",X"13",X"B6",X"1A",X"1A",X"2B",X"77",X"B6",X"23",X"13",X"E5",X"1A", - X"A6",X"2F",X"E6",X"77",X"CA",X"07",X"15",X"65",X"23",X"77",X"44",X"13",X"E1",X"4D",X"1A",X"C9", - X"A6",X"2F",X"E6",X"77",X"CA",X"E0",X"15",X"75",X"01",X"3E",X"D6",X"32",X"13",X"20",X"1A",X"2B", - X"E5",X"2F",X"69",X"60",X"77",X"A6",X"07",X"E6",X"01",X"3E",X"D6",X"32",X"13",X"20",X"1A",X"23", - X"2B",X"13",X"2F",X"1A",X"77",X"A6",X"E0",X"E6",X"88",X"CA",X"3E",X"15",X"32",X"01",X"20",X"D6", - X"4F",X"20",X"DE",X"7C",X"47",X"00",X"3C",X"CD",X"19",X"CA",X"C3",X"02",X"02",X"14",X"D6",X"7D", - X"1D",X"82",X"3C",X"CD",X"CD",X"15",X"1D",X"82",X"CD",X"15",X"1D",X"82",X"3C",X"CD",X"CD",X"15", - X"DE",X"7C",X"47",X"00",X"57",X"CD",X"CD",X"15",X"3C",X"CD",X"C9",X"15",X"D6",X"7D",X"4F",X"20", - X"57",X"CD",X"CD",X"15",X"1D",X"82",X"57",X"CD",X"1D",X"82",X"57",X"CD",X"CD",X"15",X"1D",X"82", - X"E5",X"01",X"31",X"C3",X"00",X"02",X"D2",X"3A",X"C9",X"15",X"F5",X"3A",X"A7",X"20",X"FE",X"C8", - X"3A",X"16",X"20",X"D7",X"C2",X"A7",X"16",X"AA",X"3D",X"20",X"D2",X"32",X"A7",X"20",X"AA",X"C2", - X"D2",X"00",X"16",X"96",X"D0",X"3A",X"D6",X"20",X"10",X"3E",X"D2",X"32",X"C3",X"20",X"40",X"DA"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd deleted file mode 100644 index f19c46b3..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/4.t33.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom4t33 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom4t33 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"41",X"9F",X"41",X"BE",X"41",X"DD",X"41",X"FC",X"1A",X"A5",X"1A",X"B8",X"1A",X"D3",X"41",X"80", - X"3A",X"1A",X"20",X"DB",X"A7",X"CD",X"D2",X"06",X"DC",X"3A",X"CD",X"20",X"06",X"9D",X"29",X"D2", - X"3A",X"19",X"20",X"FB",X"E6",X"C3",X"00",X"1D",X"1A",X"29",X"1F",X"E6",X"03",X"FE",X"F0",X"DA", - X"01",X"07",X"F0",X"FF",X"01",X"F0",X"FF",X"01",X"F0",X"00",X"05",X"B0",X"FF",X"07",X"F0",X"F0", - X"00",X"40",X"FF",X"FF",X"FF",X"FF",X"F8",X"D8",X"E0",X"B0",X"00",X"01",X"E0",X"FF",X"FF",X"40", - X"F8",X"F8",X"F8",X"FF",X"FF",X"50",X"20",X"70",X"03",X"02",X"F8",X"FF",X"03",X"F8",X"FF",X"00", - X"FF",X"00",X"7C",X"FF",X"01",X"FC",X"FF",X"01",X"20",X"FF",X"FF",X"00",X"7F",X"FF",X"00",X"00", - X"38",X"6C",X"38",X"FF",X"FF",X"10",X"00",X"10",X"7C",X"FC",X"00",X"01",X"7C",X"FF",X"FF",X"7C", - X"FE",X"BE",X"FE",X"FF",X"FF",X"36",X"3E",X"36",X"FF",X"FF",X"00",X"3F",X"00",X"00",X"FF",X"FF", - X"FF",X"00",X"00",X"FF",X"F8",X"FE",X"1F",X"00",X"3E",X"FF",X"FF",X"1C",X"08",X"1C",X"08",X"FF", - X"BD",X"EF",X"BF",X"FF",X"FF",X"EA",X"6C",X"AE",X"00",X"00",X"FF",X"00",X"EF",X"FF",X"FF",X"EF", - X"D2",X"DE",X"01",X"01",X"DE",X"FF",X"01",X"7E",X"6C",X"FF",X"FF",X"28",X"00",X"28",X"FF",X"FF", - X"01",X"D8",X"FF",X"00",X"50",X"D8",X"50",X"FF",X"FF",X"01",X"DC",X"7E",X"01",X"01",X"DC",X"FF", - X"FC",X"A4",X"02",X"02",X"FC",X"FF",X"02",X"B8",X"FF",X"00",X"BC",X"FF",X"03",X"BC",X"FF",X"03", - X"01",X"A0",X"FF",X"00",X"00",X"A0",X"FF",X"FF",X"FF",X"03",X"B0",X"B8",X"01",X"03",X"B0",X"FF", - X"28",X"CD",X"C3",X"0A",X"17",X"E7",X"FF",X"FF",X"A3",X"3A",X"FE",X"20",X"D2",X"01",X"1E",X"5F", - X"32",X"F1",X"20",X"DF",X"88",X"CD",X"C3",X"17",X"FF",X"FF",X"FF",X"FF",X"CD",X"FF",X"18",X"8D", - X"FE",X"1B",X"CA",X"80",X"1B",X"C0",X"8E",X"C3",X"16",X"E6",X"D1",X"3A",X"A7",X"20",X"C0",X"CA", - X"A7",X"E1",X"10",X"CA",X"FE",X"19",X"CA",X"01",X"E5",X"1B",X"7E",X"24",X"B6",X"23",X"B6",X"23", - X"67",X"00",X"49",X"C3",X"EB",X"18",X"C3",X"2B",X"19",X"10",X"D6",X"7D",X"6F",X"20",X"DE",X"7C", - X"18",X"49",X"15",X"FE",X"5C",X"D2",X"FE",X"1B",X"1B",X"DD",X"E6",X"7D",X"FE",X"1F",X"D2",X"19", - X"C3",X"1B",X"18",X"49",X"25",X"E5",X"23",X"7E",X"D2",X"10",X"18",X"49",X"09",X"FE",X"21",X"DA", - X"D6",X"7D",X"6F",X"20",X"DE",X"7C",X"67",X"00",X"23",X"B6",X"E1",X"B6",X"C2",X"A7",X"18",X"81", - X"20",X"D8",X"2D",X"C3",X"3A",X"16",X"20",X"D7",X"49",X"C3",X"32",X"18",X"20",X"D9",X"32",X"97", - X"CF",X"32",X"C3",X"20",X"05",X"5E",X"0F",X"3E",X"CA",X"A7",X"16",X"2D",X"7D",X"C3",X"3D",X"16", - X"C3",X"20",X"1B",X"7D",X"06",X"C5",X"11",X"00",X"CF",X"32",X"C3",X"20",X"16",X"5F",X"D5",X"32", - X"1F",X"1A",X"79",X"12",X"47",X"B0",X"FE",X"7B",X"20",X"B0",X"1A",X"B7",X"12",X"1F",X"13",X"4F", - X"C1",X"78",X"C0",X"A7",X"C3",X"2B",X"17",X"CC",X"CA",X"BF",X"1B",X"B8",X"C3",X"13",X"1B",X"A2", - X"EB",X"77",X"23",X"23",X"23",X"23",X"3C",X"7E",X"08",X"3E",X"90",X"C3",X"00",X"1B",X"03",X"3E", - X"77",X"23",X"D6",X"7D",X"6F",X"0A",X"00",X"00",X"70",X"23",X"71",X"23",X"72",X"23",X"73",X"23", - X"32",X"05",X"22",X"00",X"81",X"C9",X"0F",X"E6",X"C2",X"A7",X"19",X"26",X"00",X"3A",X"C6",X"22", - X"32",X"0F",X"20",X"ED",X"21",X"C3",X"00",X"1B",X"12",X"4F",X"ED",X"3A",X"3C",X"20",X"E6",X"3C", - X"12",X"D8",X"10",X"D8",X"0F",X"D8",X"11",X"D8",X"1A",X"88",X"1A",X"6B",X"1A",X"4E",X"1A",X"31", - X"42",X"C2",X"3A",X"1B",X"20",X"F4",X"00",X"85",X"E6",X"81",X"4F",X"0F",X"1B",X"D1",X"A7",X"12", - X"3D",X"20",X"ED",X"C3",X"D1",X"1B",X"24",X"24",X"3A",X"6F",X"20",X"F3",X"67",X"8C",X"F4",X"3A", - X"DF",X"3A",X"F5",X"20",X"32",X"97",X"20",X"DF",X"D2",X"C3",X"CD",X"1F",X"17",X"88",X"20",X"26", - X"1B",X"00",X"12",X"7C",X"7D",X"1B",X"3A",X"12",X"00",X"3A",X"6F",X"22",X"05",X"C3",X"00",X"1B", - X"1D",X"A5",X"EE",X"3A",X"A7",X"20",X"C5",X"C2",X"20",X"DF",X"01",X"FE",X"EE",X"C3",X"CD",X"13", - X"22",X"05",X"ED",X"3A",X"5F",X"20",X"19",X"16",X"3E",X"06",X"32",X"0C",X"20",X"EE",X"32",X"97", - X"FE",X"22",X"D2",X"02",X"19",X"1B",X"54",X"C3",X"32",X"1A",X"22",X"02",X"1A",X"13",X"01",X"32", - X"00",X"18",X"26",X"6F",X"7E",X"22",X"FE",X"2B",X"FE",X"19",X"CA",X"01",X"1B",X"68",X"49",X"C3", - X"F9",X"CA",X"57",X"1F",X"77",X"97",X"4E",X"2B",X"CA",X"0C",X"1F",X"7A",X"2B",X"5E",X"A7",X"7E", - X"A7",X"00",X"F8",X"C2",X"09",X"18",X"FE",X"7C",X"46",X"2B",X"95",X"C3",X"3A",X"06",X"20",X"DF", - X"26",X"18",X"7E",X"27",X"C2",X"A7",X"02",X"06",X"DA",X"25",X"18",X"C3",X"3E",X"FE",X"BB",X"DA", - X"01",X"3E",X"DF",X"32",X"3A",X"20",X"20",X"EF",X"98",X"C3",X"26",X"04",X"C3",X"3E",X"18",X"BB", - X"01",X"3E",X"F4",X"32",X"3E",X"20",X"32",X"02",X"32",X"3C",X"20",X"EF",X"32",X"97",X"20",X"F3", - X"18",X"ED",X"8A",X"CD",X"97",X"18",X"F6",X"32",X"20",X"F0",X"00",X"3A",X"FE",X"22",X"CA",X"05", - X"2B",X"EB",X"C3",X"7D",X"1B",X"E0",X"00",X"00",X"32",X"20",X"20",X"DF",X"C2",X"C3",X"C9",X"04", - X"00",X"01",X"FF",X"01",X"FF",X"00",X"FE",X"FF",X"FF",X"FF",X"FF",X"00",X"01",X"00",X"01",X"01", - X"49",X"C3",X"79",X"18",X"04",X"32",X"78",X"22",X"C6",X"7D",X"6F",X"20",X"CE",X"7C",X"67",X"00", - X"18",X"94",X"EB",X"22",X"C3",X"20",X"1B",X"C6",X"03",X"32",X"C3",X"22",X"19",X"5C",X"C3",X"2B", - X"06",X"9D",X"10",X"D2",X"3A",X"1A",X"20",X"EB",X"32",X"97",X"20",X"DF",X"EC",X"3A",X"CD",X"20", - X"03",X"FE",X"F0",X"DA",X"00",X"19",X"10",X"C3",X"A7",X"CD",X"D2",X"06",X"1A",X"10",X"1F",X"E6", - X"32",X"7C",X"22",X"03",X"00",X"3A",X"CD",X"22",X"C3",X"1A",X"1D",X"E6",X"32",X"7D",X"22",X"04", - X"23",X"23",X"F9",X"3A",X"BD",X"20",X"41",X"C3",X"18",X"8A",X"CA",X"C9",X"19",X"D0",X"23",X"23", - X"7E",X"23",X"13",X"12",X"7E",X"23",X"13",X"12",X"00",X"02",X"16",X"5F",X"7E",X"21",X"13",X"12", - X"19",X"9D",X"F9",X"3A",X"CD",X"20",X"19",X"72",X"C9",X"23",X"BC",X"CD",X"FE",X"00",X"DA",X"0D", - X"20",X"F9",X"D9",X"C3",X"23",X"1E",X"77",X"97",X"77",X"78",X"12",X"3D",X"23",X"13",X"32",X"7B", - X"CA",X"DA",X"3A",X"19",X"20",X"F8",X"72",X"CD",X"D6",X"C3",X"CD",X"1E",X"00",X"BC",X"07",X"FE", - X"43",X"60",X"FF",X"FF",X"FF",X"FF",X"3C",X"77",X"78",X"19",X"0B",X"FE",X"BE",X"C2",X"C3",X"19", - X"1F",X"17",X"97",X"23",X"C3",X"77",X"1F",X"14",X"13",X"12",X"7B",X"23",X"F8",X"32",X"C3",X"20", - X"F7",X"3A",X"CD",X"20",X"19",X"72",X"77",X"78",X"BC",X"CD",X"FE",X"00",X"DA",X"0C",X"13",X"38", - X"6A",X"C3",X"3E",X"19",X"C3",X"30",X"04",X"8F",X"12",X"3C",X"23",X"13",X"32",X"7B",X"20",X"F7", - X"DB",X"32",X"32",X"20",X"20",X"DC",X"00",X"C9",X"57",X"97",X"EB",X"32",X"32",X"20",X"20",X"EC", - X"20",X"FE",X"67",X"8C",X"25",X"FE",X"25",X"DA",X"1C",X"0A",X"FF",X"3A",X"85",X"20",X"3A",X"6F", - X"26",X"1E",X"1B",X"25",X"12",X"7C",X"7D",X"1B",X"FE",X"1E",X"DA",X"3E",X"1E",X"1B",X"1B",X"CA", - X"1E",X"1B",X"5F",X"1A",X"B3",X"0A",X"BC",X"C3",X"CD",X"12",X"1D",X"A5",X"26",X"C9",X"C3",X"3E", - X"0F",X"07",X"00",X"FF",X"00",X"00",X"FF",X"07",X"80",X"1D",X"09",X"80",X"FF",X"0B",X"80",X"00", - X"01",X"07",X"C0",X"FF",X"01",X"C0",X"FF",X"01",X"FE",X"FF",X"3F",X"F0",X"FF",X"07",X"C0",X"F0", - X"80",X"80",X"80",X"FF",X"FF",X"00",X"21",X"FF",X"80",X"C0",X"00",X"01",X"80",X"FF",X"FF",X"80", - X"C2",X"19",X"18",X"49",X"23",X"23",X"FE",X"7E",X"40",X"7F",X"11",X"3E",X"6F",X"85",X"FE",X"7E", - X"FF",X"FF",X"00",X"00",X"02",X"05",X"80",X"FF",X"C2",X"08",X"06",X"A7",X"F8",X"C3",X"FF",X"1A", - X"FF",X"FF",X"C0",X"00",X"07",X"01",X"00",X"FF",X"08",X"00",X"FF",X"05",X"80",X"00",X"08",X"00", - X"FF",X"FF",X"80",X"40",X"00",X"01",X"20",X"FF",X"01",X"00",X"FF",X"01",X"00",X"00",X"01",X"00", - X"FF",X"FF",X"EB",X"97",X"00",X"E9",X"02",X"3E",X"02",X"40",X"FF",X"01",X"20",X"00",X"02",X"00", - X"21",X"20",X"E0",X"FF",X"FE",X"22",X"CD",X"20",X"FB",X"32",X"21",X"20",X"01",X"00",X"FC",X"22", - X"00",X"1E",X"E5",X"2B",X"75",X"CD",X"E1",X"02",X"02",X"7F",X"23",X"00",X"A7",X"7E",X"D6",X"CA", - X"3A",X"23",X"20",X"F7",X"C2",X"BD",X"1E",X"C2",X"A7",X"7A",X"82",X"CA",X"23",X"19",X"23",X"23", - X"20",X"FE",X"87",X"CD",X"23",X"02",X"A7",X"7E",X"CD",X"00",X"1F",X"92",X"00",X"21",X"22",X"20", - X"7A",X"E1",X"C3",X"A7",X"1F",X"10",X"00",X"00",X"14",X"CA",X"2B",X"1F",X"CD",X"E5",X"02",X"6B", - X"FF",X"01",X"00",X"00",X"00",X"01",X"FF",X"FF",X"80",X"80",X"03",X"07",X"80",X"FF",X"03",X"00", - X"20",X"FA",X"C3",X"BD",X"02",X"48",X"02",X"3E",X"A3",X"CA",X"23",X"19",X"23",X"23",X"3A",X"23", - X"CD",X"20",X"05",X"A2",X"7E",X"23",X"CA",X"A7",X"FB",X"32",X"21",X"20",X"FF",X"FF",X"FC",X"22", - X"A7",X"7A",X"3E",X"CA",X"23",X"13",X"23",X"23",X"1F",X"3E",X"E5",X"2B",X"61",X"CD",X"E1",X"02", - X"92",X"CD",X"21",X"1F",X"E0",X"FF",X"FE",X"22",X"3A",X"23",X"20",X"F8",X"C2",X"BD",X"1F",X"2C", - X"19",X"67",X"E5",X"2B",X"57",X"CD",X"E1",X"02",X"CD",X"20",X"05",X"AA",X"7E",X"23",X"CA",X"A7", - X"1F",X"74",X"03",X"FE",X"E9",X"CA",X"3E",X"13",X"A7",X"7A",X"63",X"C3",X"00",X"19",X"CA",X"A7", - X"1D",X"70",X"2B",X"5E",X"97",X"56",X"CA",X"BA",X"32",X"01",X"20",X"DF",X"13",X"03",X"C3",X"23", - X"03",X"AA",X"2B",X"1C",X"2B",X"2B",X"C3",X"7D",X"1F",X"8B",X"77",X"12",X"8B",X"C3",X"1E",X"1F", - X"3A",X"04",X"20",X"F6",X"06",X"C3",X"3A",X"04",X"1F",X"EA",X"F5",X"3A",X"A7",X"20",X"10",X"C2", - X"CA",X"02",X"1F",X"B8",X"C8",X"21",X"C3",X"20",X"20",X"EF",X"01",X"FE",X"B2",X"CA",X"FE",X"1F", - X"C4",X"21",X"5E",X"20",X"56",X"23",X"4E",X"23",X"1F",X"BB",X"C0",X"21",X"C3",X"20",X"1F",X"BB", - X"E1",X"1D",X"C1",X"D1",X"E6",X"7D",X"CA",X"1F",X"46",X"23",X"C5",X"EB",X"E5",X"D5",X"53",X"CD", - X"5F",X"8B",X"F3",X"3A",X"8A",X"20",X"1A",X"57",X"04",X"2A",X"54",X"D5",X"3A",X"5D",X"20",X"F4", - X"18",X"10",X"00",X"32",X"C3",X"22",X"1B",X"DE",X"C2",X"A7",X"18",X"2D",X"F0",X"3A",X"C3",X"20", - X"2B",X"1D",X"2B",X"2B",X"C3",X"7D",X"1B",X"DE",X"FE",X"79",X"DA",X"20",X"1D",X"A1",X"97",X"C3", - X"C9",X"09",X"00",X"D3",X"02",X"D3",X"A6",X"C3",X"00",X"CD",X"CD",X"40",X"05",X"B2",X"CB",X"CD", - X"FF",X"0F",X"0F",X"F0",X"FF",X"FF",X"FF",X"FF",X"F0",X"08",X"FF",X"0F",X"0F",X"F0",X"F0",X"FF", - X"60",X"FF",X"FF",X"18",X"18",X"60",X"60",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"18",X"60", - X"FF",X"FF",X"30",X"FF",X"FF",X"C0",X"C0",X"30",X"FF",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"30",X"FF",X"FF",X"C0",X"C0",X"30",X"FF",X"FF", - X"FF",X"07",X"80",X"78",X"07",X"00",X"78",X"FF",X"80",X"78",X"07",X"00",X"78",X"FF",X"00",X"80", - X"FF",X"0F",X"00",X"F0",X"0F",X"00",X"F0",X"FF",X"00",X"80",X"FF",X"07",X"F0",X"FF",X"00",X"00", - X"FF",X"FF",X"00",X"E0",X"1E",X"01",X"E0",X"FF",X"00",X"00",X"FF",X"0F",X"00",X"F0",X"0F",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"01",X"00",X"FF",X"1E",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"3C",X"C0",X"FF",X"03",X"C0",X"00",X"03",X"3C", - X"00",X"FF",X"78",X"80",X"FF",X"07",X"80",X"00",X"FF",X"FF",X"FF",X"FF",X"80",X"00",X"07",X"78", - X"11",X"FF",X"FF",X"1F",X"1F",X"0E",X"00",X"FF",X"07",X"78",X"00",X"FF",X"78",X"80",X"FF",X"07", - X"32",X"FF",X"FF",X"3A",X"3E",X"1C",X"00",X"FF",X"FF",X"0E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"74",X"FF",X"FF",X"74",X"74",X"38",X"00",X"FF",X"FF",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"02",X"FF",X"D1",X"B6",X"66",X"C3",X"00",X"1F",X"FF",X"38",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"7C",X"23",X"40",X"FE",X"F6",X"C2",X"C9",X"1C",X"00",X"00",X"21",X"00",X"24",X"00",X"00",X"36", - X"FF",X"00",X"00",X"80",X"FF",X"FF",X"FF",X"FF",X"C0",X"C0",X"01",X"03",X"C0",X"FF",X"01",X"80", - X"FF",X"70",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"00",X"FF",X"E8",X"C8",X"70",X"00",X"FF", - X"01",X"00",X"00",X"FF",X"FF",X"E0",X"FF",X"FF",X"F0",X"FF",X"01",X"F0",X"FF",X"01",X"10",X"E0", - X"02",X"01",X"00",X"FF",X"00",X"C0",X"FF",X"01",X"E0",X"FF",X"03",X"E0",X"FF",X"02",X"60",X"C0", - X"05",X"03",X"00",X"FF",X"00",X"80",X"FF",X"03",X"C0",X"FF",X"05",X"C0",X"FF",X"05",X"C0",X"80", - X"D6",X"7D",X"4F",X"20",X"DE",X"7C",X"47",X"00",X"00",X"FF",X"0A",X"00",X"03",X"5F",X"57",X"0A", - X"2F",X"1A",X"0A",X"5F",X"C3",X"A3",X"1C",X"E9",X"C5",X"E5",X"2F",X"1A",X"77",X"A6",X"D5",X"13", - X"81",X"CD",X"FE",X"1D",X"C2",X"FF",X"1D",X"60",X"FE",X"1A",X"C2",X"FF",X"1D",X"63",X"E1",X"C1", - X"67",X"00",X"D6",X"79",X"4F",X"20",X"DE",X"78",X"13",X"C9",X"C6",X"7D",X"6F",X"20",X"CE",X"7C", - X"40",X"FE",X"9F",X"DA",X"26",X"1D",X"1A",X"25",X"47",X"00",X"25",X"FE",X"F0",X"DA",X"7C",X"1F", - X"57",X"0A",X"D6",X"7D",X"4F",X"20",X"DE",X"7C",X"06",X"C9",X"1A",X"3E",X"0A",X"C9",X"03",X"5F", - X"C3",X"D5",X"1E",X"2A",X"D1",X"02",X"13",X"03",X"47",X"00",X"C5",X"E5",X"B6",X"1A",X"13",X"77", - X"CD",X"E1",X"1D",X"81",X"FF",X"FE",X"B2",X"C2",X"1A",X"23",X"FF",X"FE",X"B5",X"C2",X"C1",X"1D", - X"EB",X"46",X"D5",X"C5",X"CD",X"E5",X"1D",X"53",X"C9",X"1D",X"23",X"5E",X"23",X"56",X"23",X"4E", - X"1B",X"0F",X"4F",X"12",X"02",X"C2",X"3A",X"1E",X"D1",X"E1",X"C3",X"C1",X"19",X"30",X"E6",X"81", - X"C3",X"67",X"1E",X"02",X"3A",X"C6",X"C3",X"6F",X"20",X"FD",X"6F",X"85",X"FC",X"3A",X"8C",X"20"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd deleted file mode 100644 index db8a803b..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/5.t32.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom5t32 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom5t32 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"77",X"5E",X"00",X"FF",X"75",X"00",X"FF",X"36",X"80",X"FF",X"77",X"80",X"FF",X"5F",X"00",X"80", - X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"14",X"36",X"00",X"FF",X"14",X"00", - X"16",X"C2",X"32",X"3D",X"22",X"42",X"6F",X"C3",X"31",X"CA",X"3A",X"42",X"22",X"42",X"CA",X"A7", - X"DD",X"32",X"C3",X"20",X"17",X"6F",X"FF",X"FF",X"3E",X"17",X"32",X"05",X"22",X"42",X"06",X"3E", - X"26",X"1D",X"CA",X"A7",X"42",X"55",X"43",X"3A",X"43",X"3A",X"A7",X"22",X"F2",X"CA",X"3A",X"45", - X"33",X"FE",X"65",X"DA",X"3E",X"42",X"32",X"01",X"3D",X"22",X"43",X"32",X"3A",X"22",X"20",X"D4", - X"00",X"22",X"00",X"00",X"D3",X"2A",X"3E",X"20",X"22",X"49",X"7B",X"C3",X"AF",X"42",X"49",X"32", - X"86",X"C3",X"2A",X"42",X"20",X"D3",X"26",X"7C",X"94",X"3D",X"D6",X"85",X"6F",X"01",X"3D",X"26", - X"3E",X"22",X"32",X"00",X"22",X"46",X"3A",X"C9",X"94",X"25",X"D6",X"85",X"6F",X"02",X"44",X"22", - X"A7",X"42",X"B2",X"CA",X"AF",X"42",X"48",X"32",X"20",X"E2",X"3A",X"A7",X"22",X"48",X"AA",X"CA", - X"C9",X"42",X"CA",X"A7",X"42",X"A1",X"32",X"AF",X"3A",X"22",X"22",X"45",X"33",X"FE",X"BB",X"D2", - X"42",X"BB",X"3A",X"C9",X"22",X"47",X"CA",X"A7",X"22",X"48",X"45",X"3A",X"FE",X"22",X"DA",X"33", - X"32",X"01",X"22",X"47",X"49",X"3A",X"A7",X"22",X"42",X"C7",X"32",X"3D",X"22",X"47",X"3E",X"C9", - X"17",X"D2",X"CD",X"43",X"42",X"E9",X"58",X"CD",X"78",X"C2",X"3A",X"47",X"22",X"45",X"26",X"FE", - X"2A",X"47",X"22",X"44",X"43",X"06",X"46",X"3A",X"3E",X"1D",X"32",X"A0",X"22",X"43",X"F2",X"C3", - X"57",X"0A",X"FF",X"C9",X"FF",X"FF",X"FF",X"FF",X"E6",X"22",X"87",X"03",X"0A",X"4F",X"03",X"5F", - X"44",X"2A",X"06",X"22",X"C3",X"47",X"42",X"EE",X"45",X"05",X"44",X"4F",X"44",X"AC",X"44",X"00", - X"42",X"E9",X"58",X"CD",X"3A",X"1D",X"22",X"46",X"49",X"3A",X"A7",X"22",X"8E",X"C2",X"CD",X"47", - X"22",X"44",X"D6",X"7D",X"6F",X"40",X"DE",X"7C",X"32",X"3C",X"22",X"46",X"03",X"E6",X"2A",X"F5", - X"2A",X"43",X"22",X"44",X"C6",X"7D",X"6F",X"1F",X"67",X"00",X"44",X"22",X"F1",X"22",X"47",X"C2", - X"42",X"E9",X"AA",X"CD",X"C9",X"1D",X"40",X"CD",X"CE",X"7C",X"67",X"00",X"44",X"22",X"CD",X"22", - X"40",X"A9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CD",X"42",X"46",X"D6",X"28",X"CD",X"C3",X"0A", - X"20",X"AB",X"01",X"FE",X"7A",X"DA",X"3E",X"43",X"E2",X"3A",X"A7",X"20",X"74",X"CA",X"3A",X"43", - X"43",X"6A",X"0C",X"3E",X"07",X"36",X"C0",X"C3",X"C3",X"46",X"43",X"7C",X"A7",X"3A",X"C3",X"20", - X"0F",X"07",X"00",X"FF",X"07",X"00",X"FF",X"07",X"80",X"19",X"0F",X"C0",X"FF",X"1F",X"80",X"00", - X"FF",X"07",X"00",X"00",X"07",X"07",X"00",X"FF",X"00",X"00",X"07",X"07",X"00",X"FF",X"07",X"00", - X"00",X"FF",X"02",X"00",X"FF",X"07",X"00",X"00",X"07",X"00",X"FF",X"07",X"00",X"00",X"07",X"07", - X"00",X"00",X"02",X"02",X"00",X"FF",X"02",X"00",X"02",X"02",X"00",X"FF",X"02",X"00",X"FF",X"02", - X"00",X"00",X"04",X"0E",X"00",X"FF",X"04",X"00",X"FF",X"02",X"00",X"00",X"02",X"00",X"FF",X"FF", - X"00",X"00",X"00",X"08",X"FF",X"FF",X"00",X"C0",X"FF",X"00",X"00",X"FF",X"1C",X"00",X"FF",X"08", - X"FF",X"10",X"00",X"00",X"00",X"10",X"FF",X"FF",X"38",X"EF",X"00",X"07",X"00",X"FF",X"38",X"00", - X"00",X"00",X"01",X"00",X"FF",X"00",X"FF",X"FF",X"00",X"00",X"00",X"80",X"01",X"03",X"00",X"FF", - X"20",X"3E",X"0F",X"C3",X"3E",X"40",X"D3",X"00",X"E2",X"32",X"3E",X"20",X"D3",X"20",X"C9",X"01", - X"40",X"FE",X"14",X"C2",X"DF",X"40",X"C3",X"C9",X"21",X"07",X"24",X"00",X"00",X"36",X"7C",X"23", - X"E2",X"3A",X"A7",X"20",X"35",X"CA",X"F1",X"40",X"0C",X"92",X"FF",X"FF",X"FF",X"FF",X"F5",X"FF", - X"3B",X"3B",X"C9",X"F1",X"10",X"3E",X"27",X"C3",X"20",X"F6",X"36",X"C3",X"F1",X"40",X"07",X"D3", - X"C3",X"20",X"40",X"27",X"04",X"21",X"11",X"3E",X"97",X"40",X"27",X"C3",X"97",X"40",X"EA",X"32", - X"CD",X"D5",X"09",X"F1",X"11",X"00",X"FD",X"E0",X"40",X"90",X"00",X"06",X"02",X"0E",X"C5",X"E5", - X"C2",X"D5",X"40",X"59",X"C1",X"D1",X"04",X"E1",X"7C",X"19",X"C1",X"D1",X"FE",X"90",X"C5",X"2C", - X"13",X"13",X"DF",X"D5",X"59",X"C3",X"DF",X"40",X"FE",X"78",X"CA",X"0B",X"40",X"7F",X"C5",X"E5", - X"20",X"C3",X"FF",X"4E",X"FF",X"FF",X"EA",X"3B",X"DF",X"DF",X"DF",X"DF",X"DF",X"DF",X"DF",X"DF", - X"26",X"02",X"26",X"26",X"26",X"06",X"26",X"00",X"26",X"19",X"26",X"08",X"26",X"0B",X"26",X"04", - X"CA",X"43",X"17",X"EA",X"28",X"CD",X"C2",X"0A",X"26",X"0C",X"26",X"04",X"26",X"12",X"4E",X"C3", - X"17",X"EA",X"3C",X"A7",X"32",X"27",X"20",X"AD",X"40",X"AC",X"AD",X"3A",X"FE",X"20",X"CA",X"99", - X"F3",X"08",X"45",X"C3",X"3E",X"08",X"D3",X"00",X"E2",X"CD",X"C3",X"09",X"17",X"EA",X"53",X"D2", - X"41",X"76",X"E2",X"3A",X"A7",X"20",X"E8",X"CA",X"D3",X"01",X"D3",X"06",X"D3",X"07",X"C3",X"04", - X"03",X"DB",X"E3",X"C3",X"3A",X"40",X"20",X"E2",X"DB",X"40",X"07",X"00",X"C3",X"07",X"15",X"F9", - X"DB",X"C9",X"E6",X"03",X"C9",X"10",X"23",X"23",X"CA",X"A7",X"40",X"F9",X"00",X"DB",X"10",X"E6", - X"CD",X"C5",X"0B",X"D3",X"0A",X"C1",X"C5",X"0B",X"23",X"E5",X"2E",X"66",X"C1",X"1D",X"0B",X"0A", - X"D3",X"C3",X"67",X"0B",X"3A",X"F5",X"20",X"E2",X"D3",X"CD",X"C1",X"0B",X"0B",X"0A",X"C1",X"C5", - X"00",X"CE",X"32",X"27",X"20",X"AB",X"F1",X"C9",X"CA",X"A7",X"41",X"2F",X"3A",X"F1",X"20",X"AB", - X"C9",X"20",X"1B",X"2B",X"DA",X"B8",X"41",X"5A",X"A7",X"3A",X"CE",X"20",X"27",X"00",X"A7",X"32", - X"FF",X"FF",X"1B",X"2B",X"DA",X"B8",X"41",X"6A",X"33",X"C8",X"C3",X"33",X"05",X"03",X"FF",X"FF", - X"FF",X"FF",X"A5",X"11",X"21",X"20",X"20",X"A1",X"33",X"C8",X"C3",X"33",X"05",X"18",X"FF",X"FF", - X"FF",X"FF",X"A9",X"11",X"21",X"20",X"20",X"A1",X"03",X"06",X"C3",X"EF",X"05",X"03",X"FF",X"FF", - X"E2",X"32",X"C3",X"20",X"00",X"B6",X"FF",X"FF",X"03",X"06",X"C3",X"EF",X"05",X"18",X"00",X"3E", - X"FF",X"05",X"70",X"E8",X"07",X"05",X"50",X"FF",X"78",X"78",X"07",X"05",X"78",X"FF",X"07",X"F8", - X"40",X"FF",X"01",X"00",X"FF",X"00",X"F0",X"FF",X"07",X"60",X"FF",X"03",X"40",X"60",X"01",X"03", - X"F0",X"FF",X"0B",X"A0",X"FF",X"0E",X"C0",X"E0",X"0E",X"F0",X"FF",X"0A",X"D0",X"F0",X"0B",X"0E", - X"00",X"80",X"00",X"02",X"FF",X"FF",X"20",X"E0",X"06",X"0E",X"C0",X"FF",X"06",X"80",X"FF",X"02", - X"C0",X"E0",X"16",X"17",X"C0",X"FF",X"1B",X"80",X"1D",X"1D",X"E0",X"FF",X"1B",X"E0",X"FF",X"17", - X"05",X"00",X"FF",X"00",X"C0",X"FF",X"3B",X"C0",X"FF",X"0B",X"00",X"80",X"05",X"0B",X"00",X"FF", - X"2F",X"80",X"FF",X"2B",X"00",X"80",X"1B",X"3B",X"FF",X"3B",X"C0",X"40",X"2F",X"3A",X"C0",X"FF", - X"00",X"0A",X"FF",X"FF",X"80",X"80",X"77",X"77",X"00",X"FF",X"1B",X"00",X"FF",X"0A",X"00",X"00", - X"43",X"DE",X"43",X"D3",X"43",X"C8",X"43",X"81",X"43",X"F0",X"45",X"91",X"45",X"7F",X"45",X"64", - X"E0",X"FF",X"EC",X"00",X"E1",X"1E",X"00",X"E7",X"80",X"C0",X"FB",X"7F",X"C3",X"C1",X"03",X"01", - X"0E",X"00",X"F0",X"FF",X"E6",X"00",X"3B",X"10",X"FF",X"07",X"00",X"E0",X"00",X"EA",X"7E",X"71", - X"3C",X"13",X"08",X"00",X"F0",X"FF",X"E0",X"00",X"00",X"3C",X"FF",X"1C",X"00",X"D0",X"38",X"BF", - X"27",X"03",X"E0",X"FF",X"EE",X"00",X"01",X"C0",X"03",X"70",X"FF",X"7E",X"00",X"F0",X"E0",X"EA", - X"C0",X"FF",X"FD",X"00",X"00",X"00",X"FF",X"07",X"FF",X"03",X"00",X"E0",X"80",X"BF",X"03",X"01", - X"1E",X"00",X"00",X"00",X"FF",X"1C",X"00",X"00",X"00",X"80",X"00",X"7F",X"0E",X"00",X"00",X"FF", - X"FE",X"5F",X"F0",X"70",X"38",X"FF",X"7B",X"80",X"00",X"00",X"08",X"00",X"FF",X"FF",X"E0",X"F0", - X"80",X"7A",X"9F",X"1C",X"03",X"00",X"BC",X"FF",X"38",X"C7",X"00",X"F9",X"FF",X"01",X"00",X"B8", - X"00",X"F4",X"0E",X"EF",X"0F",X"04",X"02",X"00",X"F9",X"00",X"0E",X"04",X"00",X"0F",X"FF",X"07", - X"00",X"BC",X"F8",X"FA",X"09",X"00",X"B8",X"FF",X"3C",X"FF",X"F8",X"00",X"00",X"9C",X"FF",X"1F", - X"70",X"FF",X"3F",X"00",X"00",X"C0",X"FF",X"01",X"7B",X"00",X"FF",X"F0",X"00",X"F8",X"E0",X"6F", - X"07",X"00",X"00",X"00",X"FF",X"07",X"00",X"00",X"00",X"E0",X"80",X"1F",X"03",X"00",X"80",X"FF", - X"A7",X"22",X"E2",X"CA",X"3D",X"46",X"4A",X"32",X"00",X"00",X"02",X"00",X"FF",X"FF",X"4A",X"3A", - X"4B",X"3A",X"FE",X"22",X"DA",X"02",X"46",X"F9",X"C9",X"22",X"43",X"3A",X"32",X"22",X"22",X"4A", - X"3E",X"C9",X"C3",X"08",X"46",X"F2",X"FF",X"FF",X"1F",X"00",X"4B",X"32",X"CD",X"22",X"40",X"27", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"47",X"10",X"46",X"10",X"46",X"76",X"45",X"9E", - X"80",X"FF",X"B3",X"00",X"87",X"78",X"03",X"9C",X"00",X"00",X"EE",X"FD",X"0F",X"05",X"0F",X"07", - X"39",X"01",X"C0",X"FF",X"9B",X"00",X"EF",X"40",X"FF",X"1F",X"00",X"80",X"00",X"AB",X"F8",X"C7", - X"F0",X"4E",X"20",X"00",X"C0",X"FF",X"83",X"00",X"00",X"F0",X"FF",X"70",X"00",X"C0",X"E0",X"FE", - X"80",X"AB",X"9F",X"0F",X"80",X"FF",X"BB",X"00",X"0F",X"C0",X"00",X"F9",X"FF",X"01",X"00",X"C0", - X"0E",X"06",X"00",X"FF",X"F7",X"00",X"03",X"00",X"07",X"00",X"FF",X"0F",X"00",X"80",X"00",X"FE", - X"00",X"FF",X"78",X"00",X"00",X"00",X"FF",X"70",X"FF",X"1C",X"00",X"00",X"00",X"FE",X"38",X"01", - X"45",X"3A",X"FE",X"22",X"DA",X"3D",X"47",X"8E",X"00",X"00",X"00",X"00",X"20",X"00",X"FF",X"FF", - X"43",X"32",X"C3",X"22",X"47",X"F8",X"08",X"CD",X"08",X"CD",X"CD",X"43",X"1D",X"58",X"A0",X"3E", - X"46",X"32",X"E6",X"22",X"F5",X"03",X"44",X"2A",X"CD",X"43",X"1D",X"58",X"46",X"3A",X"3C",X"22", - X"22",X"67",X"22",X"44",X"C2",X"F1",X"47",X"BE",X"7D",X"22",X"40",X"C6",X"7C",X"6F",X"00",X"CE", - X"00",X"DE",X"22",X"67",X"22",X"44",X"08",X"CD",X"44",X"2A",X"7D",X"22",X"01",X"D6",X"7C",X"6F", - X"A7",X"22",X"D2",X"CA",X"3E",X"47",X"32",X"A0",X"CD",X"43",X"1D",X"AA",X"F5",X"C9",X"43",X"3A", - X"43",X"4A",X"48",X"4F",X"52",X"48",X"49",X"4E",X"22",X"43",X"C3",X"F1",X"01",X"45",X"FF",X"FF", - X"41",X"48",X"4D",X"42",X"50",X"55",X"45",X"52",X"53",X"20",X"20",X"4C",X"53",X"41",X"54",X"54", - X"D3",X"AF",X"C3",X"01",X"42",X"7B",X"FF",X"FF",X"52",X"59",X"D3",X"AF",X"C3",X"01",X"42",X"6C", - X"E0",X"FC",X"E7",X"1F",X"FF",X"1C",X"DC",X"00",X"F8",X"E0",X"3F",X"73",X"3C",X"7E",X"00",X"FF", - X"C3",X"5E",X"83",X"3D",X"00",X"07",X"FF",X"00",X"1D",X"C1",X"0E",X"C3",X"00",X"01",X"80",X"FF", - X"7E",X"FE",X"02",X"3F",X"FF",X"01",X"DE",X"00",X"1E",X"00",X"BC",X"E7",X"03",X"07",X"00",X"FF", - X"9C",X"00",X"1D",X"70",X"00",X"FF",X"E0",X"F8",X"3C",X"3C",X"00",X"FF",X"38",X"5C",X"FF",X"3D", - X"00",X"FF",X"80",X"C0",X"FF",X"03",X"00",X"FF",X"FF",X"1F",X"F0",X"00",X"0F",X"C0",X"00",X"01", - X"C0",X"00",X"7F",X"00",X"C1",X"7E",X"01",X"0E",X"3E",X"80",X"E7",X"F7",X"07",X"C3",X"FF",X"03", - X"FF",X"00",X"E0",X"00",X"D5",X"38",X"73",X"3C",X"00",X"FF",X"10",X"C0",X"3C",X"DD",X"1C",X"E1", - X"FF",X"3B",X"E0",X"00",X"7F",X"E0",X"13",X"27",X"00",X"08",X"00",X"FF",X"70",X"E0",X"7E",X"C1", - X"C0",X"00",X"D5",X"80",X"03",X"03",X"00",X"FF",X"00",X"FF",X"C0",X"E0",X"03",X"CD",X"FF",X"03", - X"7F",X"00",X"01",X"0E",X"00",X"FF",X"00",X"00",X"00",X"C0",X"07",X"D9",X"FF",X"01",X"80",X"00", - X"00",X"08",X"FF",X"FF",X"E0",X"80",X"FD",X"CF",X"1C",X"EF",X"FF",X"00",X"00",X"00",X"3C",X"00", - X"9F",X"5F",X"03",X"70",X"FF",X"00",X"70",X"00",X"F0",X"F9",X"00",X"01",X"00",X"FF",X"80",X"F0", - X"0E",X"78",X"0F",X"F5",X"02",X"1C",X"FF",X"00",X"77",X"04",X"38",X"0F",X"00",X"07",X"00",X"FF", - X"F8",X"F8",X"09",X"DF",X"FF",X"04",X"78",X"00",X"78",X"00",X"F0",X"9C",X"0E",X"1F",X"00",X"FF", - X"70",X"00",X"76",X"C0",X"00",X"01",X"00",X"FF",X"F3",X"F0",X"00",X"FF",X"E0",X"70",X"FF",X"F5", - X"3B",X"00",X"00",X"07",X"00",X"FF",X"00",X"00",X"80",X"E0",X"03",X"5F",X"FF",X"00",X"C0",X"00", - X"9C",X"DE",X"1F",X"0F",X"FF",X"0F",X"00",X"00",X"02",X"0F",X"FF",X"00",X"00",X"FF",X"F8",X"00", - X"40",X"00",X"F0",X"77",X"70",X"87",X"FF",X"03",X"FD",X"00",X"07",X"F8",X"07",X"39",X"00",X"FF", - X"00",X"FF",X"C0",X"80",X"F9",X"07",X"01",X"EF",X"80",X"00",X"57",X"E0",X"CF",X"F0",X"01",X"20", - X"00",X"FF",X"00",X"80",X"0F",X"37",X"FF",X"0F",X"FF",X"00",X"80",X"00",X"FE",X"80",X"4D",X"9F", - X"00",X"00",X"1C",X"67",X"FF",X"07",X"00",X"00",X"00",X"00",X"57",X"00",X"0F",X"0E",X"00",X"FF", - X"70",X"BC",X"FF",X"03",X"00",X"00",X"F0",X"00",X"FE",X"00",X"05",X"38",X"00",X"FF",X"00",X"00", - X"1F",X"F7",X"00",X"07",X"C0",X"FF",X"DF",X"00",X"00",X"20",X"FF",X"FF",X"C0",X"7F",X"DF",X"DF", - X"00",X"FF",X"20",X"00",X"FF",X"00",X"00",X"FF",X"1F",X"F8",X"FF",X"00",X"00",X"00",X"20",X"F8", - X"40",X"E0",X"00",X"FF",X"40",X"00",X"FF",X"00",X"BF",X"00",X"1F",X"E0",X"FF",X"00",X"00",X"00", - X"00",X"00",X"00",X"80",X"FF",X"FF",X"F8",X"FC",X"00",X"FF",X"C0",X"00",X"01",X"80",X"FF",X"00", - X"0E",X"71",X"FF",X"7E",X"00",X"AE",X"E0",X"1E",X"3F",X"17",X"3C",X"1C",X"CE",X"FF",X"1E",X"E0", - X"00",X"C3",X"FF",X"01",X"80",X"FD",X"C3",X"3F",X"E7",X"07",X"6F",X"FF",X"BE",X"00",X"03",X"C1", - X"FF",X"07",X"00",X"AF",X"7E",X"3E",X"02",X"00",X"83",X"01",X"0F",X"FF",X"3E",X"00",X"00",X"E7", - X"38",X"1F",X"FC",X"FF",X"0F",X"00",X"FF",X"70",X"EE",X"FF",X"1E",X"00",X"FF",X"3C",X"00",X"FE", - X"00",X"C0",X"FF",X"01",X"00",X"00",X"80",X"00",X"00",X"F8",X"E0",X"07",X"E0",X"FF",X"01",X"00", - X"FF",X"42",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"3E",X"01",X"D3",X"8F",X"C3"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd deleted file mode 100644 index bf2ef75f..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/roms/6.t31.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity rom6t31 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of rom6t31 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"10",X"13",X"03",X"01",X"00",X"05",X"05",X"06",X"08",X"14",X"00",X"05",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"04",X"01",X"12",X"09",X"14",X"0E",X"0F", - X"57",X"21",X"36",X"22",X"21",X"00",X"2E",X"88",X"00",X"1B",X"00",X"1B",X"00",X"1B",X"00",X"00", - X"32",X"00",X"22",X"5B",X"1C",X"C2",X"C3",X"49",X"13",X"C3",X"21",X"49",X"22",X"57",X"3E",X"34", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"05",X"18",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"C2",X"0D",X"4A",X"55",X"18",X"11",X"19",X"00",X"0C",X"21",X"0E",X"2E",X"36",X"08",X"23",X"00", - X"FF",X"04",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"7C",X"C2",X"37",X"4A",X"53",X"D3",X"C3", - X"CA",X"81",X"4A",X"83",X"01",X"3E",X"59",X"32",X"03",X"DB",X"7F",X"EE",X"E6",X"F3",X"FE",X"81", - X"32",X"AF",X"22",X"59",X"00",X"DB",X"80",X"E6",X"AF",X"22",X"3A",X"C9",X"22",X"59",X"C8",X"A7", - X"22",X"5A",X"CA",X"A7",X"4A",X"A5",X"32",X"AF",X"97",X"CA",X"3E",X"4A",X"A7",X"01",X"3A",X"C9", - X"22",X"5A",X"C9",X"AF",X"18",X"01",X"1A",X"04",X"22",X"5A",X"93",X"C3",X"3E",X"4A",X"32",X"01", - X"06",X"C8",X"D5",X"04",X"1C",X"11",X"19",X"00",X"13",X"77",X"05",X"23",X"AF",X"C2",X"0D",X"4A", - X"4B",X"E0",X"AC",X"CD",X"21",X"4A",X"2A",X"16",X"C3",X"D1",X"4A",X"AF",X"16",X"21",X"11",X"26", - X"11",X"2E",X"4D",X"00",X"AC",X"CD",X"21",X"4A",X"A0",X"11",X"CD",X"4C",X"4A",X"AC",X"16",X"21", - X"60",X"11",X"21",X"4D",X"36",X"16",X"AC",X"CD",X"32",X"16",X"40",X"11",X"CD",X"4C",X"4A",X"AC", - X"4A",X"AC",X"DF",X"DF",X"DF",X"DF",X"C9",X"DF",X"11",X"4A",X"4D",X"C0",X"16",X"21",X"CD",X"3A", - X"1F",X"00",X"44",X"24",X"1F",X"24",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"3E",X"00",X"41",X"41",X"22",X"41",X"00",X"00",X"7F",X"00",X"49",X"49",X"36",X"49",X"00",X"00", - X"7F",X"00",X"49",X"49",X"41",X"49",X"00",X"00",X"7F",X"00",X"41",X"41",X"3E",X"41",X"00",X"00", - X"3E",X"00",X"41",X"41",X"47",X"45",X"00",X"00",X"7F",X"00",X"48",X"48",X"40",X"48",X"00",X"00", - X"00",X"00",X"7F",X"41",X"00",X"41",X"00",X"00",X"7F",X"00",X"08",X"08",X"7F",X"08",X"00",X"00", - X"7F",X"00",X"14",X"08",X"41",X"22",X"00",X"00",X"02",X"00",X"01",X"01",X"7E",X"01",X"00",X"00", - X"7F",X"00",X"18",X"20",X"7F",X"20",X"00",X"00",X"7F",X"00",X"01",X"01",X"01",X"01",X"00",X"00", - X"3E",X"00",X"41",X"41",X"3E",X"41",X"00",X"00",X"7F",X"00",X"08",X"10",X"7F",X"04",X"00",X"00", - X"3E",X"00",X"45",X"41",X"3D",X"42",X"00",X"00",X"7F",X"00",X"48",X"48",X"30",X"48",X"00",X"00", - X"32",X"00",X"49",X"49",X"26",X"49",X"00",X"00",X"7F",X"00",X"4C",X"48",X"31",X"4A",X"00",X"00", - X"7E",X"00",X"01",X"01",X"7E",X"01",X"00",X"00",X"40",X"00",X"7F",X"40",X"40",X"40",X"00",X"00", - X"7F",X"00",X"0C",X"02",X"7F",X"02",X"00",X"00",X"7C",X"00",X"01",X"02",X"7C",X"02",X"00",X"00", - X"60",X"00",X"0F",X"10",X"60",X"10",X"00",X"00",X"63",X"00",X"08",X"14",X"63",X"14",X"00",X"00", - X"08",X"00",X"08",X"08",X"08",X"08",X"00",X"00",X"43",X"00",X"49",X"45",X"61",X"51",X"00",X"00", - X"00",X"00",X"FF",X"C0",X"00",X"00",X"FF",X"F8",X"00",X"00",X"F8",X"00",X"00",X"00",X"FF",X"00", - X"FC",X"00",X"00",X"FF",X"FF",X"80",X"00",X"1F",X"00",X"00",X"FF",X"FF",X"F0",X"00",X"07",X"FF", - X"C2",X"23",X"48",X"03",X"A0",X"3E",X"43",X"32",X"00",X"21",X"36",X"00",X"23",X"00",X"FE",X"7C", - X"32",X"3D",X"22",X"4C",X"CA",X"A7",X"48",X"22",X"C3",X"22",X"40",X"CD",X"3A",X"F5",X"22",X"4C", - X"C3",X"33",X"1F",X"9F",X"D5",X"1A",X"11",X"E5",X"C9",X"F1",X"03",X"3E",X"4C",X"32",X"33",X"22", - X"0D",X"13",X"2C",X"C2",X"C9",X"48",X"FF",X"FF",X"4B",X"00",X"AA",X"CD",X"E1",X"0B",X"24",X"D1", - X"46",X"1A",X"DA",X"B8",X"48",X"57",X"7E",X"C2",X"AB",X"11",X"21",X"20",X"20",X"A7",X"03",X"0E", - X"50",X"32",X"11",X"22",X"20",X"A5",X"4D",X"21",X"1B",X"48",X"0D",X"2B",X"48",X"C2",X"AF",X"48", - X"22",X"4F",X"03",X"0E",X"46",X"1A",X"DA",X"B8",X"06",X"22",X"EF",X"03",X"A3",X"11",X"21",X"20", - X"6C",X"C2",X"C3",X"48",X"05",X"18",X"20",X"3E",X"48",X"89",X"18",X"C2",X"1B",X"05",X"0D",X"2B", - X"21",X"48",X"20",X"A1",X"4D",X"11",X"06",X"22",X"50",X"32",X"11",X"22",X"20",X"A9",X"5E",X"C3", - X"07",X"D3",X"51",X"21",X"3E",X"22",X"77",X"01",X"EF",X"03",X"80",X"C3",X"3A",X"49",X"22",X"50", - X"49",X"A0",X"0F",X"0E",X"2C",X"CD",X"3A",X"48",X"77",X"23",X"77",X"23",X"99",X"21",X"11",X"29", - X"11",X"49",X"0B",X"90",X"08",X"0E",X"F1",X"CD",X"22",X"50",X"21",X"A7",X"2D",X"17",X"76",X"C2", - X"CD",X"11",X"48",X"2C",X"93",X"21",X"11",X"29",X"21",X"09",X"28",X"95",X"B0",X"11",X"0E",X"49", - X"29",X"91",X"D8",X"11",X"0E",X"49",X"CD",X"0F",X"49",X"C8",X"0F",X"0E",X"2C",X"CD",X"21",X"48", - X"12",X"0E",X"2C",X"CD",X"21",X"48",X"2F",X"8D",X"48",X"2C",X"0F",X"21",X"11",X"28",X"49",X"E8", - X"0B",X"21",X"11",X"29",X"4A",X"08",X"10",X"0E",X"00",X"11",X"0E",X"4A",X"CD",X"03",X"48",X"2C", - X"0E",X"4A",X"CD",X"05",X"48",X"2C",X"03",X"3E",X"2C",X"CD",X"21",X"48",X"2E",X"88",X"20",X"11", - X"22",X"22",X"22",X"55",X"55",X"2A",X"0E",X"22",X"28",X"C3",X"11",X"4A",X"22",X"51",X"54",X"32", - X"22",X"50",X"C2",X"A7",X"49",X"4F",X"03",X"DB",X"D5",X"01",X"2C",X"CD",X"DF",X"48",X"3A",X"D1", - X"C4",X"20",X"49",X"6D",X"03",X"DB",X"10",X"E6",X"40",X"E6",X"64",X"C4",X"DB",X"49",X"E6",X"03", - X"C2",X"00",X"49",X"16",X"92",X"C3",X"DB",X"49",X"33",X"CA",X"C3",X"4A",X"4E",X"50",X"22",X"54", - X"20",X"E6",X"6D",X"C4",X"DB",X"49",X"E6",X"00",X"E6",X"00",X"C4",X"40",X"49",X"64",X"00",X"DB", - X"C0",X"1B",X"12",X"AF",X"1A",X"C9",X"12",X"3D",X"C3",X"10",X"49",X"40",X"3C",X"1A",X"FE",X"12", - X"C3",X"0B",X"48",X"BC",X"FF",X"FF",X"FF",X"FF",X"F0",X"A7",X"1A",X"3E",X"C9",X"12",X"98",X"11", - X"48",X"94",X"01",X"3E",X"E2",X"32",X"C3",X"20",X"11",X"CD",X"3A",X"40",X"22",X"50",X"CA",X"A7", - X"FF",X"05",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"48",X"95",X"32",X"AF",X"20",X"E2",X"18",X"C3", - X"01",X"0C",X"09",X"14",X"0E",X"0F",X"00",X"13",X"0F",X"03",X"07",X"0E",X"01",X"12",X"15",X"14", - X"01",X"00",X"08",X"03",X"09",X"05",X"05",X"16",X"0F",X"19",X"00",X"15",X"01",X"08",X"05",X"16", - X"0F",X"14",X"01",X"04",X"13",X"19",X"08",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00", - X"0C",X"10",X"01",X"05",X"05",X"13",X"12",X"00",X"1B",X"09",X"03",X"13",X"12",X"0F",X"00",X"05", - X"0F",X"19",X"12",X"15",X"09",X"00",X"09",X"0E",X"07",X"05",X"13",X"09",X"05",X"14",X"00",X"12", - X"08",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"14",X"0C",X"01",X"00",X"13",X"09",X"17", - X"07",X"E0",X"07",X"E0",X"03",X"FF",X"FF",X"C0",X"1F",X"80",X"01",X"F8",X"0F",X"C0",X"03",X"F0", - X"00",X"7F",X"FE",X"00",X"00",X"3F",X"FC",X"00",X"01",X"FF",X"FF",X"80",X"00",X"FF",X"FF",X"00", - X"06",X"06",X"EE",X"7E",X"77",X"FF",X"05",X"23",X"0F",X"0E",X"15",X"21",X"11",X"25",X"00",X"1A", - X"19",X"4E",X"28",X"C3",X"0D",X"4E",X"C5",X"F5",X"2A",X"C2",X"7C",X"4E",X"3E",X"FE",X"3D",X"CA", - X"FF",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"DF",X"C1",X"00",X"C2",X"F1",X"4E",X"22", - X"3A",X"24",X"22",X"54",X"CA",X"3D",X"49",X"92",X"5B",X"3A",X"A7",X"22",X"1C",X"C2",X"13",X"49", - X"C3",X"3D",X"49",X"16",X"FF",X"FF",X"FF",X"FF",X"01",X"3E",X"5B",X"32",X"3A",X"22",X"22",X"54", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"3F",X"FF",X"00",X"00",X"0F",X"FF",X"00",X"00",X"FF",X"F0",X"00",X"03",X"FF",X"FC",X"00",X"00", - X"FF",X"FC",X"00",X"00",X"FF",X"F0",X"00",X"03",X"0F",X"FF",X"00",X"00",X"3F",X"FF",X"00",X"00", - X"F0",X"00",X"07",X"FF",X"00",X"00",X"FF",X"FF",X"FF",X"80",X"00",X"1F",X"FC",X"00",X"00",X"FF", - X"00",X"00",X"FF",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"FF",X"F8",X"00",X"00",X"FF",X"C0", - X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00", - X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00", - X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"F8",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00", - X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00",X"00",X"00",X"F8",X"00", - X"FF",X"FC",X"3F",X"FF",X"FF",X"FE",X"7F",X"FF",X"FF",X"F0",X"0F",X"FF",X"FF",X"F8",X"1F",X"FF", - X"00",X"3F",X"FC",X"00",X"00",X"1F",X"F8",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"7F",X"FE",X"00", - X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00", - X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00", - X"00",X"7F",X"FE",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"1F",X"F8",X"00",X"00",X"3F",X"FC",X"00", - X"FF",X"F8",X"1F",X"FF",X"FF",X"F0",X"0F",X"FF",X"FF",X"FE",X"7F",X"FF",X"FF",X"FC",X"3F",X"FF", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"E0",X"00",X"F8",X"03",X"E0",X"00",X"F8",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"00",X"F8",X"03", - X"FE",X"00",X"F8",X"03",X"FF",X"80",X"F8",X"03",X"F0",X"00",X"F8",X"03",X"FC",X"00",X"F8",X"03", - X"EF",X"F8",X"F8",X"03",X"E3",X"FC",X"F8",X"03",X"FF",X"C0",X"F8",X"03",X"FF",X"E0",X"F8",X"03", - X"C0",X"3F",X"7F",X"FF",X"80",X"0F",X"7F",X"FF",X"E1",X"FF",X"FC",X"07",X"C0",X"FF",X"FE",X"0F", - X"00",X"01",X"07",X"F8",X"00",X"00",X"00",X"00",X"00",X"07",X"3F",X"FF",X"00",X"03",X"1F",X"FE", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"FF",X"FF",X"FF",X"FF",X"E0",X"1F",X"F8",X"03", - X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03", - X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03", - X"E0",X"1F",X"F8",X"03",X"00",X"1F",X"F8",X"00",X"E0",X"1F",X"F8",X"03",X"E0",X"1F",X"F8",X"03", - X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00",X"00",X"1F",X"F8",X"00", - X"00",X"FF",X"FF",X"00",X"01",X"FF",X"FF",X"80",X"00",X"3F",X"FC",X"00",X"00",X"7F",X"FE",X"00", - X"0F",X"C0",X"03",X"F0",X"1F",X"80",X"01",X"F8",X"03",X"FF",X"FF",X"C0",X"07",X"E0",X"07",X"E0", - X"FC",X"00",X"00",X"3F",X"F8",X"00",X"00",X"1F",X"3F",X"00",X"00",X"FC",X"FE",X"00",X"00",X"7F", - X"FE",X"00",X"00",X"7F",X"3F",X"00",X"00",X"FC",X"F8",X"00",X"00",X"1F",X"FC",X"00",X"00",X"3F"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Vortex_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt deleted file mode 100644 index 871b6a6a..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/README.txt +++ /dev/null @@ -1,27 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Western Gun Part II port to MiST by Gehstock --- 05 June 2019 --- ---------------------------------------------------------------------------------- --- --- Midway 8080 Hardware --- Audio based on work by Paul Walsh. --- Audio and scan converter by MikeJ. ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F1 : Start --- SPACE : Fire --- RIGHT/LEFT : Movement --- --- Joystick support. --- --- ---------------------------------------------------------------------------------- - -ToDo: Color Prom - Controls + DIP - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf deleted file mode 100644 index b277111e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:00:31 July 15, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "18:00:31 July 15, 2019" - -# Revisions - -PROJECT_REVISION = "WesternGunPtII" -PROJECT_REVISION = "SpaceInvaders" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf deleted file mode 100644 index 2a568027..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.qsf +++ /dev/null @@ -1,172 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 19:48:57 August 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# WesternGunPtII_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/westerngun_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/westerngun_memory.sv -set_global_assignment -name VHDL_FILE rtl/westerngun_overlay.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name TOP_LEVEL_ENTITY westerngun_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# -------------------------------- -# start ENTITY(spaceinvaders_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(spaceinvaders_mist) -# ------------------------------ -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc deleted file mode 100644 index f91c127c..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/WesternGunPtII.sdc +++ /dev/null @@ -1,126 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat deleted file mode 100644 index 83fb0c47..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/clean.bat +++ /dev/null @@ -1,15 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -del PLLJ_PLLSPE_INFO.txt -del *.qws -del *.ppf -del *.qip -del *.ddb -pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd deleted file mode 100644 index 65b92d54..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T8080se.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- 8080 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original 8080 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- STACK status output not supported --- --- File history : --- --- 0237 : First version --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T8080se is - generic( - Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - ); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T8080se; - -architecture rtl of T8080se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal INT_n : std_logic; - signal HALT_n : std_logic; - signal BUSRQ_n : std_logic; - signal BUSAK_n : std_logic; - signal DO_i : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - signal One : std_logic; - -begin - - INT_n <= not INT; - BUSRQ_n <= HOLD; - HLDA <= not BUSAK_n; - SYNC <= '1' when TState = "001" else '0'; - VAIT <= '1' when TState = "010" else '0'; - One <= '1'; - - DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA - DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n - DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! - DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA - DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT - DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 - DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP - DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 0) - port map( - CEN => CLKEN, - M1_n => open, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => open, - HALT_n => HALT_n, - WAIT_n => READY, - INT_n => INT_n, - NMI_n => One, - RESET_n => RESET_n, - BUSRQ_n => One, - BUSAK_n => BUSAK_n, - CLK_n => CLK, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO_i, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n, - IntE => INTE); - - process (RESET_n, CLK) - begin - if RESET_n = '0' then - DBIN <= '0'; - WR_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK'event and CLK = '1' then - if CLKEN = '1' then - DBIN <= '0'; - WR_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and READY = '0') then - DBIN <= IntCycle_n; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then - DBIN <= '1'; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then - WR_n <= '0'; - end if; - end if; - end if; - if TState = "010" and READY = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index e09def1e..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,361 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd deleted file mode 100644 index 876ed1fc..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders.vhd +++ /dev/null @@ -1,277 +0,0 @@ --- Space Invaders core logic --- 9.984MHz clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Cleaned up reset logic --- --- 0300 : MikeJ tidyup for audio release - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity invaderst is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - Coin : in std_logic; - Sel1Player : in std_logic; - Sel2Player : in std_logic; - Fire : in std_logic; - MoveLeft1 : in std_logic; - MoveRight1 : in std_logic; - MoveUp1 : in std_logic; - MoveDown1 : in std_logic; - MoveLeft2 : in std_logic; - MoveRight2 : in std_logic; - MoveUp2 : in std_logic; - MoveDown2 : in std_logic; - DIP : in std_logic_vector(8 downto 1); - RDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - RWD : out std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - AD : out std_logic_vector(15 downto 0); - SoundCtrl3 : out std_logic_vector(5 downto 0); - SoundCtrl5 : out std_logic_vector(5 downto 0); - Rst_n_s : out std_logic; - RWE_n : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic - ); -end invaderst; - -architecture rtl of invaderst is - - component mw8080 - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); - end component; - - signal GDB0 : std_logic_vector(7 downto 0); - signal GDB1 : std_logic_vector(7 downto 0); - signal GDB2 : std_logic_vector(7 downto 0); - signal S : std_logic_vector(7 downto 0); - signal GDB : std_logic_vector(7 downto 0); - signal DB : std_logic_vector(7 downto 0); - signal Sounds : std_logic_vector(7 downto 0); - signal AD_i : std_logic_vector(15 downto 0); - signal PortWr : std_logic_vector(6 downto 2); - signal EA : std_logic_vector(2 downto 0); - signal D5 : std_logic_vector(15 downto 0); - signal WD_Cnt : unsigned(7 downto 0); - signal Sample : std_logic; - signal Rst_n_s_i : std_logic; -begin - - Rst_n_s <= Rst_n_s_i; - RWD <= DB; - AD <= AD_i; - - process (Rst_n, Clk) - variable Rst_n_r : std_logic; - begin - if Rst_n = '0' then - Rst_n_r := '0'; - Rst_n_s_i <= '0'; - elsif Clk'event and Clk = '1' then - Rst_n_s_i <= Rst_n_r; - if WD_Cnt = 255 then - Rst_n_s_i <= '0'; - end if; - Rst_n_r := '1'; - end if; - end process; - - process (Rst_n_s_i, Clk) - variable Old_S0 : std_logic; - begin - if Rst_n_s_i = '0' then - WD_Cnt <= (others => '0'); - Old_S0 := '1'; - elsif Clk'event and Clk = '1' then - if Sounds(0) = '1' and Old_S0 = '0' then - WD_Cnt <= WD_Cnt + 1; - end if; - if PortWr(6) = '1' then - WD_Cnt <= (others => '0'); - end if; - Old_S0 := Sounds(0); - end if; - end process; - - u_mw8080: mw8080 - port map( - Rst_n => Rst_n,--Rst_n_s_i, - Clk => Clk, - ENA => ENA, - RWE_n => RWE_n, - RDB => RDB, - IB => IB, - RAB => RAB, - Sounds => Sounds, - Ready => open, - GDB => GDB, - DB => DB, - AD => AD_i, - Status => open, - Systb => open, - Int => open, - Hold_n => '1', - IntE => open, - DBin_n => open, - Vait => open, - HldA => open, - Sample => Sample, - Wr => open, - Video => Video, - HSync => HSync, - VSync => VSync); - - with AD_i(9 downto 8) select - GDB <= GDB0 when "00", - GDB1 when "01", - GDB2 when "10", - S when others; - - GDB0(0) <= '0'; - GDB0(1) <= '0'; - GDB0(2) <= '0'; - GDB0(3) <= '0'; - GDB0(4) <= '0'; - GDB0(5) <= '0'; - GDB0(6) <= '0'; - GDB0(7) <= '0'; - - GDB1(0) <= not MoveRight1; - GDB1(1) <= not MoveLeft1; - GDB1(2) <= not MoveUp1; - GDB1(3) <= not MoveDown1; - GDB1(4) <= not MoveRight2; - GDB1(5) <= not MoveLeft2; - GDB1(6) <= not MoveUp2; - GDB1(7) <= not MoveDown2; - - GDB2(0) <= not Fire; - GDB2(1) <= not Fire; - GDB2(2) <= not Sel1Player; - GDB2(3) <= not Sel2Player; - GDB2(4) <= '1';--Lives - GDB2(5) <= '1';--Cabinet - GDB2(6) <= '1';--unused - GDB2(7) <= not Coin; - - PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; - PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; - PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; - PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; - PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; - - process (Rst_n_s_i, Clk) - variable OldSample : std_logic; - begin - if Rst_n_s_i = '0' then - D5 <= (others => '0'); - EA <= (others => '0'); - SoundCtrl3 <= (others => '0'); - SoundCtrl5 <= (others => '0'); - OldSample := '0'; - elsif Clk'event and Clk = '1' then - if PortWr(2) = '1' then - EA <= DB(2 downto 0); - end if; - if PortWr(3) = '1' then - SoundCtrl3 <= DB(5 downto 0); - end if; - if PortWr(4) = '1' and OldSample = '0' then - D5(15 downto 8) <= DB; - D5(7 downto 0) <= D5(15 downto 8); - end if; - if PortWr(5) = '1' then - SoundCtrl5 <= DB(5 downto 0); - end if; - OldSample := Sample; - end if; - end process; - - with EA select - S <= D5(15 downto 8) when "000", - D5(14 downto 7) when "001", - D5(13 downto 6) when "010", - D5(12 downto 5) when "011", - D5(11 downto 4) when "100", - D5(10 downto 3) when "101", - D5( 9 downto 2) when "110", - D5( 8 downto 1) when others; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd deleted file mode 100644 index f16cf379..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/invaders_audio.vhd +++ /dev/null @@ -1,496 +0,0 @@ - --- Version : 0300 --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- minor tidy up by MikeJ -------------------------------------------------------------------------------- --- Company: --- Engineer: PaulWalsh --- --- Create Date: 08:45:29 11/04/05 --- Design Name: --- Module Name: Invaders Audio --- Project Name: Space Invaders --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity invaders_audio is - Port ( - Clk : in std_logic; - S1 : in std_logic_vector(5 downto 0); - S2 : in std_logic_vector(5 downto 0); - Aud : out std_logic_vector(7 downto 0) - ); -end; - --* Port 3: (S1) - --* bit 0=UFO (repeats) - --* bit 1=Shot - --* bit 2=Base hit - --* bit 3=Invader hit - --* bit 4=Bonus base - --* - --* Port 5: (S2) - --* bit 0=Fleet movement 1 - --* bit 1=Fleet movement 2 - --* bit 2=Fleet movement 3 - --* bit 3=Fleet movement 4 - --* bit 4=UFO 2 - -architecture Behavioral of invaders_audio is - - signal ClkDiv : unsigned(10 downto 0) := (others => '0'); - signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); - signal Clk7680_ena : std_logic; - signal Clk480_ena : std_logic; - signal Clk240_ena : std_logic; - signal Clk60_ena : std_logic; - - signal s1_t1 : std_logic_vector(5 downto 0); - signal s2_t1 : std_logic_vector(5 downto 0); - signal tempsum : std_logic_vector(7 downto 0); - - signal vco_cnt : std_logic_vector(3 downto 0); - - signal TriDir1 : std_logic; - signal Fnum : std_logic_vector(3 downto 0); - signal comp : std_logic; - - signal SS : std_logic; - - signal TrigSH : std_logic; - signal SHCnt : std_logic_vector(8 downto 0); - signal SH : std_logic_vector(7 downto 0); - signal SauHit : std_logic_vector(8 downto 0); - signal SHitTri : std_logic_vector(5 downto 0); - - signal TrigIH : std_logic; - signal IHDir : std_logic; - signal IHDir1 : std_logic; - signal IHCnt : std_logic_vector(8 downto 0); - signal IH : std_logic_vector(7 downto 0); - signal InHit : std_logic_vector(8 downto 0); - signal IHitTri : std_logic_vector(5 downto 0); - - signal TrigEx : std_logic; - signal Excnt : std_logic_vector(9 downto 0); - signal ExShift : std_logic_vector(15 downto 0); - signal Ex : std_logic_vector(2 downto 0); - signal Explo : std_logic; - - signal TrigMis : std_logic; - signal MisShift : std_logic_vector(15 downto 0); - signal MisCnt : std_logic_vector(8 downto 0); - signal miscnt1 : unsigned(7 downto 0); - signal Mis : std_logic_vector(2 downto 0); - signal Missile : std_logic; - - signal EnBG : std_logic; - signal BGFnum : std_logic_vector(7 downto 0); - signal BGCnum : std_logic_vector(7 downto 0); - signal bg_cnt : unsigned(7 downto 0); - signal BG : std_logic; - -begin - - -- do a crude addition of all sound samples - p_audio_mix : process - variable IHVol : std_logic_vector(6 downto 0); - variable SHVol : std_logic_vector(6 downto 0); - begin - wait until rising_edge(Clk); - - IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); - SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); - - tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); - - Aud(7) <= tempsum (7); - Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; - Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; - Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); - Aud(3 downto 0) <= tempsum (3 downto 0); - - end process; - - p_clkdiv : process - begin - wait until rising_edge(Clk); - Clk7680_ena <= '0'; - if ClkDiv = 1277 then - Clk7680_ena <= '1'; - ClkDiv <= (others => '0'); - else - ClkDiv <= ClkDiv + 1; - end if; - end process; - - p_clkdiv2 : process - begin - wait until rising_edge(Clk); - Clk480_ena <= '0'; - Clk240_ena <= '0'; - Clk60_ena <= '0'; - - if (Clk7680_ena = '1') then - ClkDiv2 <= ClkDiv2 + 1; - - if (ClkDiv2(3 downto 0) = "0000") then - Clk480_ena <= '1'; - end if; - - if (ClkDiv2(4 downto 0) = "00000") then - Clk240_ena <= '1'; - end if; - - if (ClkDiv2(7 downto 0) = "00000000") then - Clk60_ena <= '1'; - end if; - - end if; - end process; - - p_delay : process - begin - wait until rising_edge(Clk); - s1_t1 <= S1; - s2_t1 <= S2; - end process; ---*************************Saucer Sound*************************************** - --- Implement a VCOscilator: frequency is set using counter end point(Fnum) - p_saucer_vco : process - variable term : std_logic_vector(3 downto 0); - begin - wait until rising_edge(Clk); - term := 8 + Fnum; - if (S1(0) = '1') and (Clk7680_ena = '1') then - if vco_cnt = term then - - vco_cnt <= (others => '0'); - SS <= not SS; - else - vco_cnt <= vco_cnt + 1; - end if; - end if; - end process; - --- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator - -- this is 6Hz ?? 0123454321 - p_saucer_lfo : process - begin - wait until rising_edge(Clk); - if (Clk60_ena = '1') then - if Fnum = 4 then -- 5 -1 - Comp <= '1'; - elsif Fnum = 1 then -- 0 +1 - Comp <= '0'; - end if; - - if comp = '1' then - Fnum <= Fnum - 1 ; - else - Fnum <= Fnum + 1 ; - end if; - end if; - end process; - ---**********************SAUCER HIT Sound************************** - --- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO - p_saucer_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if SHitTri = 48 then - SHitTri <= "000000"; - else - SHitTri <= SHitTri+1; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx - p_saucer_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if TriDir1 = '1' then - if (SauHit +58 - SHitTri) < 190 + 256 then - SauHit <= SauHit +58 - SHitTri; - else - SauHit <= "110111110"; - TriDir1 <= '0'; - end if; - else - if (SauHit -58 + SHitTri) > 256 then - SauHit <= SauHit -58 + SHitTri; - else - SauHit <= "100000000"; - TriDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Saucer Hit Sound - p_saucer_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigSH = '1') then - SHCnt <= "100000000"; - SH <= "11111111"; - elsif (SHCnt(8) = '1') then - SHCnt <= SHCnt + "1"; - if SHCnt(7 downto 0) = x"60" then -- 96 - SH <= "01111111"; - elsif SHCnt(7 downto 0) = x"90" then -- 144 - SH <= "00111111"; - elsif SHCnt(7 downto 0) = x"C0" then -- 192 - SH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Saucer Hit Sound - p_saucer_hit : process - begin - wait until rising_edge(Clk); - if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge - TrigSH <= '1'; - elsif (Clk480_ena = '1') then - TrigSH <= '0'; - end if; - end process; - ---***********************Invader Hit Sound***************************** --- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO - p_invader_hit_lfo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if IHitTri = 48-2 then - IHDir <= '0'; - elsif IHitTri =0+2 then - IHDir <= '1'; - end if; - - if IHDir ='1' then - IHitTri <= IHitTri + 2; - else - IHitTri <= IHitTri - 2; - end if; - end if; - end process; - --- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx - p_invader_hit_vco : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if IHDir1 = '1' then - if (InHit +10 + IHitTri) < 110 + 256 then - InHit <= InHit +10 + IHitTri; - else - InHit <= "101101110"; - IHDir1 <= '0'; - end if; - else - if (InHit -10 - IHitTri) > 256 then - InHit <= InHit -10 - IHitTri; - else - InHit <= "100000000"; - IHDir1 <= '1'; - end if; - end if; - end if; - end process; - --- Implement the ADSR for Invader Hit Sound - p_invader_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigIH = '1') then - IHCnt <= "100000000"; - IH <= "11111111"; - elsif (IHCnt(8) = '1') then - IHCnt <= IHCnt + "1"; - if IHCnt(7 downto 0) = x"14" then -- 20 - IH <= "01111111"; - elsif IHCnt(7 downto 0) = x"1C" then -- 28 - IH <= "11111111"; - elsif IHCnt(7 downto 0) = x"30" then -- 48 - IH <= "00000000"; - end if; - end if; - end if; - end process; - - -- Implement the trigger for The Invader Hit Sound - p_invader_hit : process - begin - wait until rising_edge(Clk); - if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge - TrigIH <= '1'; - elsif (Clk480_ena = '1') then - TrigIH <= '0'; - end if; - end process; - ---***********************Explosion***************************** --- Implement a Pseudo Random Noise Generator - p_explosion_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (ExShift = x"0000") then - ExShift <= "0000000010101001"; - else - ExShift(0) <= Exshift(14) xor ExShift(15); - ExShift(15 downto 1) <= ExShift (14 downto 0); - end if; - end if; - end process; - Explo <= ExShift(0); - - p_explosion_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigEx = '1') then - ExCnt <= "1000000000"; - Ex <= "100"; - elsif (ExCnt(9) = '1') then - ExCnt <= ExCnt + "1"; - if ExCnt(8 downto 0) = '0' & x"64" then -- 100 - Ex <= "010"; - elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 - Ex <= "001"; - elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 - Ex <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Explosion Sound - p_explosion_trig : process - begin - wait until rising_edge(Clk); - if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge - TrigEx <= '1'; - elsif (Clk480_ena = '1') then - TrigEx <= '0'; - end if; - end process; - ---***********************Missile***************************** --- Implement a Pseudo Random Noise Generator - p_missile_pseudo : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if (MisShift = x"0000") then - MisShift <= "0000000010101001"; - else - MisShift(0) <= MisShift(14) xor MisShift(15); - MisShift(15 downto 1) <= MisShift (14 downto 0); - end if; - - miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); - if miscnt1 > 60 then - miscnt1 <= "00000000"; - Missile <= not Missile; - end if; - - end if; - end process; - --- Implement the ADSR for The Missile Sound - p_missile_adsr : process - begin - wait until rising_edge(Clk); - if (Clk480_ena = '1') then - if (TrigMis = '1') then - MisCnt <= "100000000"; - Mis <= "100"; - elsif (MisCnt(8) = '1') then - MisCnt <= MisCnt + "1"; - if MisCnt(7 downto 0) = x"4b" then -- 75 - Mis <= "010"; - elsif MisCnt(7 downto 0) = x"70" then -- 112 - Mis <= "001"; - elsif MisCnt(7 downto 0) = x"96" then -- 150 - Mis <= "000"; - end if; - end if; - end if; - end process; - --- Implement the trigger for The Missile Sound - p_missile_trig : process - begin - wait until rising_edge(Clk); - if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge - TrigMis <= '1'; - elsif (Clk480_ena = '1') then - TrigMis <= '0'; - end if; - end process; - --- ******************************** Background invader moving tones ************************** - EnBG <= S2(0) or S2(1) or S2(2) or S2(3); - - with S2(3 downto 0) select - BGFnum <= x"66" when "0001", - x"74" when "0010", - x"7C" when "0100", - x"87" when "1000", - x"87" when others; - - with S2(3 downto 0) select - BGCnum <= x"33" when "0001", - x"3A" when "0010", - x"3E" when "0100", - x"43" when "1000", - x"43" when others; - --- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) - - p_background : process - begin - wait until rising_edge(Clk); - if (Clk7680_ena = '1') then - if EnBG = '0' then - bg_cnt <= x"00"; - BG <= '0'; - else - bg_cnt <= bg_cnt + 1; - - if bg_cnt = unsigned(BGfnum) then - bg_cnt <= x"00"; - BG <= '0'; - elsif bg_cnt=unsigned(BGCnum) then - BG <='1'; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd deleted file mode 100644 index b9a88f96..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/mw8080.vhd +++ /dev/null @@ -1,336 +0,0 @@ --- Midway 8080 main board --- 9.984MHz Clock --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0241 : First release --- --- 0242 : Removed the ROM --- --- 0300 : MikeJ tidyup for audio release --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity mw8080 is - port( - Rst_n : in std_logic; - Clk : in std_logic; - ENA : out std_logic; - RWE_n : out std_logic; - RDB : in std_logic_vector(7 downto 0); - RAB : out std_logic_vector(12 downto 0); - Sounds : out std_logic_vector(7 downto 0); - Ready : out std_logic; - GDB : in std_logic_vector(7 downto 0); - IB : in std_logic_vector(7 downto 0); - DB : out std_logic_vector(7 downto 0); - AD : out std_logic_vector(15 downto 0); - Status : out std_logic_vector(7 downto 0); - Systb : out std_logic; - Int : out std_logic; - Hold_n : in std_logic; - IntE : out std_logic; - DBin_n : out std_logic; - Vait : out std_logic; - HldA : out std_logic; - Sample : out std_logic; - Wr : out std_logic; - Video : out std_logic; - HSync : out std_logic; - VSync : out std_logic); -end mw8080; - -architecture struct of mw8080 is - - component T8080se - generic( - Mode : integer := 2; - T2Write : integer := 0); - port( - RESET_n : in std_logic; - CLK : in std_logic; - CLKEN : in std_logic; - READY : in std_logic; - HOLD : in std_logic; - INT : in std_logic; - INTE : out std_logic; - DBIN : out std_logic; - SYNC : out std_logic; - VAIT : out std_logic; - HLDA : out std_logic; - WR_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0)); - end component; - - signal Ready_i : std_logic; - signal Hold : std_logic; - signal IntTrig : std_logic; - signal IntTrigOld : std_logic; - signal Int_i : std_logic; - signal IntE_i : std_logic; - signal DBin : std_logic; - signal Sync : std_logic; - signal Wr_n, Rd_n : std_logic; - signal ClkEnCnt : unsigned(2 downto 0); - signal Status_i : std_logic_vector(7 downto 0); - signal A : std_logic_vector(15 downto 0); - signal ISel : std_logic_vector(1 downto 0); - signal DI : std_logic_vector(7 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal RR : std_logic_vector(9 downto 0); - - signal VidEn : std_logic; - signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 - signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 - signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 - signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 - signal Shift : std_logic_vector(7 downto 0); - -begin - ENA <= ClkEnCnt(2); - Status <= Status_i; - Ready <= Ready_i; - DB <= DO; - Systb <= Sync; - Int <= Int_i; - Hold <= not Hold_n; - IntE <= IntE_i; - DBin_n <= not DBin; - Sample <= not Wr_n and Status_i(4); - Wr <= not Wr_n; - AD <= A; - Sounds(0) <= CntE7(3); - Sounds(1) <= CntE7(2); - Sounds(2) <= CntE7(1); - Sounds(3) <= CntE7(0); - Sounds(4) <= CntE6(3); - Sounds(5) <= CntE6(2); - Sounds(6) <= CntE6(1); - Sounds(7) <= CntE6(0); - - IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); - - ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); - ISel(1) <= Status_i(0) nor Status_i(6); - - with ISel select - DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", - GDB when "01", - IB when "10", - RR(7 downto 0) when others; - - RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); - RAB <= A(12 downto 0) when CntD5(2) = '1' else - std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); - - u_8080: T8080se - generic map ( - Mode => 2, - T2Write => 1) - port map ( - RESET_n => Rst_n, - CLK => Clk, - CLKEN => ClkEnCnt(2), - READY => Ready_i, - HOLD => Hold, - INT => Int_i, - INTE => IntE_i, - DBIN => DBin, - SYNC => Sync, - VAIT => Vait, - HLDA => HLDA, - WR_n => Wr_n, - A => A, - DI => DI, - DO => DO); - - -- Clock enables - process (Rst_n, Clk) - begin - if Rst_n = '0' then - ClkEnCnt <= "000"; - VidEn <= '0'; - elsif Clk'event and Clk = '1' then - VidEn <= not VidEn; - if ClkEnCnt = 4 then - ClkEnCnt <= "000"; - else - ClkEnCnt <= ClkEnCnt + 1; - end if; - end if; - end process; - - -- Glue - process (Rst_n, Clk) - variable OldASEL : std_logic; - begin - if Rst_n = '0' then - Status_i <= (others => '0'); - IntTrigOld <= '0'; - Int_i <= '0'; - OldASEL := '0'; - Ready_i <= '0'; - RR <= (others => '0'); - elsif Clk'event and Clk = '1' then - -- E3 - -- Interrupt - IntTrigOld <= IntTrig; - if Status_i(0) = '1' then - Int_i <= '0'; - elsif IntTrigOld = '0' and IntTrig = '1' then - Int_i <= IntE_i; - end if; - - -- D7 - -- Status register - if Sync = '1' then - Status_i <= DO; - end if; - - -- A3, C3, E3 - -- RAM register/ready logic - if Sync = '1' and A(13) = '1' then - Ready_i <= '0'; - elsif Ready_i = '1' then - Ready_i <= '1'; - else - Ready_i <= RR(9); - end if; - if Sync = '1' and A(13) = '1' then - RR <= (others => '0'); - elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge - (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge - RR(7 downto 0) <= RDB; - RR(8) <= '1'; - RR(9) <= RR(8); - end if; - OldASEL := CntD5(2); - end if; - end process; - - -- Video counters - process (Rst_n, Clk) - begin - if Rst_n = '0' then - CntD5 <= (others => '0'); - CntE5 <= (others => '0'); - CntE6 <= (others => '0'); - CntE7 <= (others => '0'); - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - CntD5 <= CntD5 + 1; - if CntD5 = 15 then - - CntE5 <= CntE5 + 1; - if CntE5(3 downto 0) = 15 then - if CntE5(4) = '0' then - CntE5 <= "11100"; - - CntE6 <= CntE6 + 1; - if CntE6 = 15 then - - CntE7 <= CntE7 + 1; - if CntE7(3 downto 0) = 15 then - if CntE7(4) = '0' then - CntE6 <= "1010"; - CntE7 <= "11101"; - else - CntE7 <= "00010"; - end if; - end if; - end if; - end if; - else - end if; - end if; - end if; - end if; - end process; - - -- Video shift register - process (Rst_n, Clk) - begin - if Rst_n = '0' then - Shift <= (others => '0'); - Video <= '0'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then - Shift(7 downto 0) <= RDB(7 downto 0); - else - Shift(6 downto 0) <= Shift(7 downto 1); - Shift(7) <= '0'; - end if; - Video <= Shift(0); - end if; - end if; - end process; - - -- Sync - process (Rst_n, Clk) - begin - if Rst_n = '0' then - HSync <= '1'; - VSync <= '1'; - elsif Clk'event and Clk = '1' then - if VidEn = '1' then - if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then - HSync <= '0'; - else - HSync <= '1'; - end if; - if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then - VSync <= '0'; - else - VSync <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd deleted file mode 100644 index 97a42db7..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/pll.vhd +++ /dev/null @@ -1,382 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 10, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 20, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire4, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex deleted file mode 100644 index 251ad2c5..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic32.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:200000003321C12EB0CD33213E1432FE6711DF2021357201021BCD64213E5C32FE6711FA5F -:2000200020218272010209CD64213E0132FD67214D7211EE1A010B03C5CD5921C111561C00 -:200040002ECDCD5921212473110321D50627C5CD6D0FC1D12E54CD6D0F3E0332FD672E609F -:200060000609C3332108492214814242811422490800008080F0F8B0BC3A3A3A1818080884 -:20008000080808C8F810141F7F575E7D1530000000020204000000000090441F3F3F7F7FD8 -:2000A0003F1D0900000000000800A040A060E08E1170E0C050787641404040CED1F0E0C0F6 -:2000C000E0E07632341800D0600609F8F671416040404040C0C0C0E0F0FFF9010000000123 -:2000E00003060C0F0F0704050505050504070F3F7F7FFFFFF8E0F0FC3EFC01030703070F32 -:2001000003050400000200C001002000401000401011C1DC0FFFFE0DE09F0FD0C10FCAE0B1 -:200120000606600000000000000080C8F8C1FFC04000001A77CD3D2105C23321C93AFD6715 -:20014000233DC240213AFC67133DC24821C91AB677CD3D2105C24E21C9C5CD4E2123C10DD8 -:20016000C25921C9C5D5CD3321EB2AFE6719D1C10DC26421C93A8060470F21F660DA822119 -:200180002EFB3AE160A7CAB721AF32E160E52AE260EBE17E8327775F237E8A277757F50E12 -:2001A000E30AA7C2BC21F1237ECE00277747237E23666F78C3A30FAF327F60C93AD960BA8B -:2001C000CAC621D2A621AF02C5D5E50EFF0A3C02CD12083AD860673E0ACDD80D3E02327FA5 -:2001E00060E1D1C1C3A6213A0B603DF5320B60CDDE06F1F52EEF772EF5E607874F06001106 -:20020000EB22EB097E1223137E12CD930D0601CD9623F1FE04CA1F22E607FE07C2BE223EBD -:200220000ECDB92321194C118F100E09CDE40F21164C0E09CDE40F119506CD810F3EFF3228 -:20024000C4603AC460A7C24222060ECD8A233E40CDD90FAFCDB92311FB22210A4801100B79 -:20026000C51A13D5E5F579FE09DA7122F107C37322F10FF5C53E26D27C223E10CDD80D3ED4 -:2002800001CDD90FC10DC26622F1E123D1C105C260223A80600F21F660DA9E222EFB060354 -:2002A000AFF5F17E8F277723F505C2A222F13E80CD0623CDD102CD930D0600C38A23AFCDB7 -:2002C000B923060ACD8A23118506CD810FCD760F3E0832C4603E50CDD90FCDD102211A496A -:2002E000CDD7233E30CDD90FC3B6222020000000202020000000200060504001070F1F3F54 -:200300007F7FFFFE7C3832C06021F660111D443A80600FDA1A232EFB16563AC060A7C8E66F -:2003200004C22A23CDA00FC30923EB0630CDAC0DC309233A80600F21F860DA3F232EFD118F -:20034000F36006FE0478FE02CA5F231ABE2B1BCA4423D25F237D805F2EF10603CD6D0FC34B -:200360009D0FCD930DCD3323AFCD12083A8960A7F27A233A8160A7C4BF231185100E0A210B -:20038000104BCDE40F3E40C3D90F3A8860E6E0B0328860D306C93ADF60A7C878A73A8A609A -:2003A000FAAA23B0328A60D304C9A0C3A4233ADF60A7C83A8B60E60FB0328B60D305C9115F -:2003C000301021134C0E07CDE40F3A80600F3E1BDAD4233CC3D80D114F100E06C3E40FE631 -:2003E000F0C2B91A21C0723601C9FFFFFFF53AC072A7CA0024F10F0F0FC3CA1AFFFFFFFF71 -:20040000F1C9FFFFFF323B6021C0723600C9F5AF32C072211F5AF1C900FFE6203E80C22302 -:20042000243E00328960C9FFFFFFE6100F0F0F0FC603C9FFFFFF210246114A240E13CDBE24 -:200440000D112210C9FFFFFFFFFF09130008130E26020E110F0E110013080E0D09FFFFFF92 -:20046000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C -:20048000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C -:2004A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C -:2004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C -:2004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C -:20050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB -:20052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB -:20054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB -:20056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B -:20058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B -:2005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B -:2005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B -:2005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B -:20060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA -:20062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA -:20064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA -:20066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A -:20068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A -:2006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A -:2006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A -:2006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A -:20070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9 -:20072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9 -:20074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9 -:20076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99 -:20078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79 -:2007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59 -:2007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39 -:2007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex deleted file mode 100644 index c763f525..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic33.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:200000007B3C87C6186F0604C93E08C3F9171C7BFE18D231181AA7FA291879D608BED22995 -:2000200018C620BEDA291837C9232305C20E18AFC9214F60351EFFAFC9CD0E18D24D183A40 -:20004000376023BEDA5218CD2A18C33C187B324760C97B324760114C601A86122B1B1A86F8 -:2000600012622E4636012E4F34C9CD0E18D24D183A376023BED25218CD2A18C36D182CCD7F -:200080000E18D24D183A36602BBE23DA5218CD2918C382182CCD0E18D24D183A36602BBE69 -:2000A00023D25218CD2918C398182155607E34E60307070707C6405F2E461663E5D53A830A -:2000C00060A74FFACB183E01325260060ACD6D0F2E467E2347FE01CA081979A7FAA81678DB -:2000E000A7CAE718C31F19CD6C16CAF11835C3A816CD2C196FCD0C08A7FAA8167D5D87C6D5 -:20010000196FCD5218C3A8163A4C60E680A9CA1419C3DD16AF32526021556035C3A816CD11 -:200120007B17E1D1CDB5173A126012C987C6506F26605E2356131AA7FA3F19722B73C97B78 -:20014000D6195FC335193A83604F3A6E60E680A9C82167607EA7CA191A237EA7C2BA1923EB -:20016000354E23CA9E19CDB40F3A6F608467326E60CDA110CD400F79E603CA8219FE01C2B2 -:2001800098191AA7F28F197BD6305FD28F1915EB226A600620CD96233E0F326260C9CDB4D6 -:2001A0000F118067CDA110CD400F218A03227D60AF216760772377C34014347E2323FAE858 -:2001C00019FE63C2D61921306F226A600620CDAE2306DFC39623CDB40FCDA110CD400FEB0E -:2001E000226A603E02C39A193DFA0B1A2A6D60CDA110EB2A65607E21E16036FF2336002321 -:2002000077EBC61ACDD80DAFC3C00FFEB0C03A8B60E6DFCDB923C39E1906DFCD96233A0980 -:2002200060FE04D83A3560A7C82A7D602B227D607DB4C03EFF3267603A0A60A7F83E01323A -:200240000A60C921306036002E383ADF60A7CAE61A3A8960A7FA5F1A3A80600FD26F1ADB98 -:2002600000F5E60FBE7723CA751A3604C3AF1ADB01F5C3621A35C2AF1A3604A74723CAD761 -:200280001A347EA7FA8E1AFE04DA8E1A3603788701B600814F2323230ABE770323C2A91AB3 -:2002A0000ABE77C2AB1AC3AF1A0A772E3A36FE113C6021A060F1E6F0C8BECAC21A77EB3676 -:2002C00004C9EB35C036040F0F0F0F01CB00814F0AA7C8323B60C935F2AF1A36FB2E3DAF15 -:2002E000772377C3AF1A3AA060F57EC3621A73C0005FD800FDFE01E97F01F87F01E85B01EA -:20030000F87201E8F601F856014CC000CC8001C4000084000080000080000071C0005BD83F -:2003200000FFFE01ED7F01F97F01E85B01F87201E8F601FC56008CC000848801841C008080 -:200340003F00004C00008000007E0270430341FF015B6E00FEFF00EC1F00F8CF00ECFE0099 -:20036000FF0000EB0000F97800803800800C00800F00000000008000004C00803F00841C24 -:20038000008488018CC000FC5600E8F601F87201E85B01F97F01ED7F01FFFE015BD800719C -:2003A000C000800000800000840000C40000CC80014CC000F85601E8F601F87201E85B01FF -:2003C000F87F01E97F01FDFE015FD80073C0000400000800003000006400006480014CC045 -:2003E00000FC5601E8F601F87201E85B01F97F01ED7F01FFFE015BD80071C00070000070F4 -:2004000000005C00005E800140C000F95601EBF601FE7201EC5B01F87F01EE7F01FEFE01D3 -:200420005AD80073C00000000071C0005BD800FFFE01ED7F01F97F01E85B01F87201E8F682 -:2004400001FC56014CC00064800164000030000008000004000078C00048D800F8FE01EE7A -:200460007F01FE7F01EA5B01FC7201EFF601FB560141C000408001C000008000008000000F -:20048000800000F0C00090D800F8FE01EE7F01FE7F01EA5B01FC7201EFF601FB5600C1C074 -:2004A00000808801801C00803F00004C00008000007E0270430340FF01586E00F8FF00EBEE -:2004C0001F00FACF00EEFE00FE0000E80000F878008838008E0C008E0F0002000000800079 -:2004E000004C00803F00801C00808801C1C000FB5600EFF601FC7201EA5B01FE7F01EE7FF4 -:2005000001F8FE0190D800F0C000800000800000800000C0000040800141C000FB5601EF88 -:20052000F601FC7201EA5B01FE7F01EE7F01F8FE0148D80078C00004000008000030000098 -:20054000E00000A08001C1C000FB5600EFF601FC7201EA5B01FE7F01EE7F01F8FE0190D8E2 -:2005600000F0C000F00000F000009C00009E000080C000FAD800EEFE01FE7F01E87F01FDCF -:200580005B01EF7201FBF6018C5601F0C000008001F0C00090D800F8FE01EE7F01FE7F019C -:2005A000EA5B01FC7201EFF601FB5601C1C000A08001E0000030000008000004000003028B -:2005C0000E0B06021674F4F62E9FFEF7E662323018080000000018107050301C100C0406A0 -:2005E0000E0E0E0E0E0F0F0F0B0100000000FF000000000818303262E6F7FE9F2EF6F47493 -:200600001602060B0E020300000000010B0F0F0F0E0E0E0E0E06040C101C3050701018FFC6 -:20062000CDB910C5E51AD303DB032FA67723130DC2251EAFD303012000E109C105C2231EBF -:20064000C9CDB910C5E51AD303DB03B67723130DC2461EAFD303012000E109C105C2441EB3 -:20066000C9212760C3B40FCDB910C51AD303DB03B6772313AFD303DB03B677011F0009C17D -:2006800005C26A1EC9CDB910E5C5E51AD303DB032FA6772313AFD303DB032FA6770D23C22C -:2006A0008B1EE101200009C105C2891EE1C9CDB910AF328560C51AD303DB03F5A6CAC51E76 -:2006C0003EFF328560F1B6772313AFD303DB03F5A6CAD91E3EFF328560F1B677011F000918 -:2006E000C105C2B51EC92100673600237CFE7EC2E91E21006711DB1206143E07D3021AD38D -:2007000003131AD303DB037723AFD303DB0377231305C2FE1E21020222FC6721016801141F -:2007200010C5110567CD3321C10DCA3E1F790F3E10DA351FAF856FD23B1F24C3211F2142F4 -:200740000022FE67210068110467010808C5CD6421213E0022FE67214068C1111667CD64B6 -:200760002121486B010914110167C5CD3321C10DC2671F21100022FE673E0132FC672188BC -:200780006A01060C116520CD6421AF32FE6721B06CE5117120011014CD64213E2832FE6776 -:2007A000118520010814E123C5CD642111992021D96CC1CD64213E0132FD673E2B32FE6733 -:2007C00011652021306F010E06C5CD6421215A6FC13E2932FE67116B20CD642121D6711187 -:2007E000EE1A0624C5CD6D0F210072C111561CCD6D0F3E0432FD6711AD202E300619C5CDD4 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex deleted file mode 100644 index 3e90c4b8..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic34.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:2000000026262607082712020E1104262626241C250211040308132626262626262626269F -:200020002626080D120411132626020E080D1B260F0B0018041126261B26020E080D1C2638 -:200040000F0B0018041112261C26020E080D1207040B0F26190F141207011413130E0D0EA4 -:200060000D0B18261B260F0B00180411261B260E11261C260F0B00180411120604132626F2 -:20008000110400031806000C0426260E150411010E0D14122619191912020E110426172649 -:2000A0001C3E05D3027DD3037CD303DB036F3E02D303DB0367AFD303C9C5E5CDA110C1790F -:2000C000E607D302C1C93A8060670E007EA7FAD2100C2B05C2CC1079C93A0060A7C03A02EB -:2000E00060A7C03A0960A7CA26113A0A60473A8060673A03603CFE14DAFE10CD42116F78A8 -:20010000A7CA21113CCA2C117DFE10D221117E4FA77DFAF510320360CDAC113EFF3202608A -:20012000C97D4EC315113EFF328260C97DFE10DA0E117E4FA77DF21511320360CDAC11C3B9 -:20014000EA10A7F26C11FE94C25511C375113E92C355113E8032036007C6176F1105607EF9 -:200160001223137E123EFF320260E1C978A7CA53113CCA4E11CDA111210D6035CA85113A9E -:20018000806067AFC936193EFF32006078A7C29311E1C92B7EA7CA9F1135F29F1136FFE19C -:2001A000C9210460347EFE03D83600C92E18F587856F79E60F874F060011F311EB09010558 -:2001C000601A8612022313031A861202F15F1AA7F80A21376096D2DF11FEF3D2E211C9FE7E -:2001E0000AD02B0B0A96D2EB112F3CFE0CD0AF323560C9000000020202020002FE00FEFEF9 -:20020000FEFE00FE02010202FFFFFEFE013A0060A7C83A0260A7C03A0160A7F03A0960A75A -:20022000CA26113A8060673A036016023CFE18C23512CD49126F7E4FA77DFA2C12320360D7 -:20024000CDAC113EFF320260C915CA5E12CDA111210E6035CA61123E13320360E1C9210EEC -:200260006036323E08320160E1C93A0260A7C83A8060673A0360E61F6F7EA7FA8112CD8691 -:2002800012AF320260C921B3121128003A0460193DF28F12EB2A0560010114C3A4127EA76C -:2002A000C03EE8C9E5CDB910C5E51AD303DB037723131AD303DB03770DC2B0122313AFD361 -:2002C00003DB0377E101200009C105C2A812E1C9CDB40F0E01118067C3A4120000000000BF -:2002E0000204020C33981A6018E01BE07AE07BE07BE07AE01B2018B01A10330002000200E4 -:200300000000000000000000004060C030803080378075BC77A877F075C037E03030300CC7 -:20032000600400000000000000000000000000001E805E807F84019C00F0017001F07D70FE -:2003400015F00D9C0484070000000000000000000000007EFEFFC8FEFECA881323464FB054 -:2003600079C27E13237EA7C28E13235E2356E5EBE5217613E3E9E1110C0019C35313050498 -:20038000C284133D05702B77111000C37A13352B2BC388133A3260A7C82125607EA7C8FE8A -:2003A00001CAB513FE02CAE31323FE03CA0F14FE05C8C3301436023A3B60878747215B0029 -:2003C000856F22276078112A60217B00856F0136600A86120323130A861223137E122313CD -:2003E0007E12C93A8660A7C0CD611E0E01D5E5C5CD851EC1E1112C601A856F131A8467224C -:200400002A60D1CDAE1E3A8560A7C8328660C935CA30147EFE0FC023CDB40F0E01CD851EB9 -:20042000E51168142127607323720604E1C36A1ECD611E0E01CD851EAF2125607723361064 -:200440002A6560237E4DA7C24D14216C1422656006072167607EA7C02E69116E06790FDA15 -:200460006514117B14C36D0F0906060902030101010205030201010202010032BE1D18E0E6 -:20048000D8FC2137603A8360A7CAAF143A8960A7FA9C143A80600F3EA0D2A5143E60BEDA43 -:2004A000B714C3A914BED2B7143EFD323060C93E04323260C3BF143EFE323060C3AF142B85 -:2004C0002B7EA7CA0C15CD1A16213F603A3A60A73A3B60FA0815BEC2DC14C608772B113795 -:2004E000601A86FEBFDAEA143EBEFE33D2F1143E33122B1B1A86FE9DDAFD143E9CFE34D296 -:2005000004153E3412C3261677C305153E023232602E77357E23FA6A1547E6023A8860CAD8 -:200520002715F613C32915E620328860D30678FE10CA5C15D24415CDB40F0E01CDA412EB83 -:20054000227860C9CD1A16213F603A3B60BEC25315C60877CD26160608C39623CD1A162A5F -:2005600036607CD60267227B60C9FEE0C0CDD012211C4206E0CDAC0D3EFF32356031008077 -:200580003ADF60A7CA9301AF32C260CDB92306C1CD9B23FB3E40CDD90FCD75213A8260A78B -:2005A000C2011621136006343A3760FE78DAB21506BD703EFFCD700DCD0E0D3A8160A7CA7E -:2005C000E6152EFFCD0C0835CAD4157CEE03328060C38B04CD6223AF3281603A8060EE033A -:2005E000328060C38B042EFFCD0C0835C20716CD62233ADB60A7C2CD0306C0CD9623C39DC9 -:2006000001CDE721C3BB15000000C3B2043A3F6007211500856F5E2356C9CD0D1601030F4B -:200620002A3660C3201ECD0D1601030F2A3660C3411E2145607E34E603070707075F1663BF -:2006400023E5D53A8360A74FCA50163E01324260060ACD6D0F2E467E2347FE01CAD4167986 -:20066000A7CAA81678A7CA8416C36E173A3560A7CAA7175E237E4F266387878787F60F6F1B -:200680007EA779C9CD6C16CA8E1635C3A816A7CA9F16FE01CAB016FE02CABC16C3C8163A54 -:2006A0003660CDE817CD3918E1D1060ACD6D0FC93A3660CDE817CD6A18C3A8163A3760CDDC -:2006C000E817CD7E18C3A8163A3760CDE817CD9418C3A8163A4C60E680A9CA63173A356098 -:2006E000A7CA52172A4960EB2A4B60010103E5CD851EEB7EA7F2FC1611FAFF19224960EB46 -:20070000E1014D600A85FED1D25217FE10DA52176F030A84FEDDD25217FE20DA521767E59D -:20072000224B600603CDAE1E3A8560A7E1CA5B171136601AD603BDD25E17C613BDDA5E17E4 -:20074000131AD603BCD25E17C611BCDA5E17AF323560AF3248603E02324660C3A8163E04D4 -:20076000C35317AF32426021456035C3A816CD7B17E1D1CDB5173A116012C923357E2A49D4 -:2007800060EB2A4B60010103FAB217FE02CAAB17FE03CA9917E1C3A816E5CD851E21E51796 -:2007A000224960E1224B60E1C3A816CD671EE1C3A816C3851E133600230609CD6D0F547DAF -:2007C000D6085FEB0605C36D0F020202020205FF020202050202FF000700040304FF000773 -:2007E00000010601FF0502054F3A4F60E603CA0918FE013EF8CAF917AF814F3A8060675774 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex deleted file mode 100644 index 25cd8543..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:20000000F83FFEFFFEFFAEEA486E94AA3A8060677EC9F6C0211F42C3C00FCDE61E0E15118C -:20002000FC0F211E45CDBE0D0E07211F53CDBE0D3ADB60CDC00FCD910FCD970FCD9D0F11DE -:200040005A080E02CD6A08CDB70DCD6A08D5110001CDB00DD10DC24408C9460610084896B7 -:20006000100459E6100848851040EB56235E2346237E23EBC93A3560A7C83A3160A7C021C4 -:2000800025607EA7C03ADF60A7CAB008112F601AA7C2A408CDE108A0C836013E10120610BA -:2000A000CD9623C9CDE108A0C01206EFCD9623C936012ADD60237EA7F2C10821D608C3B66C -:2000C0000822DD603238603ADC603C32DC606F7EE6F032A060C90009080A02060405010ADA -:2000E000FF3A8960A7FAF1083A8060E60347DB02C90601DB02C93A2560FE02C02A2A603A3A -:200100008660A7C21F093E07BDD2F9093EE0BDDAF9093E17BCD2F9093EE6BCDAF909C93A37 -:200120006760A7CA2C097DFEDDD287093A8060573A0060473E18BDD264093EC7BDDA6409EB -:200140003E26BCD264093ED7BCDA6409EB2E100E381E6078A71604CA5C09160844CD940907 -:20016000CDF909C9EB78A7C279092E000E1844113010CD9409CDF909C92E140E4044113099 -:2001800004CD9409C36A092168607EA7C2F9093662C3F909D5E52A2A60E37EA7FAEF09EB39 -:2001A0000A03E1EBD604BBD2F109C618BBDAF1090AD605BAD2F109C617BADAF109EB0A6766 -:2001C0000B0A6F227560EB7EF6F07721736036682B36002B361ED13E053225603ADF60A781 -:2001E000CAED0921E16036FF2373233600E1C9D1030323D115C29409C93E03322560AF322E -:200200008660C92100607EA7CA180A237EA7C2140ACD2F0ACDEE0AC92E087EA7C82E0BFE87 -:200220000FD0FE03DA2B0A2B3601C9233600C916002E3FCD0C080E1379FE10D2440A440A08 -:20024000A7FA5C0AE5CDC80A6FFE03CA670AFE0ECA6B0A7DCD720AE6F0B377E12B2B0DF221 -:20026000380A7A320F60C951C3530A79F68057C3530A473A1060A77821AA0AFA810A218C6A -:200280000A856FD2870A245E69C30C080707050105010507050307070303050005070303E2 -:2002A0000100010001000100030001030107010501050707030301070100030307070300EB -:2002C00005000500050005007EE60F5F2D7EE6F0B3D6C2D2EA0AF2E30AD6CFD2EA0AD6C6C0 -:2002E000C3EA0AD666D2EA0AD6C6E61FB8C93A8060673A0160A7C2C80B3A0F60A7CA4E0C57 -:20030000F2530B2E130604CDCA10A7CA770C2E1411920C0604CD6D0F06082E40CD6D0F0E90 -:20032000033A0F6081E6136F7EA7FA380BF6F07779C6146F7EE60F770DF2210BCDAE0C3ECD -:2003400010320F6032076006803E1332036078320160C9010C600AA7C24E0C0E033EFF3259 -:20036000876011A20CD53A8060673A0F6081E6136F7EA7F2C20BD11BD51A472E37160FCD92 -:20038000C80ACA920B2D15F27F0BC3A80B556BC3850B5D6A7EA7FA8D0BF6F07779C6146F40 -:2003A0007EE60F77AF3287600DF2660BD13A8760A7C24E0CAF3207603E19320E600610C34E -:2003C000490BD11BD5C3A80BFE08CADD0BA7F2680C2E170604CDCA10A7CA600CC906032EFA -:2003E00017543A0F6080E6135F7EA7FAF40B36FF1AE60F122B05F2E20B11A20C2E14060483 -:20040000CD6D0F2E400608CD6D0FCDE30C3A0C60A7FA430C3A0760A7C28B0C2108607E2EA6 -:200420000BA7CA4E0C2FC60F570157007EE606814F0A5FAF821DC2340C5F030A2393D2420A -:200440000CAF773A1060EEFF321060CD2F0A21036036FFAF2B772B772B773E32320E60C904 -:200460003E08320160C3F90B3C320160E601CA740CC3E30CC3C20CCDB80C3EF02E10060492 -:20048000CDB70D3E10320F60C3EE0AAF320160C3EE0AFAFBFCF9367668A89A7668440014AE -:2004A0001C08F8F2F4F6CC12041204DACCDA2E101108070604CD6D0F2E381130070608C39C -:2004C0006D0F21174611200F010808CD4E0F21044641CD4E0F21045941CD4E0F2117594116 -:2004E000C34E0F21174611200F010808CD5D0F21044641CD5D0F21045941CD5D0F21175966 -:2005000041C35D0F3A8060571E48AFC3140D3A8060571E483284603E04F507213F0D4F0614 -:20052000000946234E21020FC5E3C13A8460A7CA380DCD490DC33B0DCD5C0DF13DC8C31956 -:200540000D4F17450D4F03592DC57E1213230DC24A0D011E0009C105C2490DC9C51AB67772 -:2005600013230DC25D0D011E0009C105C25C0DC9A7F52EE4CD0C081100600615F1C2830DCC -:200580000613EBC36D0F2100423600237CFE5EC2890DC92100421103003600237DE61FFE13 -:2005A0001DDA990D197CFE5EDA990DC9AF112000771905C2B00DC9772305C2B70DC91AD5CA -:2005C000CDD80DD1130DC2BE0DC911E00DE526006F29292919EBE1C9CDCA0D0608C3400FBD -:2005E000001F2444241F0000007F494949360000003E414141220000007F4141413E0000FE -:20060000007F494949410000007F484848400000003E414145470000007F0808087F000046 -:200620000000417F410000000022147F14220000027EC2FE7E020000007F0101010100008B -:20064000007F2018207F0000007F1008047F0000003E4141413E0000007F48484830000064 -:2006600060F0783C78F06000007F484C4A31000000324949492600000040407F404000006E -:20068000007E0101017E0000007C0201027C0000007F020C027F00000022140814220000DC -:2006A0000060100F106000000602083070E0C000003E4549513E00000000217F01000000FF -:2006C00000234549493100000042414959660000000C14247F04000000725151514E0000EA -:2006E000001E29494946000000404748506000000036494949360000003149494A3C0000CC -:200700000008142241000000000041221408000000000000000000000008080808080000B3 -:200720002070F97D3F1F0F3F040E9FBEFCF8F0FCFCF0F8FCBE9F0E043F0F1F3F7DF97020B7 -:20074000C51A771301200009C105C2400FC9C51AB6771301200009C105C24E0FC9C51A2F61 -:20076000A6771301200009C105C25D0FC91A77231305C26D0FC92100601110060613C36D9E -:200780000F2190600610C36D0F1157070640C36D0F21F660C3A00F21FB60C3A00F21F160A7 -:2007A000CDB40FA7C2A90F3ECCCDC00F7ACDC00F7BC3C00F5E23562346237E23666F78C9A5 -:2007C000C5D5F50F0F0F0FE60FC61ACDD80DF1E60FC61ACDD80DD1C1C932C0603AC060A7A1 -:2007E000C2DC0FC9D51ACDD80DD13E0832C0603AC060A7C2EF0F130DC2E40FC9241B252690 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex deleted file mode 100644 index 8c4fdccf..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic35sound.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:20000000550412093795B276D296F9F20F047AB99083B5B900F9927A05461FB821B0003432 -:20002000AFA9AEC660148C0937F29FBB04341A3427C618148C343FFBAE346734780937F2A8 -:200040009F148CF903F1C655F903F3C65534AFC61803F3C618FEC62F165C043DEE3D042FB6 -:200060007666367104189A8F266C0418A5BE1024BDB5BE1124BDBE1224BDBE13BB00B9005B -:2000800024BEBE14B821B0FF14F724BE34AF03F296F6BE1524BEBE1614F7B69D1E24BE14D8 -:2000A000F78A70BFF514A9049FFF1FE3AEC6F6343FFD03FCAE47530F37ABFE9767AD371731 -:2000C000ACBA0C8A8014E69A7F14E616D6090909F2EE468204C3FE6BAE6CF6DEFDAE4203DA -:2000E0000062EAC304A9FEA8E8E8A8E8EB9327624682161504F083F94380A983FFFFFFFFE9 -:200100000BF20B460AA40A0B097B000008F3087207F90786071A06B40654BF00B820B000CC -:2001200054009620EE20835400F235C626AA5400F235AB5400AE379626FAAE34D52427FEFE -:20014000530FE7A3ACFE530FE717A3ADFE537047AEFC9767ACFD67ADEE5123F86DAD23FF56 -:200160007CACFDC6261C838A708A8034A49A7F34A616752469EE6993F943F0A3AE34AF3767 -:200180001769C689CEFE96891E276AEE8A9767AEE69942038062F6991EFB37176EE6A1AE93 -:2001A00083BE01830909FDA8FCE8A90796A9830937BC046728F728ECB328530F8315341AB0 -:2001C000342796C60415343FFB37176AAE346734D324C0FBAE56DEB821F096DE0482FEC691 -:2001E0002616E524D5EEDE83FFFFFFFFFFFFFFFF0102030405060708090A0A010102010157 -:20020000B820FF1F2FC6112F20960E20A38320E383B0FF2F440C000402BCBAC1BA000402F8 -:20022000BAB8BCBA000403B802B804B902B904BB02BB04B902B9000403B402B404B602B60E -:2002400004B802B804B602B6000403B102B104B202B204B402B404B202B20004A602AA06AD -:20026000B004A602AA06B004A602ABB2B2B2B2B2B206B40003049A06A003A2A09B09A603AC -:200280009A06A003A2A09B0998000696049A029A06980296029696049A9800040596029AF2 -:2002A00006A004A202A004A202A0049A029606980004960296059690049A029A069A960463 -:2002C00096029A08A003A0049B029A06980000000402B4B000006002FF06BCBBBAB9B8B79E -:2002E000B6B4B3B2B1B0ACABAAA9A8A7A6A8AAACB0B2B4B6B8BA300CBC000603B0B0AAB038 -:20030000B2B010AA06AA10A806AA10A806B0B0AAB0B2B010AAA806AAA810A6001507903F74 -:2003200015960E039007963F159A0E0396079A2AA0159A079090903F1596001803A610A60D -:200340000AA618A610A90AA810A80AA610A60AA420A60006A4A8ACB2B4B0AAA6A2A6AAB02C -:20036000B2ACA8A4000402C0BCBBBAB9B8B7B6B4B3B2B1B0000802A4A4A6A8A8A6A4A2A0B0 -:20038000A0A2A40EA404A210A208A4A4A6A8A8A6A4A2A0A0A2A40EA204A010A00CA0A6045B -:2003A000A618A60CA00CA804A418A60CA0A604AA0CB0AA04A60CA2A804AA18A6000802AA8D -:2003C00004AAAA08AAACAAACB004B0B008B0B2B0B2000802A804A8A808ACA8AA04AAAA08C5 -:2003E000B0AA0004A8A808ACA8AA04AAAA08B0AA00B8C0BCC0B8C0BCC0C2C3C2C3C6C8000F -:20040000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC -:20042000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDC -:20044000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBC -:20046000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C -:20048000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C -:2004A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C -:2004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C -:2004E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C -:20050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB -:20052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB -:20054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB -:20056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B -:20058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B -:2005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B -:2005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B -:2005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B -:20060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA -:20062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA -:20064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA -:20066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A -:20068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A -:2006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A -:2006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A -:2006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A -:20070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9 -:20072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9 -:20074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9 -:20076000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99 -:20078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79 -:2007A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59 -:2007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39 -:2007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19 -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex deleted file mode 100644 index 2ff5aef2..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/roms/ic36.hex +++ /dev/null @@ -1,66 +0,0 @@ -:020000040000FA -:20000000C3DB000000FF0000F5C5D5E5C3B00100F5C5D5E5C3D602EE1A1B1B481B751BA279 -:200020001BCF1BFC1B291C561C831CB01CDD1C0A1D371D641D911D0000FA06FA06000000DF -:2000400000FB05FB0500000000FC04FC0400000000FD03FD030000030302060208010A0776 -:2000600002020203030408010F0100080403030202020701020C0C080F08000C0C020106DD -:200080000E00050F0E03030E0904000FFD03FD06FD00FBFEFDFDFDFE03FC00FE0EFD030007 -:2000A00004080C10140105090D111502060A0E121603070B0F1317FF000300FD000003002A -:2000C000020202FE0000FD00FE02FEFE010505030204040708060102060807310080DB0250 -:2000E000E640CA0024CDEF05CD860DAF32826032866032C36032E160CDA423CDB9232F328A -:20010000C2603E613280603E0ACD9023DB02CD1A243E1532D960CD1A08AF32C160FB3E2054 -:20012000CDD90F118506CD810FCDBA063EFF32C36021014B1118100E0ACDBE0D21154A0E0E -:200140000CCDBE0D2110480E10CDE40F210E480E11CDE40F3ED0CDD90FAF32C360211A51FB -:20016000CDD7233E40CDD90FCD930DAFCD9023CD3F08CDBA06CDD206CD4007CD040D3E0172 -:2001800032C160CD7508CDF608CD030A3A3560A7C27E01CDF6083A3560A7CA9301AF32C125 -:2001A0006032DF6032C360FB3E20CDD90FC3E800AF3283603AC260A7CA96023ADF60A7C255 -:2001C000C9013AC1600FD27302213060CD53131108602E0F0610CDC6101213A7C2ED012FA6 -:2001E0001312320C60011160AF0203021B2E170618CDC61012A7C202022F3282603E0FC321 -:2002000037023ADF60A7CA58023A3560A7CA37023A0160A7FA6E02C23D021E0A1A1BA70631 -:200220000ACA31020601FA31021A3D0FE6073C3C473A8B60E620B0CDB923C34702FE08CA11 -:2002400047020610CDB3233A2F60473A7F60B0473A8A60E6EDCDA3233A3560A7CA6502CD7E -:20026000D910CD0D12CD431AE1D1C1F1FBC9060DC331023AC360A7CA680221906035C268A6 -:2002800002360C0E03CDB602212472DA90022EA4229160C368023AC460A7F26802219060DD -:2002A00035C2680236050E02CDB60221D071DA90022EFAC3900223E5CDB40FCDA412EBE1DB -:2002C0007DC6066F7E2B35FAD1024E2B8277790FC9AF32C460C93E8032836021C06035DB06 -:2002E0000207DA020321DA607EA7CA0703237EFE99CAFE02C6012777211F5ACDC00FAFC3B3 -:2003000004033EFF32DA603AC260A7CAB7033ADF60A7C223033ADB60A7C2CD033AC1600F86 -:20032000D27C03212060CD53132130607EFEFD3EFEC23503AF773A8660A7C24303CD6A12FA -:20034000C36802217160357EFA630323CA6803CDB40F0E01CDA412EB2272600604CD962382 -:20036000C3680236FFC36802CDD012AF3286603E0432256006FBCD9623C368023AC360A7C7 -:20038000CA680221986035C26802CD8612CDA111210660CD9E12C6FE772E9836050E02CDAE -:2003A000B602212473DAAA032E54229960219D60CD9E1277C368023AC460A7CA6802F283BC -:2003C0000321986035C268023605C39D03310080AF328860CDB92332C46032C2603C32DFE8 -:2003E00060CDA423FBCD930D0600CD8A23CD1A080E0421124E115510CDBE0D210A4D0E0605 -:20040000CDBE0D210E490E0E3ADB603DCA2D04116D10CDBE0D0698DB020F0F0F0FDA280420 -:200420000707DA3704C3ED033E01C33A04CDBE0DDB02E604CAED030699AF3281603ADB60B7 -:20044000802732DB60CD0E24CDC00FDB02CD2A240032FF6132FF6232E36132E36221F6606C -:2004600011B006060ACD6D0FCD910FCD970F3A8160A7C27D042AFE600630CDAC0DCDBA06A6 -:20048000CDD206CDD8063E61328060CD930D0600CD8A233A8960A7FABF053E40F5CDDB05C6 -:2004A000117B1021104B0E0ACDBE0DF1CDD90FCD930DCDBD06AF328260328660CD40073AA8 -:2004C0008160A7CAD3043E30CD0623CD930D0600CD8A23CD3F08CD040D3A8060672E373E8C -:2004E0000F320360F5562B5E2BE5EB220560CD6F12E1F13DF2E104AFCD700D1A32376006EC -:2005000010C5CD431AC105C201053A3B60323F600E10C5790FDA1E05CD1A16C32105CD2667 -:20052000163E03CDD90FC10DC2120521000022FE6721011022FC67010204210763C5E53A33 -:200540000B60A7113F00FACC05FE04D265051E4FFE01D257051E47CD642121040019EBE1D5 -:2005600023C1CD6421211F45E50660CDAC0D2EFFCD0C08F5CD1208F1E13DCA87054F3E0A09 -:20058000CDD80D0DC27E057C32D8603EFF32C260CD7508CDF608CD030ACD75213A8260A7CB -:2005A000CA90053E60CDD90F3A3560A7CAAC05AF32C260310080CD7521CDE721C3B2043AF9 -:2005C0008160A7C4BF233EA0F5C3A004FEFCD25505FEECD257051E37C357053A80600F3E9A -:2005E00020D2E505AF473A8860E61FB0C39023CDBA062EC01103000603CD6D0F2EDA11A53D -:20060000060606CD6D0F2EF111AB06060FC36D0F000000FF01B8A800101000070319320075 -:200620000050407901000000941300100000040000000000000010048214FF68790004EF78 -:20064000010100000100100032160000000000000000000000001000AA180000009F00A529 -:2006600000AB00B10000400046196C14000032EF1D18E01004FFFF006814000020B06C14EB -:2006800000000005000C2472203038800305247310B89880FE05D0710E38302202052473B2 -:2006A0001038BF22FE000000D608000000001D4D0000001D440000001D56CD760F21206004 -:2006C0001125060651CD6D0F2E71117606060FC36D0F210061C3E306210062C3E3062E0033 -:2006E000CD0C08064811F806CD6D0FCD9F072EE41110060615C36D0F05050505070707073D -:200700000101010103030303F1F3F5F7F8F2F4F6CCDACCA8CC76CC44CC129A12681236126D -:2007200004120444047604A804DA36DA68DA9ADA9A44364436A89AA8CC12041204DACCDAA1 -:20074000210063CD890FCD890F21010822FC672142630608C3332100FF00C91706FF00FECF -:200760000000C91706FF0000FF01D017061200020101D01706121000FF02D717FF09FE008D -:200780000202D717FF092000FF03DE170F0902000303DE170F093004040505060607072E91 -:2007A000480E0411EA07D5061ECD6D0FD10DC2A607AFD3033E04D30247110808C51A6F13E9 -:2007C000D5780F0E0ED2E0073A0B602FE607C61BCDCA0D010701CD881ED1C105C2BC07C941 -:2007E0003600230DC2E007C3D907AEEAFEFFFEFFF83FF83FF83FF83FF83FF83FF83FF83FFD -:00000001FF diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv deleted file mode 100644 index 684014b4..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_memory.sv +++ /dev/null @@ -1,93 +0,0 @@ - -module westerngun_memory( -input Clock, -input RW_n, -input [15:0]Addr, -input [15:0]Ram_Addr, -output [7:0]Ram_out, -input [7:0]Ram_in, -output [7:0]Rom_out -); - -wire [7:0]rom_data_0; -wire [7:0]rom_data_1; -wire [7:0]rom_data_2; -wire [7:0]rom_data_3; -wire [7:0]rom_data_4; - - -sprom #( - .init_file("./roms/ic36.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_h ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_0) - ); - -sprom #( - .init_file("./roms/ic35.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_g ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_1) - ); - -sprom #( - .init_file("./roms/ic34.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_f ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_2) - ); - -sprom #( - .init_file("./roms/ic33.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_e ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_3) - ); - -sprom #( - .init_file("./roms/ic32.hex"), - .widthad_a(11), - .width_a(8)) -u_rom_d ( - .clock(Clock), - .Address(Addr[10:0]), - .q(rom_data_4) - ); - -always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin - Rom_out = 8'b00000000; - case (Addr[15:11]) - 5'b00000 : Rom_out = rom_data_0; - 5'b00001 : Rom_out = rom_data_1; - 5'b00010 : Rom_out = rom_data_2; - 5'b00011 : Rom_out = rom_data_3; - 5'b01000 : Rom_out = rom_data_4; - default : Rom_out = 8'b00000000; - endcase - -end - -spram #( - .addr_width_g(14), - .data_width_g(8)) -u_ram0( - .address(Ram_Addr[13:0]), - .clken(1'b1), - .clock(Clock), - .data(Ram_in), - .wren(~RW_n), - .q(Ram_out) - ); -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv deleted file mode 100644 index 83286f52..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_mist.sv +++ /dev/null @@ -1,218 +0,0 @@ -module westerngun_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "WesternGunPtII;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Overlay, On, Off;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - - -wire clk_core, clk_sys; -wire pll_locked; -pll pll -( - .inclk0(CLOCK_27), - .areset(), - .c0(clk_core), - .c1(clk_sys) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; -wire [7:0] joystick_0,joystick_1; -wire scandoublerD; -wire ypbpr; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; -wire [7:0] audio; -wire hsync,vsync; -wire hs, vs; -wire r,g,b; - -wire [15:0]RAB; -wire [15:0]AD; -wire [7:0]RDB; -wire [7:0]RWD; -wire [7:0]IB; -wire [5:0]SoundCtrl3; -wire [5:0]SoundCtrl5; -wire Rst_n_s; -wire RWE_n; -wire Video; -wire HSync; -wire VSync; - -invaderst invaderst( - .Rst_n(~(status[0] | status[6] | buttons[1])), - .Clk(clk_core), - .ENA(), - .Coin(btn_coin), - .Sel1Player(~btn_one_player), - .Sel2Player(~btn_two_players), - .Fire(~m_fire), - .MoveLeft1(~m_left), - .MoveRight1(~m_right), - .MoveUp1(~m_up), - .MoveDown1(~m_down), - .MoveLeft2(~m_left), - .MoveRight2(~m_right), - .MoveUp2(~m_up), - .MoveDown2(~m_down), -// .DIP(dip), - .RDB(RDB), - .IB(IB), - .RWD(RWD), - .RAB(RAB), - .AD(AD), - .SoundCtrl3(SoundCtrl3), - .SoundCtrl5(SoundCtrl5), - .Rst_n_s(Rst_n_s), - .RWE_n(RWE_n), - .Video(Video), - .HSync(HSync), - .VSync(VSync) - ); - -westerngun_memory westerngun_memory ( - .Clock(clk_sys), - .RW_n(RWE_n), - .Addr(AD), - .Ram_Addr(RAB), - .Ram_out(RDB), - .Ram_in(RWD), - .Rom_out(IB) - ); - -invaders_audio invaders_audio ( - .Clk(clk_sys), - .S1(SoundCtrl3), - .S2(SoundCtrl5), - .Aud(audio) - ); - -westerngun_overlay westerngun_overlay ( - .Video(Video), - .Overlay(~status[5]), - .CLK(clk_sys), - .Rst_n_s(Rst_n_s), - .HSync(HSync), - .VSync(VSync), - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - .O_HSYNC(hs), - .O_VSYNC(vs) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_sys), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r,r}), - .G({g,g,g}), - .B({b,b,b}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoubler_disable(scandoublerD), - .ce_divider(0), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac dac ( - .clk_i(clk_sys), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge clk_sys) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd deleted file mode 100644 index ffa6ec94..00000000 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/WesternGunPtII_MiST/rtl/westerngun_overlay.vhd +++ /dev/null @@ -1,127 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - - -entity westerngun_overlay is - port( - Video : in std_logic; - Overlay : in std_logic; - CLK : in std_logic; - Rst_n_s : in std_logic; - HSync : in std_logic; - VSync : in std_logic; - O_VIDEO_R : out std_logic; - O_VIDEO_G : out std_logic; - O_VIDEO_B : out std_logic; - O_HSYNC : out std_logic; - O_VSYNC : out std_logic - ); -end westerngun_overlay; - -architecture rtl of westerngun_overlay is - - signal HCnt : std_logic_vector(11 downto 0); - signal VCnt : std_logic_vector(11 downto 0); - signal HSync_t1 : std_logic; - signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; - signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; - signal VideoRGB : std_logic_vector(2 downto 0); -begin - process (Rst_n_s, Clk) - variable cnt : unsigned(3 downto 0); - begin - if Rst_n_s = '0' then - cnt := "0000"; - elsif Clk'event and Clk = '1' then - if cnt = 9 then - cnt := "0000"; - else - cnt := cnt + 1; - end if; - end if; - end process; - - p_overlay : process(Rst_n_s, Clk) - variable HStart : boolean; - begin - if Rst_n_s = '0' then - HCnt <= (others => '0'); - VCnt <= (others => '0'); - HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; - Overlay_G1 <= false; - Overlay_G2 <= false; - Overlay_R1 <= false; - elsif Clk'event and Clk = '1' then - HSync_t1 <= HSync; - HStart := (HSync_t1 = '0') and (HSync = '1'); - - if HStart then - HCnt <= (others => '0'); - else - HCnt <= HCnt + "1"; - end if; - - if (VSync = '0') then - VCnt <= (others => '0'); - elsif HStart then - VCnt <= VCnt + "1"; - end if; - - if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; - end if; - end if; - - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; - end if; - - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then - Overlay_R1 <= true; - elsif (HCnt = x"1E6") then - Overlay_R1 <= false; - end if; - - end if; - end process; - - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) - begin - if (Video = '0') then - VideoRGB <= "000"; - else - if Overlay_G1 or Overlay_G2 then - VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; - end if; - end if; - end process; - - - O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); - O_HSYNC <= HSync; - O_VSYNC <= VSync; - - -end; \ No newline at end of file diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/DIGDUG2.ROM b/Arcade_MiST/Namco Mappy Hardware/Releases/DIGDUG2.ROM deleted file mode 100644 index e7621a76..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/DIGDUG2.ROM and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/DRUAGA.ROM b/Arcade_MiST/Namco Mappy Hardware/Releases/DRUAGA.ROM deleted file mode 100644 index c168e6cb..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/DRUAGA.ROM and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/DigDug2.rbf b/Arcade_MiST/Namco Mappy Hardware/Releases/DigDug2.rbf deleted file mode 100644 index ea2d49f9..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/DigDug2.rbf and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/GROBDA.ROM b/Arcade_MiST/Namco Mappy Hardware/Releases/GROBDA.ROM deleted file mode 100644 index 299d5937..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/GROBDA.ROM and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/MAPPY.ROM b/Arcade_MiST/Namco Mappy Hardware/Releases/MAPPY.ROM deleted file mode 100644 index 739dc435..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/MAPPY.ROM and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/MOTOS.ROM b/Arcade_MiST/Namco Mappy Hardware/Releases/MOTOS.ROM deleted file mode 100644 index 3e31a44f..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/MOTOS.ROM and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/Mappy.rbf b/Arcade_MiST/Namco Mappy Hardware/Releases/Mappy.rbf deleted file mode 100644 index 1b69683d..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/Mappy.rbf and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/Motos.rbf b/Arcade_MiST/Namco Mappy Hardware/Releases/Motos.rbf deleted file mode 100644 index bcf5398a..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/Motos.rbf and /dev/null differ diff --git a/Arcade_MiST/Namco Mappy Hardware/Releases/TheTowerofDruaga.rbf b/Arcade_MiST/Namco Mappy Hardware/Releases/TheTowerofDruaga.rbf deleted file mode 100644 index 8b0b6e9a..00000000 Binary files a/Arcade_MiST/Namco Mappy Hardware/Releases/TheTowerofDruaga.rbf and /dev/null differ diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf deleted file mode 100644 index 224eed1f..00000000 Binary files a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf and /dev/null differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/Snapshot/RallyX.rbf b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/Snapshot/RallyX.rbf deleted file mode 100644 index 224eed1f..00000000 Binary files a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/Snapshot/RallyX.rbf and /dev/null differ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/POPEYE.ROM b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/POPEYE.ROM deleted file mode 100644 index 66091ffa..00000000 Binary files a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/POPEYE.ROM and /dev/null differ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf b/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf deleted file mode 100644 index c72028ac..00000000 Binary files a/Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf and /dev/null differ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM deleted file mode 100644 index cdb95838..00000000 Binary files a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM and /dev/null differ diff --git a/Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/Release/DKong.rbf b/Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/Release/DKong.rbf deleted file mode 100644 index b3ea3db0..00000000 Binary files a/Arcade_MiST/Nintendo Radar Scope Hardware/Donkey Kong/Release/DKong.rbf and /dev/null differ diff --git a/Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/Releases/DKongJr.rbf b/Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/Releases/DKongJr.rbf deleted file mode 100644 index 3609a325..00000000 Binary files a/Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/Releases/DKongJr.rbf and /dev/null differ diff --git a/Arcade_MiST/Non Arcade/2048_MiST/Release/2048.rbf b/Arcade_MiST/Non Arcade/2048_MiST/Release/2048.rbf deleted file mode 100644 index 42bae8af..00000000 Binary files a/Arcade_MiST/Non Arcade/2048_MiST/Release/2048.rbf and /dev/null differ diff --git a/Arcade_MiST/Non Arcade/Arkanoid_MiST/Release/Arkanoid.rbf b/Arcade_MiST/Non Arcade/Arkanoid_MiST/Release/Arkanoid.rbf deleted file mode 100644 index defce72d..00000000 Binary files a/Arcade_MiST/Non Arcade/Arkanoid_MiST/Release/Arkanoid.rbf and /dev/null differ diff --git a/Arcade_MiST/Non Arcade/FlappyBird_MiST/Release/FlappyBird_MiST.rbf b/Arcade_MiST/Non Arcade/FlappyBird_MiST/Release/FlappyBird_MiST.rbf deleted file mode 100644 index 904dfee6..00000000 Binary files a/Arcade_MiST/Non Arcade/FlappyBird_MiST/Release/FlappyBird_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Non Arcade/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf b/Arcade_MiST/Non Arcade/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf deleted file mode 100644 index d81fa285..00000000 Binary files a/Arcade_MiST/Non Arcade/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf and /dev/null differ diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NINJAKUN.ROM b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NINJAKUN.ROM deleted file mode 100644 index f713fdd4..00000000 Binary files a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NINJAKUN.ROM and /dev/null differ diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NinjaKun_MiST.rbf b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NinjaKun_MiST.rbf deleted file mode 100644 index 0928d221..00000000 Binary files a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Release/NinjaKun_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf b/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf deleted file mode 100644 index f8bf0ffb..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Release/Birdiy.rbf b/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Release/Birdiy.rbf deleted file mode 100644 index e1f05d9a..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Release/Birdiy.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf b/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf deleted file mode 100644 index f7896150..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf b/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf deleted file mode 100644 index cc85e0aa..00000000 Binary files a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf b/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf deleted file mode 100644 index 46a07748..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/Release/Eggor.rbf b/Arcade_MiST/Pacman Hardware/Eggor_MiST/Release/Eggor.rbf deleted file mode 100644 index 5b0422f7..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Eggor_MiST/Release/Eggor.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf b/Arcade_MiST/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf deleted file mode 100644 index 431e8c7a..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf b/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf deleted file mode 100644 index e4cac949..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf b/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf deleted file mode 100644 index 1f0ac350..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf b/Arcade_MiST/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf deleted file mode 100644 index 3c234559..00000000 Binary files a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf b/Arcade_MiST/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf deleted file mode 100644 index 559a9721..00000000 Binary files a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/Release/ManiacMiner.rbf b/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/Release/ManiacMiner.rbf deleted file mode 100644 index e2d04702..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/Release/ManiacMiner.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf b/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf deleted file mode 100644 index 6f199993..00000000 Binary files a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf b/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf deleted file mode 100644 index f54cbe35..00000000 Binary files a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf b/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf deleted file mode 100644 index 1181c186..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf b/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf deleted file mode 100644 index 93f3a981..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf b/Arcade_MiST/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf deleted file mode 100644 index e89f57c0..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf b/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf deleted file mode 100644 index 5bd3d38e..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf b/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf deleted file mode 100644 index 9567128a..00000000 Binary files a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf b/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf deleted file mode 100644 index fc6ce978..00000000 Binary files a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf and /dev/null differ diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf b/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf deleted file mode 100644 index aef9a554..00000000 Binary files a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf and /dev/null differ diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf deleted file mode 100644 index 619cb3ac..00000000 Binary files a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/Release/phoenix_mist.rbf b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/Release/phoenix_mist.rbf deleted file mode 100644 index bb64275e..00000000 Binary files a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/Release/phoenix_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Release/Pleiads_mist.rbf b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Release/Pleiads_mist.rbf deleted file mode 100644 index 7429e376..00000000 Binary files a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Release/Pleiads_mist.rbf and /dev/null differ diff --git a/Arcade_MiST/Phoenix Hardware/Survival_MIST/Snapshot/Survival_MiST.rbf b/Arcade_MiST/Phoenix Hardware/Survival_MIST/Snapshot/Survival_MiST.rbf deleted file mode 100644 index e220e548..00000000 Binary files a/Arcade_MiST/Phoenix Hardware/Survival_MIST/Snapshot/Survival_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM deleted file mode 100644 index df86695d..00000000 Binary files a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM and /dev/null differ diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf deleted file mode 100644 index 53acfab0..00000000 Binary files a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf and /dev/null differ diff --git a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BOMBJACK.ROM b/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BOMBJACK.ROM deleted file mode 100644 index 6bade369..00000000 Binary files a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BOMBJACK.ROM and /dev/null differ diff --git a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BombJack.rbf b/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BombJack.rbf deleted file mode 100644 index 393c5eb6..00000000 Binary files a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/Release/BombJack.rbf and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/COLONY7.ROM b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/COLONY7.ROM deleted file mode 100644 index 09141fc5..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/COLONY7.ROM and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf deleted file mode 100644 index 0f404cff..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/DEFENDER.ROM b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/DEFENDER.ROM deleted file mode 100644 index 17a95fee..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/DEFENDER.ROM and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf deleted file mode 100644 index 40caf603..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM deleted file mode 100644 index 632beeff..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/JIN.ROM and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf deleted file mode 100644 index 8fdb1535..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/MAYDAY.ROM b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/MAYDAY.ROM deleted file mode 100644 index 0508ad5a..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/MAYDAY.ROM and /dev/null differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf deleted file mode 100644 index 770e9968..00000000 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf and /dev/null differ diff --git a/Computer_MiST/Acorn - Electron_MiST/Snapshot/AtomElectron_Mist.rbf b/Computer_MiST/Acorn - Electron_MiST/Snapshot/AtomElectron_Mist.rbf deleted file mode 100644 index 636bb217..00000000 Binary files a/Computer_MiST/Acorn - Electron_MiST/Snapshot/AtomElectron_Mist.rbf and /dev/null differ diff --git a/Computer_MiST/Acorn - System1/Snapshot/Acorn_System1.rbf b/Computer_MiST/Acorn - System1/Snapshot/Acorn_System1.rbf deleted file mode 100644 index 9acf5abb..00000000 Binary files a/Computer_MiST/Acorn - System1/Snapshot/Acorn_System1.rbf and /dev/null differ diff --git a/Computer_MiST/Apple - 1_MiST/snapshot/apple-one(serial Transfer).rbf b/Computer_MiST/Apple - 1_MiST/snapshot/apple-one(serial Transfer).rbf deleted file mode 100644 index 92417a56..00000000 Binary files a/Computer_MiST/Apple - 1_MiST/snapshot/apple-one(serial Transfer).rbf and /dev/null differ diff --git a/Computer_MiST/Apple - 1_MiST/snapshot/apple-one.rbf b/Computer_MiST/Apple - 1_MiST/snapshot/apple-one.rbf deleted file mode 100644 index 086ff7af..00000000 Binary files a/Computer_MiST/Apple - 1_MiST/snapshot/apple-one.rbf and /dev/null differ diff --git a/Computer_MiST/Apple - 2_MiST/snapshot/AppleII_MiST.rbf b/Computer_MiST/Apple - 2_MiST/snapshot/AppleII_MiST.rbf deleted file mode 100644 index e25000fc..00000000 Binary files a/Computer_MiST/Apple - 2_MiST/snapshot/AppleII_MiST.rbf and /dev/null differ diff --git a/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.qsf b/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.qsf index 0f158c95..7e19594c 100644 --- a/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.qsf +++ b/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.qsf @@ -150,13 +150,6 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -#set_location_assignment PLL_1 -to #"pll:pll|altpll:altpll_component" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/b2m_mist.sv set_global_assignment -name VERILOG_FILE rtl/b2m_top.v set_global_assignment -name VERILOG_FILE rtl/k580wi53.v set_global_assignment -name VERILOG_FILE rtl/k580wm80a.v @@ -164,10 +157,23 @@ set_global_assignment -name VERILOG_FILE rtl/k580wn59.v set_global_assignment -name VERILOG_FILE rtl/k580ww55.v set_global_assignment -name VERILOG_FILE rtl/b2m_video.v set_global_assignment -name VERILOG_FILE rtl/b2m_kbd.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VERILOG_FILE rtl/build_id.v set_global_assignment -name VERILOG_FILE rtl/SDRAM_Controller.v +set_global_assignment -name QIP_FILE rtl/bios.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/b2m_mist.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* set_global_assignment -name VERILOG_FILE rtl/sd_card.v -set_global_assignment -name VERILOG_FILE rtl/clk20mhz.v -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VHDL_FILE rtl/bios.vhd -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +#set_location_assignment PLL_1 -to #"pll:pll|altpll:altpll_component" +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name QIP_FILE rtl/clk20mhz.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.srf b/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.srf index 0fdd3ca9..d2ea016f 100644 --- a/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.srf +++ b/Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.srf @@ -1,2 +1,7 @@ -{ "" "" "" "*" { } { } 0 13012 "" 0 0 "Quartus II" 0 -1 0 ""} { "" "" "" "*" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13012 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 14320 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Computer_MiST/Bashkiria2M_MiST/Snapshot/Bashkiria2m_Mist.rbf b/Computer_MiST/Bashkiria2M_MiST/Snapshot/Bashkiria2m_Mist.rbf deleted file mode 100644 index eee3db4a..00000000 Binary files a/Computer_MiST/Bashkiria2M_MiST/Snapshot/Bashkiria2m_Mist.rbf and /dev/null differ diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/BIOS4.HEX b/Computer_MiST/Bashkiria2M_MiST/rtl/BIOS4.HEX new file mode 100644 index 00000000..317f47f1 --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/BIOS4.HEX @@ -0,0 +1,257 @@ +:20000000C313E0C355E8C3CBF1C372E2C3CCE2C3F5F132F33EAAD310D311D312D3133E801D +:20002000D36B3E30D3633E76D3633E94D3633E0DD3623E90D3473EF0D3463E15D3793E4020 +:20004000D3793EFED3793E16D3743EDFD3753EFFD375AFD36A32FEDF32FFDF3EC33204DF26 +:200060002113E02205DFFB0100603EE9D3613E07D3613E15D3790B79B0C276E03E25D3799C +:2000800001FFFF0B79B0C283E03100DFCD66EE0120DF2126DFCD55F07AFEDCCC3CF83AFF12 +:2000A000DFB7C29EE03100DFCD10FF3E25D3793EFFD3753E20D374CD04E92119E1CDC2E35E +:2000C0002125E1CDC2E33100DF218CE1CDC2E3CD72E221C6E0E5FE3FCAABE0FE0DC8FE53F4 +:2000E000CA05E2FE52CA53E2FE57CA5AE2FE4CCA6AE3FE47CA41E2FE59CA53E3FE55CA603E +:20010000E3CD07E1C3C6E0210DE1C3C2E30D0A2DDEE8D8D1DAD02D0D001B42B7B0B3C0C3D6 +:20012000B7C7B8BA00C4E3DDDAE6D8D83A0D0A532DE3E1E2D0DDDED2DAD020EFE7D5D9DADF +:20014000D80D0A4C2DD7D0D3E0E3D7DAD020D8D720BFB7C30D0A522DE7E2D5DDD8D520E192 +:2001600020BCBB0D0A572DD7D0DFD8E1EC20DDD020BCBB0D0A472DD2EBDFDEDBDDD8E2EC5B +:2001800020DFE0DED3E0D0DCDCE30D000A3E000D0ABFDED4D3DEE2DED2ECE2D520DCD0D322 +:2001A000DDD8E2DEE4DEDD20D4DBEF2000B7B0BFB8C1B800C7C2B5BDB8CF000D0AD820DD88 +:2001C000D0D6DCD8E2D5203CB2BA3E000A2AB7B0BFB8C1CC2A0D000A2AC7C2B5BDB8B52A6C +:2001E0000D000A2ADEE8D8D1DAD020BAC12A0D000AD2EBDADBEEE7D820DCD0D3DDD8E2DE96 +:20020000E4DEDD0D00CDCCE23DC201E12A1ADFCD41E3E5CD46E3CD4EE3E17EE5CDD5E3CD53 +:200220004EE3CD72E2E1FE0DCA3DE2FE2EC8E5CDCFE22A1ADF7CB7C201E17DE17723C30F7C +:20024000E2CDCCE23DC201E13100DF21C6E0E52A1ADFE9CD61E2CDE2EFC9CD61E2CDA8EFAD +:20026000C9CDCCE2FE02C201E12A1ADF444D2A1CDFC911DADF0600CD6FE4FE0DCA89E2FEC6 +:200280007FCA9DE2FE20DA77E2CDCEE31213FE0DCAACE20478FE20CAACE2C377E2AFB0CA08 +:2002A00077E2051B3E7FCDCEE3C377E221DADF2217DF783216DFE52116DF7EB73E0DCACACE +:2002C000E2352A17DF7E232217DFE1C9CDB6E22119DF360023FE0DCA01E3CD08E3CD20E36C +:2002E000FE0DCA01E3CDB6E2CD08E3CD20E3FE0DCA01E3CDB6E2CD08E3CD20E3FE0DC201E4 +:20030000E11119DF1A13B7C9EB210000CD2BE329292929B56FCDB6E2CD38E3C20CE3EBC9E5 +:2003200073237223E52119DF34E1C9D630FE0AD8C6F9FE10D8C301E1FE0DC8FE2CC8FE20A3 +:20034000C93E0AC3CEE37CCDD5E37DC3D5E33E20C3CEE3CD61E2CD44E4CDF1E3C207E1C934 +:20036000CD61E2CD44E4CD1CE4C9CDCCE2FE03C201E12A1ADF444D2A1CDFE52A1EDF545D2C +:20038000E13E90D3477BD3457AF6C0D3467AE6C0C2A1E33E0CD347DB44F53E0DD347C3AC06 +:2003A000E33E0ED347DB44F53E0FD347F10213CDB6E3DA85E3C97894DABFE3C07995D003D9 +:2003C00037C9F57ECDCEE323B7C2C3E3F1C9C54FCDD7E7C1C9F51F1F1F1FE60FCDE2E3F11E +:2003E000E60FFE0AD2ECE3C630C3CEE3C637C3CEE3C5CD65E4C0DB78B7C0CD65E4C0DB78F6 +:20040000FEFFC0CD65E4C0DB7802CDB6E3DA03E4CD65E4C0DB78C1CD55F0BAC9C5CD55F077 +:20042000C1D5CD5DE4AFD378CD5DE43EFFD378CD5DE40AD378CDB6E3DA2FE4CD5DE4DB7871 +:20044000F1D378C93E96D3633E07D3623E15D3793E40D3793EFED3793E27D379C9DB79E66E +:2004600005CA5DE4C9DB79E63ACA65E4FE02C9C5D53EFF32D7DFCDAFE4FEFFCA76E44F3A8A +:2004800045DFB7CA9DE4110008CDFCE6CA96E41B7BB2C289E42F3245DF79D1C1C911002029 +:2004A000C389E4AF32D7DFCDAFE4FEFFC02FC9C5D5E53A25DFB7CACBE42A6EDF7E3225DF48 +:2004C000B7CAACE623226EDFC3B4E63E04F5065816001E7F210128F33E02D36A4E3AFEDFB3 +:2004E000D36AFB3E01F5A1C209E5147AB8FAF5E41600C313E5F107D2E5E47D07D205E52161 +:200500000129C3D7E46FC3D7E47BFE7FC213E55AC3EAE4F13AD6DFBA7A32D6DFCA23E5F1EB +:20052000C3CBE4F13DC2CDE47BFE7FCAB2E67AB7CA63E5FE38FAB2E6FE407BFA4FE5FE3826 +:20054000FAB2E6FE40F2B2E6CDC7E65AC330E6FE38FA5CE5FE40F2B2E6C38BE67ACDC7E633 +:20056000C37AE506007BFE38FA7AE5FE40F230E6FE3CC2B2E63E1BC3B4E616003A26DF4F15 +:20058000A8E604CA8CE52A27DFC3DFE52187E77800E610C2DFE57BFE20D2EAE5211FE7797A +:2005A000A80600E603CAD9E5FE01C2CFE57BFE05CAD9E5FE07CAD9E5FE0FCAD9E5FE11CAA6 +:2005C000D9E5FE18CAD9E5FE1BCAD9E5C3D7E52167E7FE02CAD9E50620197E80C3B4E67B93 +:2005E0000600FE30D2B2E6C3D9E5D620FE10D220E65FFE0BC20BE679A8E602CA0BE679A800 +:20060000E6013EF1C2B4E63DC3B4E679A80600E601C21AE6213FE7C3D9E52157E7C3D9E556 +:20062000D610FE08D2B2E65F214FE70600C3D9E53A26DF4F7B1600D640FE10DA5CE6D618DA +:200640002F3C5F79A8E601C24CE616057B82110A002168DF193DC254E6C3BCE45FFE08CA55 +:200660006CE6FE0ACA6CE6FE0BC276E679A8E601C283E6C37DE679A8E608C283E621B7E78B +:20068000C386E621C7E70600C3D9E53AD7DFB7CAB2E67AFE397BCA9FE6FE397AC2B2E6CD79 +:2006A000C7E63A26DFA83226DFCD7FEBCDFCE6C2ACE63EFF4FFEFFCAC3E63A26DFE610C440 +:2006C00039F879E1D1C1C90600FE38CAD3E6FE3FC2D6E60601C9FE3EC2DEE60602C9FE3D1C +:2006E000C2E6E60604C9FE3BC2EEE60608C9FE3AC2F6E60610C9FE3CC00620C9F33E02D34F +:200700006A3A7F28B7C214E73A8028E612C214E73AFF29B73AFEDFD36AFB3E00C82FC955C8 +:2007200041544C5760467E4A59564B5251427B445B454E43485A477D584F5D4950534D2A77 +:20074000265E252423405F3C272BFF217C292820097F1C1D031F0D383736353433322D2CB3 +:200760003B3DFF315C3039B3C4B5B4C6B1B0CEBEBDBCBBBAB9B8C5B2B6C3C2C1C0CFBFCA8F +:20078000C7C9CDC8B7CBCC1501140C17FF06FF0A19160B121102FF041B050E03081A07FFD0 +:2007A000180F1D0910130DFFFF1EFFFFFF001FFFFFFFFFFF1CFFFF37363534333231303F94 +:2007C0002E223EFFFF39380C181108151A16172F103A2EFFFF1419F3F5C5D5E5CD55E8211F +:2007E0004CE8E5C335DF79FE1BC2F8E73EC33235DF2164EC2236DFC9FE08C202E83E12C359 +:200800001BE8FE0CC20CE83E13C31BE8FE1BD224E8FE11CA24E8FE10DA24E8C6314FCDEC2F +:20082000E7C335DFFE7FCA7CE8FE09CA85E8FE0ACAC2E8FE0DCAEAE8FE1FCA04E9FE07CA4B +:20084000BEE8FE20D8E1CDC9E9CD9DE9CD55E8E1D1C1F1FBC9F52A38DFCD48EAE53E02CDF0 +:200860006AE8E13E03CD6AE8F1C9D36A060A7E2F772C05C26EE83AFEDFD36AC9CDB4E93EAC +:2008800020CDC9E9C93A43DF473A3EDFB8CAB7E847AFB8CA99E8D29EE8C608C392E8470032 +:2008A0003A43DFB8DAA8E878323EDF473A3FDF4FCDC3ED2238DFC9CDEAE8CDC2E8C9CD39A1 +:2008C000F8C93A41DF473A3FDFFE17CADFE8B8C83C323FDF2A38DF7DC60A6F2238DFC93A73 +:2008E00026DFE620CAECEAC288E93A42DF473A3EDFB8C82A38DF90253DC2F7E878323EDF06 +:200900002238DFC9F5C5D5E5210644223ADF21EC44223CDFCD6EE9CD25E9CD88E9CD7FEBB9 +:20092000E1D1C1F1C9E5F53EFFD310D311D312D313210040E53E02CD5DE9E13E03CD5DE913 +:200940003A21DFD3103A22DFD3113A23DFD3123A24DFD313AF3244DFD369F1E1C9D36A36C9 +:2009600000237CFE70C25FE93AFEDFD36AC9AF3242DF3240DF3E273243DF3E173241DF3A56 +:2009800026DFE61F3226DFC93A42DF323EDF473A40DF323FDF4FCDC3ED2238DFC93A43DF89 +:2009A000473A3EDFB8CAB7E83C323EDF2A38DF242238DFC93A42DF473A3EDFB8C83D323E60 +:2009C000DF2A38DF252238DFC9F5AF32D9DFCD48EA11D9DF0601CD5AEAF1CDEBE90608CDF5 +:2009E0005AEA060111D9DFCD5AEAC9E52132EAE50129DFFE40D2FBE9D620C90303FE60D210 +:200A000005EAD640C90303FE80D20FEAD660C90303FEB0D219EAD680C90303FED0D223EA5F +:200A2000D6B0C90303FEF3D22DEAD6D0C90129DFAFE1F50A6F030A67F1110800B7CA45EAE3 +:200A4000193DC33CEAEBE1C9D5F52A38DFEB2A3ADF7D836F7C8267F1D1C91A4FD511D5EA1C +:200A6000D53A20DFFE01C26DEA160059C9FE02C276EA511E00C9FE03C27EEA5159C9FE041E +:200A8000C289EA1600792F5FC9FE06C293EA51792F5FC9FE07C29CEA511EFFC9FE08C2A7E4 +:200AA000EA792F571E00C9FE09C2B1EA792F5759C9FE0BC2BAEA16FF59C9FE0CC2C4EA7948 +:200AC0002F575FC9FE0DC2CFEA792F571EFFC9D116FF792F5F3E02D36A723E03D36A733AF6 +:200AE000FEDFD36AD1132C05C25AEAC92100003922ECDF21ECDFF92A3CDF7DC60A6F223C6D +:200B0000DF3E02F5D36A061AE50E283600240DC20BEBE12C05C208EBF13DCA2FEBF53E0618 +:200B20003207EB2A3ADF7DC6046F3E03C304EB3E1A3207EB2A3CDFE5D17DC60A6FDB74E63D +:200B400001C23DEB3A44DFC60AD3693244DF3E03D36A060AE5D50E281A77AF1214240DC215 +:200B600058EBD1E12C1C05C254EB2A3ADF7DC60A6F223ADF2AECDFF93AFEDFD36AC90DF5EB +:200B8000C5D5E53A20DFF53E043220DF2146DF3A26DFE604C2B1EB3A26DFE602C2A8EB01EB +:200BA00052ECCD44ECC3B7EB0155ECCD44ECC3B7EB0158ECCD44EC362F233A26DFE601CA37 +:200BC000C7EB3648C3C9EB364223365023362F233A26DFE608C2DEEB015BECC3E1EB015EB4 +:200BE000ECCD44EC3A26DFE620C2F8EB362F230161ECCD44ECC301EC362023014FECCD44D9 +:200C0000EC06281146DFAF32D9DF2A38DFE52A3CDF3E0B856F2238DFC5E5D511D9DF0601BB +:200C2000CD5AEAD11AD5CDEBE90608CD5AEAD1E124C11305C215ECE12238DFF13220DFE194 +:200C4000D1C1F1C916030A77230315C246ECC9202020BBD0E2C0E3E1B3E0E4C6E4E0C3DFC2 +:200C6000BAC0E3DB79D641FE1AD2ADEC5F16002179EC19195E2356EBE95EEF2EED73ED7910 +:200C8000ED82EF8CEF7CEF6FEF6DED52ED67ED7FEDADEC66EE85EDE5EEADECADECADECB9A3 +:200CA000EC1DEEADECEFEC0AEF9BEEADEC3EC33235DF21E6E72236DFC9AF32D8DF21C4EC10 +:200CC0002236DFC93AD8DFB7C2DEEC2168DF7932D8DF110A00193DC2D5EC2217DFC9792A9E +:200CE00017DF77232217DFB7C032D8DFC3ADEC3E0332D8DF2101ED2236DF2129DF22ECDF0A +:200D0000C93AD8DF2AECDFFE03C21BEDF5793D075F16001922ECDFF1C326EDFE02C224ED92 +:200D200071C326ED23713D32D8DFC0C3ADECCD8EEE213EED2236DF2155DF2217DFC979B764 +:200D4000CA4CED2A17DF77232217DFC9CD7FEBC3ADEC3A40DF473A3FDFB8CAADEC3DF53AE3 +:200D60003EDF47F1C368EFCDC2E8C3ADECCD9DE9C3ADECCDB4E9C3ADECCD88E9C3ADECCD55 +:200D80006EE9C3ADEC3A20DFF50F0FE603F53A42DF473A40DF4FCDC3ED11064419F1F5E66F +:200DA000013220DFE53E0232D9DFCDDCEDE1F1E6023220DF3E0332D9DFCDDCEDF13220DF8E +:200DC000C3ADEC21000078B7CAD0ED243DC2CBED79B7C87DC60A0DC2D4ED6FC93A42DF4756 +:200DE0003A43DF903C4F3A40DF473A41DF903C47C5E53AD9DFD36A3A20DFB7C202EE57C3DA +:200E000004EE16FF3E0A722C3DC206EE05C204EE3AFEDFD36AE124C10DC2F0EDC93E043236 +:200E2000D8DF2131EE2236DF3A26DFF6203226DFC93AD8DFF50D215DEEE5FE04C244EE797C +:200E40003242DFC9FE03C24EEE793240DFC9FE02C258EE793243DFC9793241DFE1F13D323A +:200E6000D8DFCA79EDC93E0A01F6FF21D6DF09772336002B3DC26EEE0E151193EF2120DF79 +:200E80001A7713230DC280EECD8EEEC3ADEC2154DF3E1A3620233DC293EEC93E0232D8DF12 +:200EA00021A7EE2236DFC93AD8DF0DF5FE02C2C1EE79D620FE18DABBEE3E17323FDFC3CEDA +:200EC000EE79D620FE28DACBEE3E27323EDFF13D32D8DFC03A3EDF473A3FDF4FCDC3ED228D +:200EE00038DFC3ADEC21ECEE2236DFC979E60FF5F50F0FE60347F1E603B8C203EFF13E0267 +:200F0000C304EFF13220DFC3ADEC3E0432D8DF2116EF2236DFC93AD8DFF52155EFE5FE041A +:200F2000C22DEF79FE80C83222DFD311C9FE03C23CEF79FE80C83223DFD312C9FE02C24B98 +:200F4000EF79FE80C83224DFD313C979FE80C83221DFD310E1F13D32D8DFCAADECC93A438A +:200F6000DF323EDF473A41DF323FDF4FC3DCEE3A42DF323EDF473A3FDFC36BEF3A43DFC3F1 +:200F800072EF3A3EDF473A40DFC368EF3A3EDF47C365EF02FFCD1EF000001FE7EFF2EFF385 +:200FA000EFF4EFF2EFF5EFF6F5D5E5C5CD55F0218FE1CDC2E321ADE1CDC2E321BBE1CDC2AE +:200FC000E3CD6FE4FE0DCACEEFC1E1C32BF021CCE1CDC2E3C1E11EB0CD63F03E0DD362C3E9 +:200FE0002BF0221EDF210000392217DF2A1EDFF5D5E5C5218FE1CDC2E321B4E1CDC2E3215E +:20100000BBE1CDC2E3CD6FE4FE0DC2C9EF21D7E1CDC2E3AFC1E1CD86F0F3C247F07ACD55B6 +:20102000F0BACA2BF021E2E1CDC2E32113E02205DFCD38F0D1F1FBC93EFFD3753E20D3740C +:2010400021F0E1CDC2E3C921B7F1CDC2E3CD38F02A17DFF9C9F516000A8257CDB6E3DA58CB +:20106000F0F1C9F5C5E5D5C5CDACF07D914F7C984703E156CDDBF0230B78B1C273F0D1CD80 +:20108000DBF0E1C1F1C9F5C5E5E5C5CD2DF1C1E10B03C5CD5CF1C17A0279ADC291F078AC9C +:2010A000C291F0C5CD5CF1C1E1C1F1C9F3E52122F12205DF21401F3E9ED3633E02D3623E9A +:2010C00010D3633EFDD3753E0DCD22F13E0C763E0D762B7CB5C2CCF0E1F3C93E0CFB763E2B +:2010E0000C763E0D763E0D763E08F53E0C767A0F573E0617767A07573E063F17767A0F5778 +:201100003E0D76F13DC2EAF03E0C763E0D763E0C763E0D763E0C763E0D763E0C763E0D7640 +:20112000F3C9D36B7BD3603E61D374FBC92147F02205DFF33E10D3633EFDD37521E803CD2C +:2011400085F12B7CB5C23FF1445CFBCD85F1091DC24BF12424247CA71F845FC9CD85F1CD5F +:2011600085F17993DA5FF106081600CD85F17993D278F1F5CD85F1F17A1F5705C26BF1CD0C +:2011800085F1CD85F1DB74E610CA85F1DB74E610C28CF1AFD363DB602F4F3E10D3633EFF2E +:2011A000D360C9C5D5CD5CF17AD1C1C9F5D51EB051CDDBF0D1F1C90A2A20DEE8D8D1DAD031 +:2011C00020E7E2D5DDD8EF202A0D001100000100C02101C0CD81E32A00C07CBDC80321FF63 +:2011E000C3CD81E3CD59E22A00C02B7E23CDC2E3B7CA2DF2570600CD6FE4FE0DCA20F2FEC9 +:2012000019C20EF24F78B7CAF7F105C31AF2FE1AC2F7F14F78BACAF7F104CDD7E7C3F7F1C0 +:2012200078010800B7CA2DF2093DC324F25E2356D5234E2346235E2356D5235E2356EBD163 +:20124000CD81E3CD66EEE1E9DB74E604C83EFFC9F5C5CD48F2CA52F279FE80D46BF22FD372 +:20126000683E09D36B3DD36BC1F1C9FEF0C275F23EB5C37CF2FEF1C27CF23ED5FED0D288F6 +:20128000F2D6B00E00C38CF2D6D00E01E5D521A1F216005F195E79B77BC29EF2C620D1E1E3 +:2012A000C9C1C2D7C7C4C5D6DAC9CACBCCCDCECFD0D2D3D4D5C6C8C3DEDBDDDFD9D8DCC046 +:2012C000D1C50E40C3CAF2C50E80F306F63E0BD36B3DD36BDB7404A1CAD4F278A7F2EBF2F5 +:2012E0002F3CFE0A0600FAEBF2067F78C1FBC900000000000000000C1E1E0C0C000C00367A +:201300003636000000000036367F367F36360000187C063C603718006333180C6663001C31 +:20132000361C6E3B336E000606030000000000180C0606060C1800060C1818180C0600003C +:20134000663CFF3C660000000C0C3F0C0C000000000000000C0C060000003F00000000007E +:20136000000000000C0C006030180C060301003E63737B6F673E000C0E0C0C0C0C3F001E4D +:2013800033301C06333F003F33181C30331E00383C36337F3078003F031F3030331E001CFD +:2013A00006031F33331E003F3330180C0C0C001E33331E33331E001E33333E30180E000065 +:2013C0000C0C00000C0C00000C0C00000C0C06180C0603060C180000003F003F00000006CC +:2013E0000C1830180C06001E3330180C000C003E637B7B031E00000C1E33333F3333003F92 +:2014000066663E66663F003C66030303663C001F36666666361F007F46161E16467F007F3B +:2014200046161E16060F003C66030373667C003333333F333333001E0C0C0C0C0C1E0078A9 +:2014400030303033331E006766361E366667000F06060646667F0063777F7F6B636300639C +:20146000676F7B736363001C36636363361C003F66663E06060F001E3333333B1E38007FEA +:2014800066663E366667001E33060C18331E003F2D0C0C0C0C1E003333333333331E003336 +:2014A000333333331E0C006363636B7F7763006363361C1C3663003333331E0C0C1E007F10 +:2014C0006331184C667F001E06060606061E0003060C18306040001E18181818181E00081C +:2014E0001C366300000000000000000000007F0C0C18000000000000001E303E336E000754 +:2015000006063E66663B0000001E3303331E003830303E33336E0000001E333F031E001C5E +:2015200036060F06060F0000006E33333E301F0706366E666667000C000E0C0C0C1E003074 +:201540000030303033331E070666361E3667000E0C0C0C0C0C1E000000337F7F6B630000AC +:20156000001F333333330000001E3333331E0000003B66663E060F00006E33333E30780097 +:20158000003B6E66060F0000003E031E301F00080C3E0C0C2C18000000333333336E000091 +:2015A000003333331E0C000000636B7F7F3600000063361C36630000003333333E301F00F2 +:2015C000003F190C263F00380C0C070C0C38000808080000080808070C0C380C0C07006E87 +:2015E0003B00000000000000081C3663637F000C1E33333F3333007F06063E66663F003FC9 +:2016000066663E66663F007F66060606060F003C36363636367F637F46161E16467F006B3E +:201620006B3E1C3E696B003E63603860633E006363737B6F6763001C63737B6F67630063A3 +:20164000331B0F1B336300786C66666666630063777F7F6B6363003333333F333333003EE5 +:2016600063636363633E007F636363636363003F66663E06060F003C66030303663C003F7C +:201680002D0C0C0C0C1E006363637E60201E00187EDBDB7E183C0063361C1C36636300336C +:2016A00033333333337F606363637E60606000636B6B6B6B6B7F00636B6B6B6B6B7F60072C +:2016C000060636666636006363636F5B5B6F000303033F63633F003E63607C60633E00330B +:2016E0006B6B6F6B6B33007E63637E6C66630000001E303E337E0000003F033F633F000045 +:20170000001F331F331F0000003F030303030000003C3636367F6300001E333F031E00004A +:20172000006B6B3E6B6B0000001E3318331E0000006363737F660000186363737F660000B1 +:2017400000331B0F1B73000000786C66666700000063777F6B6300000063637F6363000055 +:20176000003E6363633E0000007F636363630000003F63633F030300003E6303633E00002A +:20178000003F0C0C0C0C00000063667C603E000000187EDB7E1818000063361C366300008A +:2017A00000333333337F60000033333E30300000006B6B6B6B7F0000006B6B6B6B7F6000C4 +:2017C0000007063E663E00000063636F5B6F00000003033F633F0000003F6078603F00007E +:2017E00000336B6F6B330000007E637E666300147F46161E16467F00121E333F031E006407 +:20180000C3A3E4C36FE4C3A3F1C3D7E7C3ACF1C350F2C3FCE6C348F2C3C2E3C3F1E3C32D9A +:20182000F1C3ACF0C3E2EFC3A8EFC355F0C31CE4C3A5E0C31CFDC340FDC32EFDC335FDC3D5 +:2018400080F8C3F0F8C3ABF9C380FAC316FBC372FBC3BEFBC305FCC339FCC3A0FCC325E955 +:20186000C304E9C381E3C3FFFFC3B6E3C37EF8C37EF8C344E4C3D5E3C3C1F2C3C7F2C9FFE2 +:20188000CDBAF8D8E5D5C57A1F7B1F1F1FE63FC640574B5879E6074F060021E8F80946EBE6 +:2018A0003ADCDF4FCDC5F87832DFDF22DDDFC1E1D122EFDF7832F1DFEBC978C60AD83E7FA6 +:2018C000933E019AC91602F33E02D36A79A278CAD6F8B6C3D8F82FA6773E03D36A15C2CC6A +:2018E000F83AFEDFD36AFBC90102040810204080CDBAF8D8E5D5C52AEFDF7B956F7A9C670F +:20190000DCA3F90E02DA0AF90E003AF1DFEB906FDCA3F93E0067DA1BF93E40B14F7B957A4D +:201920009C3E01D229F9EB3E80B132E0DF29CDA3F92B22E3DFEB22E5DF545D2922E1DF3A25 +:20194000DCDF4F3ADFDF472ADDDF7CD640DA37FA3E7094DA37FA7AB3CAA7F81BD5E52AE3F6 +:20196000DFEB2AE5DF23193AE0DFDA74F9F681EB2AE1DF1922E5DFE1570FD290F90F78D2ED +:201980008AF90FD28FF925C38FF907D28FF924477A07D29CF9072DDA9CF92C2CCDC5F8D1E1 +:2019A000C356F97C2F677D2F6F23C9CDBAF8D8E5D5C5EB22E9DF68260022EBDF3AF7DF4780 +:2019C0002AF8DFEBCD91FADA37FA5916003AEEDF6F62EBA7C4A8FA22D7DF593AEDDF6F6271 +:2019E000EBA7C4A8FA22F5DF48CDC5FAE52AF5DFCDA8FA2422F3DF2AD7DFEBCDA8FA22D986 +:201A0000DFEBD1CDA8FA22D7DF2AF5DFCDA8FA22F5DF3AF9DF4FCD3BFACD80F8DA37FA0CC2 +:201A20003E48A9C227FA4FCD3BFACDF0F8DA37FA3AF8DFA9C21FFAC1D1E1C9CDC5FA22E123 +:201A4000DFEB22E5DF2AD9DFCD9DFAE52AE5DFEB2AF5DFCD9DFAD119EB2AEBDF197CC6FF4D +:201A6000D8452AE5DFEB2AF3DFCD9DFAE52AE1DFEB2AD7DFCD9DFAD119EB2AE9DF19EBC97E +:201A8000CD91FAD822EDDFEB22F8DFEB7832F7DFC97AC6B9D87BC6B9D878C6B9C9CDA8FA3E +:201AA0007C26000FDCA3F9C9D5C57CAA477D21FF00540E080FD2B9FA19EB29EB0DC2B4FAFD +:201AC0006C60C1D1C9C579010000161292FADCFA0C92FADCFA0492FADCFA0D9282076F2685 +:201AE0000011F0FA195E236E60517CAAC1C8EBC900FF16FF2CFC42F758F16CE880DE93D2FA +:201B0000A5C4B5B5C4A5D293DE80E86CF158F742FC2CFF16FF0078C6F0D8C5D5E5CD61FB06 +:201B20000E20F31ACD53FB473E02D36A703AFEDFD36A131ACD53FB473E03D36A703AFEDF33 +:201B4000D36A13230DC223FBFB3AFEDFD36AAFE1D1C1C9E5C5670608291F05C258FBC1E1C8 +:201B6000C9780F0F0F47E6F04F78E6034721003C09C978C6F0D87AC6D1D87BC68CD8C5D586 +:201B8000E5CD61FB7B075F3E4082570602D50E10F33E02D36A1A2424772525B6123E03D395 +:201BA0006A1A2424772525B61223130DC291FB3AFEDFD36AFBD11405C28DFBC34EFB78C672 +:201BC000F0D87AC6D1D87BC68CD8C5D5E57B076F3E408267E5CD61FB11000219EBE10602CA +:201BE000E50E10F33E02D36A1A773E03D36A1A7713230DC2E4FB3AFEDFD36AFBE12405C2D3 +:201C0000E0FBC34EFBCDBAF8D8C5D5E5CD34FCCDBAF8DA30FC7891D434FC0504CD84F8CD59 +:201C200034FCC541CDF0F8C1CD34FC4FB8C21BFCE1D1C1C9EB78414FC9CD8AFCD8C5E5E569 +:201C40007CC64067474DCD7AFCDA6CFCF33E02D36A0A772B773E03D36A0A7723777C2505B0 +:201C6000D64092C24DFC3AFEDFD36AFBE17D2D93C23FFCE1CD7AFCA7C1C97D2EF59307D8E0 +:201C80003C83D8C60AD8D60A6FC97AC6D1D87BC60BD87CC6D0D87DC60AD87C92D87D93C912 +:201CA000CD8AFCD8C5E5E57CC640474DCDDDFCDACFFC7CC64067D53E0232D6DFCDEAFC3E33 +:201CC0000332D6DFCDEAFCD17D2D0D93C2B6FCE17C2592C2A6FCE1CDDDFCA7C1C97C920793 +:201CE0003C82673E2F94D0262FC9F3E53AD6DFD36A0A2100001608292907D200FD2C2C2CD7 +:201D000015C2F7FC555C3AFEDFD36AE13AD6DFD36A7325723AFEDFD36A24FBC9F5E604CAF8 +:201D200029FDF13A20DFC32AFDF132DCDFC9E52139FEC339FDE52132FEC5010020C342FD6E +:201D4000E5C53E8832FFDF32FADF7932FDDF3E25D3793EA6D36378D3623E10D3633E76D3F0 +:201D6000633EC33204DF22FBDF2171FD2205DFC1E1F5C5D5E53AFADFA7C294FD3C32FADFEF +:201D8000D3603E25D3793EFDD3753E61D374FBE1D1C1F1C9AF32FADF2AFBDF7EA7C2C6FD68 +:201DA0003EFFD375AF32FFDF3E76D3633E96D3633E0DD3623EFFD3753E20D3742100E0221E +:201DC00005DFFBC38FFDF2D0FD32FFDF23C39BFDE6700F0F0F0F4F3AFDDF81E6074F7E2333 +:201DE00022FBDFE60FFE0DF20EFE3D075F1600211AFE1956235E0DCA04FEA77A1F577B1FFD +:201E00005FC3F6FD7BD3617AD3613E05D3793AFFDFE67F073DD360C386FDEEEAE178D4E0A2 +:201E2000C8D6BDA0B2FBA8EB9F7096888E0C86017DE1905B9051A06500885B003EAFD31A2D +:201E40003EFFD31B07D31B07D31B07D31B07D31B07D31B07D31B07D31BC93EFFD31BD31BC2 +:201E6000D31BD31BD31BD31BD31BD31BDB1BC92100001100004FCD40FE79CD42FE7ACD4274 +:201E8000FE7BCD42FE7CCD42FE7DCD42FE3E95CD42FE11808021204ECD5AFE4F92BB79D01F +:201EA0002B7CB5C298FED601C9C5D5E511FF00CD95FEE1D1C1C9CD3DFE0610CD40FE05C2B3 +:201EC000BBFECD3CFE3E40CD6FFEFE01C03E77CD6FFEE6FEC03E69CD6FFEFE01CACDFEB70C +:201EE000C9CDA9FED8E5EB295C65AF576F3E51CD75FEE1D80600E51101FFCD95FEE1FEFEDD +:201F0000C0CD5AFE7723CD5AFE772305C201FFC93E02D36A3A8028E604C0AFD36ACD24FF0E +:201F2000DA3DFEE9CDB6FE37C01100002100C0CDE1FED8CD42FFD02AC6C1EB2100C0CDE1AC +:201F4000FED8CDBAFF37C02A16C0EB2A0EC03A10C0193DC251FFEB2A1CC01922F0C1EB2AE7 +:201F600011C04D4429292929E579E60FC5CC9EFFD5E5060B11CBFF1ABEC2AAFF132305C2F4 +:201F800077FFC1C1C1110F00195E23561B1B2AF0C13A0DC0193DC294FFD15A5719EBD52139 +:201FA00000C2E5CDE1FEE1D113C9E111200019D1C10B78B1C269FFC137C92136C07E23FEAE +:201FC00046C07E23FE41C07EFE54C9424F4F5420202020524F4D0000000000000000000020 +:201FE00000000000000000001B592C2C2DDEE8D8D1DAD020D7D0D3E0E3D7DAD82D00FFF6C7 +:00000001FF diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/SDRAM_Controller.v b/Computer_MiST/Bashkiria2M_MiST/rtl/SDRAM_Controller.v index 324daca6..74b48929 100644 --- a/Computer_MiST/Bashkiria2M_MiST/rtl/SDRAM_Controller.v +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/SDRAM_Controller.v @@ -7,7 +7,7 @@ module SDRAM_Controller( input clk100, // Clock 100MHz input reset, // System reset inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits - output reg[12:0] DRAM_ADDR, // SDRAM Address bus 12 Bits + output reg[11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits output reg DRAM_LDQM, // SDRAM Low-byte Data Mask output reg DRAM_UDQM, // SDRAM High-byte Data Mask output reg DRAM_WE_N, // SDRAM Write Enable @@ -17,7 +17,7 @@ module SDRAM_Controller( output DRAM_BA_0, // SDRAM Bank Address 0 output DRAM_BA_1, // SDRAM Bank Address 0 input [21:0] iaddr, - input [15:0] idata, + input [7:0] idata, input rd, input we_n, output reg [15:0] odata, @@ -50,17 +50,17 @@ reg[15:0] data; reg exrd,exwen; reg ubn,lbn,rdvid; -assign DRAM_DQ[7:0] = (state==ST_WRITE0) ? data[7:0] : 8'bZZZZZZZZ; -assign DRAM_DQ[15:8] = (state == ST_WRITE0) ? data[7:0] : 8'bZZZZZZZZ; +assign DRAM_DQ[7:0] = (state==ST_WRITE0) ? data : 8'bZZZZZZZZ; +assign DRAM_DQ[15:8] = (state == ST_WRITE0) ? data : 8'bZZZZZZZZ; assign DRAM_CS_N = 1'b0; assign DRAM_BA_0 = addr[20]; assign DRAM_BA_1 = addr[21]; always @(*) begin case (state) - ST_RESET0: DRAM_ADDR = 13'b100000; - ST_RAS0: DRAM_ADDR = addr[20:8]; - default: DRAM_ADDR = {5'b00100,addr[7:0]}; + ST_RESET0: DRAM_ADDR = 12'b100000; + ST_RAS0: DRAM_ADDR = addr[19:8]; + default: DRAM_ADDR = {4'b0100,addr[7:0]}; endcase case (state) ST_RESET0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b000; diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_mist.sv b/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_mist.sv index ccb9b603..948f976c 100644 --- a/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_mist.sv +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_mist.sv @@ -1,5 +1,6 @@ -module b2m_mist( - input CLOCK_27, +module b2m_mist +( + input CLOCK_27, output LED, output SPI_DO, input SPI_DI, @@ -8,17 +9,17 @@ module b2m_mist( input SPI_SS3, input SPI_SS4, input CONF_DATA0, - inout [15:0] SDRAM_DQ, - output [12:0] SDRAM_A, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE, + inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits + output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits + output SDRAM_DQML, // SDRAM Low-byte Data Mask + output SDRAM_DQMH, // SDRAM High-byte Data Mask + output SDRAM_nWE, // SDRAM Write Enable + output SDRAM_nCAS, // SDRAM Column Address Strobe + output SDRAM_nRAS, // SDRAM Row Address Strobe + output SDRAM_nCS, // SDRAM Chip Select + output [1:0] SDRAM_BA, // SDRAM Bank Address + output SDRAM_CLK, // SDRAM Clock + output SDRAM_CKE, // SDRAM Clock Enable output AUDIO_L, output AUDIO_R, output VGA_HS, @@ -32,28 +33,34 @@ module b2m_mist( `include "rtl\build_id.v" localparam CONF_STR = { - "Bashkiria 2M;;", + "B2M;;", "O2,Turbo ,ON,OFF;", "O3,Color Mode ,COLOR,B/W;", "O4,Video Mode ,PAL,NTSC;", - "O56,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", + "O56,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", "T7,Reset;", "V,v1.00.",`BUILD_DATE }; assign LED = 1'b1; -assign AUDIO_R = AUDIO_L; - wire clk_sys; +wire clk12p5; +wire clk100; wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; -wire scandoublerD; -wire ypbpr; -wire ps2_kbd_clk; -wire ps2_kbd_data; -wire [15:0] audio; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [15:0] audio; +//assign LED = 1; + +wire hblank, vblank; +wire ce_vid; wire hs, vs; wire [3:0] r,g,b; @@ -61,11 +68,102 @@ wire [3:0] r,g,b; pll pll( .inclk0(CLOCK_27), .c0(clk_sys),//50 + .c1(clk12p5) ); + +video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(0)) video_mixer( + .clk_sys(clk_sys), + .ce_pix(clk12p5), + .ce_pix_actual(clk12p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r[1:0]}), + .G({g,g[1:0]}), + .B({b,b[1:0]}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(1),//scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[6:5] == 3, status[6:5] == 2}), + .hq2x(status[6:5]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) + ); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ), + .sd_lba (sd_lba ), + .sd_rd (sd_rd ), + .sd_wr (sd_wr ), + .sd_ack (sd_ack ), + .sd_conf (sd_conf ), + .sd_sdhc (sd_sdhc ), + .sd_buff_dout (sd_data_out ), + .sd_buff_din (sd_data_in ), + .sd_dout_strobe (sd_data_in_strobe), + .sd_din_strobe (sd_data_out_strobe) + ); + + +wire [31:0] sd_lba; +wire sd_rd; +wire sd_wr; +wire sd_ack; +wire sd_conf; +wire sd_sdhc; +wire allow_sdhc; +wire [7:0] sd_data_in; +wire sd_data_in_strobe; +wire [7:0] sd_data_out; +wire sd_data_out_strobe; +wire sd_cs; +wire sd_sck; +wire sd_sdi; +wire sd_sdo; + +sd_card sd_card( + .io_lba (sd_lba), + .io_rd (sd_rd), + .io_wr (sd_wr), + .io_ack (sd_ack), + .io_conf (sd_conf), + .io_sdhc (sd_sdhc), + .io_din (sd_data_out), + .io_din_strobe (sd_data_in_strobe), + .io_dout (sd_data_in), + .io_dout_strobe(sd_data_out_strobe), + .allow_sdhc (allow_sdhc), + .sd_cs (sd_cs), + .sd_sck (sd_sck), + .sd_sdi (sd_sdi), + .sd_sdo (sd_sdo) + ); + b2m_top b2m_top( .clk50mhz(clk_sys), - .res(~(status[0] | status[7] | buttons[1])), + .res(~(status[0] || status[7] || buttons[1])), .color_mode(~status[3] ), .video_mode(status[4] ), .turbo(~status[2] ), @@ -94,95 +192,14 @@ b2m_top b2m_top( .SD_CMD(sd_sdi), .SD_CLK(sd_sck) ); - -mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video( - .clk_sys ( clk_sys ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS3 ( SPI_SS3 ), - .SPI_DI ( SPI_DI ), - .R ( r), - .G ( g), - .B ( b), - .HSync ( hs ), - .VSync ( vs ), - .VGA_R ( VGA_R ), - .VGA_G ( VGA_G ), - .VGA_B ( VGA_B ), - .VGA_VS ( VGA_VS ), - .VGA_HS ( VGA_HS ), - .scandoubler_disable( 1'b1),//scandoublerD ), - .scanlines ( status[6:5] ), - .ce_divider (1), - .ypbpr ( ypbpr ) - ); - -user_io #(.STRLEN(($size(CONF_STR)>>3))) user_io( - .clk_sys (clk_sys ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_kbd_clk (ps2_kbd_clk ), - .ps2_kbd_data (ps2_kbd_data ), - .status (status ), - .sd_lba (sd_lba ), - .sd_rd (sd_rd ), - .sd_wr (sd_wr ), - .sd_ack (sd_ack ), - .sd_conf (sd_conf ), - .sd_sdhc (sd_sdhc ), - .sd_dout (sd_data_out ), - .sd_din (sd_data_in ), - .sd_dout_strobe (sd_data_in_strobe), - .sd_din_strobe (sd_data_out_strobe) - ); - -dac #( - .C_bits(16)) -dac( + +dac dac( .clk_i(clk_sys), .res_n_i(1), .dac_i(audio), .dac_o(AUDIO_L) - ); - -wire [31:0] sd_lba; -wire sd_rd; -wire sd_wr; -wire sd_ack; -wire sd_conf; -wire sd_sdhc; -wire allow_sdhc; -wire [7:0] sd_data_in; -wire sd_data_in_strobe; -wire [7:0] sd_data_out; -wire sd_data_out_strobe; -wire sd_cs; -wire sd_sck; -wire sd_sdi; -wire sd_sdo; - -sd_card sd_card( - .io_lba (sd_lba), - .io_rd (sd_rd), - .io_wr (sd_wr), - .io_ack (sd_ack), - .io_conf (sd_conf), - .io_sdhc (sd_sdhc), - .io_din (sd_data_out), - .io_din_strobe (sd_data_in_strobe), - .io_dout (sd_data_in), - .io_dout_strobe(sd_data_out_strobe), - .allow_sdhc (allow_sdhc), - .sd_cs (sd_cs), - .sd_sck (sd_sck), - .sd_sdi (sd_sdi), - .sd_sdo (sd_sdo) - ); + ); + +assign AUDIO_R = AUDIO_L; endmodule diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_top.v b/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_top.v index 489ec818..53274274 100644 --- a/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_top.v +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/b2m_top.v @@ -107,10 +107,11 @@ reg[7:0] mem_o; always @(negedge memvidbusy) vid_data <= dramout; always @(negedge memcpubusy) mem_o <= dramout[7:0]; + bios rom( - .addr(addrbus[12:0]), - .clk(clk50mhz), - .data(rom_o) + .address(addrbus[12:0]), + .clock(clk50mhz), + .q(rom_o) ); //////////////////// CPU //////////////////// @@ -160,7 +161,7 @@ wire cpu_ce = cpu_ce2; always @(posedge clk50mhz) begin vidce2<=vidce; - cpu_cnt <= cpu_cnt + 1'b1; + cpu_cnt <= cpu_cnt + 1; if (cpu_sync) sysctl <= cpu_o; if (addrbus[0]&~sio_we_n) sound_on <= ~cpu_o[5]; if(turbo==1 && {vidce2,vidce}==2'b01 && cpu_cnt>3){cpu_cnt,cpu_ce2}<={10'b0,~memcpubusy&~memvidbusy}; @@ -332,7 +333,7 @@ always @(posedge clk50mhz) begin if (line6bit > 32) tapein <= 1'b1; end*/ - +//I2C_AV_Config sndcfg(.iCLK(clk50mhz), .iRST_N(reset_n), .I2C_SCLK(I2C_SCLK), .I2C_SDAT(I2C_SDAT)); //////////////////// SD CARD //////////////////// reg sdcs; diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/bios.v b/Computer_MiST/Bashkiria2M_MiST/rtl/bios.v new file mode 100644 index 00000000..365c70d0 --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/bios.v @@ -0,0 +1,159 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: bios.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module bios ( + address, + clock, + q); + + input [12:0] address; + input clock; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({8{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./rtl/BIOS4.HEX", + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./rtl/BIOS4.HEX" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/BIOS4.HEX" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL bios.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL bios_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/bios.vhd b/Computer_MiST/Bashkiria2M_MiST/rtl/bios.vhd deleted file mode 100644 index 18ca1d0d..00000000 --- a/Computer_MiST/Bashkiria2M_MiST/rtl/bios.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity bios is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of bios is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"C3",X"13",X"E0",X"C3",X"55",X"E8",X"C3",X"CB",X"F1",X"C3",X"72",X"E2",X"C3",X"CC",X"E2",X"C3", - X"F5",X"F1",X"32",X"F3",X"3E",X"AA",X"D3",X"10",X"D3",X"11",X"D3",X"12",X"D3",X"13",X"3E",X"80", - X"D3",X"6B",X"3E",X"30",X"D3",X"63",X"3E",X"76",X"D3",X"63",X"3E",X"94",X"D3",X"63",X"3E",X"0D", - X"D3",X"62",X"3E",X"90",X"D3",X"47",X"3E",X"F0",X"D3",X"46",X"3E",X"15",X"D3",X"79",X"3E",X"40", - X"D3",X"79",X"3E",X"FE",X"D3",X"79",X"3E",X"16",X"D3",X"74",X"3E",X"DF",X"D3",X"75",X"3E",X"FF", - X"D3",X"75",X"AF",X"D3",X"6A",X"32",X"FE",X"DF",X"32",X"FF",X"DF",X"3E",X"C3",X"32",X"04",X"DF", - X"21",X"13",X"E0",X"22",X"05",X"DF",X"FB",X"01",X"00",X"60",X"3E",X"E9",X"D3",X"61",X"3E",X"07", - X"D3",X"61",X"3E",X"15",X"D3",X"79",X"0B",X"79",X"B0",X"C2",X"76",X"E0",X"3E",X"25",X"D3",X"79", - X"01",X"FF",X"FF",X"0B",X"79",X"B0",X"C2",X"83",X"E0",X"31",X"00",X"DF",X"CD",X"66",X"EE",X"01", - X"20",X"DF",X"21",X"26",X"DF",X"CD",X"55",X"F0",X"7A",X"FE",X"DC",X"CC",X"3C",X"F8",X"3A",X"FF", - X"DF",X"B7",X"C2",X"9E",X"E0",X"31",X"00",X"DF",X"CD",X"10",X"FF",X"3E",X"25",X"D3",X"79",X"3E", - X"FF",X"D3",X"75",X"3E",X"20",X"D3",X"74",X"CD",X"04",X"E9",X"21",X"19",X"E1",X"CD",X"C2",X"E3", - X"21",X"25",X"E1",X"CD",X"C2",X"E3",X"31",X"00",X"DF",X"21",X"8C",X"E1",X"CD",X"C2",X"E3",X"CD", - X"72",X"E2",X"21",X"C6",X"E0",X"E5",X"FE",X"3F",X"CA",X"AB",X"E0",X"FE",X"0D",X"C8",X"FE",X"53", - X"CA",X"05",X"E2",X"FE",X"52",X"CA",X"53",X"E2",X"FE",X"57",X"CA",X"5A",X"E2",X"FE",X"4C",X"CA", - X"6A",X"E3",X"FE",X"47",X"CA",X"41",X"E2",X"FE",X"59",X"CA",X"53",X"E3",X"FE",X"55",X"CA",X"60", - X"E3",X"CD",X"07",X"E1",X"C3",X"C6",X"E0",X"21",X"0D",X"E1",X"C3",X"C2",X"E3",X"0D",X"0A",X"2D", - X"DE",X"E8",X"D8",X"D1",X"DA",X"D0",X"2D",X"0D",X"00",X"1B",X"42",X"B7",X"B0",X"B3",X"C0",X"C3", - X"B7",X"C7",X"B8",X"BA",X"00",X"C4",X"E3",X"DD",X"DA",X"E6",X"D8",X"D8",X"3A",X"0D",X"0A",X"53", - X"2D",X"E3",X"E1",X"E2",X"D0",X"DD",X"DE",X"D2",X"DA",X"D0",X"20",X"EF",X"E7",X"D5",X"D9",X"DA", - X"D8",X"0D",X"0A",X"4C",X"2D",X"D7",X"D0",X"D3",X"E0",X"E3",X"D7",X"DA",X"D0",X"20",X"D8",X"D7", - X"20",X"BF",X"B7",X"C3",X"0D",X"0A",X"52",X"2D",X"E7",X"E2",X"D5",X"DD",X"D8",X"D5",X"20",X"E1", - X"20",X"BC",X"BB",X"0D",X"0A",X"57",X"2D",X"D7",X"D0",X"DF",X"D8",X"E1",X"EC",X"20",X"DD",X"D0", - X"20",X"BC",X"BB",X"0D",X"0A",X"47",X"2D",X"D2",X"EB",X"DF",X"DE",X"DB",X"DD",X"D8",X"E2",X"EC", - X"20",X"DF",X"E0",X"DE",X"D3",X"E0",X"D0",X"DC",X"DC",X"E3",X"0D",X"00",X"0A",X"3E",X"00",X"0D", - X"0A",X"BF",X"DE",X"D4",X"D3",X"DE",X"E2",X"DE",X"D2",X"EC",X"E2",X"D5",X"20",X"DC",X"D0",X"D3", - X"DD",X"D8",X"E2",X"DE",X"E4",X"DE",X"DD",X"20",X"D4",X"DB",X"EF",X"20",X"00",X"B7",X"B0",X"BF", - X"B8",X"C1",X"B8",X"00",X"C7",X"C2",X"B5",X"BD",X"B8",X"CF",X"00",X"0D",X"0A",X"D8",X"20",X"DD", - X"D0",X"D6",X"DC",X"D8",X"E2",X"D5",X"20",X"3C",X"B2",X"BA",X"3E",X"00",X"0A",X"2A",X"B7",X"B0", - X"BF",X"B8",X"C1",X"CC",X"2A",X"0D",X"00",X"0A",X"2A",X"C7",X"C2",X"B5",X"BD",X"B8",X"B5",X"2A", - X"0D",X"00",X"0A",X"2A",X"DE",X"E8",X"D8",X"D1",X"DA",X"D0",X"20",X"BA",X"C1",X"2A",X"0D",X"00", - X"0A",X"D2",X"EB",X"DA",X"DB",X"EE",X"E7",X"D8",X"20",X"DC",X"D0",X"D3",X"DD",X"D8",X"E2",X"DE", - X"E4",X"DE",X"DD",X"0D",X"00",X"CD",X"CC",X"E2",X"3D",X"C2",X"01",X"E1",X"2A",X"1A",X"DF",X"CD", - X"41",X"E3",X"E5",X"CD",X"46",X"E3",X"CD",X"4E",X"E3",X"E1",X"7E",X"E5",X"CD",X"D5",X"E3",X"CD", - X"4E",X"E3",X"CD",X"72",X"E2",X"E1",X"FE",X"0D",X"CA",X"3D",X"E2",X"FE",X"2E",X"C8",X"E5",X"CD", - X"CF",X"E2",X"2A",X"1A",X"DF",X"7C",X"B7",X"C2",X"01",X"E1",X"7D",X"E1",X"77",X"23",X"C3",X"0F", - X"E2",X"CD",X"CC",X"E2",X"3D",X"C2",X"01",X"E1",X"31",X"00",X"DF",X"21",X"C6",X"E0",X"E5",X"2A", - X"1A",X"DF",X"E9",X"CD",X"61",X"E2",X"CD",X"E2",X"EF",X"C9",X"CD",X"61",X"E2",X"CD",X"A8",X"EF", - X"C9",X"CD",X"CC",X"E2",X"FE",X"02",X"C2",X"01",X"E1",X"2A",X"1A",X"DF",X"44",X"4D",X"2A",X"1C", - X"DF",X"C9",X"11",X"DA",X"DF",X"06",X"00",X"CD",X"6F",X"E4",X"FE",X"0D",X"CA",X"89",X"E2",X"FE", - X"7F",X"CA",X"9D",X"E2",X"FE",X"20",X"DA",X"77",X"E2",X"CD",X"CE",X"E3",X"12",X"13",X"FE",X"0D", - X"CA",X"AC",X"E2",X"04",X"78",X"FE",X"20",X"CA",X"AC",X"E2",X"C3",X"77",X"E2",X"AF",X"B0",X"CA", - X"77",X"E2",X"05",X"1B",X"3E",X"7F",X"CD",X"CE",X"E3",X"C3",X"77",X"E2",X"21",X"DA",X"DF",X"22", - X"17",X"DF",X"78",X"32",X"16",X"DF",X"E5",X"21",X"16",X"DF",X"7E",X"B7",X"3E",X"0D",X"CA",X"CA", - X"E2",X"35",X"2A",X"17",X"DF",X"7E",X"23",X"22",X"17",X"DF",X"E1",X"C9",X"CD",X"B6",X"E2",X"21", - X"19",X"DF",X"36",X"00",X"23",X"FE",X"0D",X"CA",X"01",X"E3",X"CD",X"08",X"E3",X"CD",X"20",X"E3", - X"FE",X"0D",X"CA",X"01",X"E3",X"CD",X"B6",X"E2",X"CD",X"08",X"E3",X"CD",X"20",X"E3",X"FE",X"0D", - X"CA",X"01",X"E3",X"CD",X"B6",X"E2",X"CD",X"08",X"E3",X"CD",X"20",X"E3",X"FE",X"0D",X"C2",X"01", - X"E1",X"11",X"19",X"DF",X"1A",X"13",X"B7",X"C9",X"EB",X"21",X"00",X"00",X"CD",X"2B",X"E3",X"29", - X"29",X"29",X"29",X"B5",X"6F",X"CD",X"B6",X"E2",X"CD",X"38",X"E3",X"C2",X"0C",X"E3",X"EB",X"C9", - X"73",X"23",X"72",X"23",X"E5",X"21",X"19",X"DF",X"34",X"E1",X"C9",X"D6",X"30",X"FE",X"0A",X"D8", - X"C6",X"F9",X"FE",X"10",X"D8",X"C3",X"01",X"E1",X"FE",X"0D",X"C8",X"FE",X"2C",X"C8",X"FE",X"20", - X"C9",X"3E",X"0A",X"C3",X"CE",X"E3",X"7C",X"CD",X"D5",X"E3",X"7D",X"C3",X"D5",X"E3",X"3E",X"20", - X"C3",X"CE",X"E3",X"CD",X"61",X"E2",X"CD",X"44",X"E4",X"CD",X"F1",X"E3",X"C2",X"07",X"E1",X"C9", - X"CD",X"61",X"E2",X"CD",X"44",X"E4",X"CD",X"1C",X"E4",X"C9",X"CD",X"CC",X"E2",X"FE",X"03",X"C2", - X"01",X"E1",X"2A",X"1A",X"DF",X"44",X"4D",X"2A",X"1C",X"DF",X"E5",X"2A",X"1E",X"DF",X"54",X"5D", - X"E1",X"3E",X"90",X"D3",X"47",X"7B",X"D3",X"45",X"7A",X"F6",X"C0",X"D3",X"46",X"7A",X"E6",X"C0", - X"C2",X"A1",X"E3",X"3E",X"0C",X"D3",X"47",X"DB",X"44",X"F5",X"3E",X"0D",X"D3",X"47",X"C3",X"AC", - X"E3",X"3E",X"0E",X"D3",X"47",X"DB",X"44",X"F5",X"3E",X"0F",X"D3",X"47",X"F1",X"02",X"13",X"CD", - X"B6",X"E3",X"DA",X"85",X"E3",X"C9",X"78",X"94",X"DA",X"BF",X"E3",X"C0",X"79",X"95",X"D0",X"03", - X"37",X"C9",X"F5",X"7E",X"CD",X"CE",X"E3",X"23",X"B7",X"C2",X"C3",X"E3",X"F1",X"C9",X"C5",X"4F", - X"CD",X"D7",X"E7",X"C1",X"C9",X"F5",X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",X"CD",X"E2",X"E3",X"F1", - X"E6",X"0F",X"FE",X"0A",X"D2",X"EC",X"E3",X"C6",X"30",X"C3",X"CE",X"E3",X"C6",X"37",X"C3",X"CE", - X"E3",X"C5",X"CD",X"65",X"E4",X"C0",X"DB",X"78",X"B7",X"C0",X"CD",X"65",X"E4",X"C0",X"DB",X"78", - X"FE",X"FF",X"C0",X"CD",X"65",X"E4",X"C0",X"DB",X"78",X"02",X"CD",X"B6",X"E3",X"DA",X"03",X"E4", - X"CD",X"65",X"E4",X"C0",X"DB",X"78",X"C1",X"CD",X"55",X"F0",X"BA",X"C9",X"C5",X"CD",X"55",X"F0", - X"C1",X"D5",X"CD",X"5D",X"E4",X"AF",X"D3",X"78",X"CD",X"5D",X"E4",X"3E",X"FF",X"D3",X"78",X"CD", - X"5D",X"E4",X"0A",X"D3",X"78",X"CD",X"B6",X"E3",X"DA",X"2F",X"E4",X"CD",X"5D",X"E4",X"DB",X"78", - X"F1",X"D3",X"78",X"C9",X"3E",X"96",X"D3",X"63",X"3E",X"07",X"D3",X"62",X"3E",X"15",X"D3",X"79", - X"3E",X"40",X"D3",X"79",X"3E",X"FE",X"D3",X"79",X"3E",X"27",X"D3",X"79",X"C9",X"DB",X"79",X"E6", - X"05",X"CA",X"5D",X"E4",X"C9",X"DB",X"79",X"E6",X"3A",X"CA",X"65",X"E4",X"FE",X"02",X"C9",X"C5", - X"D5",X"3E",X"FF",X"32",X"D7",X"DF",X"CD",X"AF",X"E4",X"FE",X"FF",X"CA",X"76",X"E4",X"4F",X"3A", - X"45",X"DF",X"B7",X"CA",X"9D",X"E4",X"11",X"00",X"08",X"CD",X"FC",X"E6",X"CA",X"96",X"E4",X"1B", - X"7B",X"B2",X"C2",X"89",X"E4",X"2F",X"32",X"45",X"DF",X"79",X"D1",X"C1",X"C9",X"11",X"00",X"20", - X"C3",X"89",X"E4",X"AF",X"32",X"D7",X"DF",X"CD",X"AF",X"E4",X"FE",X"FF",X"C0",X"2F",X"C9",X"C5", - X"D5",X"E5",X"3A",X"25",X"DF",X"B7",X"CA",X"CB",X"E4",X"2A",X"6E",X"DF",X"7E",X"32",X"25",X"DF", - X"B7",X"CA",X"AC",X"E6",X"23",X"22",X"6E",X"DF",X"C3",X"B4",X"E6",X"3E",X"04",X"F5",X"06",X"58", - X"16",X"00",X"1E",X"7F",X"21",X"01",X"28",X"F3",X"3E",X"02",X"D3",X"6A",X"4E",X"3A",X"FE",X"DF", - X"D3",X"6A",X"FB",X"3E",X"01",X"F5",X"A1",X"C2",X"09",X"E5",X"14",X"7A",X"B8",X"FA",X"F5",X"E4", - X"16",X"00",X"C3",X"13",X"E5",X"F1",X"07",X"D2",X"E5",X"E4",X"7D",X"07",X"D2",X"05",X"E5",X"21", - X"01",X"29",X"C3",X"D7",X"E4",X"6F",X"C3",X"D7",X"E4",X"7B",X"FE",X"7F",X"C2",X"13",X"E5",X"5A", - X"C3",X"EA",X"E4",X"F1",X"3A",X"D6",X"DF",X"BA",X"7A",X"32",X"D6",X"DF",X"CA",X"23",X"E5",X"F1", - X"C3",X"CB",X"E4",X"F1",X"3D",X"C2",X"CD",X"E4",X"7B",X"FE",X"7F",X"CA",X"B2",X"E6",X"7A",X"B7", - X"CA",X"63",X"E5",X"FE",X"38",X"FA",X"B2",X"E6",X"FE",X"40",X"7B",X"FA",X"4F",X"E5",X"FE",X"38", - X"FA",X"B2",X"E6",X"FE",X"40",X"F2",X"B2",X"E6",X"CD",X"C7",X"E6",X"5A",X"C3",X"30",X"E6",X"FE", - X"38",X"FA",X"5C",X"E5",X"FE",X"40",X"F2",X"B2",X"E6",X"C3",X"8B",X"E6",X"7A",X"CD",X"C7",X"E6", - X"C3",X"7A",X"E5",X"06",X"00",X"7B",X"FE",X"38",X"FA",X"7A",X"E5",X"FE",X"40",X"F2",X"30",X"E6", - X"FE",X"3C",X"C2",X"B2",X"E6",X"3E",X"1B",X"C3",X"B4",X"E6",X"16",X"00",X"3A",X"26",X"DF",X"4F", - X"A8",X"E6",X"04",X"CA",X"8C",X"E5",X"2A",X"27",X"DF",X"C3",X"DF",X"E5",X"21",X"87",X"E7",X"78", - X"00",X"E6",X"10",X"C2",X"DF",X"E5",X"7B",X"FE",X"20",X"D2",X"EA",X"E5",X"21",X"1F",X"E7",X"79", - X"A8",X"06",X"00",X"E6",X"03",X"CA",X"D9",X"E5",X"FE",X"01",X"C2",X"CF",X"E5",X"7B",X"FE",X"05", - X"CA",X"D9",X"E5",X"FE",X"07",X"CA",X"D9",X"E5",X"FE",X"0F",X"CA",X"D9",X"E5",X"FE",X"11",X"CA", - X"D9",X"E5",X"FE",X"18",X"CA",X"D9",X"E5",X"FE",X"1B",X"CA",X"D9",X"E5",X"C3",X"D7",X"E5",X"21", - X"67",X"E7",X"FE",X"02",X"CA",X"D9",X"E5",X"06",X"20",X"19",X"7E",X"80",X"C3",X"B4",X"E6",X"7B", - X"06",X"00",X"FE",X"30",X"D2",X"B2",X"E6",X"C3",X"D9",X"E5",X"D6",X"20",X"FE",X"10",X"D2",X"20", - X"E6",X"5F",X"FE",X"0B",X"C2",X"0B",X"E6",X"79",X"A8",X"E6",X"02",X"CA",X"0B",X"E6",X"79",X"A8", - X"E6",X"01",X"3E",X"F1",X"C2",X"B4",X"E6",X"3D",X"C3",X"B4",X"E6",X"79",X"A8",X"06",X"00",X"E6", - X"01",X"C2",X"1A",X"E6",X"21",X"3F",X"E7",X"C3",X"D9",X"E5",X"21",X"57",X"E7",X"C3",X"D9",X"E5", - X"D6",X"10",X"FE",X"08",X"D2",X"B2",X"E6",X"5F",X"21",X"4F",X"E7",X"06",X"00",X"C3",X"D9",X"E5", - X"3A",X"26",X"DF",X"4F",X"7B",X"16",X"00",X"D6",X"40",X"FE",X"10",X"DA",X"5C",X"E6",X"D6",X"18", - X"2F",X"3C",X"5F",X"79",X"A8",X"E6",X"01",X"C2",X"4C",X"E6",X"16",X"05",X"7B",X"82",X"11",X"0A", - X"00",X"21",X"68",X"DF",X"19",X"3D",X"C2",X"54",X"E6",X"C3",X"BC",X"E4",X"5F",X"FE",X"08",X"CA", - X"6C",X"E6",X"FE",X"0A",X"CA",X"6C",X"E6",X"FE",X"0B",X"C2",X"76",X"E6",X"79",X"A8",X"E6",X"01", - X"C2",X"83",X"E6",X"C3",X"7D",X"E6",X"79",X"A8",X"E6",X"08",X"C2",X"83",X"E6",X"21",X"B7",X"E7", - X"C3",X"86",X"E6",X"21",X"C7",X"E7",X"06",X"00",X"C3",X"D9",X"E5",X"3A",X"D7",X"DF",X"B7",X"CA", - X"B2",X"E6",X"7A",X"FE",X"39",X"7B",X"CA",X"9F",X"E6",X"FE",X"39",X"7A",X"C2",X"B2",X"E6",X"CD", - X"C7",X"E6",X"3A",X"26",X"DF",X"A8",X"32",X"26",X"DF",X"CD",X"7F",X"EB",X"CD",X"FC",X"E6",X"C2", - X"AC",X"E6",X"3E",X"FF",X"4F",X"FE",X"FF",X"CA",X"C3",X"E6",X"3A",X"26",X"DF",X"E6",X"10",X"C4", - X"39",X"F8",X"79",X"E1",X"D1",X"C1",X"C9",X"06",X"00",X"FE",X"38",X"CA",X"D3",X"E6",X"FE",X"3F", - X"C2",X"D6",X"E6",X"06",X"01",X"C9",X"FE",X"3E",X"C2",X"DE",X"E6",X"06",X"02",X"C9",X"FE",X"3D", - X"C2",X"E6",X"E6",X"06",X"04",X"C9",X"FE",X"3B",X"C2",X"EE",X"E6",X"06",X"08",X"C9",X"FE",X"3A", - X"C2",X"F6",X"E6",X"06",X"10",X"C9",X"FE",X"3C",X"C0",X"06",X"20",X"C9",X"F3",X"3E",X"02",X"D3", - X"6A",X"3A",X"7F",X"28",X"B7",X"C2",X"14",X"E7",X"3A",X"80",X"28",X"E6",X"12",X"C2",X"14",X"E7", - X"3A",X"FF",X"29",X"B7",X"3A",X"FE",X"DF",X"D3",X"6A",X"FB",X"3E",X"00",X"C8",X"2F",X"C9",X"55", - X"41",X"54",X"4C",X"57",X"60",X"46",X"7E",X"4A",X"59",X"56",X"4B",X"52",X"51",X"42",X"7B",X"44", - X"5B",X"45",X"4E",X"43",X"48",X"5A",X"47",X"7D",X"58",X"4F",X"5D",X"49",X"50",X"53",X"4D",X"2A", - X"26",X"5E",X"25",X"24",X"23",X"40",X"5F",X"3C",X"27",X"2B",X"FF",X"21",X"7C",X"29",X"28",X"20", - X"09",X"7F",X"1C",X"1D",X"03",X"1F",X"0D",X"38",X"37",X"36",X"35",X"34",X"33",X"32",X"2D",X"2C", - X"3B",X"3D",X"FF",X"31",X"5C",X"30",X"39",X"B3",X"C4",X"B5",X"B4",X"C6",X"B1",X"B0",X"CE",X"BE", - X"BD",X"BC",X"BB",X"BA",X"B9",X"B8",X"C5",X"B2",X"B6",X"C3",X"C2",X"C1",X"C0",X"CF",X"BF",X"CA", - X"C7",X"C9",X"CD",X"C8",X"B7",X"CB",X"CC",X"15",X"01",X"14",X"0C",X"17",X"FF",X"06",X"FF",X"0A", - X"19",X"16",X"0B",X"12",X"11",X"02",X"FF",X"04",X"1B",X"05",X"0E",X"03",X"08",X"1A",X"07",X"FF", - X"18",X"0F",X"1D",X"09",X"10",X"13",X"0D",X"FF",X"FF",X"1E",X"FF",X"FF",X"FF",X"00",X"1F",X"FF", - X"FF",X"FF",X"FF",X"FF",X"1C",X"FF",X"FF",X"37",X"36",X"35",X"34",X"33",X"32",X"31",X"30",X"3F", - X"2E",X"22",X"3E",X"FF",X"FF",X"39",X"38",X"0C",X"18",X"11",X"08",X"15",X"1A",X"16",X"17",X"2F", - X"10",X"3A",X"2E",X"FF",X"FF",X"14",X"19",X"F3",X"F5",X"C5",X"D5",X"E5",X"CD",X"55",X"E8",X"21", - X"4C",X"E8",X"E5",X"C3",X"35",X"DF",X"79",X"FE",X"1B",X"C2",X"F8",X"E7",X"3E",X"C3",X"32",X"35", - X"DF",X"21",X"64",X"EC",X"22",X"36",X"DF",X"C9",X"FE",X"08",X"C2",X"02",X"E8",X"3E",X"12",X"C3", - X"1B",X"E8",X"FE",X"0C",X"C2",X"0C",X"E8",X"3E",X"13",X"C3",X"1B",X"E8",X"FE",X"1B",X"D2",X"24", - X"E8",X"FE",X"11",X"CA",X"24",X"E8",X"FE",X"10",X"DA",X"24",X"E8",X"C6",X"31",X"4F",X"CD",X"EC", - X"E7",X"C3",X"35",X"DF",X"FE",X"7F",X"CA",X"7C",X"E8",X"FE",X"09",X"CA",X"85",X"E8",X"FE",X"0A", - X"CA",X"C2",X"E8",X"FE",X"0D",X"CA",X"EA",X"E8",X"FE",X"1F",X"CA",X"04",X"E9",X"FE",X"07",X"CA", - X"BE",X"E8",X"FE",X"20",X"D8",X"E1",X"CD",X"C9",X"E9",X"CD",X"9D",X"E9",X"CD",X"55",X"E8",X"E1", - X"D1",X"C1",X"F1",X"FB",X"C9",X"F5",X"2A",X"38",X"DF",X"CD",X"48",X"EA",X"E5",X"3E",X"02",X"CD", - X"6A",X"E8",X"E1",X"3E",X"03",X"CD",X"6A",X"E8",X"F1",X"C9",X"D3",X"6A",X"06",X"0A",X"7E",X"2F", - X"77",X"2C",X"05",X"C2",X"6E",X"E8",X"3A",X"FE",X"DF",X"D3",X"6A",X"C9",X"CD",X"B4",X"E9",X"3E", - X"20",X"CD",X"C9",X"E9",X"C9",X"3A",X"43",X"DF",X"47",X"3A",X"3E",X"DF",X"B8",X"CA",X"B7",X"E8", - X"47",X"AF",X"B8",X"CA",X"99",X"E8",X"D2",X"9E",X"E8",X"C6",X"08",X"C3",X"92",X"E8",X"47",X"00", - X"3A",X"43",X"DF",X"B8",X"DA",X"A8",X"E8",X"78",X"32",X"3E",X"DF",X"47",X"3A",X"3F",X"DF",X"4F", - X"CD",X"C3",X"ED",X"22",X"38",X"DF",X"C9",X"CD",X"EA",X"E8",X"CD",X"C2",X"E8",X"C9",X"CD",X"39", - X"F8",X"C9",X"3A",X"41",X"DF",X"47",X"3A",X"3F",X"DF",X"FE",X"17",X"CA",X"DF",X"E8",X"B8",X"C8", - X"3C",X"32",X"3F",X"DF",X"2A",X"38",X"DF",X"7D",X"C6",X"0A",X"6F",X"22",X"38",X"DF",X"C9",X"3A", - X"26",X"DF",X"E6",X"20",X"CA",X"EC",X"EA",X"C2",X"88",X"E9",X"3A",X"42",X"DF",X"47",X"3A",X"3E", - X"DF",X"B8",X"C8",X"2A",X"38",X"DF",X"90",X"25",X"3D",X"C2",X"F7",X"E8",X"78",X"32",X"3E",X"DF", - X"22",X"38",X"DF",X"C9",X"F5",X"C5",X"D5",X"E5",X"21",X"06",X"44",X"22",X"3A",X"DF",X"21",X"EC", - X"44",X"22",X"3C",X"DF",X"CD",X"6E",X"E9",X"CD",X"25",X"E9",X"CD",X"88",X"E9",X"CD",X"7F",X"EB", - X"E1",X"D1",X"C1",X"F1",X"C9",X"E5",X"F5",X"3E",X"FF",X"D3",X"10",X"D3",X"11",X"D3",X"12",X"D3", - X"13",X"21",X"00",X"40",X"E5",X"3E",X"02",X"CD",X"5D",X"E9",X"E1",X"3E",X"03",X"CD",X"5D",X"E9", - X"3A",X"21",X"DF",X"D3",X"10",X"3A",X"22",X"DF",X"D3",X"11",X"3A",X"23",X"DF",X"D3",X"12",X"3A", - X"24",X"DF",X"D3",X"13",X"AF",X"32",X"44",X"DF",X"D3",X"69",X"F1",X"E1",X"C9",X"D3",X"6A",X"36", - X"00",X"23",X"7C",X"FE",X"70",X"C2",X"5F",X"E9",X"3A",X"FE",X"DF",X"D3",X"6A",X"C9",X"AF",X"32", - X"42",X"DF",X"32",X"40",X"DF",X"3E",X"27",X"32",X"43",X"DF",X"3E",X"17",X"32",X"41",X"DF",X"3A", - X"26",X"DF",X"E6",X"1F",X"32",X"26",X"DF",X"C9",X"3A",X"42",X"DF",X"32",X"3E",X"DF",X"47",X"3A", - X"40",X"DF",X"32",X"3F",X"DF",X"4F",X"CD",X"C3",X"ED",X"22",X"38",X"DF",X"C9",X"3A",X"43",X"DF", - X"47",X"3A",X"3E",X"DF",X"B8",X"CA",X"B7",X"E8",X"3C",X"32",X"3E",X"DF",X"2A",X"38",X"DF",X"24", - X"22",X"38",X"DF",X"C9",X"3A",X"42",X"DF",X"47",X"3A",X"3E",X"DF",X"B8",X"C8",X"3D",X"32",X"3E", - X"DF",X"2A",X"38",X"DF",X"25",X"22",X"38",X"DF",X"C9",X"F5",X"AF",X"32",X"D9",X"DF",X"CD",X"48", - X"EA",X"11",X"D9",X"DF",X"06",X"01",X"CD",X"5A",X"EA",X"F1",X"CD",X"EB",X"E9",X"06",X"08",X"CD", - X"5A",X"EA",X"06",X"01",X"11",X"D9",X"DF",X"CD",X"5A",X"EA",X"C9",X"E5",X"21",X"32",X"EA",X"E5", - X"01",X"29",X"DF",X"FE",X"40",X"D2",X"FB",X"E9",X"D6",X"20",X"C9",X"03",X"03",X"FE",X"60",X"D2", - X"05",X"EA",X"D6",X"40",X"C9",X"03",X"03",X"FE",X"80",X"D2",X"0F",X"EA",X"D6",X"60",X"C9",X"03", - X"03",X"FE",X"B0",X"D2",X"19",X"EA",X"D6",X"80",X"C9",X"03",X"03",X"FE",X"D0",X"D2",X"23",X"EA", - X"D6",X"B0",X"C9",X"03",X"03",X"FE",X"F3",X"D2",X"2D",X"EA",X"D6",X"D0",X"C9",X"01",X"29",X"DF", - X"AF",X"E1",X"F5",X"0A",X"6F",X"03",X"0A",X"67",X"F1",X"11",X"08",X"00",X"B7",X"CA",X"45",X"EA", - X"19",X"3D",X"C3",X"3C",X"EA",X"EB",X"E1",X"C9",X"D5",X"F5",X"2A",X"38",X"DF",X"EB",X"2A",X"3A", - X"DF",X"7D",X"83",X"6F",X"7C",X"82",X"67",X"F1",X"D1",X"C9",X"1A",X"4F",X"D5",X"11",X"D5",X"EA", - X"D5",X"3A",X"20",X"DF",X"FE",X"01",X"C2",X"6D",X"EA",X"16",X"00",X"59",X"C9",X"FE",X"02",X"C2", - X"76",X"EA",X"51",X"1E",X"00",X"C9",X"FE",X"03",X"C2",X"7E",X"EA",X"51",X"59",X"C9",X"FE",X"04", - X"C2",X"89",X"EA",X"16",X"00",X"79",X"2F",X"5F",X"C9",X"FE",X"06",X"C2",X"93",X"EA",X"51",X"79", - X"2F",X"5F",X"C9",X"FE",X"07",X"C2",X"9C",X"EA",X"51",X"1E",X"FF",X"C9",X"FE",X"08",X"C2",X"A7", - X"EA",X"79",X"2F",X"57",X"1E",X"00",X"C9",X"FE",X"09",X"C2",X"B1",X"EA",X"79",X"2F",X"57",X"59", - X"C9",X"FE",X"0B",X"C2",X"BA",X"EA",X"16",X"FF",X"59",X"C9",X"FE",X"0C",X"C2",X"C4",X"EA",X"79", - X"2F",X"57",X"5F",X"C9",X"FE",X"0D",X"C2",X"CF",X"EA",X"79",X"2F",X"57",X"1E",X"FF",X"C9",X"D1", - X"16",X"FF",X"79",X"2F",X"5F",X"3E",X"02",X"D3",X"6A",X"72",X"3E",X"03",X"D3",X"6A",X"73",X"3A", - X"FE",X"DF",X"D3",X"6A",X"D1",X"13",X"2C",X"05",X"C2",X"5A",X"EA",X"C9",X"21",X"00",X"00",X"39", - X"22",X"EC",X"DF",X"21",X"EC",X"DF",X"F9",X"2A",X"3C",X"DF",X"7D",X"C6",X"0A",X"6F",X"22",X"3C", - X"DF",X"3E",X"02",X"F5",X"D3",X"6A",X"06",X"1A",X"E5",X"0E",X"28",X"36",X"00",X"24",X"0D",X"C2", - X"0B",X"EB",X"E1",X"2C",X"05",X"C2",X"08",X"EB",X"F1",X"3D",X"CA",X"2F",X"EB",X"F5",X"3E",X"06", - X"32",X"07",X"EB",X"2A",X"3A",X"DF",X"7D",X"C6",X"04",X"6F",X"3E",X"03",X"C3",X"04",X"EB",X"3E", - X"1A",X"32",X"07",X"EB",X"2A",X"3C",X"DF",X"E5",X"D1",X"7D",X"C6",X"0A",X"6F",X"DB",X"74",X"E6", - X"01",X"C2",X"3D",X"EB",X"3A",X"44",X"DF",X"C6",X"0A",X"D3",X"69",X"32",X"44",X"DF",X"3E",X"03", - X"D3",X"6A",X"06",X"0A",X"E5",X"D5",X"0E",X"28",X"1A",X"77",X"AF",X"12",X"14",X"24",X"0D",X"C2", - X"58",X"EB",X"D1",X"E1",X"2C",X"1C",X"05",X"C2",X"54",X"EB",X"2A",X"3A",X"DF",X"7D",X"C6",X"0A", - X"6F",X"22",X"3A",X"DF",X"2A",X"EC",X"DF",X"F9",X"3A",X"FE",X"DF",X"D3",X"6A",X"C9",X"0D",X"F5", - X"C5",X"D5",X"E5",X"3A",X"20",X"DF",X"F5",X"3E",X"04",X"32",X"20",X"DF",X"21",X"46",X"DF",X"3A", - X"26",X"DF",X"E6",X"04",X"C2",X"B1",X"EB",X"3A",X"26",X"DF",X"E6",X"02",X"C2",X"A8",X"EB",X"01", - X"52",X"EC",X"CD",X"44",X"EC",X"C3",X"B7",X"EB",X"01",X"55",X"EC",X"CD",X"44",X"EC",X"C3",X"B7", - X"EB",X"01",X"58",X"EC",X"CD",X"44",X"EC",X"36",X"2F",X"23",X"3A",X"26",X"DF",X"E6",X"01",X"CA", - X"C7",X"EB",X"36",X"48",X"C3",X"C9",X"EB",X"36",X"42",X"23",X"36",X"50",X"23",X"36",X"2F",X"23", - X"3A",X"26",X"DF",X"E6",X"08",X"C2",X"DE",X"EB",X"01",X"5B",X"EC",X"C3",X"E1",X"EB",X"01",X"5E", - X"EC",X"CD",X"44",X"EC",X"3A",X"26",X"DF",X"E6",X"20",X"C2",X"F8",X"EB",X"36",X"2F",X"23",X"01", - X"61",X"EC",X"CD",X"44",X"EC",X"C3",X"01",X"EC",X"36",X"20",X"23",X"01",X"4F",X"EC",X"CD",X"44", - X"EC",X"06",X"28",X"11",X"46",X"DF",X"AF",X"32",X"D9",X"DF",X"2A",X"38",X"DF",X"E5",X"2A",X"3C", - X"DF",X"3E",X"0B",X"85",X"6F",X"22",X"38",X"DF",X"C5",X"E5",X"D5",X"11",X"D9",X"DF",X"06",X"01", - X"CD",X"5A",X"EA",X"D1",X"1A",X"D5",X"CD",X"EB",X"E9",X"06",X"08",X"CD",X"5A",X"EA",X"D1",X"E1", - X"24",X"C1",X"13",X"05",X"C2",X"15",X"EC",X"E1",X"22",X"38",X"DF",X"F1",X"32",X"20",X"DF",X"E1", - X"D1",X"C1",X"F1",X"C9",X"16",X"03",X"0A",X"77",X"23",X"03",X"15",X"C2",X"46",X"EC",X"C9",X"20", - X"20",X"20",X"BB",X"D0",X"E2",X"C0",X"E3",X"E1",X"B3",X"E0",X"E4",X"C6",X"E4",X"E0",X"C3",X"DF", - X"BA",X"C0",X"E3",X"DB",X"79",X"D6",X"41",X"FE",X"1A",X"D2",X"AD",X"EC",X"5F",X"16",X"00",X"21", - X"79",X"EC",X"19",X"19",X"5E",X"23",X"56",X"EB",X"E9",X"5E",X"EF",X"2E",X"ED",X"73",X"ED",X"79", - X"ED",X"82",X"EF",X"8C",X"EF",X"7C",X"EF",X"6F",X"EF",X"6D",X"ED",X"52",X"ED",X"67",X"ED",X"7F", - X"ED",X"AD",X"EC",X"66",X"EE",X"85",X"ED",X"E5",X"EE",X"AD",X"EC",X"AD",X"EC",X"AD",X"EC",X"B9", - X"EC",X"1D",X"EE",X"AD",X"EC",X"EF",X"EC",X"0A",X"EF",X"9B",X"EE",X"AD",X"EC",X"3E",X"C3",X"32", - X"35",X"DF",X"21",X"E6",X"E7",X"22",X"36",X"DF",X"C9",X"AF",X"32",X"D8",X"DF",X"21",X"C4",X"EC", - X"22",X"36",X"DF",X"C9",X"3A",X"D8",X"DF",X"B7",X"C2",X"DE",X"EC",X"21",X"68",X"DF",X"79",X"32", - X"D8",X"DF",X"11",X"0A",X"00",X"19",X"3D",X"C2",X"D5",X"EC",X"22",X"17",X"DF",X"C9",X"79",X"2A", - X"17",X"DF",X"77",X"23",X"22",X"17",X"DF",X"B7",X"C0",X"32",X"D8",X"DF",X"C3",X"AD",X"EC",X"3E", - X"03",X"32",X"D8",X"DF",X"21",X"01",X"ED",X"22",X"36",X"DF",X"21",X"29",X"DF",X"22",X"EC",X"DF", - X"C9",X"3A",X"D8",X"DF",X"2A",X"EC",X"DF",X"FE",X"03",X"C2",X"1B",X"ED",X"F5",X"79",X"3D",X"07", - X"5F",X"16",X"00",X"19",X"22",X"EC",X"DF",X"F1",X"C3",X"26",X"ED",X"FE",X"02",X"C2",X"24",X"ED", - X"71",X"C3",X"26",X"ED",X"23",X"71",X"3D",X"32",X"D8",X"DF",X"C0",X"C3",X"AD",X"EC",X"CD",X"8E", - X"EE",X"21",X"3E",X"ED",X"22",X"36",X"DF",X"21",X"55",X"DF",X"22",X"17",X"DF",X"C9",X"79",X"B7", - X"CA",X"4C",X"ED",X"2A",X"17",X"DF",X"77",X"23",X"22",X"17",X"DF",X"C9",X"CD",X"7F",X"EB",X"C3", - X"AD",X"EC",X"3A",X"40",X"DF",X"47",X"3A",X"3F",X"DF",X"B8",X"CA",X"AD",X"EC",X"3D",X"F5",X"3A", - X"3E",X"DF",X"47",X"F1",X"C3",X"68",X"EF",X"CD",X"C2",X"E8",X"C3",X"AD",X"EC",X"CD",X"9D",X"E9", - X"C3",X"AD",X"EC",X"CD",X"B4",X"E9",X"C3",X"AD",X"EC",X"CD",X"88",X"E9",X"C3",X"AD",X"EC",X"CD", - X"6E",X"E9",X"C3",X"AD",X"EC",X"3A",X"20",X"DF",X"F5",X"0F",X"0F",X"E6",X"03",X"F5",X"3A",X"42", - X"DF",X"47",X"3A",X"40",X"DF",X"4F",X"CD",X"C3",X"ED",X"11",X"06",X"44",X"19",X"F1",X"F5",X"E6", - X"01",X"32",X"20",X"DF",X"E5",X"3E",X"02",X"32",X"D9",X"DF",X"CD",X"DC",X"ED",X"E1",X"F1",X"E6", - X"02",X"32",X"20",X"DF",X"3E",X"03",X"32",X"D9",X"DF",X"CD",X"DC",X"ED",X"F1",X"32",X"20",X"DF", - X"C3",X"AD",X"EC",X"21",X"00",X"00",X"78",X"B7",X"CA",X"D0",X"ED",X"24",X"3D",X"C2",X"CB",X"ED", - X"79",X"B7",X"C8",X"7D",X"C6",X"0A",X"0D",X"C2",X"D4",X"ED",X"6F",X"C9",X"3A",X"42",X"DF",X"47", - X"3A",X"43",X"DF",X"90",X"3C",X"4F",X"3A",X"40",X"DF",X"47",X"3A",X"41",X"DF",X"90",X"3C",X"47", - X"C5",X"E5",X"3A",X"D9",X"DF",X"D3",X"6A",X"3A",X"20",X"DF",X"B7",X"C2",X"02",X"EE",X"57",X"C3", - X"04",X"EE",X"16",X"FF",X"3E",X"0A",X"72",X"2C",X"3D",X"C2",X"06",X"EE",X"05",X"C2",X"04",X"EE", - X"3A",X"FE",X"DF",X"D3",X"6A",X"E1",X"24",X"C1",X"0D",X"C2",X"F0",X"ED",X"C9",X"3E",X"04",X"32", - X"D8",X"DF",X"21",X"31",X"EE",X"22",X"36",X"DF",X"3A",X"26",X"DF",X"F6",X"20",X"32",X"26",X"DF", - X"C9",X"3A",X"D8",X"DF",X"F5",X"0D",X"21",X"5D",X"EE",X"E5",X"FE",X"04",X"C2",X"44",X"EE",X"79", - X"32",X"42",X"DF",X"C9",X"FE",X"03",X"C2",X"4E",X"EE",X"79",X"32",X"40",X"DF",X"C9",X"FE",X"02", - X"C2",X"58",X"EE",X"79",X"32",X"43",X"DF",X"C9",X"79",X"32",X"41",X"DF",X"E1",X"F1",X"3D",X"32", - X"D8",X"DF",X"CA",X"79",X"ED",X"C9",X"3E",X"0A",X"01",X"F6",X"FF",X"21",X"D6",X"DF",X"09",X"77", - X"23",X"36",X"00",X"2B",X"3D",X"C2",X"6E",X"EE",X"0E",X"15",X"11",X"93",X"EF",X"21",X"20",X"DF", - X"1A",X"77",X"13",X"23",X"0D",X"C2",X"80",X"EE",X"CD",X"8E",X"EE",X"C3",X"AD",X"EC",X"21",X"54", - X"DF",X"3E",X"1A",X"36",X"20",X"23",X"3D",X"C2",X"93",X"EE",X"C9",X"3E",X"02",X"32",X"D8",X"DF", - X"21",X"A7",X"EE",X"22",X"36",X"DF",X"C9",X"3A",X"D8",X"DF",X"0D",X"F5",X"FE",X"02",X"C2",X"C1", - X"EE",X"79",X"D6",X"20",X"FE",X"18",X"DA",X"BB",X"EE",X"3E",X"17",X"32",X"3F",X"DF",X"C3",X"CE", - X"EE",X"79",X"D6",X"20",X"FE",X"28",X"DA",X"CB",X"EE",X"3E",X"27",X"32",X"3E",X"DF",X"F1",X"3D", - X"32",X"D8",X"DF",X"C0",X"3A",X"3E",X"DF",X"47",X"3A",X"3F",X"DF",X"4F",X"CD",X"C3",X"ED",X"22", - X"38",X"DF",X"C3",X"AD",X"EC",X"21",X"EC",X"EE",X"22",X"36",X"DF",X"C9",X"79",X"E6",X"0F",X"F5", - X"F5",X"0F",X"0F",X"E6",X"03",X"47",X"F1",X"E6",X"03",X"B8",X"C2",X"03",X"EF",X"F1",X"3E",X"02", - X"C3",X"04",X"EF",X"F1",X"32",X"20",X"DF",X"C3",X"AD",X"EC",X"3E",X"04",X"32",X"D8",X"DF",X"21", - X"16",X"EF",X"22",X"36",X"DF",X"C9",X"3A",X"D8",X"DF",X"F5",X"21",X"55",X"EF",X"E5",X"FE",X"04", - X"C2",X"2D",X"EF",X"79",X"FE",X"80",X"C8",X"32",X"22",X"DF",X"D3",X"11",X"C9",X"FE",X"03",X"C2", - X"3C",X"EF",X"79",X"FE",X"80",X"C8",X"32",X"23",X"DF",X"D3",X"12",X"C9",X"FE",X"02",X"C2",X"4B", - X"EF",X"79",X"FE",X"80",X"C8",X"32",X"24",X"DF",X"D3",X"13",X"C9",X"79",X"FE",X"80",X"C8",X"32", - X"21",X"DF",X"D3",X"10",X"E1",X"F1",X"3D",X"32",X"D8",X"DF",X"CA",X"AD",X"EC",X"C9",X"3A",X"43", - X"DF",X"32",X"3E",X"DF",X"47",X"3A",X"41",X"DF",X"32",X"3F",X"DF",X"4F",X"C3",X"DC",X"EE",X"3A", - X"42",X"DF",X"32",X"3E",X"DF",X"47",X"3A",X"3F",X"DF",X"C3",X"6B",X"EF",X"3A",X"43",X"DF",X"C3", - X"72",X"EF",X"3A",X"3E",X"DF",X"47",X"3A",X"40",X"DF",X"C3",X"68",X"EF",X"3A",X"3E",X"DF",X"47", - X"C3",X"65",X"EF",X"02",X"FF",X"CD",X"1E",X"F0",X"00",X"00",X"1F",X"E7",X"EF",X"F2",X"EF",X"F3", - X"EF",X"F4",X"EF",X"F2",X"EF",X"F5",X"EF",X"F6",X"F5",X"D5",X"E5",X"C5",X"CD",X"55",X"F0",X"21", - X"8F",X"E1",X"CD",X"C2",X"E3",X"21",X"AD",X"E1",X"CD",X"C2",X"E3",X"21",X"BB",X"E1",X"CD",X"C2", - X"E3",X"CD",X"6F",X"E4",X"FE",X"0D",X"CA",X"CE",X"EF",X"C1",X"E1",X"C3",X"2B",X"F0",X"21",X"CC", - X"E1",X"CD",X"C2",X"E3",X"C1",X"E1",X"1E",X"B0",X"CD",X"63",X"F0",X"3E",X"0D",X"D3",X"62",X"C3", - X"2B",X"F0",X"22",X"1E",X"DF",X"21",X"00",X"00",X"39",X"22",X"17",X"DF",X"2A",X"1E",X"DF",X"F5", - X"D5",X"E5",X"C5",X"21",X"8F",X"E1",X"CD",X"C2",X"E3",X"21",X"B4",X"E1",X"CD",X"C2",X"E3",X"21", - X"BB",X"E1",X"CD",X"C2",X"E3",X"CD",X"6F",X"E4",X"FE",X"0D",X"C2",X"C9",X"EF",X"21",X"D7",X"E1", - X"CD",X"C2",X"E3",X"AF",X"C1",X"E1",X"CD",X"86",X"F0",X"F3",X"C2",X"47",X"F0",X"7A",X"CD",X"55", - X"F0",X"BA",X"CA",X"2B",X"F0",X"21",X"E2",X"E1",X"CD",X"C2",X"E3",X"21",X"13",X"E0",X"22",X"05", - X"DF",X"CD",X"38",X"F0",X"D1",X"F1",X"FB",X"C9",X"3E",X"FF",X"D3",X"75",X"3E",X"20",X"D3",X"74", - X"21",X"F0",X"E1",X"CD",X"C2",X"E3",X"C9",X"21",X"B7",X"F1",X"CD",X"C2",X"E3",X"CD",X"38",X"F0", - X"2A",X"17",X"DF",X"F9",X"C9",X"F5",X"16",X"00",X"0A",X"82",X"57",X"CD",X"B6",X"E3",X"DA",X"58", - X"F0",X"F1",X"C9",X"F5",X"C5",X"E5",X"D5",X"C5",X"CD",X"AC",X"F0",X"7D",X"91",X"4F",X"7C",X"98", - X"47",X"03",X"E1",X"56",X"CD",X"DB",X"F0",X"23",X"0B",X"78",X"B1",X"C2",X"73",X"F0",X"D1",X"CD", - X"DB",X"F0",X"E1",X"C1",X"F1",X"C9",X"F5",X"C5",X"E5",X"E5",X"C5",X"CD",X"2D",X"F1",X"C1",X"E1", - X"0B",X"03",X"C5",X"CD",X"5C",X"F1",X"C1",X"7A",X"02",X"79",X"AD",X"C2",X"91",X"F0",X"78",X"AC", - X"C2",X"91",X"F0",X"C5",X"CD",X"5C",X"F1",X"C1",X"E1",X"C1",X"F1",X"C9",X"F3",X"E5",X"21",X"22", - X"F1",X"22",X"05",X"DF",X"21",X"40",X"1F",X"3E",X"9E",X"D3",X"63",X"3E",X"02",X"D3",X"62",X"3E", - X"10",X"D3",X"63",X"3E",X"FD",X"D3",X"75",X"3E",X"0D",X"CD",X"22",X"F1",X"3E",X"0C",X"76",X"3E", - X"0D",X"76",X"2B",X"7C",X"B5",X"C2",X"CC",X"F0",X"E1",X"F3",X"C9",X"3E",X"0C",X"FB",X"76",X"3E", - X"0C",X"76",X"3E",X"0D",X"76",X"3E",X"0D",X"76",X"3E",X"08",X"F5",X"3E",X"0C",X"76",X"7A",X"0F", - X"57",X"3E",X"06",X"17",X"76",X"7A",X"07",X"57",X"3E",X"06",X"3F",X"17",X"76",X"7A",X"0F",X"57", - X"3E",X"0D",X"76",X"F1",X"3D",X"C2",X"EA",X"F0",X"3E",X"0C",X"76",X"3E",X"0D",X"76",X"3E",X"0C", - X"76",X"3E",X"0D",X"76",X"3E",X"0C",X"76",X"3E",X"0D",X"76",X"3E",X"0C",X"76",X"3E",X"0D",X"76", - X"F3",X"C9",X"D3",X"6B",X"7B",X"D3",X"60",X"3E",X"61",X"D3",X"74",X"FB",X"C9",X"21",X"47",X"F0", - X"22",X"05",X"DF",X"F3",X"3E",X"10",X"D3",X"63",X"3E",X"FD",X"D3",X"75",X"21",X"E8",X"03",X"CD", - X"85",X"F1",X"2B",X"7C",X"B5",X"C2",X"3F",X"F1",X"44",X"5C",X"FB",X"CD",X"85",X"F1",X"09",X"1D", - X"C2",X"4B",X"F1",X"24",X"24",X"24",X"7C",X"A7",X"1F",X"84",X"5F",X"C9",X"CD",X"85",X"F1",X"CD", - X"85",X"F1",X"79",X"93",X"DA",X"5F",X"F1",X"06",X"08",X"16",X"00",X"CD",X"85",X"F1",X"79",X"93", - X"D2",X"78",X"F1",X"F5",X"CD",X"85",X"F1",X"F1",X"7A",X"1F",X"57",X"05",X"C2",X"6B",X"F1",X"CD", - X"85",X"F1",X"CD",X"85",X"F1",X"DB",X"74",X"E6",X"10",X"CA",X"85",X"F1",X"DB",X"74",X"E6",X"10", - X"C2",X"8C",X"F1",X"AF",X"D3",X"63",X"DB",X"60",X"2F",X"4F",X"3E",X"10",X"D3",X"63",X"3E",X"FF", - X"D3",X"60",X"C9",X"C5",X"D5",X"CD",X"5C",X"F1",X"7A",X"D1",X"C1",X"C9",X"F5",X"D5",X"1E",X"B0", - X"51",X"CD",X"DB",X"F0",X"D1",X"F1",X"C9",X"0A",X"2A",X"20",X"DE",X"E8",X"D8",X"D1",X"DA",X"D0", - X"20",X"E7",X"E2",X"D5",X"DD",X"D8",X"EF",X"20",X"2A",X"0D",X"00",X"11",X"00",X"00",X"01",X"00", - X"C0",X"21",X"01",X"C0",X"CD",X"81",X"E3",X"2A",X"00",X"C0",X"7C",X"BD",X"C8",X"03",X"21",X"FF", - X"C3",X"CD",X"81",X"E3",X"CD",X"59",X"E2",X"2A",X"00",X"C0",X"2B",X"7E",X"23",X"CD",X"C2",X"E3", - X"B7",X"CA",X"2D",X"F2",X"57",X"06",X"00",X"CD",X"6F",X"E4",X"FE",X"0D",X"CA",X"20",X"F2",X"FE", - X"19",X"C2",X"0E",X"F2",X"4F",X"78",X"B7",X"CA",X"F7",X"F1",X"05",X"C3",X"1A",X"F2",X"FE",X"1A", - X"C2",X"F7",X"F1",X"4F",X"78",X"BA",X"CA",X"F7",X"F1",X"04",X"CD",X"D7",X"E7",X"C3",X"F7",X"F1", - X"78",X"01",X"08",X"00",X"B7",X"CA",X"2D",X"F2",X"09",X"3D",X"C3",X"24",X"F2",X"5E",X"23",X"56", - X"D5",X"23",X"4E",X"23",X"46",X"23",X"5E",X"23",X"56",X"D5",X"23",X"5E",X"23",X"56",X"EB",X"D1", - X"CD",X"81",X"E3",X"CD",X"66",X"EE",X"E1",X"E9",X"DB",X"74",X"E6",X"04",X"C8",X"3E",X"FF",X"C9", - X"F5",X"C5",X"CD",X"48",X"F2",X"CA",X"52",X"F2",X"79",X"FE",X"80",X"D4",X"6B",X"F2",X"2F",X"D3", - X"68",X"3E",X"09",X"D3",X"6B",X"3D",X"D3",X"6B",X"C1",X"F1",X"C9",X"FE",X"F0",X"C2",X"75",X"F2", - X"3E",X"B5",X"C3",X"7C",X"F2",X"FE",X"F1",X"C2",X"7C",X"F2",X"3E",X"D5",X"FE",X"D0",X"D2",X"88", - X"F2",X"D6",X"B0",X"0E",X"00",X"C3",X"8C",X"F2",X"D6",X"D0",X"0E",X"01",X"E5",X"D5",X"21",X"A1", - X"F2",X"16",X"00",X"5F",X"19",X"5E",X"79",X"B7",X"7B",X"C2",X"9E",X"F2",X"C6",X"20",X"D1",X"E1", - X"C9",X"C1",X"C2",X"D7",X"C7",X"C4",X"C5",X"D6",X"DA",X"C9",X"CA",X"CB",X"CC",X"CD",X"CE",X"CF", - X"D0",X"D2",X"D3",X"D4",X"D5",X"C6",X"C8",X"C3",X"DE",X"DB",X"DD",X"DF",X"D9",X"D8",X"DC",X"C0", - X"D1",X"C5",X"0E",X"40",X"C3",X"CA",X"F2",X"C5",X"0E",X"80",X"F3",X"06",X"F6",X"3E",X"0B",X"D3", - X"6B",X"3D",X"D3",X"6B",X"DB",X"74",X"04",X"A1",X"CA",X"D4",X"F2",X"78",X"A7",X"F2",X"EB",X"F2", - X"2F",X"3C",X"FE",X"0A",X"06",X"00",X"FA",X"EB",X"F2",X"06",X"7F",X"78",X"C1",X"FB",X"C9",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"1E",X"1E",X"0C",X"0C",X"00",X"0C",X"00",X"36", - X"36",X"36",X"00",X"00",X"00",X"00",X"00",X"36",X"36",X"7F",X"36",X"7F",X"36",X"36",X"00",X"00", - X"18",X"7C",X"06",X"3C",X"60",X"37",X"18",X"00",X"63",X"33",X"18",X"0C",X"66",X"63",X"00",X"1C", - X"36",X"1C",X"6E",X"3B",X"33",X"6E",X"00",X"06",X"06",X"03",X"00",X"00",X"00",X"00",X"00",X"18", - X"0C",X"06",X"06",X"06",X"0C",X"18",X"00",X"06",X"0C",X"18",X"18",X"18",X"0C",X"06",X"00",X"00", - X"66",X"3C",X"FF",X"3C",X"66",X"00",X"00",X"00",X"0C",X"0C",X"3F",X"0C",X"0C",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"0C",X"0C",X"06",X"00",X"00",X"00",X"3F",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"60",X"30",X"18",X"0C",X"06",X"03",X"01",X"00",X"3E", - X"63",X"73",X"7B",X"6F",X"67",X"3E",X"00",X"0C",X"0E",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"1E", - X"33",X"30",X"1C",X"06",X"33",X"3F",X"00",X"3F",X"33",X"18",X"1C",X"30",X"33",X"1E",X"00",X"38", - X"3C",X"36",X"33",X"7F",X"30",X"78",X"00",X"3F",X"03",X"1F",X"30",X"30",X"33",X"1E",X"00",X"1C", - X"06",X"03",X"1F",X"33",X"33",X"1E",X"00",X"3F",X"33",X"30",X"18",X"0C",X"0C",X"0C",X"00",X"1E", - X"33",X"33",X"1E",X"33",X"33",X"1E",X"00",X"1E",X"33",X"33",X"3E",X"30",X"18",X"0E",X"00",X"00", - X"0C",X"0C",X"00",X"00",X"0C",X"0C",X"00",X"00",X"0C",X"0C",X"00",X"00",X"0C",X"0C",X"06",X"18", - X"0C",X"06",X"03",X"06",X"0C",X"18",X"00",X"00",X"00",X"3F",X"00",X"3F",X"00",X"00",X"00",X"06", - X"0C",X"18",X"30",X"18",X"0C",X"06",X"00",X"1E",X"33",X"30",X"18",X"0C",X"00",X"0C",X"00",X"3E", - X"63",X"7B",X"7B",X"03",X"1E",X"00",X"00",X"0C",X"1E",X"33",X"33",X"3F",X"33",X"33",X"00",X"3F", - X"66",X"66",X"3E",X"66",X"66",X"3F",X"00",X"3C",X"66",X"03",X"03",X"03",X"66",X"3C",X"00",X"1F", - X"36",X"66",X"66",X"66",X"36",X"1F",X"00",X"7F",X"46",X"16",X"1E",X"16",X"46",X"7F",X"00",X"7F", - X"46",X"16",X"1E",X"16",X"06",X"0F",X"00",X"3C",X"66",X"03",X"03",X"73",X"66",X"7C",X"00",X"33", - X"33",X"33",X"3F",X"33",X"33",X"33",X"00",X"1E",X"0C",X"0C",X"0C",X"0C",X"0C",X"1E",X"00",X"78", - X"30",X"30",X"30",X"33",X"33",X"1E",X"00",X"67",X"66",X"36",X"1E",X"36",X"66",X"67",X"00",X"0F", - X"06",X"06",X"06",X"46",X"66",X"7F",X"00",X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63", - X"67",X"6F",X"7B",X"73",X"63",X"63",X"00",X"1C",X"36",X"63",X"63",X"63",X"36",X"1C",X"00",X"3F", - X"66",X"66",X"3E",X"06",X"06",X"0F",X"00",X"1E",X"33",X"33",X"33",X"3B",X"1E",X"38",X"00",X"7F", - X"66",X"66",X"3E",X"36",X"66",X"67",X"00",X"1E",X"33",X"06",X"0C",X"18",X"33",X"1E",X"00",X"3F", - X"2D",X"0C",X"0C",X"0C",X"0C",X"1E",X"00",X"33",X"33",X"33",X"33",X"33",X"33",X"1E",X"00",X"33", - X"33",X"33",X"33",X"33",X"1E",X"0C",X"00",X"63",X"63",X"63",X"6B",X"7F",X"77",X"63",X"00",X"63", - X"63",X"36",X"1C",X"1C",X"36",X"63",X"00",X"33",X"33",X"33",X"1E",X"0C",X"0C",X"1E",X"00",X"7F", - X"63",X"31",X"18",X"4C",X"66",X"7F",X"00",X"1E",X"06",X"06",X"06",X"06",X"06",X"1E",X"00",X"03", - X"06",X"0C",X"18",X"30",X"60",X"40",X"00",X"1E",X"18",X"18",X"18",X"18",X"18",X"1E",X"00",X"08", - X"1C",X"36",X"63",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"0C", - X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1E",X"30",X"3E",X"33",X"6E",X"00",X"07", - X"06",X"06",X"3E",X"66",X"66",X"3B",X"00",X"00",X"00",X"1E",X"33",X"03",X"33",X"1E",X"00",X"38", - X"30",X"30",X"3E",X"33",X"33",X"6E",X"00",X"00",X"00",X"1E",X"33",X"3F",X"03",X"1E",X"00",X"1C", - X"36",X"06",X"0F",X"06",X"06",X"0F",X"00",X"00",X"00",X"6E",X"33",X"33",X"3E",X"30",X"1F",X"07", - X"06",X"36",X"6E",X"66",X"66",X"67",X"00",X"0C",X"00",X"0E",X"0C",X"0C",X"0C",X"1E",X"00",X"30", - X"00",X"30",X"30",X"30",X"33",X"33",X"1E",X"07",X"06",X"66",X"36",X"1E",X"36",X"67",X"00",X"0E", - X"0C",X"0C",X"0C",X"0C",X"0C",X"1E",X"00",X"00",X"00",X"33",X"7F",X"7F",X"6B",X"63",X"00",X"00", - X"00",X"1F",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"1E",X"33",X"33",X"33",X"1E",X"00",X"00", - X"00",X"3B",X"66",X"66",X"3E",X"06",X"0F",X"00",X"00",X"6E",X"33",X"33",X"3E",X"30",X"78",X"00", - X"00",X"3B",X"6E",X"66",X"06",X"0F",X"00",X"00",X"00",X"3E",X"03",X"1E",X"30",X"1F",X"00",X"08", - X"0C",X"3E",X"0C",X"0C",X"2C",X"18",X"00",X"00",X"00",X"33",X"33",X"33",X"33",X"6E",X"00",X"00", - X"00",X"33",X"33",X"33",X"1E",X"0C",X"00",X"00",X"00",X"63",X"6B",X"7F",X"7F",X"36",X"00",X"00", - X"00",X"63",X"36",X"1C",X"36",X"63",X"00",X"00",X"00",X"33",X"33",X"33",X"3E",X"30",X"1F",X"00", - X"00",X"3F",X"19",X"0C",X"26",X"3F",X"00",X"38",X"0C",X"0C",X"07",X"0C",X"0C",X"38",X"00",X"08", - X"08",X"08",X"00",X"00",X"08",X"08",X"08",X"07",X"0C",X"0C",X"38",X"0C",X"0C",X"07",X"00",X"6E", - X"3B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"1C",X"36",X"63",X"63",X"7F",X"00",X"0C", - X"1E",X"33",X"33",X"3F",X"33",X"33",X"00",X"7F",X"06",X"06",X"3E",X"66",X"66",X"3F",X"00",X"3F", - X"66",X"66",X"3E",X"66",X"66",X"3F",X"00",X"7F",X"66",X"06",X"06",X"06",X"06",X"0F",X"00",X"3C", - X"36",X"36",X"36",X"36",X"36",X"7F",X"63",X"7F",X"46",X"16",X"1E",X"16",X"46",X"7F",X"00",X"6B", - X"6B",X"3E",X"1C",X"3E",X"69",X"6B",X"00",X"3E",X"63",X"60",X"38",X"60",X"63",X"3E",X"00",X"63", - X"63",X"73",X"7B",X"6F",X"67",X"63",X"00",X"1C",X"63",X"73",X"7B",X"6F",X"67",X"63",X"00",X"63", - X"33",X"1B",X"0F",X"1B",X"33",X"63",X"00",X"78",X"6C",X"66",X"66",X"66",X"66",X"63",X"00",X"63", - X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"33",X"33",X"33",X"3F",X"33",X"33",X"33",X"00",X"3E", - X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"7F",X"63",X"63",X"63",X"63",X"63",X"63",X"00",X"3F", - X"66",X"66",X"3E",X"06",X"06",X"0F",X"00",X"3C",X"66",X"03",X"03",X"03",X"66",X"3C",X"00",X"3F", - X"2D",X"0C",X"0C",X"0C",X"0C",X"1E",X"00",X"63",X"63",X"63",X"7E",X"60",X"20",X"1E",X"00",X"18", - X"7E",X"DB",X"DB",X"7E",X"18",X"3C",X"00",X"63",X"36",X"1C",X"1C",X"36",X"63",X"63",X"00",X"33", - X"33",X"33",X"33",X"33",X"33",X"7F",X"60",X"63",X"63",X"63",X"7E",X"60",X"60",X"60",X"00",X"63", - X"6B",X"6B",X"6B",X"6B",X"6B",X"7F",X"00",X"63",X"6B",X"6B",X"6B",X"6B",X"6B",X"7F",X"60",X"07", - X"06",X"06",X"36",X"66",X"66",X"36",X"00",X"63",X"63",X"63",X"6F",X"5B",X"5B",X"6F",X"00",X"03", - X"03",X"03",X"3F",X"63",X"63",X"3F",X"00",X"3E",X"63",X"60",X"7C",X"60",X"63",X"3E",X"00",X"33", - X"6B",X"6B",X"6F",X"6B",X"6B",X"33",X"00",X"7E",X"63",X"63",X"7E",X"6C",X"66",X"63",X"00",X"00", - X"00",X"1E",X"30",X"3E",X"33",X"7E",X"00",X"00",X"00",X"3F",X"03",X"3F",X"63",X"3F",X"00",X"00", - X"00",X"1F",X"33",X"1F",X"33",X"1F",X"00",X"00",X"00",X"3F",X"03",X"03",X"03",X"03",X"00",X"00", - X"00",X"3C",X"36",X"36",X"36",X"7F",X"63",X"00",X"00",X"1E",X"33",X"3F",X"03",X"1E",X"00",X"00", - X"00",X"6B",X"6B",X"3E",X"6B",X"6B",X"00",X"00",X"00",X"1E",X"33",X"18",X"33",X"1E",X"00",X"00", - X"00",X"63",X"63",X"73",X"7F",X"66",X"00",X"00",X"18",X"63",X"63",X"73",X"7F",X"66",X"00",X"00", - X"00",X"33",X"1B",X"0F",X"1B",X"73",X"00",X"00",X"00",X"78",X"6C",X"66",X"66",X"67",X"00",X"00", - X"00",X"63",X"77",X"7F",X"6B",X"63",X"00",X"00",X"00",X"63",X"63",X"7F",X"63",X"63",X"00",X"00", - X"00",X"3E",X"63",X"63",X"63",X"3E",X"00",X"00",X"00",X"7F",X"63",X"63",X"63",X"63",X"00",X"00", - X"00",X"3F",X"63",X"63",X"3F",X"03",X"03",X"00",X"00",X"3E",X"63",X"03",X"63",X"3E",X"00",X"00", - X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"00",X"00",X"00",X"63",X"66",X"7C",X"60",X"3E",X"00",X"00", - X"00",X"18",X"7E",X"DB",X"7E",X"18",X"18",X"00",X"00",X"63",X"36",X"1C",X"36",X"63",X"00",X"00", - X"00",X"33",X"33",X"33",X"33",X"7F",X"60",X"00",X"00",X"33",X"33",X"3E",X"30",X"30",X"00",X"00", - X"00",X"6B",X"6B",X"6B",X"6B",X"7F",X"00",X"00",X"00",X"6B",X"6B",X"6B",X"6B",X"7F",X"60",X"00", - X"00",X"07",X"06",X"3E",X"66",X"3E",X"00",X"00",X"00",X"63",X"63",X"6F",X"5B",X"6F",X"00",X"00", - X"00",X"03",X"03",X"3F",X"63",X"3F",X"00",X"00",X"00",X"3F",X"60",X"78",X"60",X"3F",X"00",X"00", - X"00",X"33",X"6B",X"6F",X"6B",X"33",X"00",X"00",X"00",X"7E",X"63",X"7E",X"66",X"63",X"00",X"14", - X"7F",X"46",X"16",X"1E",X"16",X"46",X"7F",X"00",X"12",X"1E",X"33",X"3F",X"03",X"1E",X"00",X"64", - X"C3",X"A3",X"E4",X"C3",X"6F",X"E4",X"C3",X"A3",X"F1",X"C3",X"D7",X"E7",X"C3",X"AC",X"F1",X"C3", - X"50",X"F2",X"C3",X"FC",X"E6",X"C3",X"48",X"F2",X"C3",X"C2",X"E3",X"C3",X"F1",X"E3",X"C3",X"2D", - X"F1",X"C3",X"AC",X"F0",X"C3",X"E2",X"EF",X"C3",X"A8",X"EF",X"C3",X"55",X"F0",X"C3",X"1C",X"E4", - X"C3",X"A5",X"E0",X"C3",X"1C",X"FD",X"C3",X"40",X"FD",X"C3",X"2E",X"FD",X"C3",X"35",X"FD",X"C3", - X"80",X"F8",X"C3",X"F0",X"F8",X"C3",X"AB",X"F9",X"C3",X"80",X"FA",X"C3",X"16",X"FB",X"C3",X"72", - X"FB",X"C3",X"BE",X"FB",X"C3",X"05",X"FC",X"C3",X"39",X"FC",X"C3",X"A0",X"FC",X"C3",X"25",X"E9", - X"C3",X"04",X"E9",X"C3",X"81",X"E3",X"C3",X"FF",X"FF",X"C3",X"B6",X"E3",X"C3",X"7E",X"F8",X"C3", - X"7E",X"F8",X"C3",X"44",X"E4",X"C3",X"D5",X"E3",X"C3",X"C1",X"F2",X"C3",X"C7",X"F2",X"C9",X"FF", - X"CD",X"BA",X"F8",X"D8",X"E5",X"D5",X"C5",X"7A",X"1F",X"7B",X"1F",X"1F",X"1F",X"E6",X"3F",X"C6", - X"40",X"57",X"4B",X"58",X"79",X"E6",X"07",X"4F",X"06",X"00",X"21",X"E8",X"F8",X"09",X"46",X"EB", - X"3A",X"DC",X"DF",X"4F",X"CD",X"C5",X"F8",X"78",X"32",X"DF",X"DF",X"22",X"DD",X"DF",X"C1",X"E1", - X"D1",X"22",X"EF",X"DF",X"78",X"32",X"F1",X"DF",X"EB",X"C9",X"78",X"C6",X"0A",X"D8",X"3E",X"7F", - X"93",X"3E",X"01",X"9A",X"C9",X"16",X"02",X"F3",X"3E",X"02",X"D3",X"6A",X"79",X"A2",X"78",X"CA", - X"D6",X"F8",X"B6",X"C3",X"D8",X"F8",X"2F",X"A6",X"77",X"3E",X"03",X"D3",X"6A",X"15",X"C2",X"CC", - X"F8",X"3A",X"FE",X"DF",X"D3",X"6A",X"FB",X"C9",X"01",X"02",X"04",X"08",X"10",X"20",X"40",X"80", - X"CD",X"BA",X"F8",X"D8",X"E5",X"D5",X"C5",X"2A",X"EF",X"DF",X"7B",X"95",X"6F",X"7A",X"9C",X"67", - X"DC",X"A3",X"F9",X"0E",X"02",X"DA",X"0A",X"F9",X"0E",X"00",X"3A",X"F1",X"DF",X"EB",X"90",X"6F", - X"DC",X"A3",X"F9",X"3E",X"00",X"67",X"DA",X"1B",X"F9",X"3E",X"40",X"B1",X"4F",X"7B",X"95",X"7A", - X"9C",X"3E",X"01",X"D2",X"29",X"F9",X"EB",X"3E",X"80",X"B1",X"32",X"E0",X"DF",X"29",X"CD",X"A3", - X"F9",X"2B",X"22",X"E3",X"DF",X"EB",X"22",X"E5",X"DF",X"54",X"5D",X"29",X"22",X"E1",X"DF",X"3A", - X"DC",X"DF",X"4F",X"3A",X"DF",X"DF",X"47",X"2A",X"DD",X"DF",X"7C",X"D6",X"40",X"DA",X"37",X"FA", - X"3E",X"70",X"94",X"DA",X"37",X"FA",X"7A",X"B3",X"CA",X"A7",X"F8",X"1B",X"D5",X"E5",X"2A",X"E3", - X"DF",X"EB",X"2A",X"E5",X"DF",X"23",X"19",X"3A",X"E0",X"DF",X"DA",X"74",X"F9",X"F6",X"81",X"EB", - X"2A",X"E1",X"DF",X"19",X"22",X"E5",X"DF",X"E1",X"57",X"0F",X"D2",X"90",X"F9",X"0F",X"78",X"D2", - X"8A",X"F9",X"0F",X"D2",X"8F",X"F9",X"25",X"C3",X"8F",X"F9",X"07",X"D2",X"8F",X"F9",X"24",X"47", - X"7A",X"07",X"D2",X"9C",X"F9",X"07",X"2D",X"DA",X"9C",X"F9",X"2C",X"2C",X"CD",X"C5",X"F8",X"D1", - X"C3",X"56",X"F9",X"7C",X"2F",X"67",X"7D",X"2F",X"6F",X"23",X"C9",X"CD",X"BA",X"F8",X"D8",X"E5", - X"D5",X"C5",X"EB",X"22",X"E9",X"DF",X"68",X"26",X"00",X"22",X"EB",X"DF",X"3A",X"F7",X"DF",X"47", - X"2A",X"F8",X"DF",X"EB",X"CD",X"91",X"FA",X"DA",X"37",X"FA",X"59",X"16",X"00",X"3A",X"EE",X"DF", - X"6F",X"62",X"EB",X"A7",X"C4",X"A8",X"FA",X"22",X"D7",X"DF",X"59",X"3A",X"ED",X"DF",X"6F",X"62", - X"EB",X"A7",X"C4",X"A8",X"FA",X"22",X"F5",X"DF",X"48",X"CD",X"C5",X"FA",X"E5",X"2A",X"F5",X"DF", - X"CD",X"A8",X"FA",X"24",X"22",X"F3",X"DF",X"2A",X"D7",X"DF",X"EB",X"CD",X"A8",X"FA",X"22",X"D9", - X"DF",X"EB",X"D1",X"CD",X"A8",X"FA",X"22",X"D7",X"DF",X"2A",X"F5",X"DF",X"CD",X"A8",X"FA",X"22", - X"F5",X"DF",X"3A",X"F9",X"DF",X"4F",X"CD",X"3B",X"FA",X"CD",X"80",X"F8",X"DA",X"37",X"FA",X"0C", - X"3E",X"48",X"A9",X"C2",X"27",X"FA",X"4F",X"CD",X"3B",X"FA",X"CD",X"F0",X"F8",X"DA",X"37",X"FA", - X"3A",X"F8",X"DF",X"A9",X"C2",X"1F",X"FA",X"C1",X"D1",X"E1",X"C9",X"CD",X"C5",X"FA",X"22",X"E1", - X"DF",X"EB",X"22",X"E5",X"DF",X"2A",X"D9",X"DF",X"CD",X"9D",X"FA",X"E5",X"2A",X"E5",X"DF",X"EB", - X"2A",X"F5",X"DF",X"CD",X"9D",X"FA",X"D1",X"19",X"EB",X"2A",X"EB",X"DF",X"19",X"7C",X"C6",X"FF", - X"D8",X"45",X"2A",X"E5",X"DF",X"EB",X"2A",X"F3",X"DF",X"CD",X"9D",X"FA",X"E5",X"2A",X"E1",X"DF", - X"EB",X"2A",X"D7",X"DF",X"CD",X"9D",X"FA",X"D1",X"19",X"EB",X"2A",X"E9",X"DF",X"19",X"EB",X"C9", - X"CD",X"91",X"FA",X"D8",X"22",X"ED",X"DF",X"EB",X"22",X"F8",X"DF",X"EB",X"78",X"32",X"F7",X"DF", - X"C9",X"7A",X"C6",X"B9",X"D8",X"7B",X"C6",X"B9",X"D8",X"78",X"C6",X"B9",X"C9",X"CD",X"A8",X"FA", - X"7C",X"26",X"00",X"0F",X"DC",X"A3",X"F9",X"C9",X"D5",X"C5",X"7C",X"AA",X"47",X"7D",X"21",X"FF", - X"00",X"54",X"0E",X"08",X"0F",X"D2",X"B9",X"FA",X"19",X"EB",X"29",X"EB",X"0D",X"C2",X"B4",X"FA", - X"6C",X"60",X"C1",X"D1",X"C9",X"C5",X"79",X"01",X"00",X"00",X"16",X"12",X"92",X"FA",X"DC",X"FA", - X"0C",X"92",X"FA",X"DC",X"FA",X"04",X"92",X"FA",X"DC",X"FA",X"0D",X"92",X"82",X"07",X"6F",X"26", - X"00",X"11",X"F0",X"FA",X"19",X"5E",X"23",X"6E",X"60",X"51",X"7C",X"AA",X"C1",X"C8",X"EB",X"C9", - X"00",X"FF",X"16",X"FF",X"2C",X"FC",X"42",X"F7",X"58",X"F1",X"6C",X"E8",X"80",X"DE",X"93",X"D2", - X"A5",X"C4",X"B5",X"B5",X"C4",X"A5",X"D2",X"93",X"DE",X"80",X"E8",X"6C",X"F1",X"58",X"F7",X"42", - X"FC",X"2C",X"FF",X"16",X"FF",X"00",X"78",X"C6",X"F0",X"D8",X"C5",X"D5",X"E5",X"CD",X"61",X"FB", - X"0E",X"20",X"F3",X"1A",X"CD",X"53",X"FB",X"47",X"3E",X"02",X"D3",X"6A",X"70",X"3A",X"FE",X"DF", - X"D3",X"6A",X"13",X"1A",X"CD",X"53",X"FB",X"47",X"3E",X"03",X"D3",X"6A",X"70",X"3A",X"FE",X"DF", - X"D3",X"6A",X"13",X"23",X"0D",X"C2",X"23",X"FB",X"FB",X"3A",X"FE",X"DF",X"D3",X"6A",X"AF",X"E1", - X"D1",X"C1",X"C9",X"E5",X"C5",X"67",X"06",X"08",X"29",X"1F",X"05",X"C2",X"58",X"FB",X"C1",X"E1", - X"C9",X"78",X"0F",X"0F",X"0F",X"47",X"E6",X"F0",X"4F",X"78",X"E6",X"03",X"47",X"21",X"00",X"3C", - X"09",X"C9",X"78",X"C6",X"F0",X"D8",X"7A",X"C6",X"D1",X"D8",X"7B",X"C6",X"8C",X"D8",X"C5",X"D5", - X"E5",X"CD",X"61",X"FB",X"7B",X"07",X"5F",X"3E",X"40",X"82",X"57",X"06",X"02",X"D5",X"0E",X"10", - X"F3",X"3E",X"02",X"D3",X"6A",X"1A",X"24",X"24",X"77",X"25",X"25",X"B6",X"12",X"3E",X"03",X"D3", - X"6A",X"1A",X"24",X"24",X"77",X"25",X"25",X"B6",X"12",X"23",X"13",X"0D",X"C2",X"91",X"FB",X"3A", - X"FE",X"DF",X"D3",X"6A",X"FB",X"D1",X"14",X"05",X"C2",X"8D",X"FB",X"C3",X"4E",X"FB",X"78",X"C6", - X"F0",X"D8",X"7A",X"C6",X"D1",X"D8",X"7B",X"C6",X"8C",X"D8",X"C5",X"D5",X"E5",X"7B",X"07",X"6F", - X"3E",X"40",X"82",X"67",X"E5",X"CD",X"61",X"FB",X"11",X"00",X"02",X"19",X"EB",X"E1",X"06",X"02", - X"E5",X"0E",X"10",X"F3",X"3E",X"02",X"D3",X"6A",X"1A",X"77",X"3E",X"03",X"D3",X"6A",X"1A",X"77", - X"13",X"23",X"0D",X"C2",X"E4",X"FB",X"3A",X"FE",X"DF",X"D3",X"6A",X"FB",X"E1",X"24",X"05",X"C2", - X"E0",X"FB",X"C3",X"4E",X"FB",X"CD",X"BA",X"F8",X"D8",X"C5",X"D5",X"E5",X"CD",X"34",X"FC",X"CD", - X"BA",X"F8",X"DA",X"30",X"FC",X"78",X"91",X"D4",X"34",X"FC",X"05",X"04",X"CD",X"84",X"F8",X"CD", - X"34",X"FC",X"C5",X"41",X"CD",X"F0",X"F8",X"C1",X"CD",X"34",X"FC",X"4F",X"B8",X"C2",X"1B",X"FC", - X"E1",X"D1",X"C1",X"C9",X"EB",X"78",X"41",X"4F",X"C9",X"CD",X"8A",X"FC",X"D8",X"C5",X"E5",X"E5", - X"7C",X"C6",X"40",X"67",X"47",X"4D",X"CD",X"7A",X"FC",X"DA",X"6C",X"FC",X"F3",X"3E",X"02",X"D3", - X"6A",X"0A",X"77",X"2B",X"77",X"3E",X"03",X"D3",X"6A",X"0A",X"77",X"23",X"77",X"7C",X"25",X"05", - X"D6",X"40",X"92",X"C2",X"4D",X"FC",X"3A",X"FE",X"DF",X"D3",X"6A",X"FB",X"E1",X"7D",X"2D",X"93", - X"C2",X"3F",X"FC",X"E1",X"CD",X"7A",X"FC",X"A7",X"C1",X"C9",X"7D",X"2E",X"F5",X"93",X"07",X"D8", - X"3C",X"83",X"D8",X"C6",X"0A",X"D8",X"D6",X"0A",X"6F",X"C9",X"7A",X"C6",X"D1",X"D8",X"7B",X"C6", - X"0B",X"D8",X"7C",X"C6",X"D0",X"D8",X"7D",X"C6",X"0A",X"D8",X"7C",X"92",X"D8",X"7D",X"93",X"C9", - X"CD",X"8A",X"FC",X"D8",X"C5",X"E5",X"E5",X"7C",X"C6",X"40",X"47",X"4D",X"CD",X"DD",X"FC",X"DA", - X"CF",X"FC",X"7C",X"C6",X"40",X"67",X"D5",X"3E",X"02",X"32",X"D6",X"DF",X"CD",X"EA",X"FC",X"3E", - X"03",X"32",X"D6",X"DF",X"CD",X"EA",X"FC",X"D1",X"7D",X"2D",X"0D",X"93",X"C2",X"B6",X"FC",X"E1", - X"7C",X"25",X"92",X"C2",X"A6",X"FC",X"E1",X"CD",X"DD",X"FC",X"A7",X"C1",X"C9",X"7C",X"92",X"07", - X"3C",X"82",X"67",X"3E",X"2F",X"94",X"D0",X"26",X"2F",X"C9",X"F3",X"E5",X"3A",X"D6",X"DF",X"D3", - X"6A",X"0A",X"21",X"00",X"00",X"16",X"08",X"29",X"29",X"07",X"D2",X"00",X"FD",X"2C",X"2C",X"2C", - X"15",X"C2",X"F7",X"FC",X"55",X"5C",X"3A",X"FE",X"DF",X"D3",X"6A",X"E1",X"3A",X"D6",X"DF",X"D3", - X"6A",X"73",X"25",X"72",X"3A",X"FE",X"DF",X"D3",X"6A",X"24",X"FB",X"C9",X"F5",X"E6",X"04",X"CA", - X"29",X"FD",X"F1",X"3A",X"20",X"DF",X"C3",X"2A",X"FD",X"F1",X"32",X"DC",X"DF",X"C9",X"E5",X"21", - X"39",X"FE",X"C3",X"39",X"FD",X"E5",X"21",X"32",X"FE",X"C5",X"01",X"00",X"20",X"C3",X"42",X"FD", - X"E5",X"C5",X"3E",X"88",X"32",X"FF",X"DF",X"32",X"FA",X"DF",X"79",X"32",X"FD",X"DF",X"3E",X"25", - X"D3",X"79",X"3E",X"A6",X"D3",X"63",X"78",X"D3",X"62",X"3E",X"10",X"D3",X"63",X"3E",X"76",X"D3", - X"63",X"3E",X"C3",X"32",X"04",X"DF",X"22",X"FB",X"DF",X"21",X"71",X"FD",X"22",X"05",X"DF",X"C1", - X"E1",X"F5",X"C5",X"D5",X"E5",X"3A",X"FA",X"DF",X"A7",X"C2",X"94",X"FD",X"3C",X"32",X"FA",X"DF", - X"D3",X"60",X"3E",X"25",X"D3",X"79",X"3E",X"FD",X"D3",X"75",X"3E",X"61",X"D3",X"74",X"FB",X"E1", - X"D1",X"C1",X"F1",X"C9",X"AF",X"32",X"FA",X"DF",X"2A",X"FB",X"DF",X"7E",X"A7",X"C2",X"C6",X"FD", - X"3E",X"FF",X"D3",X"75",X"AF",X"32",X"FF",X"DF",X"3E",X"76",X"D3",X"63",X"3E",X"96",X"D3",X"63", - X"3E",X"0D",X"D3",X"62",X"3E",X"FF",X"D3",X"75",X"3E",X"20",X"D3",X"74",X"21",X"00",X"E0",X"22", - X"05",X"DF",X"FB",X"C3",X"8F",X"FD",X"F2",X"D0",X"FD",X"32",X"FF",X"DF",X"23",X"C3",X"9B",X"FD", - X"E6",X"70",X"0F",X"0F",X"0F",X"0F",X"4F",X"3A",X"FD",X"DF",X"81",X"E6",X"07",X"4F",X"7E",X"23", - X"22",X"FB",X"DF",X"E6",X"0F",X"FE",X"0D",X"F2",X"0E",X"FE",X"3D",X"07",X"5F",X"16",X"00",X"21", - X"1A",X"FE",X"19",X"56",X"23",X"5E",X"0D",X"CA",X"04",X"FE",X"A7",X"7A",X"1F",X"57",X"7B",X"1F", - X"5F",X"C3",X"F6",X"FD",X"7B",X"D3",X"61",X"7A",X"D3",X"61",X"3E",X"05",X"D3",X"79",X"3A",X"FF", - X"DF",X"E6",X"7F",X"07",X"3D",X"D3",X"60",X"C3",X"86",X"FD",X"EE",X"EA",X"E1",X"78",X"D4",X"E0", - X"C8",X"D6",X"BD",X"A0",X"B2",X"FB",X"A8",X"EB",X"9F",X"70",X"96",X"88",X"8E",X"0C",X"86",X"01", - X"7D",X"E1",X"90",X"5B",X"90",X"51",X"A0",X"65",X"00",X"88",X"5B",X"00",X"3E",X"AF",X"D3",X"1A", - X"3E",X"FF",X"D3",X"1B",X"07",X"D3",X"1B",X"07",X"D3",X"1B",X"07",X"D3",X"1B",X"07",X"D3",X"1B", - X"07",X"D3",X"1B",X"07",X"D3",X"1B",X"07",X"D3",X"1B",X"C9",X"3E",X"FF",X"D3",X"1B",X"D3",X"1B", - X"D3",X"1B",X"D3",X"1B",X"D3",X"1B",X"D3",X"1B",X"D3",X"1B",X"D3",X"1B",X"DB",X"1B",X"C9",X"21", - X"00",X"00",X"11",X"00",X"00",X"4F",X"CD",X"40",X"FE",X"79",X"CD",X"42",X"FE",X"7A",X"CD",X"42", - X"FE",X"7B",X"CD",X"42",X"FE",X"7C",X"CD",X"42",X"FE",X"7D",X"CD",X"42",X"FE",X"3E",X"95",X"CD", - X"42",X"FE",X"11",X"80",X"80",X"21",X"20",X"4E",X"CD",X"5A",X"FE",X"4F",X"92",X"BB",X"79",X"D0", - X"2B",X"7C",X"B5",X"C2",X"98",X"FE",X"D6",X"01",X"C9",X"C5",X"D5",X"E5",X"11",X"FF",X"00",X"CD", - X"95",X"FE",X"E1",X"D1",X"C1",X"C9",X"CD",X"3D",X"FE",X"06",X"10",X"CD",X"40",X"FE",X"05",X"C2", - X"BB",X"FE",X"CD",X"3C",X"FE",X"3E",X"40",X"CD",X"6F",X"FE",X"FE",X"01",X"C0",X"3E",X"77",X"CD", - X"6F",X"FE",X"E6",X"FE",X"C0",X"3E",X"69",X"CD",X"6F",X"FE",X"FE",X"01",X"CA",X"CD",X"FE",X"B7", - X"C9",X"CD",X"A9",X"FE",X"D8",X"E5",X"EB",X"29",X"5C",X"65",X"AF",X"57",X"6F",X"3E",X"51",X"CD", - X"75",X"FE",X"E1",X"D8",X"06",X"00",X"E5",X"11",X"01",X"FF",X"CD",X"95",X"FE",X"E1",X"FE",X"FE", - X"C0",X"CD",X"5A",X"FE",X"77",X"23",X"CD",X"5A",X"FE",X"77",X"23",X"05",X"C2",X"01",X"FF",X"C9", - X"3E",X"02",X"D3",X"6A",X"3A",X"80",X"28",X"E6",X"04",X"C0",X"AF",X"D3",X"6A",X"CD",X"24",X"FF", - X"DA",X"3D",X"FE",X"E9",X"CD",X"B6",X"FE",X"37",X"C0",X"11",X"00",X"00",X"21",X"00",X"C0",X"CD", - X"E1",X"FE",X"D8",X"CD",X"42",X"FF",X"D0",X"2A",X"C6",X"C1",X"EB",X"21",X"00",X"C0",X"CD",X"E1", - X"FE",X"D8",X"CD",X"BA",X"FF",X"37",X"C0",X"2A",X"16",X"C0",X"EB",X"2A",X"0E",X"C0",X"3A",X"10", - X"C0",X"19",X"3D",X"C2",X"51",X"FF",X"EB",X"2A",X"1C",X"C0",X"19",X"22",X"F0",X"C1",X"EB",X"2A", - X"11",X"C0",X"4D",X"44",X"29",X"29",X"29",X"29",X"E5",X"79",X"E6",X"0F",X"C5",X"CC",X"9E",X"FF", - X"D5",X"E5",X"06",X"0B",X"11",X"CB",X"FF",X"1A",X"BE",X"C2",X"AA",X"FF",X"13",X"23",X"05",X"C2", - X"77",X"FF",X"C1",X"C1",X"C1",X"11",X"0F",X"00",X"19",X"5E",X"23",X"56",X"1B",X"1B",X"2A",X"F0", - X"C1",X"3A",X"0D",X"C0",X"19",X"3D",X"C2",X"94",X"FF",X"D1",X"5A",X"57",X"19",X"EB",X"D5",X"21", - X"00",X"C2",X"E5",X"CD",X"E1",X"FE",X"E1",X"D1",X"13",X"C9",X"E1",X"11",X"20",X"00",X"19",X"D1", - X"C1",X"0B",X"78",X"B1",X"C2",X"69",X"FF",X"C1",X"37",X"C9",X"21",X"36",X"C0",X"7E",X"23",X"FE", - X"46",X"C0",X"7E",X"23",X"FE",X"41",X"C0",X"7E",X"FE",X"54",X"C9",X"42",X"4F",X"4F",X"54",X"20", - X"20",X"20",X"20",X"52",X"4F",X"4D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"59",X"2C",X"2C",X"2D",X"DE",X"E8",X"D8", - X"D1",X"DA",X"D0",X"20",X"D7",X"D0",X"D3",X"E0",X"E3",X"D7",X"DA",X"D8",X"2D",X"00",X"FF",X"F6"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd b/Computer_MiST/Bashkiria2M_MiST/rtl/dac.vhd similarity index 97% rename from Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd rename to Computer_MiST/Bashkiria2M_MiST/rtl/dac.vhd index db58d70b..2c0b2e17 100644 --- a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Invaders 2_MiST/rtl/dac.vhd +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/dac.vhd @@ -20,7 +20,7 @@ library ieee; entity dac is generic ( - C_bits : integer := 8 + C_bits : integer := 16 ); port ( clk_i : in std_logic; diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/mist_io.v b/Computer_MiST/Bashkiria2M_MiST/rtl/mist_io.v new file mode 100644 index 00000000..1f607b62 --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/mist_io.v @@ -0,0 +1,511 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + output reg sd_dout_strobe, + output reg sd_din_strobe, + + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + sd_dout_strobe <= 0; + sd_din_strobe <= 0; + + end else begin + b_wr2 <= 0; + sd_dout_strobe <= 0; + sd_din_strobe <= 0; + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) begin + b_data <= sd_buff_din; + sd_din_strobe <= 1'b1; + mount_strobe <= 0; + end + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19: begin + // flag that download begins + sd_buff_dout <= spi_dout; + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + sd_dout_strobe <= 1; + end + + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + sd_dout_strobe <= 1; + b_wr2 <= 1; + end + + 8'h18: begin + b_data <= sd_buff_din; + sd_din_strobe <= 1; + end + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/osd.v b/Computer_MiST/Bashkiria2M_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/scandoubler.v b/Computer_MiST/Bashkiria2M_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..0213d20c --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/scandoubler.v @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/unused/I2C_AV_Config.v b/Computer_MiST/Bashkiria2M_MiST/rtl/unused/I2C_AV_Config.v new file mode 100644 index 00000000..09c0b9f2 --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/unused/I2C_AV_Config.v @@ -0,0 +1,141 @@ +//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +module I2C_AV_Config ( // Host Side + iCLK, + iRST_N, + // I2C Side + I2C_SCLK, + I2C_SDAT ); +// Host Side +input iCLK; +input iRST_N; +// I2C Side +output I2C_SCLK; +inout I2C_SDAT; +// Internal Registers/Wires +reg [15:0] mI2C_CLK_DIV; +reg [23:0] mI2C_DATA; +reg mI2C_CTRL_CLK; +reg mI2C_GO; +wire mI2C_END; +wire mI2C_ACK; +reg [15:0] LUT_DATA; +reg [3:0] LUT_INDEX; +reg [1:0] mSetup_ST; + +// Clock Setting +parameter CLK_Freq = 50000000; // 50 MHz +parameter I2C_Freq = 20000; // 20 KHz +// LUT Data Number +parameter LUT_SIZE = 11; +// Audio Data Index +parameter Dummy_DATA = 0; +parameter SET_LIN_L = 1; +parameter SET_LIN_R = 2; +parameter SET_HEAD_L = 3; +parameter SET_HEAD_R = 4; +parameter A_PATH_CTRL = 5; +parameter D_PATH_CTRL = 6; +parameter POWER_ON = 7; +parameter SET_FORMAT = 8; +parameter SAMPLE_CTRL = 9; +parameter SET_ACTIVE = 10; + +///////////////////// I2C Control Clock //////////////////////// +always@(posedge iCLK or negedge iRST_N) +begin + if(!iRST_N) + begin + mI2C_CTRL_CLK <= 0; + mI2C_CLK_DIV <= 0; + end + else + begin + if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) ) + mI2C_CLK_DIV <= mI2C_CLK_DIV+16'b1; + else + begin + mI2C_CLK_DIV <= 0; + mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; + end + end +end +//////////////////////////////////////////////////////////////////// +I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock + .I2C_SCLK(I2C_SCLK), // I2C CLOCK + .I2C_SDAT(I2C_SDAT), // I2C DATA + .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] + .GO(mI2C_GO), // GO transfor + .END(mI2C_END), // END transfor + .ACK(mI2C_ACK), // ACK + .RESET(iRST_N) ); +//////////////////////////////////////////////////////////////////// +////////////////////// Config Control //////////////////////////// +always@(posedge mI2C_CTRL_CLK or negedge iRST_N) +begin + if(!iRST_N) + begin + LUT_INDEX <= 0; + mSetup_ST <= 0; + mI2C_GO <= 0; + end + else + begin + if(LUT_INDEX= 4) & (SD_COUNTER <=30))? ~CLOCK :1'b0 ); +wire I2C_SDAT=SDO?1'bz:1'b0; + +reg ACK1,ACK2,ACK3; +wire ACK=ACK1 | ACK2 |ACK3; + +//--I2C COUNTER +always @(negedge RESET or posedge CLOCK ) begin +if (!RESET) SD_COUNTER=6'b111111; +else begin +if (GO==0) + SD_COUNTER=0; + else + if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+6'b1; +end +end +//---- + +always @(negedge RESET or posedge CLOCK ) begin +if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end +else +case (SD_COUNTER) + 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end + //start + 6'd1 : begin SD=I2C_DATA;SDO=0;end + 6'd2 : SCLK=0; + //SLAVE ADDR + 6'd3 : SDO=SD[23]; + 6'd4 : SDO=SD[22]; + 6'd5 : SDO=SD[21]; + 6'd6 : SDO=SD[20]; + 6'd7 : SDO=SD[19]; + 6'd8 : SDO=SD[18]; + 6'd9 : SDO=SD[17]; + 6'd10 : SDO=SD[16]; + 6'd11 : SDO=1'b1;//ACK + + //SUB ADDR + 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end + 6'd13 : SDO=SD[14]; + 6'd14 : SDO=SD[13]; + 6'd15 : SDO=SD[12]; + 6'd16 : SDO=SD[11]; + 6'd17 : SDO=SD[10]; + 6'd18 : SDO=SD[9]; + 6'd19 : SDO=SD[8]; + 6'd20 : SDO=1'b1;//ACK + + //DATA + 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end + 6'd22 : SDO=SD[6]; + 6'd23 : SDO=SD[5]; + 6'd24 : SDO=SD[4]; + 6'd25 : SDO=SD[3]; + 6'd26 : SDO=SD[2]; + 6'd27 : SDO=SD[1]; + 6'd28 : SDO=SD[0]; + 6'd29 : SDO=1'b1;//ACK + + + //stop + 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end + 6'd31 : SCLK=1'b1; + 6'd32 : begin SDO=1'b1; END=1; end + +endcase +end + + + +endmodule diff --git a/Computer_MiST/Bashkiria2M_MiST/rtl/video_mixer.sv b/Computer_MiST/Bashkiria2M_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Computer_MiST/Bashkiria2M_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Computer_MiST/CCE - Color Computer_MiST/Snapshot/CCE_CC_MiST.rbf b/Computer_MiST/CCE - Color Computer_MiST/Snapshot/CCE_CC_MiST.rbf deleted file mode 100644 index 81ac8219..00000000 Binary files a/Computer_MiST/CCE - Color Computer_MiST/Snapshot/CCE_CC_MiST.rbf and /dev/null differ diff --git a/Computer_MiST/Commodore - Pet2001_MiST/release/Pet2001.rbf b/Computer_MiST/Commodore - Pet2001_MiST/release/Pet2001.rbf deleted file mode 100644 index 5a5844d3..00000000 Binary files a/Computer_MiST/Commodore - Pet2001_MiST/release/Pet2001.rbf and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf b/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf deleted file mode 100644 index 14500238..00000000 Binary files a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf and /dev/null differ diff --git a/Computer_MiST/ITCI - Cobra_MiST/snapshot/Cobra_MiST.rbf b/Computer_MiST/ITCI - Cobra_MiST/snapshot/Cobra_MiST.rbf deleted file mode 100644 index fcdf9eaa..00000000 Binary files a/Computer_MiST/ITCI - Cobra_MiST/snapshot/Cobra_MiST.rbf and /dev/null differ diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf deleted file mode 100644 index b9b8fa09..00000000 Binary files a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf and /dev/null differ diff --git a/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf b/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf deleted file mode 100644 index 519d8dab..00000000 Binary files a/Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf and /dev/null differ diff --git a/Computer_MiST/ORAO_MiST/snapshot/Orao_MiST.rbf b/Computer_MiST/ORAO_MiST/snapshot/Orao_MiST.rbf deleted file mode 100644 index d1ecd465..00000000 Binary files a/Computer_MiST/ORAO_MiST/snapshot/Orao_MiST.rbf and /dev/null differ diff --git a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.0).rbf b/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.0).rbf deleted file mode 100644 index 980c48f3..00000000 Binary files a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.0).rbf and /dev/null differ diff --git a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.1uk).rbf b/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.1uk).rbf deleted file mode 100644 index e047be3c..00000000 Binary files a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.1uk).rbf and /dev/null differ diff --git a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.22uk).rbf b/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.22uk).rbf deleted file mode 100644 index 21a57b0b..00000000 Binary files a/Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST(Rom1.22uk).rbf and /dev/null differ diff --git a/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87(64kb SDRAM).rbf b/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87(64kb SDRAM).rbf deleted file mode 100644 index f8b5630c..00000000 Binary files a/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87(64kb SDRAM).rbf and /dev/null differ diff --git a/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87.rbf b/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87.rbf deleted file mode 100644 index 1b210558..00000000 Binary files a/Computer_MiST/Robotron - KC87_MiST/snapshot/kc87.rbf and /dev/null differ diff --git a/Computer_MiST/Robotron - Z1013_MiST/Snapshot/Z1013_Mist.rbf b/Computer_MiST/Robotron - Z1013_MiST/Snapshot/Z1013_Mist.rbf deleted file mode 100644 index 60298887..00000000 Binary files a/Computer_MiST/Robotron - Z1013_MiST/Snapshot/Z1013_Mist.rbf and /dev/null differ diff --git a/Computer_MiST/Sharp - MZ-80_MiST/Release/mz80k_mist.rbf b/Computer_MiST/Sharp - MZ-80_MiST/Release/mz80k_mist.rbf deleted file mode 100644 index 6b8d9ebf..00000000 Binary files a/Computer_MiST/Sharp - MZ-80_MiST/Release/mz80k_mist.rbf and /dev/null differ diff --git a/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf b/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf deleted file mode 100644 index 6601e8c9..00000000 Binary files a/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf and /dev/null differ diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd b/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd new file mode 100644 index 00000000..83d1861e --- /dev/null +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 9 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv index b6d0c05a..c2f81503 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv @@ -29,10 +29,6 @@ module vectrex_mist output SDRAM_CKE ); -assign LED = !ioctl_downl; -assign AUDIO_R = AUDIO_L; -assign SDRAM_CLK = clk_24; - `include "rtl\build_id.v" localparam CONF_STR = { @@ -48,16 +44,6 @@ localparam CONF_STR = { "V,v1.50.",`BUILD_DATE }; -wire clk_24, clk_12; -wire pll_locked; -pll pll ( - .inclk0 ( CLOCK_27 ), - .areset ( 0 ), - .c0 ( clk_24 ), - .c1 ( clk_12 ), - .locked ( pll_locked ) - ); - wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; @@ -77,19 +63,38 @@ wire hb, vb; wire blankn = ~(hb | vb); wire cart_rd; wire [14:0] cart_addr; -wire [15:0] cart_do; +wire [7:0] cart_do; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; -sdram cart( + +assign LED = !ioctl_downl; + +wire clk_24, clk_12; +wire pll_locked; + +pll pll ( + .inclk0 ( CLOCK_27 ), + .areset ( 0 ), + .c0 ( clk_24 ), + .c1 ( clk_12 ), + .locked ( pll_locked ) + ); + +assign SDRAM_CLK = clk_24; +wire [15:0] sdram_do; +assign cart_do = sdram_do[7:0]; + +sdram cart +( .*, .init(~pll_locked), .clk(clk_24), .wtbt(2'b00), - .dout(cart_do), + .dout(sdram_do), .din ({ioctl_dout, ioctl_dout}), .addr(ioctl_downl ? ioctl_addr : cart_addr), .we(ioctl_downl & ioctl_wr), @@ -126,24 +131,24 @@ assign pot_x_2 = status[4] ? joy_ana_0[15:8] : joy_ana_1[15:8]; assign pot_y_1 = status[4] ? ~joy_ana_1[ 7:0] : ~joy_ana_0[ 7:0]; assign pot_y_2 = status[4] ? ~joy_ana_0[ 7:0] : ~joy_ana_1[ 7:0]; -vectrex vectrex( +vectrex vectrex ( .clock_24 ( clk_24 ), .clock_12 ( clk_12 ), .reset ( reset ), - .cpu ( status[1] ), + .cpu ( status[1] ), .video_r ( rr ), .video_g ( gg ), .video_b ( bb ), .video_csync ( cs ), .video_hblank ( hb ), .video_vblank ( vb ), - .speech_mode ( status[5] ), + .speech_mode ( status[5] ), .video_hs ( hs ), .video_vs ( vs ), .frame ( frame_line ), .audio_out ( audio ), .cart_addr ( cart_addr ), - .cart_do ( cart_do[7:0] ), + .cart_do ( cart_do ), .cart_rd ( cart_rd ), .btn11 ( status[4] ? joystick_1[4] : joystick_0[4]), .btn12 ( status[4] ? joystick_1[5] : joystick_0[5]), @@ -156,17 +161,18 @@ vectrex vectrex( .btn23 ( status[4] ? joystick_0[6] : joystick_1[6]), .btn24 ( status[4] ? joystick_0[7] : joystick_1[7]), .pot_x_2 ( pot_x_2 ), - .pot_y_2 ( pot_y_2 ) + .pot_y_2 ( pot_y_2 ), + .leds ( ), + .dbg_cpu_addr ( ) ); - -dac #( - .C_bits(10)) -dac( - .clk_i( clk_24 ), - .res_n_i( 1'b1 ), - .dac_i( audio ), - .dac_o( AUDIO_L ) + +dac dac ( + .clk_i ( clk_24 ), + .res_n_i ( 1 ), + .dac_i ( audio ), + .dac_o ( AUDIO_L ) ); +assign AUDIO_R = AUDIO_L; ////////////////// VIDEO ////////////////// @@ -183,7 +189,6 @@ mist_video #(.COLOR_DEPTH(4)) mist_video .SPI_DI(SPI_DI), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), - .ce_divider(1'b1), .scandoubler_disable(1), .rotate(2'b00), .ypbpr(ypbpr), @@ -193,7 +198,7 @@ mist_video #(.COLOR_DEPTH(4)) mist_video .G(g), .B(b), .VGA_HS(VGA_HS), - .VGA_VS(VGA_VS), + .VGA_VS(VGS_VS), .VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B) diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.sdc b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc similarity index 100% rename from Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.sdc rename to Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf index 89fde081..25908bfe 100644 --- a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf +++ b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf @@ -344,20 +344,22 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON set_global_assignment -name USE_SIGNALTAP_FILE output_files/sdram.stp +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/vectrex.vhd set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd set_global_assignment -name VHDL_FILE rtl/m6522a.vhd set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VERILOG_FILE rtl/mc6809is.v set_global_assignment -name VERILOG_FILE rtl/mc6809.v set_global_assignment -name VHDL_FILE rtl/sp0256.vhd set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/common/CPU/68000/FX68k/LICENSE b/common/CPU/68000/FX68k/LICENSE deleted file mode 100644 index f288702d..00000000 --- a/common/CPU/68000/FX68k/LICENSE +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. By contrast, -the GNU General Public License is intended to guarantee your freedom to -share and change all versions of a program--to make sure it remains free -software for all its users. We, the Free Software Foundation, use the -GNU General Public License for most of our software; it applies also to -any other work released this way by its authors. You can apply it to -your programs, too. - - When we speak of free software, we are referring to freedom, not -price. Our General Public Licenses are designed to make sure that you -have the freedom to distribute copies of free software (and charge for -them if you wish), that you receive source code or can get it if you -want it, that you can change the software or use pieces of it in new -free programs, and that you know you can do these things. - - To protect your rights, we need to prevent others from denying you -these rights or asking you to surrender the rights. Therefore, you have -certain responsibilities if you distribute copies of the software, or if -you modify it: responsibilities to respect the freedom of others. - - For example, if you distribute copies of such a program, whether -gratis or for a fee, you must pass on to the recipients the same -freedoms that you received. You must make sure that they, too, receive -or can get the source code. And you must show them these terms so they -know their rights. - - Developers that use the GNU GPL protect your rights with two steps: -(1) assert copyright on the software, and (2) offer you this License -giving you legal permission to copy, distribute and/or modify it. - - For the developers' and authors' protection, the GPL clearly explains -that there is no warranty for this free software. For both users' and -authors' sake, the GPL requires that modified versions be marked as -changed, so that their problems will not be attributed erroneously to -authors of previous versions. - - Some devices are designed to deny users access to install or run -modified versions of the software inside them, although the manufacturer -can do so. This is fundamentally incompatible with the aim of -protecting users' freedom to change the software. The systematic -pattern of such abuse occurs in the area of products for individuals to -use, which is precisely where it is most unacceptable. Therefore, we -have designed this version of the GPL to prohibit the practice for those -products. If such problems arise substantially in other domains, we -stand ready to extend this provision to those domains in future versions -of the GPL, as needed to protect the freedom of users. - - Finally, every program is threatened constantly by software patents. -States should not allow patents to restrict development and use of -software on general-purpose computers, but in those that do, we wish to -avoid the special danger that patents applied to a free program could -make it effectively proprietary. To prevent this, the GPL assures that -patents cannot be used to render the program non-free. - - The precise terms and conditions for copying, distribution and -modification follow. - - TERMS AND CONDITIONS - - 0. Definitions. - - "This License" refers to version 3 of the GNU General Public License. - - "Copyright" also means copyright-like laws that apply to other kinds of -works, such as semiconductor masks. - - "The Program" refers to any copyrightable work licensed under this -License. Each licensee is addressed as "you". "Licensees" and -"recipients" may be individuals or organizations. - - To "modify" a work means to copy from or adapt all or part of the work -in a fashion requiring copyright permission, other than the making of an -exact copy. The resulting work is called a "modified version" of the -earlier work or a work "based on" the earlier work. - - A "covered work" means either the unmodified Program or a work based -on the Program. - - To "propagate" a work means to do anything with it that, without -permission, would make you directly or secondarily liable for -infringement under applicable copyright law, except executing it on a -computer or modifying a private copy. Propagation includes copying, -distribution (with or without modification), making available to the -public, and in some countries other activities as well. - - To "convey" a work means any kind of propagation that enables other -parties to make or receive copies. Mere interaction with a user through -a computer network, with no transfer of a copy, is not conveying. - - An interactive user interface displays "Appropriate Legal Notices" -to the extent that it includes a convenient and prominently visible -feature that (1) displays an appropriate copyright notice, and (2) -tells the user that there is no warranty for the work (except to the -extent that warranties are provided), that licensees may convey the -work under this License, and how to view a copy of this License. If -the interface presents a list of user commands or options, such as a -menu, a prominent item in the list meets this criterion. - - 1. Source Code. - - The "source code" for a work means the preferred form of the work -for making modifications to it. "Object code" means any non-source -form of a work. - - A "Standard Interface" means an interface that either is an official -standard defined by a recognized standards body, or, in the case of -interfaces specified for a particular programming language, one that -is widely used among developers working in that language. - - The "System Libraries" of an executable work include anything, other -than the work as a whole, that (a) is included in the normal form of -packaging a Major Component, but which is not part of that Major -Component, and (b) serves only to enable use of the work with that -Major Component, or to implement a Standard Interface for which an -implementation is available to the public in source code form. A -"Major Component", in this context, means a major essential component -(kernel, window system, and so on) of the specific operating system -(if any) on which the executable work runs, or a compiler used to -produce the work, or an object code interpreter used to run it. - - The "Corresponding Source" for a work in object code form means all -the source code needed to generate, install, and (for an executable -work) run the object code and to modify the work, including scripts to -control those activities. However, it does not include the work's -System Libraries, or general-purpose tools or generally available free -programs which are used unmodified in performing those activities but -which are not part of the work. For example, Corresponding Source -includes interface definition files associated with source files for -the work, and the source code for shared libraries and dynamically -linked subprograms that the work is specifically designed to require, -such as by intimate data communication or control flow between those -subprograms and other parts of the work. - - The Corresponding Source need not include anything that users -can regenerate automatically from other parts of the Corresponding -Source. - - The Corresponding Source for a work in source code form is that -same work. - - 2. Basic Permissions. - - All rights granted under this License are granted for the term of -copyright on the Program, and are irrevocable provided the stated -conditions are met. This License explicitly affirms your unlimited -permission to run the unmodified Program. The output from running a -covered work is covered by this License only if the output, given its -content, constitutes a covered work. This License acknowledges your -rights of fair use or other equivalent, as provided by copyright law. - - You may make, run and propagate covered works that you do not -convey, without conditions so long as your license otherwise remains -in force. You may convey covered works to others for the sole purpose -of having them make modifications exclusively for you, or provide you -with facilities for running those works, provided that you comply with -the terms of this License in conveying all material for which you do -not control copyright. Those thus making or running the covered works -for you must do so exclusively on your behalf, under your direction -and control, on terms that prohibit them from making any copies of -your copyrighted material outside their relationship with you. - - Conveying under any other circumstances is permitted solely under -the conditions stated below. Sublicensing is not allowed; section 10 -makes it unnecessary. - - 3. Protecting Users' Legal Rights From Anti-Circumvention Law. - - No covered work shall be deemed part of an effective technological -measure under any applicable law fulfilling obligations under article -11 of the WIPO copyright treaty adopted on 20 December 1996, or -similar laws prohibiting or restricting circumvention of such -measures. - - When you convey a covered work, you waive any legal power to forbid -circumvention of technological measures to the extent such circumvention -is effected by exercising rights under this License with respect to -the covered work, and you disclaim any intention to limit operation or -modification of the work as a means of enforcing, against the work's -users, your or third parties' legal rights to forbid circumvention of -technological measures. - - 4. Conveying Verbatim Copies. - - You may convey verbatim copies of the Program's source code as you -receive it, in any medium, provided that you conspicuously and -appropriately publish on each copy an appropriate copyright notice; -keep intact all notices stating that this License and any -non-permissive terms added in accord with section 7 apply to the code; -keep intact all notices of the absence of any warranty; and give all -recipients a copy of this License along with the Program. - - You may charge any price or no price for each copy that you convey, -and you may offer support or warranty protection for a fee. - - 5. Conveying Modified Source Versions. - - You may convey a work based on the Program, or the modifications to -produce it from the Program, in the form of source code under the -terms of section 4, provided that you also meet all of these conditions: - - a) The work must carry prominent notices stating that you modified - it, and giving a relevant date. - - b) The work must carry prominent notices stating that it is - released under this License and any conditions added under section - 7. This requirement modifies the requirement in section 4 to - "keep intact all notices". - - c) You must license the entire work, as a whole, under this - License to anyone who comes into possession of a copy. This - License will therefore apply, along with any applicable section 7 - additional terms, to the whole of the work, and all its parts, - regardless of how they are packaged. This License gives no - permission to license the work in any other way, but it does not - invalidate such permission if you have separately received it. - - d) If the work has interactive user interfaces, each must display - Appropriate Legal Notices; however, if the Program has interactive - interfaces that do not display Appropriate Legal Notices, your - work need not make them do so. - - A compilation of a covered work with other separate and independent -works, which are not by their nature extensions of the covered work, -and which are not combined with it such as to form a larger program, -in or on a volume of a storage or distribution medium, is called an -"aggregate" if the compilation and its resulting copyright are not -used to limit the access or legal rights of the compilation's users -beyond what the individual works permit. Inclusion of a covered work -in an aggregate does not cause this License to apply to the other -parts of the aggregate. - - 6. Conveying Non-Source Forms. - - You may convey a covered work in object code form under the terms -of sections 4 and 5, provided that you also convey the -machine-readable Corresponding Source under the terms of this License, -in one of these ways: - - a) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by the - Corresponding Source fixed on a durable physical medium - customarily used for software interchange. - - b) Convey the object code in, or embodied in, a physical product - (including a physical distribution medium), accompanied by a - written offer, valid for at least three years and valid for as - long as you offer spare parts or customer support for that product - model, to give anyone who possesses the object code either (1) a - copy of the Corresponding Source for all the software in the - product that is covered by this License, on a durable physical - medium customarily used for software interchange, for a price no - more than your reasonable cost of physically performing this - conveying of source, or (2) access to copy the - Corresponding Source from a network server at no charge. - - c) Convey individual copies of the object code with a copy of the - written offer to provide the Corresponding Source. This - alternative is allowed only occasionally and noncommercially, and - only if you received the object code with such an offer, in accord - with subsection 6b. - - d) Convey the object code by offering access from a designated - place (gratis or for a charge), and offer equivalent access to the - Corresponding Source in the same way through the same place at no - further charge. You need not require recipients to copy the - Corresponding Source along with the object code. If the place to - copy the object code is a network server, the Corresponding Source - may be on a different server (operated by you or a third party) - that supports equivalent copying facilities, provided you maintain - clear directions next to the object code saying where to find the - Corresponding Source. Regardless of what server hosts the - Corresponding Source, you remain obligated to ensure that it is - available for as long as needed to satisfy these requirements. - - e) Convey the object code using peer-to-peer transmission, provided - you inform other peers where the object code and Corresponding - Source of the work are being offered to the general public at no - charge under subsection 6d. - - A separable portion of the object code, whose source code is excluded -from the Corresponding Source as a System Library, need not be -included in conveying the object code work. - - A "User Product" is either (1) a "consumer product", which means any -tangible personal property which is normally used for personal, family, -or household purposes, or (2) anything designed or sold for incorporation -into a dwelling. In determining whether a product is a consumer product, -doubtful cases shall be resolved in favor of coverage. For a particular -product received by a particular user, "normally used" refers to a -typical or common use of that class of product, regardless of the status -of the particular user or of the way in which the particular user -actually uses, or expects or is expected to use, the product. A product -is a consumer product regardless of whether the product has substantial -commercial, industrial or non-consumer uses, unless such uses represent -the only significant mode of use of the product. - - "Installation Information" for a User Product means any methods, -procedures, authorization keys, or other information required to install -and execute modified versions of a covered work in that User Product from -a modified version of its Corresponding Source. The information must -suffice to ensure that the continued functioning of the modified object -code is in no case prevented or interfered with solely because -modification has been made. - - If you convey an object code work under this section in, or with, or -specifically for use in, a User Product, and the conveying occurs as -part of a transaction in which the right of possession and use of the -User Product is transferred to the recipient in perpetuity or for a -fixed term (regardless of how the transaction is characterized), the -Corresponding Source conveyed under this section must be accompanied -by the Installation Information. But this requirement does not apply -if neither you nor any third party retains the ability to install -modified object code on the User Product (for example, the work has -been installed in ROM). - - The requirement to provide Installation Information does not include a -requirement to continue to provide support service, warranty, or updates -for a work that has been modified or installed by the recipient, or for -the User Product in which it has been modified or installed. Access to a -network may be denied when the modification itself materially and -adversely affects the operation of the network or violates the rules and -protocols for communication across the network. - - Corresponding Source conveyed, and Installation Information provided, -in accord with this section must be in a format that is publicly -documented (and with an implementation available to the public in -source code form), and must require no special password or key for -unpacking, reading or copying. - - 7. Additional Terms. - - "Additional permissions" are terms that supplement the terms of this -License by making exceptions from one or more of its conditions. -Additional permissions that are applicable to the entire Program shall -be treated as though they were included in this License, to the extent -that they are valid under applicable law. If additional permissions -apply only to part of the Program, that part may be used separately -under those permissions, but the entire Program remains governed by -this License without regard to the additional permissions. - - When you convey a copy of a covered work, you may at your option -remove any additional permissions from that copy, or from any part of -it. (Additional permissions may be written to require their own -removal in certain cases when you modify the work.) You may place -additional permissions on material, added by you to a covered work, -for which you have or can give appropriate copyright permission. - - Notwithstanding any other provision of this License, for material you -add to a covered work, you may (if authorized by the copyright holders of -that material) supplement the terms of this License with terms: - - a) Disclaiming warranty or limiting liability differently from the - terms of sections 15 and 16 of this License; or - - b) Requiring preservation of specified reasonable legal notices or - author attributions in that material or in the Appropriate Legal - Notices displayed by works containing it; or - - c) Prohibiting misrepresentation of the origin of that material, or - requiring that modified versions of such material be marked in - reasonable ways as different from the original version; or - - d) Limiting the use for publicity purposes of names of licensors or - authors of the material; or - - e) Declining to grant rights under trademark law for use of some - trade names, trademarks, or service marks; or - - f) Requiring indemnification of licensors and authors of that - material by anyone who conveys the material (or modified versions of - it) with contractual assumptions of liability to the recipient, for - any liability that these contractual assumptions directly impose on - those licensors and authors. - - All other non-permissive additional terms are considered "further -restrictions" within the meaning of section 10. If the Program as you -received it, or any part of it, contains a notice stating that it is -governed by this License along with a term that is a further -restriction, you may remove that term. If a license document contains -a further restriction but permits relicensing or conveying under this -License, you may add to a covered work material governed by the terms -of that license document, provided that the further restriction does -not survive such relicensing or conveying. - - If you add terms to a covered work in accord with this section, you -must place, in the relevant source files, a statement of the -additional terms that apply to those files, or a notice indicating -where to find the applicable terms. - - Additional terms, permissive or non-permissive, may be stated in the -form of a separately written license, or stated as exceptions; -the above requirements apply either way. - - 8. Termination. - - You may not propagate or modify a covered work except as expressly -provided under this License. Any attempt otherwise to propagate or -modify it is void, and will automatically terminate your rights under -this License (including any patent licenses granted under the third -paragraph of section 11). - - However, if you cease all violation of this License, then your -license from a particular copyright holder is reinstated (a) -provisionally, unless and until the copyright holder explicitly and -finally terminates your license, and (b) permanently, if the copyright -holder fails to notify you of the violation by some reasonable means -prior to 60 days after the cessation. - - Moreover, your license from a particular copyright holder is -reinstated permanently if the copyright holder notifies you of the -violation by some reasonable means, this is the first time you have -received notice of violation of this License (for any work) from that -copyright holder, and you cure the violation prior to 30 days after -your receipt of the notice. - - Termination of your rights under this section does not terminate the -licenses of parties who have received copies or rights from you under -this License. If your rights have been terminated and not permanently -reinstated, you do not qualify to receive new licenses for the same -material under section 10. - - 9. Acceptance Not Required for Having Copies. - - You are not required to accept this License in order to receive or -run a copy of the Program. Ancillary propagation of a covered work -occurring solely as a consequence of using peer-to-peer transmission -to receive a copy likewise does not require acceptance. However, -nothing other than this License grants you permission to propagate or -modify any covered work. These actions infringe copyright if you do -not accept this License. Therefore, by modifying or propagating a -covered work, you indicate your acceptance of this License to do so. - - 10. Automatic Licensing of Downstream Recipients. - - Each time you convey a covered work, the recipient automatically -receives a license from the original licensors, to run, modify and -propagate that work, subject to this License. You are not responsible -for enforcing compliance by third parties with this License. - - An "entity transaction" is a transaction transferring control of an -organization, or substantially all assets of one, or subdividing an -organization, or merging organizations. If propagation of a covered -work results from an entity transaction, each party to that -transaction who receives a copy of the work also receives whatever -licenses to the work the party's predecessor in interest had or could -give under the previous paragraph, plus a right to possession of the -Corresponding Source of the work from the predecessor in interest, if -the predecessor has it or can get it with reasonable efforts. - - You may not impose any further restrictions on the exercise of the -rights granted or affirmed under this License. For example, you may -not impose a license fee, royalty, or other charge for exercise of -rights granted under this License, and you may not initiate litigation -(including a cross-claim or counterclaim in a lawsuit) alleging that -any patent claim is infringed by making, using, selling, offering for -sale, or importing the Program or any portion of it. - - 11. Patents. - - A "contributor" is a copyright holder who authorizes use under this -License of the Program or a work on which the Program is based. The -work thus licensed is called the contributor's "contributor version". - - A contributor's "essential patent claims" are all patent claims -owned or controlled by the contributor, whether already acquired or -hereafter acquired, that would be infringed by some manner, permitted -by this License, of making, using, or selling its contributor version, -but do not include claims that would be infringed only as a -consequence of further modification of the contributor version. For -purposes of this definition, "control" includes the right to grant -patent sublicenses in a manner consistent with the requirements of -this License. - - Each contributor grants you a non-exclusive, worldwide, royalty-free -patent license under the contributor's essential patent claims, to -make, use, sell, offer for sale, import and otherwise run, modify and -propagate the contents of its contributor version. - - In the following three paragraphs, a "patent license" is any express -agreement or commitment, however denominated, not to enforce a patent -(such as an express permission to practice a patent or covenant not to -sue for patent infringement). To "grant" such a patent license to a -party means to make such an agreement or commitment not to enforce a -patent against the party. - - If you convey a covered work, knowingly relying on a patent license, -and the Corresponding Source of the work is not available for anyone -to copy, free of charge and under the terms of this License, through a -publicly available network server or other readily accessible means, -then you must either (1) cause the Corresponding Source to be so -available, or (2) arrange to deprive yourself of the benefit of the -patent license for this particular work, or (3) arrange, in a manner -consistent with the requirements of this License, to extend the patent -license to downstream recipients. "Knowingly relying" means you have -actual knowledge that, but for the patent license, your conveying the -covered work in a country, or your recipient's use of the covered work -in a country, would infringe one or more identifiable patents in that -country that you have reason to believe are valid. - - If, pursuant to or in connection with a single transaction or -arrangement, you convey, or propagate by procuring conveyance of, a -covered work, and grant a patent license to some of the parties -receiving the covered work authorizing them to use, propagate, modify -or convey a specific copy of the covered work, then the patent license -you grant is automatically extended to all recipients of the covered -work and works based on it. - - A patent license is "discriminatory" if it does not include within -the scope of its coverage, prohibits the exercise of, or is -conditioned on the non-exercise of one or more of the rights that are -specifically granted under this License. You may not convey a covered -work if you are a party to an arrangement with a third party that is -in the business of distributing software, under which you make payment -to the third party based on the extent of your activity of conveying -the work, and under which the third party grants, to any of the -parties who would receive the covered work from you, a discriminatory -patent license (a) in connection with copies of the covered work -conveyed by you (or copies made from those copies), or (b) primarily -for and in connection with specific products or compilations that -contain the covered work, unless you entered into that arrangement, -or that patent license was granted, prior to 28 March 2007. - - Nothing in this License shall be construed as excluding or limiting -any implied license or other defenses to infringement that may -otherwise be available to you under applicable patent law. - - 12. No Surrender of Others' Freedom. - - If conditions are imposed on you (whether by court order, agreement or -otherwise) that contradict the conditions of this License, they do not -excuse you from the conditions of this License. If you cannot convey a -covered work so as to satisfy simultaneously your obligations under this -License and any other pertinent obligations, then as a consequence you may -not convey it at all. For example, if you agree to terms that obligate you -to collect a royalty for further conveying from those to whom you convey -the Program, the only way you could satisfy both those terms and this -License would be to refrain entirely from conveying the Program. - - 13. Use with the GNU Affero General Public License. - - Notwithstanding any other provision of this License, you have -permission to link or combine any covered work with a work licensed -under version 3 of the GNU Affero General Public License into a single -combined work, and to convey the resulting work. The terms of this -License will continue to apply to the part which is the covered work, -but the special requirements of the GNU Affero General Public License, -section 13, concerning interaction through a network will apply to the -combination as such. - - 14. Revised Versions of this License. - - The Free Software Foundation may publish revised and/or new versions of -the GNU General Public License from time to time. Such new versions will -be similar in spirit to the present version, but may differ in detail to -address new problems or concerns. - - Each version is given a distinguishing version number. If the -Program specifies that a certain numbered version of the GNU General -Public License "or any later version" applies to it, you have the -option of following the terms and conditions either of that numbered -version or of any later version published by the Free Software -Foundation. If the Program does not specify a version number of the -GNU General Public License, you may choose any version ever published -by the Free Software Foundation. - - If the Program specifies that a proxy can decide which future -versions of the GNU General Public License can be used, that proxy's -public statement of acceptance of a version permanently authorizes you -to choose that version for the Program. - - Later license versions may give you additional or different -permissions. However, no additional obligations are imposed on any -author or copyright holder as a result of your choosing to follow a -later version. - - 15. Disclaimer of Warranty. - - THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY -APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT -HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY -OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM -IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF -ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - - 16. Limitation of Liability. - - IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS -THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY -GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE -USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF -DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD -PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), -EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF -SUCH DAMAGES. - - 17. Interpretation of Sections 15 and 16. - - If the disclaimer of warranty and limitation of liability provided -above cannot be given local legal effect according to their terms, -reviewing courts shall apply local law that most closely approximates -an absolute waiver of all civil liability in connection with the -Program, unless a warranty or assumption of liability accompanies a -copy of the Program in return for a fee. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/common/CPU/68000/FX68k/README.md b/common/CPU/68000/FX68k/README.md deleted file mode 100644 index b1c80178..00000000 --- a/common/CPU/68000/FX68k/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# fx68k -FX68K 68000 cycle accurate SystemVerilog core - -Copyright (c) 2018 by Jorge Cwik -fx68k@fxatari.com - -FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor. - -On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effective clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance. - -The core is fully synchronous. Considerable effort was made to avoid any asynchronous logic. - -Written in SystemVerilog. - -The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal. - -It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented. diff --git a/common/CPU/68000/FX68k/Rom.sv b/common/CPU/68000/FX68k/Rom.sv new file mode 100644 index 00000000..1b35c374 --- /dev/null +++ b/common/CPU/68000/FX68k/Rom.sv @@ -0,0 +1,28 @@ +// +// microrom and nanorom instantiation +// +// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed. +// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance. +// Might be more efficient to use vendor specific features such as clock enable. +// + +module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput); + reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH]; + initial begin + $readmemb("microrom.mem", uRam); + end + + always_ff @( posedge clk) + microOutput <= uRam[ microAddr]; +endmodule + + +module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput); + reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH]; + initial begin + $readmemb("nanorom.mem", nRam); + end + + always_ff @( posedge clk) + nanoOutput <= nRam[ nanoAddr]; +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/aluCorf.sv b/common/CPU/68000/FX68k/aluCorf.sv new file mode 100644 index 00000000..d73bd08e --- /dev/null +++ b/common/CPU/68000/FX68k/aluCorf.sv @@ -0,0 +1,35 @@ +// add bcd correction factor +// It would be more efficient to merge add/sub with main ALU !!! +module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry, + output [7:0] bcdResult, output dC, output logic ov); + + reg [8:0] htemp; + reg [4:0] hNib; + + wire lowC = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0); + wire highC = cin | (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0); + + always_comb begin + if( bAdd) begin + htemp = { 1'b0, binResult} + (lowC ? 4'h6 : 4'h0); + hNib = htemp[8:4] + (highC ? 4'h6 : 4'h0); + ov = hNib[3] & ~binResult[7]; + end + else begin + htemp = { 1'b0, binResult} - (lowC ? 4'h6 : 4'h0); + hNib = htemp[8:4] - (highC ? 4'h6 : 4'h0); + ov = ~hNib[3] & binResult[7]; + end + end + + assign bcdResult = { hNib[ 3:0], htemp[3:0]}; + assign dC = hNib[4] | cin; + + // Nibble > 9 + function gt9 (input [3:0] nib); + begin + gt9 = nib[3] & (nib[2] | nib[1]); + end + endfunction + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/aluGetOp.sv b/common/CPU/68000/FX68k/aluGetOp.sv new file mode 100644 index 00000000..8c779973 --- /dev/null +++ b/common/CPU/68000/FX68k/aluGetOp.sv @@ -0,0 +1,90 @@ +// Get current OP from row & col +module aluGetOp( input [15:0] row, input [2:0] col, input isCorf, + output logic [4:0] aluOp); + + always_comb begin + aluOp = 'X; + unique case( col) + 1: aluOp = OP_AND; + 5: aluOp = OP_EXT; + + default: + unique case( 1'b1) + row[1]: + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_SUBC; + 4,6: aluOp = OP_SLAA; + endcase + + row[2]: + unique case( col) + 2: aluOp = OP_ADD; + 3: aluOp = OP_ADDC; + 4: aluOp = OP_ASR; + endcase + + row[3]: + unique case( col) + 2: aluOp = OP_ADDX; + 3: aluOp = isCorf ? OP_ABCD : OP_ADD; + 4: aluOp = OP_ASL; + endcase + + row[4]: + aluOp = ( col == 4) ? OP_LSL : OP_AND; + + row[5], + row[6]: + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_SUBC; + 4: aluOp = OP_LSR; + endcase + + row[7]: // MUL + unique case( col) + 2: aluOp = OP_SUB; + 3: aluOp = OP_ADD; + 4: aluOp = OP_ROXR; + endcase + + row[8]: + // OP_AND For EXT.L + // But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1! + unique case( col) + 2: aluOp = OP_EXT; + 3: aluOp = OP_AND; + 4: aluOp = OP_ROXR; + endcase + + row[9]: + unique case( col) + 2: aluOp = OP_SUBX; + 3: aluOp = OP_SBCD; + 4: aluOp = OP_ROL; + endcase + + row[10]: + unique case( col) + 2: aluOp = OP_SUBX; + 3: aluOp = OP_SUBC; + 4: aluOp = OP_ROR; + endcase + + row[11]: + unique case( col) + 2: aluOp = OP_SUB0; + 3: aluOp = OP_SUB0; + 4: aluOp = OP_ROXL; + endcase + + row[12]: aluOp = OP_ADDX; + row[13]: aluOp = OP_EOR; + row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR; + row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc + + endcase + endcase + end +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/aluShifter.sv b/common/CPU/68000/FX68k/aluShifter.sv new file mode 100644 index 00000000..c36d26eb --- /dev/null +++ b/common/CPU/68000/FX68k/aluShifter.sv @@ -0,0 +1,32 @@ +module aluShifter( input [31:0] data, + input isByte, input isLong, swapWords, + input dir, input cin, + output logic [31:0] result); + // output reg cout + + logic [31:0] tdata; + + // size mux, put cin in position if dir == right + always_comb begin + tdata = data; + if( isByte & dir) + tdata[8] = cin; + else if( !isLong & dir) + tdata[16] = cin; + end + + always_comb begin + // Reverse alu/alue position for MUL & DIV + // Result reversed again + if( swapWords & dir) + result = { tdata[0], tdata[31:17], cin, tdata[15:1]}; + else if( swapWords) + result = { tdata[30:16], cin, tdata[14:0], tdata[31]}; + + else if( dir) + result = { cin, tdata[31:1]}; + else + result = { tdata[30:0], cin}; + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/busArbiter.sv b/common/CPU/68000/FX68k/busArbiter.sv new file mode 100644 index 00000000..89bd2fb3 --- /dev/null +++ b/common/CPU/68000/FX68k/busArbiter.sv @@ -0,0 +1,87 @@ +// +// DMA/BUS Arbitration +// + +module busArbiter( input s_clks Clks, + input BRi, BgackI, Halti, bgBlock, + output busAvail, + output logic BGn); + + enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next; + + always_comb begin + case(dmaPhase) + DRESET: next = DIDLE; + DIDLE: begin + if( bgBlock) + next = DIDLE; + else if( ~BgackI) + next = D_BA; + else if( ~BRi) + next = D1; + else + next = DIDLE; + end + + D_BA: begin // Loop while only BGACK asserted, BG negated here + if( ~BRi & !bgBlock) + next = D3; + else if( ~BgackI & !bgBlock) + next = D_BA; + else + next = DIDLE; + end + + D1: next = D_BR; // Loop while only BR asserted + D_BR: next = ~BRi & BgackI ? D_BR : D_BA; // No direct path to IDLE ! + + D3: next = D_BRA; + D_BRA: begin // Loop while both BR and BGACK asserted + case( {BgackI, BRi} ) + 2'b11: next = DIDLE; // Both deasserted + 2'b10: next = D_BR; // BR asserted only + 2'b01: next = D2; // BGACK asserted only + 2'b00: next = D_BRA; // Stay here while both asserted + endcase + end + + // Might loop here if both deasserted, should normally don't arrive here anyway? + // D2: next = (BgackI & BRi) | bgBlock ? D2: D_BA; + + D2: next = D_BA; + + default: next = DIDLE; // Should not reach here normally + endcase + end + + logic granting; + always_comb begin + unique case( next) + D1, D3, D_BR, D_BRA: granting = 1'b1; + default: granting = 1'b0; + endcase + end + + reg rGranted; + assign busAvail = Halti & BRi & BgackI & ~rGranted; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + dmaPhase <= DRESET; + rGranted <= 1'b0; + end + else if( Clks.enPhi2) begin + dmaPhase <= next; + // Internal signal changed on PHI2 + rGranted <= granting; + end + + // External Output changed on PHI1 + if( Clks.extReset) + BGn <= 1'b1; + else if( Clks.enPhi1) + BGn <= ~rGranted; + + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/busControl.sv b/common/CPU/68000/FX68k/busControl.sv new file mode 100644 index 00000000..8236fbd7 --- /dev/null +++ b/common/CPU/68000/FX68k/busControl.sv @@ -0,0 +1,197 @@ +module busControl( input s_clks Clks, input enT1, input enT4, + input permStart, permStop, iStop, + input aob0, + input isWrite, isByte, isRmc, + input busAvail, + output bgBlock, + output busAddrErr, + output waitBusCycle, + output busStarting, // Asserted during S0 + output logic addrOe, // Asserted from S1 to the end, whole bus cycle except S0 + output bciWrite, // Used for SSW on bus/addr error + + input rDtack, BeDebounced, Vpai, + output ASn, output LDSn, output UDSn, eRWn); + + reg rAS, rLDS, rUDS, rRWn; + assign ASn = rAS; + assign LDSn = rLDS; + assign UDSn = rUDS; + assign eRWn = rRWn; + + reg dataOe; + + reg bcPend; + reg isWriteReg, bciByte, isRmcReg, wendReg; + assign bciWrite = isWriteReg; + reg addrOeDelay; + reg isByteT4; + + wire canStart, busEnd; + wire bcComplete, bcReset; + + wire isRcmReset = bcComplete & bcReset & isRmcReg; + + assign busAddrErr = aob0 & ~bciByte; + + // Bus retry not really supported. + // It's BERR and HALT and not address error, and not read-modify cycle. + wire busRetry = ~busAddrErr & 1'b0; + + enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) + busPhase <= SRESET; + else if( Clks.enPhi1) + busPhase <= next; + end + + always_comb begin + case( busPhase) + SRESET: next = SIDLE; + SRMC_RES: next = SIDLE; // Single cycle special state when read phase of RMC reset + S0: next = S2; + S2: next = S4; + S4: next = busEnd ? S6 : S4; + S6: next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE); + SIDLE: next = canStart ? S0 : SIDLE; + default: next = SIDLE; + endcase + end + + // Idle phase of RMC bus cycle. Might be better to just add a new state + wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg; + + assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset; + + wire busEnding = (next == SIDLE) | (next == S0); + + assign busStarting = (busPhase == S0); + + // term signal (DTACK, BERR, VPA, adress error) + assign busEnd = ~rDtack | iStop; + + // bcComplete asserted on raising edge of S6 (together with SNC). + assign bcComplete = (busPhase == S6); + + // Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1). + // bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently + wire bciClear = bcComplete & ~busRetry; + + // Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1) + assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai); + + // Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop + assign waitBusCycle = wendReg & !bcComplete; + + // Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC) + // Except that when that RMC phase aborted on bus error, it's asserted one cycle later! + assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES); + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + addrOe <= 1'b0; + end + else if( Clks.enPhi2 & ( busPhase == S0)) // From S1, whole bus cycle except S0 + addrOe <= 1'b1; + else if( Clks.enPhi1 & (busPhase == SRMC_RES)) + addrOe <= 1'b0; + else if( Clks.enPhi1 & ~isRmcReg & busEnding) + addrOe <= 1'b0; + + if( Clks.enPhi1) + addrOeDelay <= addrOe; + + if( Clks.extReset) begin + rAS <= 1'b1; + rUDS <= 1'b1; + rLDS <= 1'b1; + rRWn <= 1'b1; + dataOe <= '0; + end + else begin + + if( Clks.enPhi2 & isWriteReg & (busPhase == S2)) + dataOe <= 1'b1; + else if( Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) ) + dataOe <= 1'b0; + + if( Clks.enPhi1 & busEnding) + rRWn <= 1'b1; + else if( Clks.enPhi1 & isWriteReg) begin + // Unlike LDS/UDS Asserted even in address error + if( (busPhase == S0) & isWriteReg) + rRWn <= 1'b0; + end + + // AS. Actually follows addrOe half cycle later! + if( Clks.enPhi1 & (busPhase == S0)) + rAS <= 1'b0; + else if( Clks.enPhi2 & (busPhase == SRMC_RES)) // Bus error on read phase of RMC. Deasserted one cycle later + rAS <= 1'b1; + else if( Clks.enPhi2 & bcComplete & ~SRMC_RES) + if( ~isRmcReg) // Keep AS asserted on the IDLE phase of RMC + rAS <= 1'b1; + + if( Clks.enPhi1 & (busPhase == S0)) begin + if( ~isWriteReg & !busAddrErr) begin + rUDS <= ~(~bciByte | ~aob0); + rLDS <= ~(~bciByte | aob0); + end + end + else if( Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin + rUDS <= ~(~bciByte | ~aob0); + rLDS <= ~(~bciByte | aob0); + end + else if( Clks.enPhi2 & bcComplete) begin + rUDS <= 1'b1; + rLDS <= 1'b1; + end + + end + + end + + // Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait. + // Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches. + // Even without wait states, ublocks of type ir (init reading) will not wait for bus completion. + // Originally latched on (permStart AND T1). + + // Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4? + // permStop also latched, but unconditionally on T1 + + // Might make more sense to register this outside this module + always_ff @( posedge Clks.clk) begin + if( enT4) begin + isByteT4 <= isByte; + end + end + + // Bus Cycle Info Latch + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) begin + bcPend <= 1'b0; + wendReg <= 1'b0; + isWriteReg <= 1'b0; + bciByte <= 1'b0; + isRmcReg <= 1'b0; + end + + else if( Clks.enPhi2 & (bciClear | bcReset)) begin + bcPend <= 1'b0; + wendReg <= 1'b0; + end + else begin + if( enT1 & permStart) begin + isWriteReg <= isWrite; + bciByte <= isByteT4; + isRmcReg <= isRmc & ~isWrite; // We need special case the end of the read phase only. + bcPend <= 1'b1; + end + if( enT1) + wendReg <= permStop; + end + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/ccrTable.sv b/common/CPU/68000/FX68k/ccrTable.sv new file mode 100644 index 00000000..b50f822f --- /dev/null +++ b/common/CPU/68000/FX68k/ccrTable.sv @@ -0,0 +1,76 @@ +// Row/col CCR update table +module ccrTable( + input [2:0] col, input [15:0] row, input finish, + output logic [MASK_NBITS-1:0] ccrMask); + + localparam + KNZ00 = 5'b01111, // ok coz operators clear them + KKZKK = 5'b00100, + KNZKK = 5'b01100, + KNZ10 = 5'b01111, // Used by OP_EXT on divison overflow + KNZ0C = 5'b01111, // Used by DIV. V should be 0, but it is ok: + // DIVU: ends with quotient - 0, so V & C always clear. + // DIVS: ends with 1i (AND), again, V & C always clear. + + KNZVC = 5'b01111, + CUPDALL = 5'b11111, + CUNUSED = 5'bxxxxx; + + + logic [MASK_NBITS-1:0] ccrMask1; + + always_comb begin + unique case( col) + 1: ccrMask = ccrMask1; + + 2,3: + unique case( 1'b1) + row[1]: ccrMask = KNZ0C; // DIV, used as 3n in col3 + row[2], + row[3], // ABCD + row[5], + row[9], // SBCD/NBCD + row[10], // SUBX/NEGX + row[12]: ccrMask = CUPDALL; // ADDX + row[6], // CMP + row[7], // MUL + row[11]: ccrMask = KNZVC; // NOT + row[4], + row[8], // Not used in col 3 + row[13], + row[14]: ccrMask = KNZ00; + row[15]: ccrMask = 5'b0; // TAS/Scc, not used in col 3 + // default: ccrMask = CUNUSED; + endcase + + 4: + unique case( row) + // 1: DIV, only n (4n & 6n) + // 14: BCLR 4n + // 6,12,13,15 // not used + `ALU_ROW_02, + `ALU_ROW_03, // ASL (originally ANZVA) + `ALU_ROW_04, + `ALU_ROW_05: ccrMask = CUPDALL; // Shifts (originally ANZ0A) + + `ALU_ROW_07: ccrMask = KNZ00; // MUL (originally KNZ0A) + `ALU_ROW_09, + `ALU_ROW_10: ccrMask = KNZ00; // RO[lr] (originally KNZ0A) + `ALU_ROW_11: ccrMask = CUPDALL; // ROXL (originally ANZ0A) + default: ccrMask = CUNUSED; + endcase + + 5: ccrMask = row[1] ? KNZ10 : 5'b0; + default: ccrMask = CUNUSED; + endcase + end + + // Column 1 (AND) + always_comb begin + if( finish) + ccrMask1 = row[7] ? KNZ00 : KNZKK; + else + ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00; + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/dataIo.sv b/common/CPU/68000/FX68k/dataIo.sv new file mode 100644 index 00000000..c20f36d3 --- /dev/null +++ b/common/CPU/68000/FX68k/dataIo.sv @@ -0,0 +1,97 @@ +// +// Data bus I/O +// At a separate module because it is a bit complicated and the timing is special. +// Here we do the low/high byte mux and the special case of MOVEP. +// +// Original implementation is rather complex because both the internal and external buses are bidirectional. +// Input is latched async at the EDB register. +// We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period. + +module dataIo( input s_clks Clks, + input enT1, enT2, enT3, enT4, + input s_nanod Nanod, input s_irdecod Irdecod, + input [15:0] iEdb, + input aob0, + + input dobIdle, + input [15:0] dobInput, + + output logic [15:0] Irc, + output logic [15:0] dbin, + output logic [15:0] oEdb + ); + + reg [15:0] dob; + + // DBIN/IRC + + // Timing is different than any other register. We can latch only on the next T4 (bus phase S7). + // We need to register all control signals correctly because the next ublock will already be started. + // Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch. + + reg xToDbin, xToIrc; + reg dbinNoLow, dbinNoHigh; + reg byteMux, isByte_T4; + + always_ff @( posedge Clks.clk) begin + + // Byte mux control. Can't latch at T1. AOB might be not ready yet. + // Must latch IRD decode at T1 (or T4). Then combine and latch only at T3. + + // Can't latch at T3, a new IRD might be loaded already at T1. + // Ok to latch at T4 if combination latched then at T3 + if( enT4) + isByte_T4 <= Irdecod.isByte; // Includes MOVEP from mem, we could OR it here + + if( enT3) begin + dbinNoHigh <= Nanod.noHighByte; + dbinNoLow <= Nanod.noLowByte; + byteMux <= Nanod.busByte & isByte_T4 & ~aob0; + end + + if( enT1) begin + // If on wait states, we continue latching until next T1 + xToDbin <= 1'b0; + xToIrc <= 1'b0; + end + else if( enT3) begin + xToDbin <= Nanod.todbin; + xToIrc <= Nanod.toIrc; + end + + // Capture on T4 of the next ucycle + // If there are wait states, we keep capturing every PHI2 until the next T1 + + if( xToIrc & Clks.enPhi2) + Irc <= iEdb; + if( xToDbin & Clks.enPhi2) begin + // Original connects both halves of EDB. + if( ~dbinNoLow) + dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0]; + if( ~dbinNoHigh) + dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8]; + end + end + + // DOB + logic byteCycle; + + always_ff @( posedge Clks.clk) begin + // Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables. + // It is safe to do on T3, then, but control signals if derived from IRD must be registered. + // Originally control signals are not registered. + + // Wait states don't affect DOB operation that is done at the start of the bus cycle. + + if( enT4) + byteCycle <= Nanod.busByte & Irdecod.isByte; // busIsByte but not MOVEP + + // Originally byte low/high interconnect is done at EDB, not at DOB. + if( enT3 & ~dobIdle) begin + dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0]; + dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8]; + end + end + assign oEdb = dob; + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/excUnit.sv b/common/CPU/68000/FX68k/excUnit.sv new file mode 100644 index 00000000..b42b4616 --- /dev/null +++ b/common/CPU/68000/FX68k/excUnit.sv @@ -0,0 +1,553 @@ +/* + Execution unit + + Executes register transfers set by the microcode. Originally through a set of bidirectional buses. + Most sources are available at T3, but DBIN only at T4! CCR also might be updated at T4, but it is not connected to these buses. + We mux at T1 and T2, then transfer to the destination at T3. The exception is AOB that need to be updated earlier. + +*/ + +module excUnit( input s_clks Clks, + input enT1, enT2, enT3, enT4, + input s_nanod Nanod, input s_irdecod Irdecod, + input [15:0] Ird, // ALU row (and others) decoder needs it + input pswS, + input [15:0] ftu, + input [15:0] iEdb, + + output logic [7:0] ccr, + output [15:0] alue, + + output prenEmpty, au05z, + output logic dcr4, ze, + output logic aob0, + output [15:0] AblOut, + output logic [15:0] Irc, + output logic [15:0] oEdb, + output logic [23:1] eab); + +localparam REG_USP = 15; +localparam REG_SSP = 16; +localparam REG_DT = 17; + + // Register file + reg [15:0] regs68L[ 18]; + reg [15:0] regs68H[ 18]; + +// synthesis translate off + /* + It is bad practice to initialize simulation registers that the hardware doesn't. + There is risk that simulation would be different than the real hardware. But in this case is the other way around. + Some ROM uses something like sub.l An,An at powerup which clears the register + Simulator power ups the registers with 'X, as they are really undetermined at the real hardware. + But the simulator doesn't realize (it can't) that the same value is substracting from itself, + and that the result should be zero even when it's 'X - 'X. + */ + + initial begin + for( int i = 0; i < 18; i++) begin + regs68L[i] <= '0; + regs68H[i] <= '0; + end + end + + // For simulation display only + wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]}; + +// synthesis translate on + + + wire [15:0] aluOut; + wire [15:0] dbin; + logic [15:0] dcrOutput; + + reg [15:0] PcL, PcH; + + reg [31:0] auReg, aob; + + reg [15:0] Ath, Atl; + + // Bus execution + reg [15:0] Dbl, Dbh; + reg [15:0] Abh, Abl; + reg [15:0] Abd, Dbd; + + assign AblOut = Abl; + assign au05z = (~| auReg[5:0]); + + logic [15:0] dblMux, dbhMux; + logic [15:0] abhMux, ablMux; + logic [15:0] abdMux, dbdMux; + + logic abdIsByte; + + logic Pcl2Dbl, Pch2Dbh; + logic Pcl2Abl, Pch2Abh; + + + // RX RY muxes + // RX and RY actual registers + logic [4:0] actualRx, actualRy; + logic [3:0] movemRx; + logic byteNotSpAlign; // Byte instruction and no sp word align + + // IRD decoded signals must be latched. See comments on decoder + // But nanostore decoding can't be latched before T4. + // + // If we need this earlier we can register IRD decode on T3 and use nano async + + logic [4:0] rxMux, ryMux; + logic [3:0] rxReg, ryReg; + logic rxIsSp, ryIsSp; + logic rxIsAreg, ryIsAreg; + + always_comb begin + + // Unique IF !! + if( Nanod.ssp) begin + rxMux = REG_SSP; + rxIsSp = 1'b1; + rxReg = 1'bX; + end + else if( Irdecod.rxIsUsp) begin + rxMux = REG_USP; + rxIsSp = 1'b1; + rxReg = 1'bX; + end + else if( Irdecod.rxIsDt & !Irdecod.implicitSp) begin + rxMux = REG_DT; + rxIsSp = 1'b0; + rxReg = 1'bX; + end + else begin + if( Irdecod.implicitSp) + rxReg = 15; + else if( Irdecod.rxIsMovem) + rxReg = movemRx; + else + rxReg = { Irdecod.rxIsAreg, Irdecod.rx}; + + if( (& rxReg)) begin + rxMux = pswS ? REG_SSP : 15; + rxIsSp = 1'b1; + end + else begin + rxMux = { 1'b0, rxReg}; + rxIsSp = 1'b0; + end + end + + // RZ has higher priority! + if( Irdecod.ryIsDt & !Nanod.rz) begin + ryMux = REG_DT; + ryIsSp = 1'b0; + ryReg = 'X; + end + else begin + ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry}; + ryIsSp = (& ryReg); + if( ryIsSp & pswS) // No implicit SP on RY + ryMux = REG_SSP; + else + ryMux = { 1'b0, ryReg}; + end + + end + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp); + + actualRx <= rxMux; + actualRy <= ryMux; + + rxIsAreg <= rxIsSp | rxMux[3]; + ryIsAreg <= ryIsSp | ryMux[3]; + end + + if( enT4) + abdIsByte <= Nanod.abdIsByte & Irdecod.isByte; + end + + // Set RX/RY low word to which bus segment is connected. + + wire ryl2Abl = Nanod.ryl2ab & (ryIsAreg | Nanod.ablAbd); + wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd); + wire ryl2Dbl = Nanod.ryl2db & (ryIsAreg | Nanod.dblDbd); + wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd); + + wire rxl2Abl = Nanod.rxl2ab & (rxIsAreg | Nanod.ablAbd); + wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd); + wire rxl2Dbl = Nanod.rxl2db & (rxIsAreg | Nanod.dblDbd); + wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd); + + // Buses. Main mux + + logic abhIdle, ablIdle, abdIdle; + logic dbhIdle, dblIdle, dbdIdle; + + always_comb begin + {abhIdle, ablIdle, abdIdle} = '0; + {dbhIdle, dblIdle, dbdIdle} = '0; + + unique case( 1'b1) + ryl2Dbd: dbdMux = regs68L[ actualRy]; + rxl2Dbd: dbdMux = regs68L[ actualRx]; + Nanod.alue2Dbd: dbdMux = alue; + Nanod.dbin2Dbd: dbdMux = dbin; + Nanod.alu2Dbd: dbdMux = aluOut; + Nanod.dcr2Dbd: dbdMux = dcrOutput; + default: begin dbdMux = 'X; dbdIdle = 1'b1; end + endcase + + unique case( 1'b1) + rxl2Dbl: dblMux = regs68L[ actualRx]; + ryl2Dbl: dblMux = regs68L[ actualRy]; + Nanod.ftu2Dbl: dblMux = ftu; + Nanod.au2Db: dblMux = auReg[15:0]; + Nanod.atl2Dbl: dblMux = Atl; + Pcl2Dbl: dblMux = PcL; + default: begin dblMux = 'X; dblIdle = 1'b1; end + endcase + + unique case( 1'b1) + Nanod.rxh2dbh: dbhMux = regs68H[ actualRx]; + Nanod.ryh2dbh: dbhMux = regs68H[ actualRy]; + Nanod.au2Db: dbhMux = auReg[31:16]; + Nanod.ath2Dbh: dbhMux = Ath; + Pch2Dbh: dbhMux = PcH; + default: begin dbhMux = 'X; dbhIdle = 1'b1; end + endcase + + unique case( 1'b1) + ryl2Abd: abdMux = regs68L[ actualRy]; + rxl2Abd: abdMux = regs68L[ actualRx]; + Nanod.dbin2Abd: abdMux = dbin; + Nanod.alu2Abd: abdMux = aluOut; + default: begin abdMux = 'X; abdIdle = 1'b1; end + endcase + + unique case( 1'b1) + Pcl2Abl: ablMux = PcL; + rxl2Abl: ablMux = regs68L[ actualRx]; + ryl2Abl: ablMux = regs68L[ actualRy]; + Nanod.ftu2Abl: ablMux = ftu; + Nanod.au2Ab: ablMux = auReg[15:0]; + Nanod.aob2Ab: ablMux = aob[15:0]; + Nanod.atl2Abl: ablMux = Atl; + default: begin ablMux = 'X; ablIdle = 1'b1; end + endcase + + unique case( 1'b1) + Pch2Abh: abhMux = PcH; + Nanod.rxh2abh: abhMux = regs68H[ actualRx]; + Nanod.ryh2abh: abhMux = regs68H[ actualRy]; + Nanod.au2Ab: abhMux = auReg[31:16]; + Nanod.aob2Ab: abhMux = aob[31:16]; + Nanod.ath2Abh: abhMux = Ath; + default: begin abhMux = 'X; abhIdle = 1'b1; end + endcase + + end + + // Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3. + + // These registers store the first level mux, without bus interconnections. + // Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster. + reg [15:0] preAbh, preAbl, preAbd; + reg [15:0] preDbh, preDbl, preDbd; + + always_ff @( posedge Clks.clk) begin + + // Register first level mux at T1 + if( enT1) begin + {preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux}; + {preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux}; + end + + // Process bus interconnection at T2. Many combinations only used on DIV + // We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment. + // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter. + + if( enT2) begin + if( Nanod.extAbh) + Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }}; + else if( abhIdle) + Abh <= ablIdle ? preAbd : preAbl; + else + Abh <= preAbh; + + if( ~ablIdle) + Abl <= preAbl; + else + Abl <= Nanod.ablAbh ? preAbh : preAbd; + + Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl; + + if( Nanod.extDbh) + Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }}; + else if( dbhIdle) + Dbh <= dblIdle ? preDbd : preDbl; + else + Dbh <= preDbh; + + if( ~dblIdle) + Dbl <= preDbl; + else + Dbl <= Nanod.dblDbh ? preDbh : preDbd; + + Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl; + + /* + Dbl <= dblMux; Dbh <= dbhMux; + Abd <= abdMux; Dbd <= dbdMux; + Abh <= abhMux; Abl <= ablMux; */ + end + end + + // AOB + // + // Originally change on T1. We do on T2, only then the output is enabled anyway. + // + // AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3. + // It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical. + // But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1. + + // We need to take directly from first level muxes that are updated and T1 + + wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob); + + always_ff @( posedge Clks.clk) begin + // UNIQUE IF ! + + if( enT1 & au2Aob) // From AU we do can on T1 + aob <= auReg; + else if( enT2) begin + if( Nanod.db2Aob) + aob <= { preDbh, ~dblIdle ? preDbl : preDbd}; + else if( Nanod.ab2Aob) + aob <= { preAbh, ~ablIdle ? preAbl : preAbd}; + end + end + + assign eab = aob[23:1]; + assign aob0 = aob[0]; + + // AU + logic [31:0] auInpMux; + + // `ifdef ALW_COMB_BUG + // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !? + // always @( Nanod.auCntrl) begin + + always_comb begin + unique case( Nanod.auCntrl) + 3'b000: auInpMux = 0; + 3'b001: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 1 : 2; // +1/+2 + 3'b010: auInpMux = -4; + 3'b011: auInpMux = { Abh, Abl}; + 3'b100: auInpMux = 2; + 3'b101: auInpMux = 4; + 3'b110: auInpMux = -2; + 3'b111: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? -1 : -2; // -1/-2 + default: auInpMux = 'X; + endcase + end + + // Simulation problem + // Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero. + // But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X. + +// synthesis translate_off + `define SIMULBUGX32 1 + wire [16:0] aulow = Dbl + auInpMux[15:0]; + wire [31:0] auResult = {Dbh + auInpMux[31:16] + aulow[16], aulow[15:0]}; +// synthesis translate_on + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) + auReg <= '0; + else if( enT3 & Nanod.auClkEn) + `ifdef SIMULBUGX32 + auReg <= auResult; + `else + auReg <= { Dbh, Dbl } + auInpMux; + `endif + end + + + // Main A/D registers + + always_ff @( posedge Clks.clk) begin + if( enT3) begin + if( Nanod.dbl2rxl | Nanod.abl2rxl) begin + if( ~rxIsAreg) begin + if( Nanod.dbl2rxl) regs68L[ actualRx] <= Dbd; + else if( abdIsByte) regs68L[ actualRx][7:0] <= Abd[7:0]; + else regs68L[ actualRx] <= Abd; + end + else + regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl; + end + + if( Nanod.dbl2ryl | Nanod.abl2ryl) begin + if( ~ryIsAreg) begin + if( Nanod.dbl2ryl) regs68L[ actualRy] <= Dbd; + else if( abdIsByte) regs68L[ actualRy][7:0] <= Abd[7:0]; + else regs68L[ actualRy] <= Abd; + end + else + regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl; + end + + // High registers are easier. Both A & D on the same buses, and not byte ops. + if( Nanod.dbh2rxh | Nanod.abh2rxh) + regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh; + if( Nanod.dbh2ryh | Nanod.abh2ryh) + regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh; + + end + end + + // PC & AT + reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) begin + { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0; + + Pcl2Dbl <= 1'b0; + Pch2Dbh <= 1'b0; + Pcl2Abl <= 1'b0; + Pch2Abh <= 1'b0; + end + else if( enT4) begin // Must latch on T4 ! + dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl; + dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh; + abh2Pch <= Nanod.abh2reg & Nanod.pchabh; + abl2Pcl <= Nanod.abl2reg & Nanod.pclabl; + + Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl; + Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh; + Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl; + Pch2Abh <= Nanod.reg2abh & Nanod.pchabh; + end + + // Unique IF !!! + if( enT1 & Nanod.au2Pc) + PcL <= auReg[15:0]; + else if( enT3) begin + if( dbl2Pcl) + PcL <= Dbl; + else if( abl2Pcl) + PcL <= Abl; + end + + // Unique IF !!! + if( enT1 & Nanod.au2Pc) + PcH <= auReg[31:16]; + else if( enT3) begin + if( dbh2Pch) + PcH <= Dbh; + else if( abh2Pch) + PcH <= Abh; + end + + // Unique IF !!! + if( enT3) begin + if( Nanod.dbl2Atl) + Atl <= Dbl; + else if( Nanod.abl2Atl) + Atl <= Abl; + end + + // Unique IF !!! + if( enT3) begin + if( Nanod.abh2Ath) + Ath <= Abh; + else if( Nanod.dbh2Ath) + Ath <= Dbh; + end + + end + + // Movem reg mask priority encoder + + wire rmIdle; + logic [3:0] prHbit; + logic [15:0] prenLatch; + + // Invert reg order for predecrement mode + assign prenEmpty = (~| prenLatch); + pren rmPren( .mask( prenLatch), .hbit (prHbit)); + + always_ff @( posedge Clks.clk) begin + // Cheating: PREN always loaded from DBIN + // Must be on T1 to branch earlier if reg mask is empty! + if( enT1 & Nanod.abl2Pren) + prenLatch <= dbin; + else if( enT3 & Nanod.updPren) begin + prenLatch [prHbit] <= 1'b0; + movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit; + end + end + + // DCR + wire [15:0] dcrCode; + + wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0]; + onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode)); + + always_ff @( posedge Clks.clk) begin + if( Clks.pwrUp) + dcr4 <= '0; + else if( enT3 & Nanod.abd2Dcr) begin + dcrOutput <= dcrCode; + dcr4 <= Abd[4]; + end + end + + // ALUB + reg [15:0] alub; + + always_ff @( posedge Clks.clk) begin + if( enT3) begin + // UNIQUE IF !! + if( Nanod.dbd2Alub) + alub <= Dbd; + else if( Nanod.abd2Alub) + alub <= Abd; // abdIsByte affects this !!?? + end + end + + wire alueClkEn = enT3 & Nanod.dbd2Alue; + + // DOB/DBIN/IRC + + logic [15:0] dobInput; + wire dobIdle = (~| Nanod.dobCtrl); + + always_comb begin + unique case (Nanod.dobCtrl) + NANO_DOB_ADB: dobInput = Abd; + NANO_DOB_DBD: dobInput = Dbd; + NANO_DOB_ALU: dobInput = aluOut; + default: dobInput = 'X; + endcase + end + + dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod, + .iEdb, .dobIdle, .dobInput, .aob0, + .Irc, .dbin, .oEdb); + + fx68kAlu alu( + .clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4, + .ird( Ird), + .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl), + .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte), + .ftu2Ccr( Nanod.ftu2Ccr), + .alub, .ftu, .alueClkEn, .alue, + .aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd), + .ze, .aluOut, .ccr); + +endmodule diff --git a/common/CPU/68000/FX68k/fx68k.sv b/common/CPU/68000/FX68k/fx68k.sv index d7717454..996d9ac3 100644 --- a/common/CPU/68000/FX68k/fx68k.sv +++ b/common/CPU/68000/FX68k/fx68k.sv @@ -231,12 +231,23 @@ module fx68k( wire rstUrom; // For the time being, address translation is done for nanorom only. - microToNanoAddr microToNanoAddr( .uAddr( nma), .orgAddr); + microToNanoAddr microToNanoAddr( + .uAddr ( nma), + .orgAddr ( orgAddr) + ); // Output of these modules will be updated at T2 at the latest (depending on clock division) - nanoRom nanoRom( .clk( Clks.clk), .nanoAddr, .nanoOutput); - uRom uRom( .clk( Clks.clk), .microAddr, .microOutput); + nanoRom nanoRom( + .clk ( Clks.clk), + .nanoAddr (nanoAddr), + .nanoOutput (nanoOutput) + ); + + uRom uRom( + .clk ( Clks.clk), + .microAddr ( microAddr), + .microOutput( microOutput)); always_ff @( posedge Clks.clk) begin // uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2 @@ -383,10 +394,10 @@ module fx68k( rFC <= '0; else if( enT1 & Nanod.permStart) begin // S0 phase of bus cycle rFC[2] <= pswS; - // If FC is type 'n' (0) at ucode, access type depends on PC relative mode + // PC relativ access is marked as FC type 'n' (0) at ucode. // We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle. - rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] & Irdecod.isPcRel); - rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & ~Irdecod.isPcRel); + rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] & ~Irdecod.isPcRel); + rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & Irdecod.isPcRel); end end @@ -628,2054 +639,4 @@ module fx68k( tvnMux = { 8'h0, Irdecod.macroTvn, 2'b00}; end -endmodule - -// Nanorom (plus) decoder for die nanocode -module nDecoder3( input s_clks Clks, input s_irdecod Irdecod, output s_nanod Nanod, - input enT2, enT4, - input [UROM_WIDTH-1:0] microLatch, - input [NANO_WIDTH-1:0] nanoLatch); - -localparam NANO_IR2IRD = 67; -localparam NANO_TOIRC = 66; -localparam NANO_ALU_COL = 63; // ALU operator column order is 63-64-65 ! -localparam NANO_ALU_FI = 61; // ALU finish-init 62-61 -localparam NANO_TODBIN = 60; -localparam NANO_ALUE = 57; // 57-59 shared with DCR control -localparam NANO_DCR = 57; // 57-59 shared with ALUE control -localparam NANO_DOBCTRL_1 = 56; // Input to control and permwrite -localparam NANO_LOWBYTE = 55; // Used by MOVEP -localparam NANO_HIGHBYTE = 54; -localparam NANO_DOBCTRL_0 = 53; // Input to control and permwrite -localparam NANO_ALU_DCTRL = 51; // 52-51 databus input mux control -localparam NANO_ALU_ACTRL = 50; // addrbus input mux control -localparam NANO_DBD2ALUB = 49; -localparam NANO_ABD2ALUB = 48; -localparam NANO_DBIN2DBD = 47; -localparam NANO_DBIN2ABD = 46; -localparam NANO_ALU2ABD = 45; -localparam NANO_ALU2DBD = 44; -localparam NANO_RZ = 43; -localparam NANO_BUSBYTE = 42; // If *both* this set and instruction is byte sized, then bus cycle is byte sized. -localparam NANO_PCLABL = 41; -localparam NANO_RXL_DBL = 40; // Switches RXL/RYL on DBL/ABL buses -localparam NANO_PCLDBL = 39; -localparam NANO_ABDHRECHARGE = 38; -localparam NANO_REG2ABL = 37; // register to ABL -localparam NANO_ABL2REG = 36; // ABL to register -localparam NANO_ABLABD = 35; -localparam NANO_DBLDBD = 34; -localparam NANO_DBL2REG = 33; // DBL to register -localparam NANO_REG2DBL = 32; // register to DBL -localparam NANO_ATLCTRL = 29; // 31-29 -localparam NANO_FTUCONTROL = 25; -localparam NANO_SSP = 24; -localparam NANO_RXH_DBH = 22; // Switches RXH/RYH on DBH/ABH buses -localparam NANO_AUOUT = 20; // 21-20 -localparam NANO_AUCLKEN = 19; -localparam NANO_AUCTRL = 16; // 18-16 -localparam NANO_DBLDBH = 15; -localparam NANO_ABLABH = 14; -localparam NANO_EXT_ABH = 13; -localparam NANO_EXT_DBH = 12; -localparam NANO_ATHCTRL = 9; // 11-9 -localparam NANO_REG2ABH = 8; // register to ABH -localparam NANO_ABH2REG = 7; // ABH to register -localparam NANO_REG2DBH = 6; // register to DBH -localparam NANO_DBH2REG = 5; // DBH to register -localparam NANO_AOBCTRL = 3; // 4-3 -localparam NANO_PCH = 0; // 1-0 PchDbh PchAbh -localparam NANO_NO_SP_ALGN = 0; // Same bits as above when both set - -localparam NANO_FTU_UPDTPEND = 1; // Also loads FTU constant according to IRD ! -localparam NANO_FTU_INIT_ST = 15; // Set S, clear T (but not TPEND) -localparam NANO_FTU_CLRTPEND = 14; -localparam NANO_FTU_TVN = 13; -localparam NANO_FTU_ABL2PREN = 12; // ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine. -localparam NANO_FTU_SSW = 11; -localparam NANO_FTU_RSTPREN = 10; -localparam NANO_FTU_IRD = 9; -localparam NANO_FTU_2ABL = 8; -localparam NANO_FTU_RDSR = 7; -localparam NANO_FTU_INL = 6; -localparam NANO_FTU_PSWI = 5; // Read Int Mask into FTU -localparam NANO_FTU_DBL = 4; -localparam NANO_FTU_2SR = 2; -localparam NANO_FTU_CONST = 1; - - reg [3:0] ftuCtrl; - - logic [2:0] athCtrl, atlCtrl; - assign athCtrl = nanoLatch[ NANO_ATHCTRL+2: NANO_ATHCTRL]; - assign atlCtrl = nanoLatch[ NANO_ATLCTRL+2: NANO_ATLCTRL]; - wire [1:0] aobCtrl = nanoLatch[ NANO_AOBCTRL+1:NANO_AOBCTRL]; - wire [1:0] dobCtrl = {nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0]}; - - always_ff @( posedge Clks.clk) begin - if( enT4) begin - // Reverse order! - ftuCtrl <= { nanoLatch[ NANO_FTUCONTROL+0], nanoLatch[ NANO_FTUCONTROL+1], nanoLatch[ NANO_FTUCONTROL+2], nanoLatch[ NANO_FTUCONTROL+3]} ; - - Nanod.auClkEn <= !nanoLatch[ NANO_AUCLKEN]; - Nanod.auCntrl <= nanoLatch[ NANO_AUCTRL+2 : NANO_AUCTRL+0]; - Nanod.noSpAlign <= (nanoLatch[ NANO_NO_SP_ALGN + 1:NANO_NO_SP_ALGN] == 2'b11); - Nanod.extDbh <= nanoLatch[ NANO_EXT_DBH]; - Nanod.extAbh <= nanoLatch[ NANO_EXT_ABH]; - Nanod.todbin <= nanoLatch[ NANO_TODBIN]; - Nanod.toIrc <= nanoLatch[ NANO_TOIRC]; - - // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense. - // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway. - - Nanod.ablAbd <= nanoLatch[ NANO_ABLABD]; - Nanod.ablAbh <= nanoLatch[ NANO_ABLABH]; - Nanod.dblDbd <= nanoLatch[ NANO_DBLDBD]; - Nanod.dblDbh <= nanoLatch[ NANO_DBLDBH]; - - Nanod.dbl2Atl <= (atlCtrl == 3'b010); - Nanod.atl2Dbl <= (atlCtrl == 3'b011); - Nanod.abl2Atl <= (atlCtrl == 3'b100); - Nanod.atl2Abl <= (atlCtrl == 3'b101); - - Nanod.aob2Ab <= (athCtrl == 3'b101); // Used on BSER1 only - - Nanod.abh2Ath <= (athCtrl == 3'b001) | (athCtrl == 3'b101); - Nanod.dbh2Ath <= (athCtrl == 3'b100); - Nanod.ath2Dbh <= (athCtrl == 3'b110); - Nanod.ath2Abh <= (athCtrl == 3'b011); - - Nanod.alu2Dbd <= nanoLatch[ NANO_ALU2DBD]; - Nanod.alu2Abd <= nanoLatch[ NANO_ALU2ABD]; - - Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11); - Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11); - Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10); - Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01); - - Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB]; - Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB]; - - // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1. - Nanod.dobCtrl <= dobCtrl; - // Nanod.adb2Dob <= (dobCtrl == 2'b10); Nanod.dbd2Dob <= (dobCtrl == 2'b01); Nanod.alu2Dob <= (dobCtrl == 2'b11); - - end - end - - // Update SSW at the start of Bus/Addr error ucode - assign Nanod.updSsw = Nanod.aob2Ab; - - assign Nanod.updTpend = (ftuCtrl == NANO_FTU_UPDTPEND); - assign Nanod.clrTpend = (ftuCtrl == NANO_FTU_CLRTPEND); - assign Nanod.tvn2Ftu = (ftuCtrl == NANO_FTU_TVN); - assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST); - assign Nanod.ftu2Dbl = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL); - assign Nanod.ftu2Abl = (ftuCtrl == NANO_FTU_2ABL); - assign Nanod.inl2psw = (ftuCtrl == NANO_FTU_INL); - assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI); - assign Nanod.ftu2Sr = (ftuCtrl == NANO_FTU_2SR); - assign Nanod.sr2Ftu = (ftuCtrl == NANO_FTU_RDSR); - assign Nanod.ird2Ftu = (ftuCtrl == NANO_FTU_IRD); // Used on bus/addr error - assign Nanod.ssw2Ftu = (ftuCtrl == NANO_FTU_SSW); - assign Nanod.initST = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST); - assign Nanod.abl2Pren = (ftuCtrl == NANO_FTU_ABL2PREN); - assign Nanod.updPren = (ftuCtrl == NANO_FTU_RSTPREN); - - assign Nanod.Ir2Ird = nanoLatch[ NANO_IR2IRD]; - - // ALU control better latched later after combining with IRD decoding - - assign Nanod.aluDctrl = nanoLatch[ NANO_ALU_DCTRL+1 : NANO_ALU_DCTRL]; - assign Nanod.aluActrl = nanoLatch[ NANO_ALU_ACTRL]; - assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]}; - wire [1:0] aluFinInit = nanoLatch[ NANO_ALU_FI+1:NANO_ALU_FI]; - assign Nanod.aluFinish = (aluFinInit == 2'b10); - assign Nanod.aluInit = (aluFinInit == 2'b01); - - // FTU 2 CCR encoded as both ALU Init and ALU Finish set. - // In theory this encoding allows writes to CCR without writing to SR - // But FTU 2 CCR and to SR are both set together at nanorom. - assign Nanod.ftu2Ccr = ( aluFinInit == 2'b11); - - assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE]; - - // Not being latched on T4 creates non unique case warning! - assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b01); - assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b10); - assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b11); - - assign Nanod.db2Aob = (aobCtrl == 2'b10); - assign Nanod.ab2Aob = (aobCtrl == 2'b01); - assign Nanod.au2Aob = (aobCtrl == 2'b11); - - assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD]; - assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD]; - - assign Nanod.permStart = (| aobCtrl); - assign Nanod.isWrite = ( | dobCtrl); - assign Nanod.waitBusFinish = nanoLatch[ NANO_TOIRC] | nanoLatch[ NANO_TODBIN] | Nanod.isWrite; - assign Nanod.busByte = nanoLatch[ NANO_BUSBYTE]; - - assign Nanod.noLowByte = nanoLatch[ NANO_LOWBYTE]; - assign Nanod.noHighByte = nanoLatch[ NANO_HIGHBYTE]; - - // Not registered. Register at T4 after combining - // Might be better to remove all those and combine here instead of at execution unit !! - assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG]; - assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG]; - assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG]; - assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG]; - assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL]; - assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH]; - assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL]; - assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH]; - - assign Nanod.ssp = nanoLatch[ NANO_SSP]; - - assign Nanod.rz = nanoLatch[ NANO_RZ]; - - // Actually DTL can't happen on PC relative mode. See IR decoder. - - wire dtldbd = 1'b0; - wire dthdbh = 1'b0; - wire dtlabd = 1'b0; - wire dthabh = 1'b0; - - wire dblSpecial = Nanod.pcldbl | dtldbd; - wire dbhSpecial = Nanod.pchdbh | dthdbh; - wire ablSpecial = Nanod.pclabl | dtlabd; - wire abhSpecial = Nanod.pchabh | dthabh; - - // - // Combine with IRD decoding - // Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4! - // - - // PC used instead of RY on PC relative instuctions - - assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL]; - wire isPcRel = Irdecod.isPcRel & !Nanod.rz; - wire pcRelDbl = isPcRel & !nanoLatch[ NANO_RXL_DBL]; - wire pcRelDbh = isPcRel & !nanoLatch[ NANO_RXH_DBH]; - wire pcRelAbl = isPcRel & nanoLatch[ NANO_RXL_DBL]; - wire pcRelAbh = isPcRel & nanoLatch[ NANO_RXH_DBH]; - - assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl; - assign Nanod.pchdbh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b01) | pcRelDbh; - - assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl; - assign Nanod.pchabh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b10) | pcRelAbh; - - // Might be better not to register these signals to allow latching RX/RY mux earlier! - // But then must latch Irdecod.isPcRel on T3! - - always_ff @( posedge Clks.clk) begin - if( enT4) begin - Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; - Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; - - Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; - Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; - - Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; - Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; - - Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; - Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; - - Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; - Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; - - Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; - Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; - - Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; - Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; - - Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; - Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; - end - - // Originally isTas only delayed on T2 (and seems only a late mask rev fix) - // Better latch the combination on T4 - if( enT4) - Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE]; - end - - -endmodule - -// -// IRD execution decoder. Complements nano code decoder -// -// IRD updated on T1, while ncode still executing. To avoid using the next IRD, -// decoded signals must be registered on T3, or T4 before using them. -// -module irdDecode( input [15:0] ird, - output s_irdecod Irdecod); - - wire [3:0] line = ird[15:12]; - logic [15:0] lineOnehot; - - // This can be registered and pipelined from the IR decoder ! - onehotEncoder4 irdLines( line, lineOnehot); - - wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11); - wire isDynShift = isRegShift & ird[5]; - - assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1]; - assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011); - - assign Irdecod.rx = ird[11:9]; - assign Irdecod.ry = ird[ 2:0]; - - wire isPreDecr = (ird[ 5:3] == 3'b100); - wire eaAreg = (ird[5:3] == 3'b001); - - // rx is A or D - // movem - always_comb begin - unique case( 1'b1) - lineOnehot[1], - lineOnehot[2], - lineOnehot[3]: - // MOVE: RX always Areg except if dest mode is Dn 000 - Irdecod.rxIsAreg = (| ird[8:6]); - - lineOnehot[4]: Irdecod.rxIsAreg = (& ird[8:6]); // not CHK (LEA) - - lineOnehot['h8]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // SBCD - lineOnehot['hc]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // ABCD/EXG An,An - - lineOnehot['h9], - lineOnehot['hb], - lineOnehot['hd]: Irdecod.rxIsAreg = - (ird[7] & ird[6]) | // SUBA/CMPA/ADDA - (eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX - default: - Irdecod.rxIsAreg = Irdecod.implicitSp; - endcase - end - - // RX is movem - always_comb begin - Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp; - end - assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr; - - // RX is DT. - // but SSP explicit or pc explicit has higher priority! - // addq/subq (scc & dbcc also, but don't use rx) - // Immediate including static bit - assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]); - - // RX is USP - assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6); - - // RY is DT - // rz or PC explicit has higher priority - - wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1]; - assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift; - - // RY is Address register - always_comb begin - logic eaIsAreg; - - // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) - eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111); - - unique case( 1'b1) - // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) - // Most lines, including misc line 4, also. - default: Irdecod.ryIsAreg = eaIsAreg; - - lineOnehot[5]: // DBcc is an exception - Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001); - - lineOnehot[6], - lineOnehot[7]: Irdecod.ryIsAreg = 1'b0; - - lineOnehot['he]: - Irdecod.ryIsAreg = ~isRegShift; - endcase - end - - // Byte sized instruction - - // Original implementation sets this for some instructions that aren't really byte size - // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ - - wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001); - wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00); // Static bit to mem - always_comb begin - unique case( 1'b1) - lineOnehot[0]: - Irdecod.isByte = - ( ird[8] & (ird[5:4] != 2'b00) ) | // Dynamic bit to mem - ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00) ) | // Static bit to mem - ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001) ) | // Movep from mem only! For byte mux - ( (ird[8:6] == 3'b000) & !xStaticMem ); // Immediate byte - - lineOnehot[1]: Irdecod.isByte = 1'b1; // MOVE.B - - - lineOnehot[4]: Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas; - lineOnehot[5]: Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc; - - lineOnehot[8], - lineOnehot[9], - lineOnehot['hb], - lineOnehot['hc], - lineOnehot['hd], - lineOnehot['he]: Irdecod.isByte = (ird[7:6] == 2'b00); - - default: Irdecod.isByte = 1'b0; - endcase - end - - // Need it for special byte size. Bus is byte, but whole register word is modified. - assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg; - - - // rxIsSP implicit use of RX for actual SP transfer - // - // This logic is simple and will include some instructions that don't actually reference SP. - // But doesn't matter as long as they don't perform any RX transfer. - - always_comb begin - unique case( 1'b1) - lineOnehot[6]: Irdecod.implicitSp = (ird[11:8] == 4'b0001); // BSR - lineOnehot[4]: - // Misc like RTS, JSR, etc - Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01); - default: Irdecod.implicitSp = 1'b0; - endcase - end - - // Modify CCR (and not SR) - // Probably overkill !! Only needs to distinguish SR vs CCR - // RTR, MOVE to CCR, xxxI to CCR - assign Irdecod.toCcr = ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) | - ( lineOnehot[0] & (ird[8:6] == 3'b000)); - - // FTU constants - // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3. - // Note: Reset instruction gets constant from ALU not from FTU! - logic [15:0] ftuConst; - wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]}; // xltate 0,1-7 into 8,1-7 - - always_comb begin - unique case( 1'b1) - lineOnehot[6], // Bcc short - lineOnehot[7]: ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] }; // MOVEQ - - lineOnehot['h5], // addq/subq/static shift double check this - lineOnehot['he]: ftuConst = { 12'b0, zero28}; - - // MULU/MULS DIVU/DIVS - lineOnehot['h8], - lineOnehot['hc]: ftuConst = 16'h0f; - - lineOnehot[4]: ftuConst = 16'h80; // TAS - - default: ftuConst = '0; - endcase - end - assign Irdecod.ftuConst = ftuConst; - - // - // TRAP Vector # for group 2 exceptions - // - - always_comb begin - if( lineOnehot[4]) begin - case ( ird[6:5]) - 2'b00,2'b01: Irdecod.macroTvn = 6; // CHK - 2'b11: Irdecod.macroTvn = 7; // TRAPV - 2'b10: Irdecod.macroTvn = {2'b10, ird[3:0]}; // TRAP - endcase - end - else - Irdecod.macroTvn = 5; // Division by zero - end - - - wire eaAdir = (ird[ 5:3] == 3'b001); - wire size11 = ird[7] & ird[6]; - - // Opcodes variants that don't affect flags - // ADDA/SUBA ADDQ/SUBQ MOVEA - - assign Irdecod.inhibitCcr = - ( (lineOnehot[9] | lineOnehot['hd]) & size11) | // ADDA/SUBA - ( lineOnehot[5] & eaAdir) | // ADDQ/SUBQ to An (originally checks for line[4] as well !?) - ( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001); // MOVEA - -endmodule - -/* - Execution unit - - Executes register transfers set by the microcode. Originally through a set of bidirectional buses. - Most sources are available at T3, but DBIN only at T4! CCR also might be updated at T4, but it is not connected to these buses. - We mux at T1 and T2, then transfer to the destination at T3. The exception is AOB that need to be updated earlier. - -*/ - -module excUnit( input s_clks Clks, - input enT1, enT2, enT3, enT4, - input s_nanod Nanod, input s_irdecod Irdecod, - input [15:0] Ird, // ALU row (and others) decoder needs it - input pswS, - input [15:0] ftu, - input [15:0] iEdb, - - output logic [7:0] ccr, - output [15:0] alue, - - output prenEmpty, au05z, - output logic dcr4, ze, - output logic aob0, - output [15:0] AblOut, - output logic [15:0] Irc, - output logic [15:0] oEdb, - output logic [23:1] eab); - -localparam REG_USP = 15; -localparam REG_SSP = 16; -localparam REG_DT = 17; - - // Register file - reg [15:0] regs68L[ 18]; - reg [15:0] regs68H[ 18]; - -// synthesis translate off - /* - It is bad practice to initialize simulation registers that the hardware doesn't. - There is risk that simulation would be different than the real hardware. But in this case is the other way around. - Some ROM uses something like sub.l An,An at powerup which clears the register - Simulator power ups the registers with 'X, as they are really undetermined at the real hardware. - But the simulator doesn't realize (it can't) that the same value is substracting from itself, - and that the result should be zero even when it's 'X - 'X. - */ - - initial begin - for( int i = 0; i < 18; i++) begin - regs68L[i] <= '0; - regs68H[i] <= '0; - end - end - - // For simulation display only - wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]}; - -// synthesis translate on - - - wire [15:0] aluOut; - wire [15:0] dbin; - logic [15:0] dcrOutput; - - reg [15:0] PcL, PcH; - - reg [31:0] auReg, aob; - - reg [15:0] Ath, Atl; - - // Bus execution - reg [15:0] Dbl, Dbh; - reg [15:0] Abh, Abl; - reg [15:0] Abd, Dbd; - - assign AblOut = Abl; - assign au05z = (~| auReg[5:0]); - - logic [15:0] dblMux, dbhMux; - logic [15:0] abhMux, ablMux; - logic [15:0] abdMux, dbdMux; - - logic abdIsByte; - - logic Pcl2Dbl, Pch2Dbh; - logic Pcl2Abl, Pch2Abh; - - - // RX RY muxes - // RX and RY actual registers - logic [4:0] actualRx, actualRy; - logic [3:0] movemRx; - logic byteNotSpAlign; // Byte instruction and no sp word align - - // IRD decoded signals must be latched. See comments on decoder - // But nanostore decoding can't be latched before T4. - // - // If we need this earlier we can register IRD decode on T3 and use nano async - - logic [4:0] rxMux, ryMux; - logic [3:0] rxReg, ryReg; - logic rxIsSp, ryIsSp; - logic rxIsAreg, ryIsAreg; - - always_comb begin - - // Unique IF !! - if( Nanod.ssp) begin - rxMux = REG_SSP; - rxIsSp = 1'b1; - rxReg = 1'bX; - end - else if( Irdecod.rxIsUsp) begin - rxMux = REG_USP; - rxIsSp = 1'b1; - rxReg = 1'bX; - end - else if( Irdecod.rxIsDt & !Irdecod.implicitSp) begin - rxMux = REG_DT; - rxIsSp = 1'b0; - rxReg = 1'bX; - end - else begin - if( Irdecod.implicitSp) - rxReg = 15; - else if( Irdecod.rxIsMovem) - rxReg = movemRx; - else - rxReg = { Irdecod.rxIsAreg, Irdecod.rx}; - - if( (& rxReg)) begin - rxMux = pswS ? REG_SSP : 15; - rxIsSp = 1'b1; - end - else begin - rxMux = { 1'b0, rxReg}; - rxIsSp = 1'b0; - end - end - - // RZ has higher priority! - if( Irdecod.ryIsDt & !Nanod.rz) begin - ryMux = REG_DT; - ryIsSp = 1'b0; - ryReg = 'X; - end - else begin - ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry}; - ryIsSp = (& ryReg); - if( ryIsSp & pswS) // No implicit SP on RY - ryMux = REG_SSP; - else - ryMux = { 1'b0, ryReg}; - end - - end - - always_ff @( posedge Clks.clk) begin - if( enT4) begin - byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp); - - actualRx <= rxMux; - actualRy <= ryMux; - - rxIsAreg <= rxIsSp | rxMux[3]; - ryIsAreg <= ryIsSp | ryMux[3]; - end - - if( enT4) - abdIsByte <= Nanod.abdIsByte & Irdecod.isByte; - end - - // Set RX/RY low word to which bus segment is connected. - - wire ryl2Abl = Nanod.ryl2ab & (ryIsAreg | Nanod.ablAbd); - wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd); - wire ryl2Dbl = Nanod.ryl2db & (ryIsAreg | Nanod.dblDbd); - wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd); - - wire rxl2Abl = Nanod.rxl2ab & (rxIsAreg | Nanod.ablAbd); - wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd); - wire rxl2Dbl = Nanod.rxl2db & (rxIsAreg | Nanod.dblDbd); - wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd); - - // Buses. Main mux - - logic abhIdle, ablIdle, abdIdle; - logic dbhIdle, dblIdle, dbdIdle; - - always_comb begin - {abhIdle, ablIdle, abdIdle} = '0; - {dbhIdle, dblIdle, dbdIdle} = '0; - - unique case( 1'b1) - ryl2Dbd: dbdMux = regs68L[ actualRy]; - rxl2Dbd: dbdMux = regs68L[ actualRx]; - Nanod.alue2Dbd: dbdMux = alue; - Nanod.dbin2Dbd: dbdMux = dbin; - Nanod.alu2Dbd: dbdMux = aluOut; - Nanod.dcr2Dbd: dbdMux = dcrOutput; - default: begin dbdMux = 'X; dbdIdle = 1'b1; end - endcase - - unique case( 1'b1) - rxl2Dbl: dblMux = regs68L[ actualRx]; - ryl2Dbl: dblMux = regs68L[ actualRy]; - Nanod.ftu2Dbl: dblMux = ftu; - Nanod.au2Db: dblMux = auReg[15:0]; - Nanod.atl2Dbl: dblMux = Atl; - Pcl2Dbl: dblMux = PcL; - default: begin dblMux = 'X; dblIdle = 1'b1; end - endcase - - unique case( 1'b1) - Nanod.rxh2dbh: dbhMux = regs68H[ actualRx]; - Nanod.ryh2dbh: dbhMux = regs68H[ actualRy]; - Nanod.au2Db: dbhMux = auReg[31:16]; - Nanod.ath2Dbh: dbhMux = Ath; - Pch2Dbh: dbhMux = PcH; - default: begin dbhMux = 'X; dbhIdle = 1'b1; end - endcase - - unique case( 1'b1) - ryl2Abd: abdMux = regs68L[ actualRy]; - rxl2Abd: abdMux = regs68L[ actualRx]; - Nanod.dbin2Abd: abdMux = dbin; - Nanod.alu2Abd: abdMux = aluOut; - default: begin abdMux = 'X; abdIdle = 1'b1; end - endcase - - unique case( 1'b1) - Pcl2Abl: ablMux = PcL; - rxl2Abl: ablMux = regs68L[ actualRx]; - ryl2Abl: ablMux = regs68L[ actualRy]; - Nanod.ftu2Abl: ablMux = ftu; - Nanod.au2Ab: ablMux = auReg[15:0]; - Nanod.aob2Ab: ablMux = aob[15:0]; - Nanod.atl2Abl: ablMux = Atl; - default: begin ablMux = 'X; ablIdle = 1'b1; end - endcase - - unique case( 1'b1) - Pch2Abh: abhMux = PcH; - Nanod.rxh2abh: abhMux = regs68H[ actualRx]; - Nanod.ryh2abh: abhMux = regs68H[ actualRy]; - Nanod.au2Ab: abhMux = auReg[31:16]; - Nanod.aob2Ab: abhMux = aob[31:16]; - Nanod.ath2Abh: abhMux = Ath; - default: begin abhMux = 'X; abhIdle = 1'b1; end - endcase - - end - - // Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3. - - // These registers store the first level mux, without bus interconnections. - // Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster. - reg [15:0] preAbh, preAbl, preAbd; - reg [15:0] preDbh, preDbl, preDbd; - - always_ff @( posedge Clks.clk) begin - - // Register first level mux at T1 - if( enT1) begin - {preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux}; - {preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux}; - end - - // Process bus interconnection at T2. Many combinations only used on DIV - // We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment. - // In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter. - - if( enT2) begin - if( Nanod.extAbh) - Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }}; - else if( abhIdle) - Abh <= ablIdle ? preAbd : preAbl; - else - Abh <= preAbh; - - if( ~ablIdle) - Abl <= preAbl; - else - Abl <= Nanod.ablAbh ? preAbh : preAbd; - - Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl; - - if( Nanod.extDbh) - Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }}; - else if( dbhIdle) - Dbh <= dblIdle ? preDbd : preDbl; - else - Dbh <= preDbh; - - if( ~dblIdle) - Dbl <= preDbl; - else - Dbl <= Nanod.dblDbh ? preDbh : preDbd; - - Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl; - - /* - Dbl <= dblMux; Dbh <= dbhMux; - Abd <= abdMux; Dbd <= dbdMux; - Abh <= abhMux; Abl <= ablMux; */ - end - end - - // AOB - // - // Originally change on T1. We do on T2, only then the output is enabled anyway. - // - // AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3. - // It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical. - // But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1. - - // We need to take directly from first level muxes that are updated and T1 - - wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob); - - always_ff @( posedge Clks.clk) begin - // UNIQUE IF ! - - if( enT1 & au2Aob) // From AU we do can on T1 - aob <= auReg; - else if( enT2) begin - if( Nanod.db2Aob) - aob <= { preDbh, ~dblIdle ? preDbl : preDbd}; - else if( Nanod.ab2Aob) - aob <= { preAbh, ~ablIdle ? preAbl : preAbd}; - end - end - - assign eab = aob[23:1]; - assign aob0 = aob[0]; - - // AU - logic [31:0] auInpMux; - - // `ifdef ALW_COMB_BUG - // Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !? - // always @( Nanod.auCntrl) begin - - always_comb begin - unique case( Nanod.auCntrl) - 3'b000: auInpMux = 0; - 3'b001: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 1 : 2; // +1/+2 - 3'b010: auInpMux = -4; - 3'b011: auInpMux = { Abh, Abl}; - 3'b100: auInpMux = 2; - 3'b101: auInpMux = 4; - 3'b110: auInpMux = -2; - 3'b111: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? -1 : -2; // -1/-2 - default: auInpMux = 'X; - endcase - end - - // Simulation problem - // Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero. - // But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X. - -// synthesis translate_off - `define SIMULBUGX32 1 - wire [16:0] aulow = Dbl + auInpMux[15:0]; - wire [31:0] auResult = {Dbh + auInpMux[31:16] + aulow[16], aulow[15:0]}; -// synthesis translate_on - - always_ff @( posedge Clks.clk) begin - if( Clks.pwrUp) - auReg <= '0; - else if( enT3 & Nanod.auClkEn) - `ifdef SIMULBUGX32 - auReg <= auResult; - `else - auReg <= { Dbh, Dbl } + auInpMux; - `endif - end - - - // Main A/D registers - - always_ff @( posedge Clks.clk) begin - if( enT3) begin - if( Nanod.dbl2rxl | Nanod.abl2rxl) begin - if( ~rxIsAreg) begin - if( Nanod.dbl2rxl) regs68L[ actualRx] <= Dbd; - else if( abdIsByte) regs68L[ actualRx][7:0] <= Abd[7:0]; - else regs68L[ actualRx] <= Abd; - end - else - regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl; - end - - if( Nanod.dbl2ryl | Nanod.abl2ryl) begin - if( ~ryIsAreg) begin - if( Nanod.dbl2ryl) regs68L[ actualRy] <= Dbd; - else if( abdIsByte) regs68L[ actualRy][7:0] <= Abd[7:0]; - else regs68L[ actualRy] <= Abd; - end - else - regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl; - end - - // High registers are easier. Both A & D on the same buses, and not byte ops. - if( Nanod.dbh2rxh | Nanod.abh2rxh) - regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh; - if( Nanod.dbh2ryh | Nanod.abh2ryh) - regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh; - - end - end - - // PC & AT - reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl; - - always_ff @( posedge Clks.clk) begin - if( Clks.extReset) begin - { dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0; - - Pcl2Dbl <= 1'b0; - Pch2Dbh <= 1'b0; - Pcl2Abl <= 1'b0; - Pch2Abh <= 1'b0; - end - else if( enT4) begin // Must latch on T4 ! - dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl; - dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh; - abh2Pch <= Nanod.abh2reg & Nanod.pchabh; - abl2Pcl <= Nanod.abl2reg & Nanod.pclabl; - - Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl; - Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh; - Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl; - Pch2Abh <= Nanod.reg2abh & Nanod.pchabh; - end - - // Unique IF !!! - if( enT1 & Nanod.au2Pc) - PcL <= auReg[15:0]; - else if( enT3) begin - if( dbl2Pcl) - PcL <= Dbl; - else if( abl2Pcl) - PcL <= Abl; - end - - // Unique IF !!! - if( enT1 & Nanod.au2Pc) - PcH <= auReg[31:16]; - else if( enT3) begin - if( dbh2Pch) - PcH <= Dbh; - else if( abh2Pch) - PcH <= Abh; - end - - // Unique IF !!! - if( enT3) begin - if( Nanod.dbl2Atl) - Atl <= Dbl; - else if( Nanod.abl2Atl) - Atl <= Abl; - end - - // Unique IF !!! - if( enT3) begin - if( Nanod.abh2Ath) - Ath <= Abh; - else if( Nanod.dbh2Ath) - Ath <= Dbh; - end - - end - - // Movem reg mask priority encoder - - wire rmIdle; - logic [3:0] prHbit; - logic [15:0] prenLatch; - - // Invert reg order for predecrement mode - assign prenEmpty = (~| prenLatch); - pren rmPren( .mask( prenLatch), .hbit (prHbit)); - - always_ff @( posedge Clks.clk) begin - // Cheating: PREN always loaded from DBIN - // Must be on T1 to branch earlier if reg mask is empty! - if( enT1 & Nanod.abl2Pren) - prenLatch <= dbin; - else if( enT3 & Nanod.updPren) begin - prenLatch [prHbit] <= 1'b0; - movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit; - end - end - - // DCR - wire [15:0] dcrCode; - - wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0]; - onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode)); - - always_ff @( posedge Clks.clk) begin - if( Clks.pwrUp) - dcr4 <= '0; - else if( enT3 & Nanod.abd2Dcr) begin - dcrOutput <= dcrCode; - dcr4 <= Abd[4]; - end - end - - // ALUB - reg [15:0] alub; - - always_ff @( posedge Clks.clk) begin - if( enT3) begin - // UNIQUE IF !! - if( Nanod.dbd2Alub) - alub <= Dbd; - else if( Nanod.abd2Alub) - alub <= Abd; // abdIsByte affects this !!?? - end - end - - wire alueClkEn = enT3 & Nanod.dbd2Alue; - - // DOB/DBIN/IRC - - logic [15:0] dobInput; - wire dobIdle = (~| Nanod.dobCtrl); - - always_comb begin - unique case (Nanod.dobCtrl) - NANO_DOB_ADB: dobInput = Abd; - NANO_DOB_DBD: dobInput = Dbd; - NANO_DOB_ALU: dobInput = aluOut; - default: dobInput = 'X; - endcase - end - - dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod, - .iEdb, .dobIdle, .dobInput, .aob0, - .Irc, .dbin, .oEdb); - - fx68kAlu alu( - .clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4, - .ird( Ird), - .aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl), - .init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte), - .ftu2Ccr( Nanod.ftu2Ccr), - .alub, .ftu, .alueClkEn, .alue, - .aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd), - .ze, .aluOut, .ccr); - -endmodule - -// -// Data bus I/O -// At a separate module because it is a bit complicated and the timing is special. -// Here we do the low/high byte mux and the special case of MOVEP. -// -// Original implementation is rather complex because both the internal and external buses are bidirectional. -// Input is latched async at the EDB register. -// We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period. - -module dataIo( input s_clks Clks, - input enT1, enT2, enT3, enT4, - input s_nanod Nanod, input s_irdecod Irdecod, - input [15:0] iEdb, - input aob0, - - input dobIdle, - input [15:0] dobInput, - - output logic [15:0] Irc, - output logic [15:0] dbin, - output logic [15:0] oEdb - ); - - reg [15:0] dob; - - // DBIN/IRC - - // Timing is different than any other register. We can latch only on the next T4 (bus phase S7). - // We need to register all control signals correctly because the next ublock will already be started. - // Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch. - - reg xToDbin, xToIrc; - reg dbinNoLow, dbinNoHigh; - reg byteMux, isByte_T4; - - always_ff @( posedge Clks.clk) begin - - // Byte mux control. Can't latch at T1. AOB might be not ready yet. - // Must latch IRD decode at T1 (or T4). Then combine and latch only at T3. - - // Can't latch at T3, a new IRD might be loaded already at T1. - // Ok to latch at T4 if combination latched then at T3 - if( enT4) - isByte_T4 <= Irdecod.isByte; // Includes MOVEP from mem, we could OR it here - - if( enT3) begin - dbinNoHigh <= Nanod.noHighByte; - dbinNoLow <= Nanod.noLowByte; - byteMux <= Nanod.busByte & isByte_T4 & ~aob0; - end - - if( enT1) begin - // If on wait states, we continue latching until next T1 - xToDbin <= 1'b0; - xToIrc <= 1'b0; - end - else if( enT3) begin - xToDbin <= Nanod.todbin; - xToIrc <= Nanod.toIrc; - end - - // Capture on T4 of the next ucycle - // If there are wait states, we keep capturing every PHI2 until the next T1 - - if( xToIrc & Clks.enPhi2) - Irc <= iEdb; - if( xToDbin & Clks.enPhi2) begin - // Original connects both halves of EDB. - if( ~dbinNoLow) - dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0]; - if( ~dbinNoHigh) - dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8]; - end - end - - // DOB - logic byteCycle; - - always_ff @( posedge Clks.clk) begin - // Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables. - // It is safe to do on T3, then, but control signals if derived from IRD must be registered. - // Originally control signals are not registered. - - // Wait states don't affect DOB operation that is done at the start of the bus cycle. - - if( enT4) - byteCycle <= Nanod.busByte & Irdecod.isByte; // busIsByte but not MOVEP - - // Originally byte low/high interconnect is done at EDB, not at DOB. - if( enT3 & ~dobIdle) begin - dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0]; - dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8]; - end - end - assign oEdb = dob; - -endmodule - - -// Provides ucode routine entries (A1/A3) for each opcode -// Also checks for illegal opcode and priv violation - -// This is one of the slowest part of the processor. -// But no need to optimize or pipeline because the result is not needed until at least 4 cycles. -// IR updated at the least one microinstruction earlier. -// Just need to configure the timing analizer correctly. - -module uaddrDecode( - input [15:0] opcode, - output [UADDR_WIDTH-1:0] a1, a2, a3, - output logic isPriv, isIllegal, isLineA, isLineF, - output [15:0] lineBmap); - - wire [3:0] line = opcode[15:12]; - logic [3:0] eaCol, movEa; - - onehotEncoder4 irLineDecod( line, lineBmap); - - assign isLineA = lineBmap[ 'hA]; - assign isLineF = lineBmap[ 'hF]; - - pla_lined pla_lined( .movEa( movEa), .col( eaCol), - .opcode( opcode), .lineBmap( lineBmap), - .palIll( isIllegal), .plaA1( a1), .plaA2( a2), .plaA3( a3) ); - - // ea decoding - assign eaCol = eaDecode( opcode[ 5:0]); - assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} ); - - // EA decode - function [3:0] eaDecode; - input [5:0] eaBits; - begin - unique case( eaBits[ 5:3]) - 3'b111: - case( eaBits[ 2:0]) - 3'b000: eaDecode = 7; // Absolute short - 3'b001: eaDecode = 8; // Absolute long - 3'b010: eaDecode = 9; // PC displacement - 3'b011: eaDecode = 10; // PC offset - 3'b100: eaDecode = 11; // Immediate - default: eaDecode = 12; // Invalid - endcase - - default: eaDecode = eaBits[5:3]; // Register based EAs - endcase - end - endfunction - - - /* - Privileged instructions: - - ANDI/EORI/ORI SR - MOVE to SR - MOVE to/from USP - RESET - RTE - STOP - */ - - always_comb begin - unique case( lineBmap) - - // ori/andi/eori SR - 'h01: isPriv = ((opcode & 16'hf5ff) == 16'h007c); - - 'h10: - begin - // No priority !!! - if( (opcode & 16'hffc0) == 16'h46c0) // move to sr - isPriv = 1'b1; - - else if( (opcode & 16'hfff0) == 16'h4e60) // move usp - isPriv = 1'b1; - - else if( opcode == 16'h4e70 || // reset - opcode == 16'h4e73 || // rte - opcode == 16'h4e72) // stop - isPriv = 1'b1; - else - isPriv = 1'b0; - end - - default: isPriv = 1'b0; - endcase - end - - -endmodule - -// bin to one-hot, 4 bits to 16-bit bitmap -module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap); - always_comb begin - case( bin) - 'b0000: bitMap = 16'h0001; - 'b0001: bitMap = 16'h0002; - 'b0010: bitMap = 16'h0004; - 'b0011: bitMap = 16'h0008; - 'b0100: bitMap = 16'h0010; - 'b0101: bitMap = 16'h0020; - 'b0110: bitMap = 16'h0040; - 'b0111: bitMap = 16'h0080; - 'b1000: bitMap = 16'h0100; - 'b1001: bitMap = 16'h0200; - 'b1010: bitMap = 16'h0400; - 'b1011: bitMap = 16'h0800; - 'b1100: bitMap = 16'h1000; - 'b1101: bitMap = 16'h2000; - 'b1110: bitMap = 16'h4000; - 'b1111: bitMap = 16'h8000; - endcase - end -endmodule - -// priority encoder -// used by MOVEM regmask -// this might benefit from device specific features -// MOVEM doesn't need speed, will read the result 2 CPU cycles after each update. -module pren( mask, hbit); - parameter size = 16; - parameter outbits = 4; - - input [size-1:0] mask; - output reg [outbits-1:0] hbit; - // output reg idle; - - always @( mask) begin - integer i; - hbit = 0; - // idle = 1; - for( i = size-1; i >= 0; i = i - 1) begin - if( mask[ i]) begin - hbit = i; - // idle = 0; - end - end - end - -endmodule - -// Microcode sequencer - -module sequencer( input s_clks Clks, input enT3, - input [UROM_WIDTH-1:0] microLatch, - input A0Err, BerrA, busAddrErr, Spuria, Avia, - input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF, - input [15:0] psw, - input prenEmpty, au05z, dcr4, ze, i11, - input [1:0] alue01, - input [15:0] Ird, - input [UADDR_WIDTH-1:0] a1, a2, a3, - output logic [3:0] tvn, - output logic [UADDR_WIDTH-1:0] nma); - - logic [UADDR_WIDTH-1:0] uNma; - logic [UADDR_WIDTH-1:0] grp1Nma; - logic [1:0] c0c1; - reg a0Rst; - wire A0Sel; - wire inGrp0Exc; - - // assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma); - // assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma; - - // word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 - // NMA : .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. .. - - wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]}; - - // Group 0 exception. - // Separated block from regular NMA. Otherwise simulation might depend on order of assigments. - always_comb begin - if( A0Err) begin - if( a0Rst) // Reset - nma = RSTP0_NMA; - else if( inGrp0Exc) // Double fault - nma = HALT1_NMA; - else // Bus or address error - nma = BSER1_NMA; - end - else - nma = uNma; - end - - always_comb begin - // Format II (conditional) or I (direct branch) - if( microLatch[1]) - uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]}; - else - case( microLatch[ 3:2]) - 0: uNma = dbNma; // DB - 1: uNma = A0Sel ? grp1Nma : a1; - 2: uNma = a2; - 3: uNma = a3; - endcase - end - - // Format II, conditional, NMA decoding - wire [1:0] enl = { Ird[6], prenEmpty}; // Updated on T3 - - wire [1:0] ms0 = { Ird[8], alue01[0]}; - wire [3:0] m01 = { au05z, Ird[8], alue01}; - wire [1:0] nz1 = { psw[ NF], psw[ ZF]}; - wire [1:0] nv = { psw[ NF], psw[ VF]}; - - logic ccTest; - wire [4:0] cbc = microLatch[ 6:2]; // CBC bits - - always_comb begin - unique case( cbc) - 'h0: c0c1 = {i11, i11}; // W/L offset EA, from IRC - - 'h1: c0c1 = (au05z) ? 2'b01 : 2'b11; // Updated on T3 - 'h11: c0c1 = (au05z) ? 2'b00 : 2'b11; - - 'h02: c0c1 = { 1'b0, ~psw[ CF]}; // C used in DIV - 'h12: c0c1 = { 1'b1, ~psw[ CF]}; - - 'h03: c0c1 = {psw[ ZF], psw[ ZF]}; // Z used in DIVU - - 'h04: // nz1, used in DIVS - case( nz1) - 'b00: c0c1 = 2'b10; - 'b10: c0c1 = 2'b01; - 'b01,'b11: c0c1 = 2'b11; - endcase - - 'h05: c0c1 = {psw[ NF], 1'b1}; // N used in CHK and DIV - 'h15: c0c1 = {1'b1, psw[ NF]}; - - // nz2, used in DIVS (same combination as nz1) - 'h06: c0c1 = { ~nz1[1] & ~nz1[0], 1'b1}; - - 'h07: // ms0 used in MUL - case( ms0) - 'b10, 'b00: c0c1 = 2'b11; - 'b01: c0c1 = 2'b01; - 'b11: c0c1 = 2'b10; - endcase - - 'h08: // m01 used in MUL - case( m01) - 'b0000,'b0001,'b0100,'b0111: c0c1 = 2'b11; - 'b0010,'b0011,'b0101: c0c1 = 2'b01; - 'b0110: c0c1 = 2'b10; - default: c0c1 = 2'b00; - endcase - - // Conditional - 'h09: c0c1 = (ccTest) ? 2'b11 : 2'b01; - 'h19: c0c1 = (ccTest) ? 2'b11 : 2'b10; - - // DCR bit 4 (high or low word) - 'h0c: c0c1 = dcr4 ? 2'b01: 2'b11; - 'h1c: c0c1 = dcr4 ? 2'b10: 2'b11; - - // DBcc done - 'h0a: c0c1 = ze ? 2'b11 : 2'b00; - - // nv, used in CHK - 'h0b: c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11; - - // V, used in trapv - 'h0d: c0c1 = { ~psw[ VF], ~psw[VF]}; - - // enl, combination of pren idle and word/long on IRD - 'h0e,'h1e: - case( enl) - 2'b00: c0c1 = 'b10; - 2'b10: c0c1 = 'b11; - // 'hx1 result 00/01 depending on condition 0e/1e - 2'b01,2'b11: - c0c1 = { 1'b0, microLatch[ 6]}; - endcase - - default: c0c1 = 'X; - endcase - end - - // CCR conditional - always_comb begin - unique case( Ird[ 11:8]) - 'h0: ccTest = 1'b1; // T - 'h1: ccTest = 1'b0; // F - 'h2: ccTest = ~psw[ CF] & ~psw[ ZF]; // HI - 'h3: ccTest = psw[ CF] | psw[ZF]; // LS - 'h4: ccTest = ~psw[ CF]; // CC (HS) - 'h5: ccTest = psw[ CF]; // CS (LO) - 'h6: ccTest = ~psw[ ZF]; // NE - 'h7: ccTest = psw[ ZF]; // EQ - 'h8: ccTest = ~psw[ VF]; // VC - 'h9: ccTest = psw[ VF]; // VS - 'ha: ccTest = ~psw[ NF]; // PL - 'hb: ccTest = psw[ NF]; // MI - 'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]); // GE - 'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]); // LT - 'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) | - (~psw[ NF] & ~psw[ VF] & ~psw[ ZF]); // GT - 'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]); // LE - endcase - end - - // Exception logic - logic rTrace, rInterrupt; - logic rIllegal, rPriv, rLineA, rLineF; - logic rExcRst, rExcAdrErr, rExcBusErr; - logic rSpurious, rAutovec; - wire grp1LatchEn, grp0LatchEn; - - // Originally control signals latched on T4. Then exception latches updated on T3 - assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]); - assign grp0LatchEn = microLatch[4] & !microLatch[1]; - - assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr; - - always_ff @( posedge Clks.clk) begin - if( grp0LatchEn & enT3) begin - rExcRst <= excRst; - rExcBusErr <= BerrA; - rExcAdrErr <= busAddrErr; - rSpurious <= Spuria; - rAutovec <= Avia; - end - - // Update group 1 exception latches - // Inputs from IR decoder updated on T1 as soon as IR loaded - // Trace pending updated on T3 at the start of the instruction - // Interrupt pending on T2 - if( grp1LatchEn & enT3) begin - rTrace <= Tpend; - rInterrupt <= intPend; - rIllegal <= isIllegal & ~isLineA & ~isLineF; - rLineA <= isLineA; - rLineF <= isLineF; - rPriv <= isPriv & !psw[ SF]; - end - end - - // exception priority - always_comb begin - grp1Nma = TRAC1_NMA; - if( rExcRst) - tvn = '0; // Might need to change that to signal in exception - else if( rExcBusErr | rExcAdrErr) - tvn = { 1'b1, rExcAdrErr}; - - // Seudo group 0 exceptions. Just for updating TVN - else if( rSpurious | rAutovec) - tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC; - - else if( rTrace) - tvn = 9; - else if( rInterrupt) begin - tvn = TVN_INTERRUPT; - grp1Nma = ITLX1_NMA; - end - else begin - unique case( 1'b1) // Can't happen more than one of these - rIllegal: tvn = 4; - rPriv: tvn = 8; - rLineA: tvn = 10; - rLineF: tvn = 11; - default: tvn = 1; // Signal no group 0/1 exception - endcase - end - end - - assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt; - - always_ff @( posedge Clks.clk) begin - if( Clks.extReset) - a0Rst <= 1'b1; - else if( enT3) - a0Rst <= 1'b0; - end - -endmodule - - -// -// DMA/BUS Arbitration -// - -module busArbiter( input s_clks Clks, - input BRi, BgackI, Halti, bgBlock, - output busAvail, - output logic BGn); - - enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next; - - always_comb begin - case(dmaPhase) - DRESET: next = DIDLE; - DIDLE: begin - if( bgBlock) - next = DIDLE; - else if( ~BgackI) - next = D_BA; - else if( ~BRi) - next = D1; - else - next = DIDLE; - end - - D_BA: begin // Loop while only BGACK asserted, BG negated here - if( ~BRi & !bgBlock) - next = D3; - else if( ~BgackI & !bgBlock) - next = D_BA; - else - next = DIDLE; - end - - D1: next = D_BR; // Loop while only BR asserted - D_BR: next = ~BRi & BgackI ? D_BR : D_BA; // No direct path to IDLE ! - - D3: next = D_BRA; - D_BRA: begin // Loop while both BR and BGACK asserted - case( {BgackI, BRi} ) - 2'b11: next = DIDLE; // Both deasserted - 2'b10: next = D_BR; // BR asserted only - 2'b01: next = D2; // BGACK asserted only - 2'b00: next = D_BRA; // Stay here while both asserted - endcase - end - - // Might loop here if both deasserted, should normally don't arrive here anyway? - // D2: next = (BgackI & BRi) | bgBlock ? D2: D_BA; - - D2: next = D_BA; - - default: next = DIDLE; // Should not reach here normally - endcase - end - - logic granting; - always_comb begin - unique case( next) - D1, D3, D_BR, D_BRA: granting = 1'b1; - default: granting = 1'b0; - endcase - end - - reg rGranted; - assign busAvail = Halti & BRi & BgackI & ~rGranted; - - always_ff @( posedge Clks.clk) begin - if( Clks.extReset) begin - dmaPhase <= DRESET; - rGranted <= 1'b0; - end - else if( Clks.enPhi2) begin - dmaPhase <= next; - // Internal signal changed on PHI2 - rGranted <= granting; - end - - // External Output changed on PHI1 - if( Clks.extReset) - BGn <= 1'b1; - else if( Clks.enPhi1) - BGn <= ~rGranted; - - end - -endmodule - -module busControl( input s_clks Clks, input enT1, input enT4, - input permStart, permStop, iStop, - input aob0, - input isWrite, isByte, isRmc, - input busAvail, - output bgBlock, - output busAddrErr, - output waitBusCycle, - output busStarting, // Asserted during S0 - output logic addrOe, // Asserted from S1 to the end, whole bus cycle except S0 - output bciWrite, // Used for SSW on bus/addr error - - input rDtack, BeDebounced, Vpai, - output ASn, output LDSn, output UDSn, eRWn); - - reg rAS, rLDS, rUDS, rRWn; - assign ASn = rAS; - assign LDSn = rLDS; - assign UDSn = rUDS; - assign eRWn = rRWn; - - reg dataOe; - - reg bcPend; - reg isWriteReg, bciByte, isRmcReg, wendReg; - assign bciWrite = isWriteReg; - reg addrOeDelay; - reg isByteT4; - - wire canStart, busEnd; - wire bcComplete, bcReset; - - wire isRcmReset = bcComplete & bcReset & isRmcReg; - - assign busAddrErr = aob0 & ~bciByte; - - // Bus retry not really supported. - // It's BERR and HALT and not address error, and not read-modify cycle. - wire busRetry = ~busAddrErr & 1'b0; - - enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next; - - always_ff @( posedge Clks.clk) begin - if( Clks.extReset) - busPhase <= SRESET; - else if( Clks.enPhi1) - busPhase <= next; - end - - always_comb begin - case( busPhase) - SRESET: next = SIDLE; - SRMC_RES: next = SIDLE; // Single cycle special state when read phase of RMC reset - S0: next = S2; - S2: next = S4; - S4: next = busEnd ? S6 : S4; - S6: next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE); - SIDLE: next = canStart ? S0 : SIDLE; - default: next = SIDLE; - endcase - end - - // Idle phase of RMC bus cycle. Might be better to just add a new state - wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg; - - assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset; - - wire busEnding = (next == SIDLE) | (next == S0); - - assign busStarting = (busPhase == S0); - - // term signal (DTACK, BERR, VPA, adress error) - assign busEnd = ~rDtack | iStop; - - // bcComplete asserted on raising edge of S6 (together with SNC). - assign bcComplete = (busPhase == S6); - - // Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1). - // bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently - wire bciClear = bcComplete & ~busRetry; - - // Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1) - assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai); - - // Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop - assign waitBusCycle = wendReg & !bcComplete; - - // Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC) - // Except that when that RMC phase aborted on bus error, it's asserted one cycle later! - assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES); - - always_ff @( posedge Clks.clk) begin - if( Clks.extReset) begin - addrOe <= 1'b0; - end - else if( Clks.enPhi2 & ( busPhase == S0)) // From S1, whole bus cycle except S0 - addrOe <= 1'b1; - else if( Clks.enPhi1 & (busPhase == SRMC_RES)) - addrOe <= 1'b0; - else if( Clks.enPhi1 & ~isRmcReg & busEnding) - addrOe <= 1'b0; - - if( Clks.enPhi1) - addrOeDelay <= addrOe; - - if( Clks.extReset) begin - rAS <= 1'b1; - rUDS <= 1'b1; - rLDS <= 1'b1; - rRWn <= 1'b1; - dataOe <= '0; - end - else begin - - if( Clks.enPhi2 & isWriteReg & (busPhase == S2)) - dataOe <= 1'b1; - else if( Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) ) - dataOe <= 1'b0; - - if( Clks.enPhi1 & busEnding) - rRWn <= 1'b1; - else if( Clks.enPhi1 & isWriteReg) begin - // Unlike LDS/UDS Asserted even in address error - if( (busPhase == S0) & isWriteReg) - rRWn <= 1'b0; - end - - // AS. Actually follows addrOe half cycle later! - if( Clks.enPhi1 & (busPhase == S0)) - rAS <= 1'b0; - else if( Clks.enPhi2 & (busPhase == SRMC_RES)) // Bus error on read phase of RMC. Deasserted one cycle later - rAS <= 1'b1; - else if( Clks.enPhi2 & bcComplete & ~SRMC_RES) - if( ~isRmcReg) // Keep AS asserted on the IDLE phase of RMC - rAS <= 1'b1; - - if( Clks.enPhi1 & (busPhase == S0)) begin - if( ~isWriteReg & !busAddrErr) begin - rUDS <= ~(~bciByte | ~aob0); - rLDS <= ~(~bciByte | aob0); - end - end - else if( Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin - rUDS <= ~(~bciByte | ~aob0); - rLDS <= ~(~bciByte | aob0); - end - else if( Clks.enPhi2 & bcComplete) begin - rUDS <= 1'b1; - rLDS <= 1'b1; - end - - end - - end - - // Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait. - // Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches. - // Even without wait states, ublocks of type ir (init reading) will not wait for bus completion. - // Originally latched on (permStart AND T1). - - // Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4? - // permStop also latched, but unconditionally on T1 - - // Might make more sense to register this outside this module - always_ff @( posedge Clks.clk) begin - if( enT4) begin - isByteT4 <= isByte; - end - end - - // Bus Cycle Info Latch - always_ff @( posedge Clks.clk) begin - if( Clks.pwrUp) begin - bcPend <= 1'b0; - wendReg <= 1'b0; - isWriteReg <= 1'b0; - bciByte <= 1'b0; - isRmcReg <= 1'b0; - end - - else if( Clks.enPhi2 & (bciClear | bcReset)) begin - bcPend <= 1'b0; - wendReg <= 1'b0; - end - else begin - if( enT1 & permStart) begin - isWriteReg <= isWrite; - bciByte <= isByteT4; - isRmcReg <= isRmc & ~isWrite; // We need special case the end of the read phase only. - bcPend <= 1'b1; - end - if( enT1) - wendReg <= permStop; - end - end - -endmodule - -// -// microrom and nanorom instantiation -// -// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed. -// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance. -// Might be more efficient to use vendor specific features such as clock enable. -// - -module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput); - reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH]; - initial begin - $readmemb("microrom.mem", uRam); - end - - always_ff @( posedge clk) - microOutput <= uRam[ microAddr]; -endmodule - - -module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput); - reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH]; - initial begin - $readmemb("nanorom.mem", nRam); - end - - always_ff @( posedge clk) - nanoOutput <= nRam[ nanoAddr]; -endmodule - -// Translate uaddr to nanoaddr -module microToNanoAddr( - input [UADDR_WIDTH-1:0] uAddr, - output [NADDR_WIDTH-1:0] orgAddr); - - wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2]; - logic [NADDR_WIDTH-1:2] orgBase; - assign orgAddr = { orgBase, uAddr[1:0]}; - - always @( baseAddr) - begin - // nano ROM (136 addresses) - case( baseAddr) - -'h00: orgBase = 7'h0 ; -'h01: orgBase = 7'h1 ; -'h02: orgBase = 7'h2 ; -'h03: orgBase = 7'h2 ; -'h08: orgBase = 7'h3 ; -'h09: orgBase = 7'h4 ; -'h0A: orgBase = 7'h5 ; -'h0B: orgBase = 7'h5 ; -'h10: orgBase = 7'h6 ; -'h11: orgBase = 7'h7 ; -'h12: orgBase = 7'h8 ; -'h13: orgBase = 7'h8 ; -'h18: orgBase = 7'h9 ; -'h19: orgBase = 7'hA ; -'h1A: orgBase = 7'hB ; -'h1B: orgBase = 7'hB ; -'h20: orgBase = 7'hC ; -'h21: orgBase = 7'hD ; -'h22: orgBase = 7'hE ; -'h23: orgBase = 7'hD ; -'h28: orgBase = 7'hF ; -'h29: orgBase = 7'h10 ; -'h2A: orgBase = 7'h11 ; -'h2B: orgBase = 7'h10 ; -'h30: orgBase = 7'h12 ; -'h31: orgBase = 7'h13 ; -'h32: orgBase = 7'h14 ; -'h33: orgBase = 7'h14 ; -'h38: orgBase = 7'h15 ; -'h39: orgBase = 7'h16 ; -'h3A: orgBase = 7'h17 ; -'h3B: orgBase = 7'h17 ; -'h40: orgBase = 7'h18 ; -'h41: orgBase = 7'h18 ; -'h42: orgBase = 7'h18 ; -'h43: orgBase = 7'h18 ; -'h44: orgBase = 7'h19 ; -'h45: orgBase = 7'h19 ; -'h46: orgBase = 7'h19 ; -'h47: orgBase = 7'h19 ; -'h48: orgBase = 7'h1A ; -'h49: orgBase = 7'h1A ; -'h4A: orgBase = 7'h1A ; -'h4B: orgBase = 7'h1A ; -'h4C: orgBase = 7'h1B ; -'h4D: orgBase = 7'h1B ; -'h4E: orgBase = 7'h1B ; -'h4F: orgBase = 7'h1B ; -'h54: orgBase = 7'h1C ; -'h55: orgBase = 7'h1D ; -'h56: orgBase = 7'h1E ; -'h57: orgBase = 7'h1F ; -'h5C: orgBase = 7'h20 ; -'h5D: orgBase = 7'h21 ; -'h5E: orgBase = 7'h22 ; -'h5F: orgBase = 7'h23 ; -'h70: orgBase = 7'h24 ; -'h71: orgBase = 7'h24 ; -'h72: orgBase = 7'h24 ; -'h73: orgBase = 7'h24 ; -'h74: orgBase = 7'h24 ; -'h75: orgBase = 7'h24 ; -'h76: orgBase = 7'h24 ; -'h77: orgBase = 7'h24 ; -'h78: orgBase = 7'h25 ; -'h79: orgBase = 7'h25 ; -'h7A: orgBase = 7'h25 ; -'h7B: orgBase = 7'h25 ; -'h7C: orgBase = 7'h25 ; -'h7D: orgBase = 7'h25 ; -'h7E: orgBase = 7'h25 ; -'h7F: orgBase = 7'h25 ; -'h84: orgBase = 7'h26 ; -'h85: orgBase = 7'h27 ; -'h86: orgBase = 7'h28 ; -'h87: orgBase = 7'h29 ; -'h8C: orgBase = 7'h2A ; -'h8D: orgBase = 7'h2B ; -'h8E: orgBase = 7'h2C ; -'h8F: orgBase = 7'h2D ; -'h94: orgBase = 7'h2E ; -'h95: orgBase = 7'h2F ; -'h96: orgBase = 7'h30 ; -'h97: orgBase = 7'h31 ; -'h9C: orgBase = 7'h32 ; -'h9D: orgBase = 7'h33 ; -'h9E: orgBase = 7'h34 ; -'h9F: orgBase = 7'h35 ; -'hA4: orgBase = 7'h36 ; -'hA5: orgBase = 7'h36 ; -'hA6: orgBase = 7'h37 ; -'hA7: orgBase = 7'h37 ; -'hAC: orgBase = 7'h38 ; -'hAD: orgBase = 7'h38 ; -'hAE: orgBase = 7'h39 ; -'hAF: orgBase = 7'h39 ; -'hB4: orgBase = 7'h3A ; -'hB5: orgBase = 7'h3A ; -'hB6: orgBase = 7'h3B ; -'hB7: orgBase = 7'h3B ; -'hBC: orgBase = 7'h3C ; -'hBD: orgBase = 7'h3C ; -'hBE: orgBase = 7'h3D ; -'hBF: orgBase = 7'h3D ; -'hC0: orgBase = 7'h3E ; -'hC1: orgBase = 7'h3F ; -'hC2: orgBase = 7'h40 ; -'hC3: orgBase = 7'h41 ; -'hC8: orgBase = 7'h42 ; -'hC9: orgBase = 7'h43 ; -'hCA: orgBase = 7'h44 ; -'hCB: orgBase = 7'h45 ; -'hD0: orgBase = 7'h46 ; -'hD1: orgBase = 7'h47 ; -'hD2: orgBase = 7'h48 ; -'hD3: orgBase = 7'h49 ; -'hD8: orgBase = 7'h4A ; -'hD9: orgBase = 7'h4B ; -'hDA: orgBase = 7'h4C ; -'hDB: orgBase = 7'h4D ; -'hE0: orgBase = 7'h4E ; -'hE1: orgBase = 7'h4E ; -'hE2: orgBase = 7'h4F ; -'hE3: orgBase = 7'h4F ; -'hE8: orgBase = 7'h50 ; -'hE9: orgBase = 7'h50 ; -'hEA: orgBase = 7'h51 ; -'hEB: orgBase = 7'h51 ; -'hF0: orgBase = 7'h52 ; -'hF1: orgBase = 7'h52 ; -'hF2: orgBase = 7'h52 ; -'hF3: orgBase = 7'h52 ; -'hF8: orgBase = 7'h53 ; -'hF9: orgBase = 7'h53 ; -'hFA: orgBase = 7'h53 ; -'hFB: orgBase = 7'h53 ; - - default: - orgBase = 'X; - endcase - end - -endmodule - -// -// For compilation test only -// - -`ifdef FX68K_TEST -module fx68kTop( input clk32, - input extReset, - // input pwrUp, - - input DTACKn, input VPAn, - input BERRn, - input BRn, BGACKn, - input IPL0n, input IPL1n, input IPL2n, - input [15:0] iEdb, - - output [15:0] oEdb, - output eRWn, output ASn, output LDSn, output UDSn, - output logic E, output VMAn, - output FC0, output FC1, output FC2, - output BGn, - output oRESETn, output oHALTEDn, - output [23:1] eab - ); - - // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency. - // In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz. - - reg [1:0] clkDivisor = '0; - always @( posedge clk32) begin - clkDivisor <= clkDivisor + 1'b1; - end - - /* - These two signals must be a single cycle pulse. They don't need to be registered. - Same signal can't be asserted twice in a row. Other than that there are no restrictions. - There can be any number of cycles, or none, even variable non constant cycles, between each pulse. - */ - - wire enPhi1 = (clkDivisor == 2'b11); - wire enPhi2 = (clkDivisor == 2'b01); - - - fx68k fx68k( .clk( clk32), - .extReset, .pwrUp( extReset), .enPhi1, .enPhi2, - - .DTACKn, .VPAn, .BERRn, .BRn, .BGACKn, - .IPL0n, .IPL1n, .IPL2n, - .iEdb, - - .oEdb, - .eRWn, .ASn, .LDSn, .UDSn, - .E, .VMAn, - .FC0, .FC1, .FC2, - .BGn, - .oRESETn, .oHALTEDn, .eab); - -endmodule -`endif +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/fx68k.txt b/common/CPU/68000/FX68k/fx68k.txt index 3397c02f..7ad0b47f 100644 --- a/common/CPU/68000/FX68k/fx68k.txt +++ b/common/CPU/68000/FX68k/fx68k.txt @@ -72,16 +72,3 @@ set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/micr set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 1 set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 1 - -The update of the CCR flags is also time critical. Some compilers might benefit with the following constraints, but this wasn't fully verified yet: - - -# Altera/Intel -# set_multicycle_path -start -setup -from [fx68k:fx68k|nanoLatch[*]] -# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 -# set_multicycle_path -start -setup -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] -# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 -# set_multicycle_path -start -hold -from [fx68k:fx68k|nanoLatch[*]] -# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 -# set_multicycle_path -start -hold -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] -# -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 diff --git a/common/CPU/68000/FX68k/fx68k.vhd b/common/CPU/68000/FX68k/fx68k.vhd deleted file mode 100644 index 1f169a8b..00000000 --- a/common/CPU/68000/FX68k/fx68k.vhd +++ /dev/null @@ -1,39 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; - -package fx68k is -COMPONENT fx68k -PORT -( - clk : in std_logic; - extReset : in std_logic; -- External sync reset on emulated system - pwrUp : in std_logic; -- Asserted together with reset on emulated system coldstart - enPhi1 : in std_logic; - enPhi2 : in std_logic; -- Clock enables. Next cycle is PHI1 or PHI2 - - eRWn : out std_logic; - ASn : out std_logic; - LDSn : out std_logic; - UDSn : out std_logic; - E : out std_logic; - VMAn : out std_logic; - FC0 : out std_logic; - FC1 : out std_logic; - FC2 : out std_logic; - BGn : out std_logic; - oRESETn : out std_logic; - oHALTEDn : out std_logic; - DTACKn : in std_logic; - VPAn : in std_logic; - BERRn : in std_logic; - BRn : in std_logic; - BGACKn : in std_logic; - IPL0n : in std_logic; - IPL1n : in std_logic; - IPL2n : in std_logic; - iEdb : in std_logic_vector(15 downto 0); - oEdb : out std_logic_vector(15 downto 0); - eab : out std_logic_vector(23 downto 1) -); -END COMPONENT; -end package; \ No newline at end of file diff --git a/common/CPU/68000/FX68k/fx68kAlu.sv b/common/CPU/68000/FX68k/fx68kAlu.sv index 95059c43..347b033d 100644 --- a/common/CPU/68000/FX68k/fx68kAlu.sv +++ b/common/CPU/68000/FX68k/fx68kAlu.sv @@ -96,15 +96,31 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, wire [15:0] cRow; wire cIsArX; wire cNoCcrEn; - rowDecoder rowDecoder( .ird( ird), .row( cRow), .noCcrEn( cNoCcrEn), .isArX( cIsArX)); + rowDecoder rowDecoder( + .ird ( ird), + .row ( cRow), + .noCcrEn ( cNoCcrEn), + .isArX ( cIsArX) + ); // Get Operation & CCR Mask from row/col // Registering them on T4 increase performance. But slowest part seems to be corf ! wire [4:0] cMask; wire [4:0] aluOp; - aluGetOp aluGetOp( .row, .col( aluColumn), .isCorf, .aluOp); - ccrTable ccrTable( .col( aluColumn), .row( row), .finish, .ccrMask( cMask)); + aluGetOp aluGetOp( + .row ( row), + .col ( aluColumn), + .isCorf ( isCorf), + .aluOp ( aluOp) + ); + + ccrTable ccrTable( + .col ( aluColumn), + .row ( row), + .finish ( finish), + .ccrMask ( cMask) + ); // Inefficient, uCode could help ! wire shftIsMul = row[7]; @@ -161,16 +177,26 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, // Can't be registered because uses bus operands that aren't available early ! wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]); - aluShifter shifter( .data( { alue, aOperand}), - .swapWords( shftIsMul | shftIsDiv), - .cin( shftCin), .dir( shftRight), .isByte( isByte), .isLong( isLong), - .result( shftResult)); + aluShifter shifter( + .data ( { alue, aOperand}), + .swapWords ( shftIsMul | shftIsDiv), + .cin ( shftCin), + .dir ( shftRight), + .isByte ( isByte), + .isLong ( isLong), + .result ( shftResult) + ); wire [7:0] bcdResult; wire bcdC, bcdV; - aluCorf aluCorf( .binResult( aluLatch[7:0]), .hCarry( coreH), - .bAdd( (oper != OP_SBCD) ), .cin( pswCcr[ XF]), - .bcdResult( bcdResult), .dC( bcdC), .ov( bcdV)); + aluCorf aluCorf( + .binResult ( aluLatch[7:0]), + .hCarry ( coreH), + .bAdd ( (oper != OP_SBCD) ), + .cin ( pswCcr[ XF]), + .bcdResult ( bcdResult), + .dC ( bcdC), + .ov ( bcdV)); // BCD adjust is among the slowest processing on ALU ! // Precompute and register BCD result on T1 @@ -306,7 +332,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, ccrTemp[XF] = pswCcr[XF]; ccrTemp[CF] = 0; ccrTemp[VF] = 0; - // Not on all operators + // Not on all operators !!! ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result); ccrTemp[ NF] = isByte ? result[7] : result[15]; @@ -315,8 +341,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, OP_EXT: // Division overflow. if( aluColumn == 5) begin - ccrTemp[VF] = 1'b1; - ccrTemp[NF] = 1'b1; ccrTemp[ ZF] = 1'b0; + ccrTemp[VF] = 1'b1; ccrTemp[NF] = 1'b1; end OP_SUB0, // used by NOT @@ -413,8 +438,7 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, logic [4:0] ccrMasked; always_comb begin ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask); - // if( finish | isCorf | isArX) // No need to check specicially for isCorf as they always have the "finish" flag anyway - if( finish | isArX) + if( finish | isCorf | isArX) ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF]; end @@ -452,388 +476,4 @@ module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4, endmodule -// add bcd correction factor -// It would be more efficient to merge add/sub with main ALU !!! -module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry, - output [7:0] bcdResult, output dC, output logic ov); - reg [8:0] htemp; - reg [4:0] hNib; - - wire lowC = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0); - wire highC = cin | (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0); - - always_comb begin - if( bAdd) begin - htemp = { 1'b0, binResult} + (lowC ? 4'h6 : 4'h0); - hNib = htemp[8:4] + (highC ? 4'h6 : 4'h0); - ov = hNib[3] & ~binResult[7]; - end - else begin - htemp = { 1'b0, binResult} - (lowC ? 4'h6 : 4'h0); - hNib = htemp[8:4] - (highC ? 4'h6 : 4'h0); - ov = ~hNib[3] & binResult[7]; - end - end - - assign bcdResult = { hNib[ 3:0], htemp[3:0]}; - assign dC = hNib[4] | cin; - - // Nibble > 9 - function gt9 (input [3:0] nib); - begin - gt9 = nib[3] & (nib[2] | nib[1]); - end - endfunction - -endmodule - - -module aluShifter( input [31:0] data, - input isByte, input isLong, swapWords, - input dir, input cin, - output logic [31:0] result); - // output reg cout - - logic [31:0] tdata; - - // size mux, put cin in position if dir == right - always_comb begin - tdata = data; - if( isByte & dir) - tdata[8] = cin; - else if( !isLong & dir) - tdata[16] = cin; - end - - always_comb begin - // Reverse alu/alue position for MUL & DIV - // Result reversed again - if( swapWords & dir) - result = { tdata[0], tdata[31:17], cin, tdata[15:1]}; - else if( swapWords) - result = { tdata[30:16], cin, tdata[14:0], tdata[31]}; - - else if( dir) - result = { cin, tdata[31:1]}; - else - result = { tdata[30:0], cin}; - end - -endmodule - - -// Get current OP from row & col -module aluGetOp( input [15:0] row, input [2:0] col, input isCorf, - output logic [4:0] aluOp); - - always_comb begin - aluOp = 'X; - unique case( col) - 1: aluOp = OP_AND; - 5: aluOp = OP_EXT; - - default: - unique case( 1'b1) - row[1]: - unique case( col) - 2: aluOp = OP_SUB; - 3: aluOp = OP_SUBC; - 4,6: aluOp = OP_SLAA; - endcase - - row[2]: - unique case( col) - 2: aluOp = OP_ADD; - 3: aluOp = OP_ADDC; - 4: aluOp = OP_ASR; - endcase - - row[3]: - unique case( col) - 2: aluOp = OP_ADDX; - 3: aluOp = isCorf ? OP_ABCD : OP_ADD; - 4: aluOp = OP_ASL; - endcase - - row[4]: - aluOp = ( col == 4) ? OP_LSL : OP_AND; - - row[5], - row[6]: - unique case( col) - 2: aluOp = OP_SUB; - 3: aluOp = OP_SUBC; - 4: aluOp = OP_LSR; - endcase - - row[7]: // MUL - unique case( col) - 2: aluOp = OP_SUB; - 3: aluOp = OP_ADD; - 4: aluOp = OP_ROXR; - endcase - - row[8]: - // OP_AND For EXT.L - // But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1! - unique case( col) - 2: aluOp = OP_EXT; - 3: aluOp = OP_AND; - 4: aluOp = OP_ROXR; - endcase - - row[9]: - unique case( col) - 2: aluOp = OP_SUBX; - 3: aluOp = OP_SBCD; - 4: aluOp = OP_ROL; - endcase - - row[10]: - unique case( col) - 2: aluOp = OP_SUBX; - 3: aluOp = OP_SUBC; - 4: aluOp = OP_ROR; - endcase - - row[11]: - unique case( col) - 2: aluOp = OP_SUB0; - 3: aluOp = OP_SUB0; - 4: aluOp = OP_ROXL; - endcase - - row[12]: aluOp = OP_ADDX; - row[13]: aluOp = OP_EOR; - row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR; - row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc - - endcase - endcase - end -endmodule - -// Decodes IRD into ALU row (1-15) -// Slow, but no need to optimize for speed since IRD is latched at least two CPU cycles before it is used -// We also register the result after combining with column from nanocode -// -// Many opcodes are not decoded because they either don't do any ALU op, -// or use only columns 1 and 5 that are the same for all rows. - -module rowDecoder( input [15:0] ird, - output logic [15:0] row, output noCcrEn, output logic isArX); - - - // Addr or data register direct - wire eaRdir = (ird[ 5:4] == 2'b00); - // Addr register direct - wire eaAdir = (ird[ 5:3] == 3'b001); - wire size11 = ird[7] & ird[6]; - - always_comb begin - case( ird[15:12]) - 'h4, - 'h9, - 'hd: - isArX = row[10] | row[12]; - default: - isArX = 1'b0; - endcase - end - - always_comb begin - unique case( ird[15:12]) - - 'h4: begin - if( ird[8]) - row = `ALU_ROW_06; // chk (or lea) - else case( ird[11:9]) - 'b000: row = `ALU_ROW_10; // negx - 'b001: row = `ALU_ROW_04; // clr - 'b010: row = `ALU_ROW_05; // neg - 'b011: row = `ALU_ROW_11; // not - 'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09; // nbcd/swap/ext(or pea) - 'b101: row = `ALU_ROW_15; // tst & tas - default: row = 0; - endcase - end - - 'h0: begin - if( ird[8]) // dynamic bit - row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; - else case( ird[ 11:9]) - 'b000: row = `ALU_ROW_14; // ori - 'b001: row = `ALU_ROW_04; // andi - 'b010: row = `ALU_ROW_05; // subi - 'b011: row = `ALU_ROW_02; // addi - 'b100: row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; // static bit - 'b101: row = `ALU_ROW_13; // eori - 'b110: row = `ALU_ROW_06; // cmpi - default: row = 0; - endcase - end - - // MOVE - // move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded. - // It's the same for move the operations performed by MOVE.B - - 'h1,'h2,'h3: row = `ALU_ROW_02; - - 'h5: - if( size11) - row = `ALU_ROW_15; // As originally and easier to decode - else - row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02; // addq/subq - 'h6: row = 0; //bcc/bra/bsr - 'h7: row = `ALU_ROW_02; // moveq - 'h8: - if( size11) // div - row = `ALU_ROW_01; - else if( ird[8] & eaRdir) // sbcd - row = `ALU_ROW_09; - else - row = `ALU_ROW_14; // or - 'h9: - if( ird[8] & ~size11 & eaRdir) - row = `ALU_ROW_10; // subx - else - row = `ALU_ROW_05; // sub/suba - 'hb: - if( ird[8] & ~size11 & ~eaAdir) - row = `ALU_ROW_13; // eor - else - row = `ALU_ROW_06; // cmp/cmpa/cmpm - 'hc: - if( size11) - row = `ALU_ROW_07; // mul - else if( ird[8] & eaRdir) // abcd - row = `ALU_ROW_03; - else - row = `ALU_ROW_04; // and - 'hd: - if( ird[8] & ~size11 & eaRdir) - row = `ALU_ROW_12; // addx - else - row = `ALU_ROW_02; // add/adda - 'he: - begin - reg [1:0] stype; - - if( size11) // memory shift/rotate - stype = ird[ 10:9]; - else // register shift/rotate - stype = ird[ 4:3]; - - case( {stype, ird[8]}) - 0: row = `ALU_ROW_02; // ASR - 1: row = `ALU_ROW_03; // ASL - 2: row = `ALU_ROW_05; // LSR - 3: row = `ALU_ROW_04; // LSL - 4: row = `ALU_ROW_08; // ROXR - 5: row = `ALU_ROW_11; // ROXL - 6: row = `ALU_ROW_10; // ROR - 7: row = `ALU_ROW_09; // ROL - endcase - end - - default: row = 0; - endcase - end - - // Decode opcodes that don't affect flags - // ADDA/SUBA ADDQ/SUBQ MOVEA - - assign noCcrEn = - // ADDA/SUBA - ( ird[15] & ~ird[13] & ird[12] & size11) | - // ADDQ/SUBQ to An - ( (ird[15:12] == 4'h5) & eaAdir) | - // MOVEA - ( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001); - -endmodule - -// Row/col CCR update table -module ccrTable( - input [2:0] col, input [15:0] row, input finish, - output logic [MASK_NBITS-1:0] ccrMask); - - localparam - KNZ00 = 5'b01111, // ok coz operators clear them - KKZKK = 5'b00100, - KNZKK = 5'b01100, - KNZ10 = 5'b01111, // Used by OP_EXT on divison overflow - KNZ0C = 5'b01111, // Used by DIV. V should be 0, but it is ok: - // DIVU: ends with quotient - 0, so V & C always clear. - // DIVS: ends with 1i (AND), again, V & C always clear. - - KNZVC = 5'b01111, - XNKVC = 5'b11011, // Used by BCD instructions. Don't modify Z at all at the binary operation. Only at the BCD correction cycle - - CUPDALL = 5'b11111, - CUNUSED = 5'bxxxxx; - - - logic [MASK_NBITS-1:0] ccrMask1; - - always_comb begin - unique case( col) - 1: ccrMask = ccrMask1; - - 2,3: - unique case( 1'b1) - row[1]: ccrMask = KNZ0C; // DIV, used as 3n in col3 - - row[3], // ABCD - row[9]: // SBCD/NBCD - ccrMask = (col == 2) ? XNKVC : CUPDALL; - - row[2], - row[5], - row[10], // SUBX/NEGX - row[12]: ccrMask = CUPDALL; // ADDX - - row[6], // CMP - row[7], // MUL - row[11]: ccrMask = KNZVC; // NOT - row[4], - row[8], // Not used in col 3 - row[13], - row[14]: ccrMask = KNZ00; - row[15]: ccrMask = 5'b0; // TAS/Scc, not used in col 3 - // default: ccrMask = CUNUSED; - endcase - - 4: - unique case( row) - // 1: DIV, only n (4n & 6n) - // 14: BCLR 4n - // 6,12,13,15 // not used - `ALU_ROW_02, - `ALU_ROW_03, // ASL (originally ANZVA) - `ALU_ROW_04, - `ALU_ROW_05: ccrMask = CUPDALL; // Shifts (originally ANZ0A) - - `ALU_ROW_07: ccrMask = KNZ00; // MUL (originally KNZ0A) - `ALU_ROW_09, - `ALU_ROW_10: ccrMask = KNZ00; // RO[lr] (originally KNZ0A) - `ALU_ROW_08, // ROXR (originally ANZ0A) - `ALU_ROW_11: ccrMask = CUPDALL; // ROXL (originally ANZ0A) - default: ccrMask = CUNUSED; - endcase - - 5: ccrMask = row[1] ? KNZ10 : 5'b0; - default: ccrMask = CUNUSED; - endcase - end - - // Column 1 (AND) - always_comb begin - if( finish) - ccrMask1 = row[7] ? KNZ00 : KNZKK; - else - ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00; - end - -endmodule diff --git a/common/CPU/68000/FX68k/fx68k_tb.sv b/common/CPU/68000/FX68k/fx68k_tb.sv new file mode 100644 index 00000000..de558a77 --- /dev/null +++ b/common/CPU/68000/FX68k/fx68k_tb.sv @@ -0,0 +1,57 @@ + +// +// For compilation test only +// + +module fx68k_tb( input clk32, + input extReset, + // input pwrUp, + + input DTACKn, input VPAn, + input BERRn, + input BRn, BGACKn, + input IPL0n, input IPL1n, input IPL2n, + input [15:0] iEdb, + + output [15:0] oEdb, + output eRWn, output ASn, output LDSn, output UDSn, + output logic E, output VMAn, + output FC0, output FC1, output FC2, + output BGn, + output oRESETn, output oHALTEDn, + output [23:1] eab + ); + + // Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency. + // In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz. + + reg [1:0] clkDivisor = '0; + always @( posedge clk32) begin + clkDivisor <= clkDivisor + 1'b1; + end + + /* + These two signals must be a single cycle pulse. They don't need to be registered. + Same signal can't be asserted twice in a row. Other than that there are no restrictions. + There can be any number of cycles, or none, even variable non constant cycles, between each pulse. + */ + + wire enPhi1 = (clkDivisor == 2'b11); + wire enPhi2 = (clkDivisor == 2'b01); + + + fx68k fx68k( .clk( clk32), + .extReset, .pwrUp( extReset), .enPhi1, .enPhi2, + + .DTACKn, .VPAn, .BERRn, .BRn, .BGACKn, + .IPL0n, .IPL1n, .IPL2n, + .iEdb, + + .oEdb, + .eRWn, .ASn, .LDSn, .UDSn, + .E, .VMAn, + .FC0, .FC1, .FC2, + .BGn, + .oRESETn, .oHALTEDn, .eab); + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/irdDecode.sv b/common/CPU/68000/FX68k/irdDecode.sv new file mode 100644 index 00000000..0a3d193a --- /dev/null +++ b/common/CPU/68000/FX68k/irdDecode.sv @@ -0,0 +1,208 @@ +// +// IRD execution decoder. Complements nano code decoder +// +// IRD updated on T1, while ncode still executing. To avoid using the next IRD, +// decoded signals must be registered on T3, or T4 before using them. +// +module irdDecode( input [15:0] ird, + output s_irdecod Irdecod); + + wire [3:0] line = ird[15:12]; + logic [15:0] lineOnehot; + + // This can be registered and pipelined from the IR decoder ! + onehotEncoder4 irdLines( line, lineOnehot); + + wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11); + wire isDynShift = isRegShift & ird[5]; + + assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1]; + assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011); + + assign Irdecod.rx = ird[11:9]; + assign Irdecod.ry = ird[ 2:0]; + + wire isPreDecr = (ird[ 5:3] == 3'b100); + wire eaAreg = (ird[5:3] == 3'b001); + + // rx is A or D + // movem + always_comb begin + unique case( 1'b1) + lineOnehot[1], + lineOnehot[2], + lineOnehot[3]: + // MOVE: RX always Areg except if dest mode is Dn 000 + Irdecod.rxIsAreg = (| ird[8:6]); + + lineOnehot[4]: Irdecod.rxIsAreg = (& ird[8:6]); // not CHK (LEA) + + lineOnehot['h8]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // SBCD + lineOnehot['hc]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // ABCD/EXG An,An + + lineOnehot['h9], + lineOnehot['hb], + lineOnehot['hd]: Irdecod.rxIsAreg = + (ird[7] & ird[6]) | // SUBA/CMPA/ADDA + (eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX + default: + Irdecod.rxIsAreg = Irdecod.implicitSp; + endcase + end + + // RX is movem + always_comb begin + Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp; + end + assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr; + + // RX is DT. + // but SSP explicit or pc explicit has higher priority! + // addq/subq (scc & dbcc also, but don't use rx) + // Immediate including static bit + assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]); + + // RX is USP + assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6); + + // RY is DT + // rz or PC explicit has higher priority + + wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1]; + assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift; + + // RY is Address register + always_comb begin + logic eaIsAreg; + + // On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) + eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111); + + unique case( 1'b1) + // MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL) + // Most lines, including misc line 4, also. + default: Irdecod.ryIsAreg = eaIsAreg; + + lineOnehot[5]: // DBcc is an exception + Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001); + + lineOnehot[6], + lineOnehot[7]: Irdecod.ryIsAreg = 1'b0; + + lineOnehot['he]: + Irdecod.ryIsAreg = ~isRegShift; + endcase + end + + // Byte sized instruction + + // Original implementation sets this for some instructions that aren't really byte size + // but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ + + wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001); + wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00); // Static bit to mem + always_comb begin + unique case( 1'b1) + lineOnehot[0]: + Irdecod.isByte = + ( ird[8] & (ird[5:4] != 2'b00) ) | // Dynamic bit to mem + ( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00) ) | // Static bit to mem + ( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001) ) | // Movep from mem only! For byte mux + ( (ird[8:6] == 3'b000) & !xStaticMem ); // Immediate byte + + lineOnehot[1]: Irdecod.isByte = 1'b1; // MOVE.B + + + lineOnehot[4]: Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas; + lineOnehot[5]: Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc; + + lineOnehot[8], + lineOnehot[9], + lineOnehot['hb], + lineOnehot['hc], + lineOnehot['hd], + lineOnehot['he]: Irdecod.isByte = (ird[7:6] == 2'b00); + + default: Irdecod.isByte = 1'b0; + endcase + end + + // Need it for special byte size. Bus is byte, but whole register word is modified. + assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg; + + + // rxIsSP implicit use of RX for actual SP transfer + // + // This logic is simple and will include some instructions that don't actually reference SP. + // But doesn't matter as long as they don't perform any RX transfer. + + always_comb begin + unique case( 1'b1) + lineOnehot[6]: Irdecod.implicitSp = (ird[11:8] == 4'b0001); // BSR + lineOnehot[4]: + // Misc like RTS, JSR, etc + Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01); + default: Irdecod.implicitSp = 1'b0; + endcase + end + + // Modify CCR (and not SR) + // Probably overkill !! Only needs to distinguish SR vs CCR + // RTR, MOVE to CCR, xxxI to CCR + assign Irdecod.toCcr = ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) | + ( lineOnehot[0] & (ird[8:6] == 3'b000)); + + // FTU constants + // This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3. + // Note: Reset instruction gets constant from ALU not from FTU! + logic [15:0] ftuConst; + wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]}; // xltate 0,1-7 into 8,1-7 + + always_comb begin + unique case( 1'b1) + lineOnehot[6], // Bcc short + lineOnehot[7]: ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] }; // MOVEQ + + lineOnehot['h5], // addq/subq/static shift double check this + lineOnehot['he]: ftuConst = { 12'b0, zero28}; + + // MULU/MULS DIVU/DIVS + lineOnehot['h8], + lineOnehot['hc]: ftuConst = 16'h0f; + + lineOnehot[4]: ftuConst = 16'h80; // TAS + + default: ftuConst = '0; + endcase + end + assign Irdecod.ftuConst = ftuConst; + + // + // TRAP Vector # for group 2 exceptions + // + + always_comb begin + if( lineOnehot[4]) begin + case ( ird[6:5]) + 2'b00,2'b01: Irdecod.macroTvn = 6; // CHK + 2'b11: Irdecod.macroTvn = 7; // TRAPV + 2'b10: Irdecod.macroTvn = {2'b10, ird[3:0]}; // TRAP + endcase + end + else + Irdecod.macroTvn = 5; // Division by zero + end + + + wire eaAdir = (ird[ 5:3] == 3'b001); + wire size11 = ird[7] & ird[6]; + + // Opcodes variants that don't affect flags + // ADDA/SUBA ADDQ/SUBQ MOVEA + + assign Irdecod.inhibitCcr = + ( (lineOnehot[9] | lineOnehot['hd]) & size11) | // ADDA/SUBA + ( lineOnehot[5] & eaAdir) | // ADDQ/SUBQ to An (originally checks for line[4] as well !?) + ( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001); // MOVEA + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/microToNanoAddr.sv b/common/CPU/68000/FX68k/microToNanoAddr.sv new file mode 100644 index 00000000..0113eb96 --- /dev/null +++ b/common/CPU/68000/FX68k/microToNanoAddr.sv @@ -0,0 +1,157 @@ +// Translate uaddr to nanoaddr +module microToNanoAddr( + input [UADDR_WIDTH-1:0] uAddr, + output [NADDR_WIDTH-1:0] orgAddr); + + wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2]; + logic [NADDR_WIDTH-1:2] orgBase; + assign orgAddr = { orgBase, uAddr[1:0]}; + + always @( baseAddr) + begin + // nano ROM (136 addresses) + case( baseAddr) + +'h00: orgBase = 7'h0 ; +'h01: orgBase = 7'h1 ; +'h02: orgBase = 7'h2 ; +'h03: orgBase = 7'h2 ; +'h08: orgBase = 7'h3 ; +'h09: orgBase = 7'h4 ; +'h0A: orgBase = 7'h5 ; +'h0B: orgBase = 7'h5 ; +'h10: orgBase = 7'h6 ; +'h11: orgBase = 7'h7 ; +'h12: orgBase = 7'h8 ; +'h13: orgBase = 7'h8 ; +'h18: orgBase = 7'h9 ; +'h19: orgBase = 7'hA ; +'h1A: orgBase = 7'hB ; +'h1B: orgBase = 7'hB ; +'h20: orgBase = 7'hC ; +'h21: orgBase = 7'hD ; +'h22: orgBase = 7'hE ; +'h23: orgBase = 7'hD ; +'h28: orgBase = 7'hF ; +'h29: orgBase = 7'h10 ; +'h2A: orgBase = 7'h11 ; +'h2B: orgBase = 7'h10 ; +'h30: orgBase = 7'h12 ; +'h31: orgBase = 7'h13 ; +'h32: orgBase = 7'h14 ; +'h33: orgBase = 7'h14 ; +'h38: orgBase = 7'h15 ; +'h39: orgBase = 7'h16 ; +'h3A: orgBase = 7'h17 ; +'h3B: orgBase = 7'h17 ; +'h40: orgBase = 7'h18 ; +'h41: orgBase = 7'h18 ; +'h42: orgBase = 7'h18 ; +'h43: orgBase = 7'h18 ; +'h44: orgBase = 7'h19 ; +'h45: orgBase = 7'h19 ; +'h46: orgBase = 7'h19 ; +'h47: orgBase = 7'h19 ; +'h48: orgBase = 7'h1A ; +'h49: orgBase = 7'h1A ; +'h4A: orgBase = 7'h1A ; +'h4B: orgBase = 7'h1A ; +'h4C: orgBase = 7'h1B ; +'h4D: orgBase = 7'h1B ; +'h4E: orgBase = 7'h1B ; +'h4F: orgBase = 7'h1B ; +'h54: orgBase = 7'h1C ; +'h55: orgBase = 7'h1D ; +'h56: orgBase = 7'h1E ; +'h57: orgBase = 7'h1F ; +'h5C: orgBase = 7'h20 ; +'h5D: orgBase = 7'h21 ; +'h5E: orgBase = 7'h22 ; +'h5F: orgBase = 7'h23 ; +'h70: orgBase = 7'h24 ; +'h71: orgBase = 7'h24 ; +'h72: orgBase = 7'h24 ; +'h73: orgBase = 7'h24 ; +'h74: orgBase = 7'h24 ; +'h75: orgBase = 7'h24 ; +'h76: orgBase = 7'h24 ; +'h77: orgBase = 7'h24 ; +'h78: orgBase = 7'h25 ; +'h79: orgBase = 7'h25 ; +'h7A: orgBase = 7'h25 ; +'h7B: orgBase = 7'h25 ; +'h7C: orgBase = 7'h25 ; +'h7D: orgBase = 7'h25 ; +'h7E: orgBase = 7'h25 ; +'h7F: orgBase = 7'h25 ; +'h84: orgBase = 7'h26 ; +'h85: orgBase = 7'h27 ; +'h86: orgBase = 7'h28 ; +'h87: orgBase = 7'h29 ; +'h8C: orgBase = 7'h2A ; +'h8D: orgBase = 7'h2B ; +'h8E: orgBase = 7'h2C ; +'h8F: orgBase = 7'h2D ; +'h94: orgBase = 7'h2E ; +'h95: orgBase = 7'h2F ; +'h96: orgBase = 7'h30 ; +'h97: orgBase = 7'h31 ; +'h9C: orgBase = 7'h32 ; +'h9D: orgBase = 7'h33 ; +'h9E: orgBase = 7'h34 ; +'h9F: orgBase = 7'h35 ; +'hA4: orgBase = 7'h36 ; +'hA5: orgBase = 7'h36 ; +'hA6: orgBase = 7'h37 ; +'hA7: orgBase = 7'h37 ; +'hAC: orgBase = 7'h38 ; +'hAD: orgBase = 7'h38 ; +'hAE: orgBase = 7'h39 ; +'hAF: orgBase = 7'h39 ; +'hB4: orgBase = 7'h3A ; +'hB5: orgBase = 7'h3A ; +'hB6: orgBase = 7'h3B ; +'hB7: orgBase = 7'h3B ; +'hBC: orgBase = 7'h3C ; +'hBD: orgBase = 7'h3C ; +'hBE: orgBase = 7'h3D ; +'hBF: orgBase = 7'h3D ; +'hC0: orgBase = 7'h3E ; +'hC1: orgBase = 7'h3F ; +'hC2: orgBase = 7'h40 ; +'hC3: orgBase = 7'h41 ; +'hC8: orgBase = 7'h42 ; +'hC9: orgBase = 7'h43 ; +'hCA: orgBase = 7'h44 ; +'hCB: orgBase = 7'h45 ; +'hD0: orgBase = 7'h46 ; +'hD1: orgBase = 7'h47 ; +'hD2: orgBase = 7'h48 ; +'hD3: orgBase = 7'h49 ; +'hD8: orgBase = 7'h4A ; +'hD9: orgBase = 7'h4B ; +'hDA: orgBase = 7'h4C ; +'hDB: orgBase = 7'h4D ; +'hE0: orgBase = 7'h4E ; +'hE1: orgBase = 7'h4E ; +'hE2: orgBase = 7'h4F ; +'hE3: orgBase = 7'h4F ; +'hE8: orgBase = 7'h50 ; +'hE9: orgBase = 7'h50 ; +'hEA: orgBase = 7'h51 ; +'hEB: orgBase = 7'h51 ; +'hF0: orgBase = 7'h52 ; +'hF1: orgBase = 7'h52 ; +'hF2: orgBase = 7'h52 ; +'hF3: orgBase = 7'h52 ; +'hF8: orgBase = 7'h53 ; +'hF9: orgBase = 7'h53 ; +'hFA: orgBase = 7'h53 ; +'hFB: orgBase = 7'h53 ; + + default: + orgBase = 'X; + endcase + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/nDecoder3.sv b/common/CPU/68000/FX68k/nDecoder3.sv new file mode 100644 index 00000000..8b6f9759 --- /dev/null +++ b/common/CPU/68000/FX68k/nDecoder3.sv @@ -0,0 +1,274 @@ +// Nanorom (plus) decoder for die nanocode +module nDecoder3( input s_clks Clks, input s_irdecod Irdecod, output s_nanod Nanod, + input enT2, enT4, + input [UROM_WIDTH-1:0] microLatch, + input [NANO_WIDTH-1:0] nanoLatch); + +localparam NANO_IR2IRD = 67; +localparam NANO_TOIRC = 66; +localparam NANO_ALU_COL = 63; // ALU operator column order is 63-64-65 ! +localparam NANO_ALU_FI = 61; // ALU finish-init 62-61 +localparam NANO_TODBIN = 60; +localparam NANO_ALUE = 57; // 57-59 shared with DCR control +localparam NANO_DCR = 57; // 57-59 shared with ALUE control +localparam NANO_DOBCTRL_1 = 56; // Input to control and permwrite +localparam NANO_LOWBYTE = 55; // Used by MOVEP +localparam NANO_HIGHBYTE = 54; +localparam NANO_DOBCTRL_0 = 53; // Input to control and permwrite +localparam NANO_ALU_DCTRL = 51; // 52-51 databus input mux control +localparam NANO_ALU_ACTRL = 50; // addrbus input mux control +localparam NANO_DBD2ALUB = 49; +localparam NANO_ABD2ALUB = 48; +localparam NANO_DBIN2DBD = 47; +localparam NANO_DBIN2ABD = 46; +localparam NANO_ALU2ABD = 45; +localparam NANO_ALU2DBD = 44; +localparam NANO_RZ = 43; +localparam NANO_BUSBYTE = 42; // If *both* this set and instruction is byte sized, then bus cycle is byte sized. +localparam NANO_PCLABL = 41; +localparam NANO_RXL_DBL = 40; // Switches RXL/RYL on DBL/ABL buses +localparam NANO_PCLDBL = 39; +localparam NANO_ABDHRECHARGE = 38; +localparam NANO_REG2ABL = 37; // register to ABL +localparam NANO_ABL2REG = 36; // ABL to register +localparam NANO_ABLABD = 35; +localparam NANO_DBLDBD = 34; +localparam NANO_DBL2REG = 33; // DBL to register +localparam NANO_REG2DBL = 32; // register to DBL +localparam NANO_ATLCTRL = 29; // 31-29 +localparam NANO_FTUCONTROL = 25; +localparam NANO_SSP = 24; +localparam NANO_RXH_DBH = 22; // Switches RXH/RYH on DBH/ABH buses +localparam NANO_AUOUT = 20; // 21-20 +localparam NANO_AUCLKEN = 19; +localparam NANO_AUCTRL = 16; // 18-16 +localparam NANO_DBLDBH = 15; +localparam NANO_ABLABH = 14; +localparam NANO_EXT_ABH = 13; +localparam NANO_EXT_DBH = 12; +localparam NANO_ATHCTRL = 9; // 11-9 +localparam NANO_REG2ABH = 8; // register to ABH +localparam NANO_ABH2REG = 7; // ABH to register +localparam NANO_REG2DBH = 6; // register to DBH +localparam NANO_DBH2REG = 5; // DBH to register +localparam NANO_AOBCTRL = 3; // 4-3 +localparam NANO_PCH = 0; // 1-0 PchDbh PchAbh +localparam NANO_NO_SP_ALGN = 0; // Same bits as above when both set + +localparam NANO_FTU_UPDTPEND = 1; // Also loads FTU constant according to IRD ! +localparam NANO_FTU_INIT_ST = 15; // Set S, clear T (but not TPEND) +localparam NANO_FTU_CLRTPEND = 14; +localparam NANO_FTU_TVN = 13; +localparam NANO_FTU_ABL2PREN = 12; // ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine. +localparam NANO_FTU_SSW = 11; +localparam NANO_FTU_RSTPREN = 10; +localparam NANO_FTU_IRD = 9; +localparam NANO_FTU_2ABL = 8; +localparam NANO_FTU_RDSR = 7; +localparam NANO_FTU_INL = 6; +localparam NANO_FTU_PSWI = 5; // Read Int Mask into FTU +localparam NANO_FTU_DBL = 4; +localparam NANO_FTU_2SR = 2; +localparam NANO_FTU_CONST = 1; + + reg [3:0] ftuCtrl; + + logic [2:0] athCtrl, atlCtrl; + assign athCtrl = nanoLatch[ NANO_ATHCTRL+2: NANO_ATHCTRL]; + assign atlCtrl = nanoLatch[ NANO_ATLCTRL+2: NANO_ATLCTRL]; + wire [1:0] aobCtrl = nanoLatch[ NANO_AOBCTRL+1:NANO_AOBCTRL]; + wire [1:0] dobCtrl = {nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0]}; + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + // Reverse order! + ftuCtrl <= { nanoLatch[ NANO_FTUCONTROL+0], nanoLatch[ NANO_FTUCONTROL+1], nanoLatch[ NANO_FTUCONTROL+2], nanoLatch[ NANO_FTUCONTROL+3]} ; + + Nanod.auClkEn <= !nanoLatch[ NANO_AUCLKEN]; + Nanod.auCntrl <= nanoLatch[ NANO_AUCTRL+2 : NANO_AUCTRL+0]; + Nanod.noSpAlign <= (nanoLatch[ NANO_NO_SP_ALGN + 1:NANO_NO_SP_ALGN] == 2'b11); + Nanod.extDbh <= nanoLatch[ NANO_EXT_DBH]; + Nanod.extAbh <= nanoLatch[ NANO_EXT_ABH]; + Nanod.todbin <= nanoLatch[ NANO_TODBIN]; + Nanod.toIrc <= nanoLatch[ NANO_TOIRC]; + + // ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense. + // It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway. + + Nanod.ablAbd <= nanoLatch[ NANO_ABLABD]; + Nanod.ablAbh <= nanoLatch[ NANO_ABLABH]; + Nanod.dblDbd <= nanoLatch[ NANO_DBLDBD]; + Nanod.dblDbh <= nanoLatch[ NANO_DBLDBH]; + + Nanod.dbl2Atl <= (atlCtrl == 3'b010); + Nanod.atl2Dbl <= (atlCtrl == 3'b011); + Nanod.abl2Atl <= (atlCtrl == 3'b100); + Nanod.atl2Abl <= (atlCtrl == 3'b101); + + Nanod.aob2Ab <= (athCtrl == 3'b101); // Used on BSER1 only + + Nanod.abh2Ath <= (athCtrl == 3'b001) | (athCtrl == 3'b101); + Nanod.dbh2Ath <= (athCtrl == 3'b100); + Nanod.ath2Dbh <= (athCtrl == 3'b110); + Nanod.ath2Abh <= (athCtrl == 3'b011); + + Nanod.alu2Dbd <= nanoLatch[ NANO_ALU2DBD]; + Nanod.alu2Abd <= nanoLatch[ NANO_ALU2ABD]; + + Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11); + Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11); + Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10); + Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01); + + Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB]; + Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB]; + + // Originally not latched. We better should because we transfer one cycle later, T3 instead of T1. + Nanod.dobCtrl <= dobCtrl; + // Nanod.adb2Dob <= (dobCtrl == 2'b10); Nanod.dbd2Dob <= (dobCtrl == 2'b01); Nanod.alu2Dob <= (dobCtrl == 2'b11); + + end + end + + // Update SSW at the start of Bus/Addr error ucode + assign Nanod.updSsw = Nanod.aob2Ab; + + assign Nanod.updTpend = (ftuCtrl == NANO_FTU_UPDTPEND); + assign Nanod.clrTpend = (ftuCtrl == NANO_FTU_CLRTPEND); + assign Nanod.tvn2Ftu = (ftuCtrl == NANO_FTU_TVN); + assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST); + assign Nanod.ftu2Dbl = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL); + assign Nanod.ftu2Abl = (ftuCtrl == NANO_FTU_2ABL); + assign Nanod.inl2psw = (ftuCtrl == NANO_FTU_INL); + assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI); + assign Nanod.ftu2Sr = (ftuCtrl == NANO_FTU_2SR); + assign Nanod.sr2Ftu = (ftuCtrl == NANO_FTU_RDSR); + assign Nanod.ird2Ftu = (ftuCtrl == NANO_FTU_IRD); // Used on bus/addr error + assign Nanod.ssw2Ftu = (ftuCtrl == NANO_FTU_SSW); + assign Nanod.initST = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST); + assign Nanod.abl2Pren = (ftuCtrl == NANO_FTU_ABL2PREN); + assign Nanod.updPren = (ftuCtrl == NANO_FTU_RSTPREN); + + assign Nanod.Ir2Ird = nanoLatch[ NANO_IR2IRD]; + + // ALU control better latched later after combining with IRD decoding + + assign Nanod.aluDctrl = nanoLatch[ NANO_ALU_DCTRL+1 : NANO_ALU_DCTRL]; + assign Nanod.aluActrl = nanoLatch[ NANO_ALU_ACTRL]; + assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]}; + wire [1:0] aluFinInit = nanoLatch[ NANO_ALU_FI+1:NANO_ALU_FI]; + assign Nanod.aluFinish = (aluFinInit == 2'b10); + assign Nanod.aluInit = (aluFinInit == 2'b01); + + // FTU 2 CCR encoded as both ALU Init and ALU Finish set. + // In theory this encoding allows writes to CCR without writing to SR + // But FTU 2 CCR and to SR are both set together at nanorom. + assign Nanod.ftu2Ccr = ( aluFinInit == 2'b11); + + assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE]; + + // Not being latched on T4 creates non unique case warning! + assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b01); + assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b10); + assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b11); + + assign Nanod.db2Aob = (aobCtrl == 2'b10); + assign Nanod.ab2Aob = (aobCtrl == 2'b01); + assign Nanod.au2Aob = (aobCtrl == 2'b11); + + assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD]; + assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD]; + + assign Nanod.permStart = (| aobCtrl); + assign Nanod.isWrite = ( | dobCtrl); + assign Nanod.waitBusFinish = nanoLatch[ NANO_TOIRC] | nanoLatch[ NANO_TODBIN] | Nanod.isWrite; + assign Nanod.busByte = nanoLatch[ NANO_BUSBYTE]; + + assign Nanod.noLowByte = nanoLatch[ NANO_LOWBYTE]; + assign Nanod.noHighByte = nanoLatch[ NANO_HIGHBYTE]; + + // Not registered. Register at T4 after combining + // Might be better to remove all those and combine here instead of at execution unit !! + assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG]; + assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG]; + assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG]; + assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG]; + assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL]; + assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH]; + assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL]; + assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH]; + + assign Nanod.ssp = nanoLatch[ NANO_SSP]; + + assign Nanod.rz = nanoLatch[ NANO_RZ]; + + // Actually DTL can't happen on PC relative mode. See IR decoder. + + wire dtldbd = 1'b0; + wire dthdbh = 1'b0; + wire dtlabd = 1'b0; + wire dthabh = 1'b0; + + wire dblSpecial = Nanod.pcldbl | dtldbd; + wire dbhSpecial = Nanod.pchdbh | dthdbh; + wire ablSpecial = Nanod.pclabl | dtlabd; + wire abhSpecial = Nanod.pchabh | dthabh; + + // + // Combine with IRD decoding + // Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4! + // + + // PC used instead of RY on PC relative instuctions + + assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL]; + wire isPcRel = Irdecod.isPcRel & !Nanod.rz; + wire pcRelDbl = isPcRel & !nanoLatch[ NANO_RXL_DBL]; + wire pcRelDbh = isPcRel & !nanoLatch[ NANO_RXH_DBH]; + wire pcRelAbl = isPcRel & nanoLatch[ NANO_RXL_DBL]; + wire pcRelAbh = isPcRel & nanoLatch[ NANO_RXH_DBH]; + + assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl; + assign Nanod.pchdbh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b01) | pcRelDbh; + + assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl; + assign Nanod.pchabh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b10) | pcRelAbh; + + // Might be better not to register these signals to allow latching RX/RY mux earlier! + // But then must latch Irdecod.isPcRel on T3! + + always_ff @( posedge Clks.clk) begin + if( enT4) begin + Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; + Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; + + Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL]; + Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL]; + + Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; + Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH]; + Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; + Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; + + Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; + Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; + + Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL]; + Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL]; + + Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH]; + Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH]; + end + + // Originally isTas only delayed on T2 (and seems only a late mask rev fix) + // Better latch the combination on T4 + if( enT4) + Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE]; + end + + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/onehotEncoder4.sv b/common/CPU/68000/FX68k/onehotEncoder4.sv new file mode 100644 index 00000000..c7771b41 --- /dev/null +++ b/common/CPU/68000/FX68k/onehotEncoder4.sv @@ -0,0 +1,23 @@ +// bin to one-hot, 4 bits to 16-bit bitmap +module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap); + always_comb begin + case( bin) + 'b0000: bitMap = 16'h0001; + 'b0001: bitMap = 16'h0002; + 'b0010: bitMap = 16'h0004; + 'b0011: bitMap = 16'h0008; + 'b0100: bitMap = 16'h0010; + 'b0101: bitMap = 16'h0020; + 'b0110: bitMap = 16'h0040; + 'b0111: bitMap = 16'h0080; + 'b1000: bitMap = 16'h0100; + 'b1001: bitMap = 16'h0200; + 'b1010: bitMap = 16'h0400; + 'b1011: bitMap = 16'h0800; + 'b1100: bitMap = 16'h1000; + 'b1101: bitMap = 16'h2000; + 'b1110: bitMap = 16'h4000; + 'b1111: bitMap = 16'h8000; + endcase + end +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/pren.sv b/common/CPU/68000/FX68k/pren.sv new file mode 100644 index 00000000..ff46c068 --- /dev/null +++ b/common/CPU/68000/FX68k/pren.sv @@ -0,0 +1,25 @@ +// priority encoder +// used by MOVEM regmask +// this might benefit from device specific features +// MOVEM doesn't need speed, will read the result 2 CPU cycles after each update. +module pren( mask, hbit); + parameter size = 16; + parameter outbits = 4; + + input [size-1:0] mask; + output reg [outbits-1:0] hbit; + // output reg idle; + + always @( mask) begin + integer i; + hbit = 0; + // idle = 1; + for( i = size-1; i >= 0; i = i - 1) begin + if( mask[ i]) begin + hbit = i; + // idle = 0; + end + end + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/rowDecoder.sv b/common/CPU/68000/FX68k/rowDecoder.sv new file mode 100644 index 00000000..8fa9c038 --- /dev/null +++ b/common/CPU/68000/FX68k/rowDecoder.sv @@ -0,0 +1,139 @@ +// Decodes IRD into ALU row (1-15) +// Slow, but no need to optimize for speed since IRD is latched at least two CPU cycles before it is used +// We also register the result after combining with column from nanocode +// +// Many opcodes are not decoded because they either don't do any ALU op, +// or use only columns 1 and 5 that are the same for all rows. + +module rowDecoder( input [15:0] ird, + output logic [15:0] row, output noCcrEn, output logic isArX); + + + // Addr or data register direct + wire eaRdir = (ird[ 5:4] == 2'b00); + // Addr register direct + wire eaAdir = (ird[ 5:3] == 3'b001); + wire size11 = ird[7] & ird[6]; + + always_comb begin + case( ird[15:12]) + 'h4, + 'h9, + 'hd: + isArX = row[10] | row[12]; + default: + isArX = 1'b0; + endcase + end + + always_comb begin + unique case( ird[15:12]) + + 'h4: begin + if( ird[8]) + row = `ALU_ROW_06; // chk (or lea) + else case( ird[11:9]) + 'b000: row = `ALU_ROW_10; // negx + 'b001: row = `ALU_ROW_04; // clr + 'b010: row = `ALU_ROW_05; // neg + 'b011: row = `ALU_ROW_11; // not + 'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09; // nbcd/swap/ext(or pea) + 'b101: row = `ALU_ROW_15; // tst & tas + default: row = 0; + endcase + end + + 'h0: begin + if( ird[8]) // dynamic bit + row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; + else case( ird[ 11:9]) + 'b000: row = `ALU_ROW_14; // ori + 'b001: row = `ALU_ROW_04; // andi + 'b010: row = `ALU_ROW_05; // subi + 'b011: row = `ALU_ROW_02; // addi + 'b100: row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; // static bit + 'b101: row = `ALU_ROW_13; // eori + 'b110: row = `ALU_ROW_06; // cmpi + default: row = 0; + endcase + end + + // MOVE + // move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded. + // It's the same for move the operations performed by MOVE.B + + 'h1,'h2,'h3: row = `ALU_ROW_02; + + 'h5: + if( size11) + row = `ALU_ROW_15; // As originally and easier to decode + else + row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02; // addq/subq + 'h6: row = 0; //bcc/bra/bsr + 'h7: row = `ALU_ROW_02; // moveq + 'h8: + if( size11) // div + row = `ALU_ROW_01; + else if( ird[8] & eaRdir) // sbcd + row = `ALU_ROW_09; + else + row = `ALU_ROW_14; // or + 'h9: + if( ird[8] & ~size11 & eaRdir) + row = `ALU_ROW_10; // subx + else + row = `ALU_ROW_05; // sub/suba + 'hb: + if( ird[8] & ~size11 & ~eaAdir) + row = `ALU_ROW_13; // eor + else + row = `ALU_ROW_06; // cmp/cmpa/cmpm + 'hc: + if( size11) + row = `ALU_ROW_07; // mul + else if( ird[8] & eaRdir) // abcd + row = `ALU_ROW_03; + else + row = `ALU_ROW_04; // and + 'hd: + if( ird[8] & ~size11 & eaRdir) + row = `ALU_ROW_12; // addx + else + row = `ALU_ROW_02; // add/adda + 'he: + begin + reg [1:0] stype; + + if( size11) // memory shift/rotate + stype = ird[ 10:9]; + else // register shift/rotate + stype = ird[ 4:3]; + + case( {stype, ird[8]}) + 0: row = `ALU_ROW_02; // ASR + 1: row = `ALU_ROW_03; // ASL + 2: row = `ALU_ROW_05; // LSR + 3: row = `ALU_ROW_04; // LSL + 4: row = `ALU_ROW_08; // ROXR + 5: row = `ALU_ROW_11; // ROXL + 6: row = `ALU_ROW_10; // ROR + 7: row = `ALU_ROW_09; // ROL + endcase + end + + default: row = 0; + endcase + end + + // Decode opcodes that don't affect flags + // ADDA/SUBA ADDQ/SUBQ MOVEA + + assign noCcrEn = + // ADDA/SUBA + ( ird[15] & ~ird[13] & ird[12] & size11) | + // ADDQ/SUBQ to An + ( (ird[15:12] == 4'h5) & eaAdir) | + // MOVEA + ( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001); + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/sequencer.sv b/common/CPU/68000/FX68k/sequencer.sv new file mode 100644 index 00000000..dade6edc --- /dev/null +++ b/common/CPU/68000/FX68k/sequencer.sv @@ -0,0 +1,237 @@ +// Microcode sequencer + +module sequencer( input s_clks Clks, input enT3, + input [UROM_WIDTH-1:0] microLatch, + input A0Err, BerrA, busAddrErr, Spuria, Avia, + input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF, + input [15:0] psw, + input prenEmpty, au05z, dcr4, ze, i11, + input [1:0] alue01, + input [15:0] Ird, + input [UADDR_WIDTH-1:0] a1, a2, a3, + output logic [3:0] tvn, + output logic [UADDR_WIDTH-1:0] nma); + + logic [UADDR_WIDTH-1:0] uNma; + logic [UADDR_WIDTH-1:0] grp1Nma; + logic [1:0] c0c1; + reg a0Rst; + wire A0Sel; + wire inGrp0Exc; + + // assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma); + // assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma; + + // word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + // NMA : .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. .. + + wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]}; + + // Group 0 exception. + // Separated block from regular NMA. Otherwise simulation might depend on order of assigments. + always_comb begin + if( A0Err) begin + if( a0Rst) // Reset + nma = RSTP0_NMA; + else if( inGrp0Exc) // Double fault + nma = HALT1_NMA; + else // Bus or address error + nma = BSER1_NMA; + end + else + nma = uNma; + end + + always_comb begin + // Format II (conditional) or I (direct branch) + if( microLatch[1]) + uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]}; + else + case( microLatch[ 3:2]) + 0: uNma = dbNma; // DB + 1: uNma = A0Sel ? grp1Nma : a1; + 2: uNma = a2; + 3: uNma = a3; + endcase + end + + // Format II, conditional, NMA decoding + wire [1:0] enl = { Ird[6], prenEmpty}; // Updated on T3 + + wire [1:0] ms0 = { Ird[8], alue01[0]}; + wire [3:0] m01 = { au05z, Ird[8], alue01}; + wire [1:0] nz1 = { psw[ NF], psw[ ZF]}; + wire [1:0] nv = { psw[ NF], psw[ VF]}; + + logic ccTest; + wire [4:0] cbc = microLatch[ 6:2]; // CBC bits + + always_comb begin + unique case( cbc) + 'h0: c0c1 = {i11, i11}; // W/L offset EA, from IRC + + 'h1: c0c1 = (au05z) ? 2'b01 : 2'b11; // Updated on T3 + 'h11: c0c1 = (au05z) ? 2'b00 : 2'b11; + + 'h02: c0c1 = { 1'b0, ~psw[ CF]}; // C used in DIV + 'h12: c0c1 = { 1'b1, ~psw[ CF]}; + + 'h03: c0c1 = {psw[ ZF], psw[ ZF]}; // Z used in DIVU + + 'h04: // nz1, used in DIVS + case( nz1) + 'b00: c0c1 = 2'b10; + 'b10: c0c1 = 2'b01; + 'b01,'b11: c0c1 = 2'b11; + endcase + + 'h05: c0c1 = {psw[ NF], 1'b1}; // N used in CHK and DIV + 'h15: c0c1 = {1'b1, psw[ NF]}; + + // nz2, used in DIVS (same combination as nz1) + 'h06: c0c1 = { ~nz1[1] & ~nz1[0], 1'b1}; + + 'h07: // ms0 used in MUL + case( ms0) + 'b10, 'b00: c0c1 = 2'b11; + 'b01: c0c1 = 2'b01; + 'b11: c0c1 = 2'b10; + endcase + + 'h08: // m01 used in MUL + case( m01) + 'b0000,'b0001,'b0100,'b0111: c0c1 = 2'b11; + 'b0010,'b0011,'b0101: c0c1 = 2'b01; + 'b0110: c0c1 = 2'b10; + default: c0c1 = 2'b00; + endcase + + // Conditional + 'h09: c0c1 = (ccTest) ? 2'b11 : 2'b01; + 'h19: c0c1 = (ccTest) ? 2'b11 : 2'b10; + + // DCR bit 4 (high or low word) + 'h0c: c0c1 = dcr4 ? 2'b01: 2'b11; + 'h1c: c0c1 = dcr4 ? 2'b10: 2'b11; + + // DBcc done + 'h0a: c0c1 = ze ? 2'b11 : 2'b00; + + // nv, used in CHK + 'h0b: c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11; + + // V, used in trapv + 'h0d: c0c1 = { ~psw[ VF], ~psw[VF]}; + + // enl, combination of pren idle and word/long on IRD + 'h0e,'h1e: + case( enl) + 2'b00: c0c1 = 'b10; + 2'b10: c0c1 = 'b11; + // 'hx1 result 00/01 depending on condition 0e/1e + 2'b01,2'b11: + c0c1 = { 1'b0, microLatch[ 6]}; + endcase + + default: c0c1 = 'X; + endcase + end + + // CCR conditional + always_comb begin + unique case( Ird[ 11:8]) + 'h0: ccTest = 1'b1; // T + 'h1: ccTest = 1'b0; // F + 'h2: ccTest = ~psw[ CF] & ~psw[ ZF]; // HI + 'h3: ccTest = psw[ CF] | psw[ZF]; // LS + 'h4: ccTest = ~psw[ CF]; // CC (HS) + 'h5: ccTest = psw[ CF]; // CS (LO) + 'h6: ccTest = ~psw[ ZF]; // NE + 'h7: ccTest = psw[ ZF]; // EQ + 'h8: ccTest = ~psw[ VF]; // VC + 'h9: ccTest = psw[ VF]; // VS + 'ha: ccTest = ~psw[ NF]; // PL + 'hb: ccTest = psw[ NF]; // MI + 'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]); // GE + 'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]); // LT + 'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) | + (~psw[ NF] & ~psw[ VF] & ~psw[ ZF]); // GT + 'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]); // LE + endcase + end + + // Exception logic + logic rTrace, rInterrupt; + logic rIllegal, rPriv, rLineA, rLineF; + logic rExcRst, rExcAdrErr, rExcBusErr; + logic rSpurious, rAutovec; + wire grp1LatchEn, grp0LatchEn; + + // Originally control signals latched on T4. Then exception latches updated on T3 + assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]); + assign grp0LatchEn = microLatch[4] & !microLatch[1]; + + assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr; + + always_ff @( posedge Clks.clk) begin + if( grp0LatchEn & enT3) begin + rExcRst <= excRst; + rExcBusErr <= BerrA; + rExcAdrErr <= busAddrErr; + rSpurious <= Spuria; + rAutovec <= Avia; + end + + // Update group 1 exception latches + // Inputs from IR decoder updated on T1 as soon as IR loaded + // Trace pending updated on T3 at the start of the instruction + // Interrupt pending on T2 + if( grp1LatchEn & enT3) begin + rTrace <= Tpend; + rInterrupt <= intPend; + rIllegal <= isIllegal & ~isLineA & ~isLineF; + rLineA <= isLineA; + rLineF <= isLineF; + rPriv <= isPriv & !psw[ SF]; + end + end + + // exception priority + always_comb begin + grp1Nma = TRAC1_NMA; + if( rExcRst) + tvn = '0; // Might need to change that to signal in exception + else if( rExcBusErr | rExcAdrErr) + tvn = { 1'b1, rExcAdrErr}; + + // Seudo group 0 exceptions. Just for updating TVN + else if( rSpurious | rAutovec) + tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC; + + else if( rTrace) + tvn = 9; + else if( rInterrupt) begin + tvn = TVN_INTERRUPT; + grp1Nma = ITLX1_NMA; + end + else begin + unique case( 1'b1) // Can't happen more than one of these + rIllegal: tvn = 4; + rPriv: tvn = 8; + rLineA: tvn = 10; + rLineF: tvn = 11; + default: tvn = 1; // Signal no group 0/1 exception + endcase + end + end + + assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt; + + always_ff @( posedge Clks.clk) begin + if( Clks.extReset) + a0Rst <= 1'b1; + else if( enT3) + a0Rst <= 1'b0; + end + +endmodule \ No newline at end of file diff --git a/common/CPU/68000/FX68k/uaddrDecode.sv b/common/CPU/68000/FX68k/uaddrDecode.sv new file mode 100644 index 00000000..3efdc011 --- /dev/null +++ b/common/CPU/68000/FX68k/uaddrDecode.sv @@ -0,0 +1,91 @@ +// Provides ucode routine entries (A1/A3) for each opcode +// Also checks for illegal opcode and priv violation + +// This is one of the slowest part of the processor. +// But no need to optimize or pipeline because the result is not needed until at least 4 cycles. +// IR updated at the least one microinstruction earlier. +// Just need to configure the timing analizer correctly. + +module uaddrDecode( + input [15:0] opcode, + output [UADDR_WIDTH-1:0] a1, a2, a3, + output logic isPriv, isIllegal, isLineA, isLineF, + output [15:0] lineBmap); + + wire [3:0] line = opcode[15:12]; + logic [3:0] eaCol, movEa; + + onehotEncoder4 irLineDecod( line, lineBmap); + + assign isLineA = lineBmap[ 'hA]; + assign isLineF = lineBmap[ 'hF]; + + pla_lined pla_lined( .movEa( movEa), .col( eaCol), + .opcode( opcode), .lineBmap( lineBmap), + .palIll( isIllegal), .plaA1( a1), .plaA2( a2), .plaA3( a3) ); + + // ea decoding + assign eaCol = eaDecode( opcode[ 5:0]); + assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} ); + + // EA decode + function [3:0] eaDecode; + input [5:0] eaBits; + begin + unique case( eaBits[ 5:3]) + 3'b111: + case( eaBits[ 2:0]) + 3'b000: eaDecode = 7; // Absolute short + 3'b001: eaDecode = 8; // Absolute long + 3'b010: eaDecode = 9; // PC displacement + 3'b011: eaDecode = 10; // PC offset + 3'b100: eaDecode = 11; // Immediate + default: eaDecode = 12; // Invalid + endcase + + default: eaDecode = eaBits[5:3]; // Register based EAs + endcase + end + endfunction + + + /* + Privileged instructions: + + ANDI/EORI/ORI SR + MOVE to SR + MOVE to/from USP + RESET + RTE + STOP + */ + + always_comb begin + unique case( lineBmap) + + // ori/andi/eori SR + 'h01: isPriv = ((opcode & 16'hf5ff) == 16'h007c); + + 'h10: + begin + // No priority !!! + if( (opcode & 16'hffc0) == 16'h46c0) // move to sr + isPriv = 1'b1; + + else if( (opcode & 16'hfff0) == 16'h4e60) // move usp + isPriv = 1'b1; + + else if( opcode == 16'h4e70 || // reset + opcode == 16'h4e73 || // rte + opcode == 16'h4e72) // stop + isPriv = 1'b1; + else + isPriv = 1'b0; + end + + default: isPriv = 1'b0; + endcase + end + + +endmodule \ No newline at end of file diff --git a/common/CPU/T65/T65.vhd b/common/CPU/T65/T65.vhd index 76bd5314..b0a11b50 100644 --- a/common/CPU/T65/T65.vhd +++ b/common/CPU/T65/T65.vhd @@ -1,65 +1,19 @@ -- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- --- Ver 313 WoS January 2015 --- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in --- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D --- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find) --- --- Ver 312 WoS January 2015 --- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay) --- Added comments in MCode section to find handling of individual opcodes more easily --- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with --- actual FPGAARCADE C64 core (sources used: SVN version 1021). --- --- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015 --- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB): --- SAX opcode --- SHA opcode --- SHX opcode --- SHY opcode --- SHS opcode --- LAS opcode --- alternate SBC opcode --- fixed NOP with immediate param (caused Lorenz trap test to fail) --- IRQ and NMI timing fixes (in conjuction with branches) --- --- Ver 304 WoS December 2014 --- Undoc opcode fixes: --- ARR opcode --- ANE/XAA opcode --- Corrected issue with NMI/IRQ prio (when asserted the same time) --- --- Ver 303 ost(ML) July 2014 --- (Sorry for some scratchpad comments that may make little sense) --- Mods and some 6502 undocumented instructions. --- Not correct opcodes acc. to Lorenz tests (incomplete list): --- NOPN (nop) --- NOPZX (nop + byte 172) --- NOPAX (nop + word da ... da: byte 0) --- ASOZ (byte $07 + byte 172) --- --- Ver 303,302 WoS April 2014 --- Bugfixes for NMI from foft --- Bugfix for BRK command (and its special flag) --- --- Ver 300,301 WoS January 2014 --- More merging --- Bugfixes by ehenciak added, started tidyup *bust* -- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* -- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- -- **** -- -- 65xx compatible microprocessor core -- --- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $ +-- Version : 0246 -- --- Copyright (c) 2002...2015 --- Daniel Wallner (jesus opencores org) --- Mike Johnson (mikej fpgaarcade com) --- Wolfgang Scherr (WoS pin4 at> --- Morten Leikvoll () +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) -- -- All rights reserved -- @@ -89,409 +43,360 @@ -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- --- Please report bugs to the author(s), but before you do so, please +-- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- --- ----- IMPORTANT NOTES ----- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ -- --- Limitations: --- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes) --- 65C02 supported : inc, dec, phx, plx, phy, ply --- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 --- Some interface signals behave incorrect --- NMI interrupt handling not nice, needs further rework (to cycle-based encoding). +-- Limitations : -- --- Usage: --- The enable signal allows clock gating / throttling without using the ready signal. --- Set it to constant '1' when using the Clk input as the CPU clock directly. +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect -- --- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0', --- otherwise some undocumented opcodes won't work correctly. --- EXAMPLE: --- CPU : entity work.T65 --- port map ( --- R_W_n => cpu_rwn_s, --- [....all other ports....] --- DI => cpu_din_s, --- DO => cpu_dout_s --- ); --- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else --- [....other sources from peripherals and memories...] +-- File history : -- --- ----- IMPORTANT NOTES ----- +-- 0246 : First release -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - use work.T65_Pack.all; +library work; + use work.pack_t65.all; +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. entity T65 is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 - Res_n : in std_logic; - Enable : in std_logic; - Clk : in std_logic; - Rdy : in std_logic; - Abort_n : in std_logic; - IRQ_n : in std_logic; - NMI_n : in std_logic; - SO_n : in std_logic; - R_W_n : out std_logic; - Sync : out std_logic; - EF : out std_logic; - MF : out std_logic; - XF : out std_logic; - ML_n : out std_logic; - VP_n : out std_logic; - VDA : out std_logic; - VPA : out std_logic; - A : out std_logic_vector(23 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB) - Regs : out std_logic_vector(63 downto 0); - DEBUG : out T_t65_dbg; - NMI_ack : out std_logic - ); + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); end T65; architecture rtl of T65 is - -- Registers - signal ABC, X, Y : std_logic_vector(15 downto 0); - signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; - signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack - signal BAH : std_logic_vector(7 downto 0); - signal BAL : std_logic_vector(8 downto 0); - signal PBR : std_logic_vector(7 downto 0); - signal DBR : std_logic_vector(7 downto 0); - signal PC : unsigned(15 downto 0); - signal S : unsigned(15 downto 0); - signal EF_i : std_logic; - signal MF_i : std_logic; - signal XF_i : std_logic; + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; - signal IR : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); - signal Mode_r : std_logic_vector(1 downto 0); - signal ALU_Op_r : T_ALU_Op; - signal Write_Data_r : T_Write_Data; - signal Set_Addr_To_r : T_Set_Addr_To; - signal PCAdder : unsigned(8 downto 0); + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); - signal RstCycle : std_logic; - signal IRQCycle : std_logic; - signal NMICycle : std_logic; + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; - signal SO_n_o : std_logic; - signal IRQ_n_o : std_logic; - signal NMI_n_o : std_logic; - signal NMIAct : std_logic; + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; - signal Break : std_logic; + signal Break : std_logic; - -- ALU signals - signal BusA : std_logic_vector(7 downto 0); - signal BusA_r : std_logic_vector(7 downto 0); - signal BusB : std_logic_vector(7 downto 0); - signal BusB_r : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal P_Out : std_logic_vector(7 downto 0); + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); - -- Micro code outputs - signal LCycle : std_logic_vector(2 downto 0); - signal ALU_Op : T_ALU_Op; - signal Set_BusA_To : T_Set_BusA_To; - signal Set_Addr_To : T_Set_Addr_To; - signal Write_Data : T_Write_Data; - signal Jump : std_logic_vector(1 downto 0); - signal BAAdd : std_logic_vector(1 downto 0); - signal BreakAtNA : std_logic; - signal ADAdd : std_logic; - signal AddY : std_logic; - signal PCAdd : std_logic; - signal Inc_S : std_logic; - signal Dec_S : std_logic; - signal LDA : std_logic; - signal LDP : std_logic; - signal LDX : std_logic; - signal LDY : std_logic; - signal LDS : std_logic; - signal LDDI : std_logic; - signal LDALU : std_logic; - signal LDAD : std_logic; - signal LDBAL : std_logic; - signal LDBAH : std_logic; - signal SaveP : std_logic; - signal Write : std_logic; + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; - signal Res_n_i : std_logic; - signal Res_n_d : std_logic; - - signal really_rdy : std_logic; - signal WRn_i : std_logic; - - signal NMI_entered : std_logic; + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; begin - NMI_ack <= NMIAct; + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); - -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor - really_rdy <= Rdy or not(WRn_i); - Sync <= '1' when MCycle = "000" else '0'; - EF <= EF_i; - MF <= MF_i; - XF <= XF_i; - R_W_n <= WRn_i; - ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; - VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; - VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; - VPA <= '1' when Jump(1) = '0' else '0'; + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; - -- debugging signals - DEBUG.I <= IR; - DEBUG.A <= ABC(7 downto 0); - DEBUG.X <= X(7 downto 0); - DEBUG.Y <= Y(7 downto 0); - DEBUG.S <= std_logic_vector(S(7 downto 0)); - DEBUG.P <= P; + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! - Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0); + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); - mcode : entity work.T65_MCode - port map( ---inputs - Mode => Mode_r, - IR => IR, - MCycle => MCycle, - P => P, ---outputs - LCycle => LCycle, - ALU_Op => ALU_Op, - Set_BusA_To => Set_BusA_To, - Set_Addr_To => Set_Addr_To, - Write_Data => Write_Data, - Jump => Jump, - BAAdd => BAAdd, - BreakAtNA => BreakAtNA, - ADAdd => ADAdd, - AddY => AddY, - PCAdd => PCAdd, - Inc_S => Inc_S, - Dec_S => Dec_S, - LDA => LDA, - LDP => LDP, - LDX => LDX, - LDY => LDY, - LDS => LDS, - LDDI => LDDI, - LDALU => LDALU, - LDAD => LDAD, - LDBAL => LDBAL, - LDBAH => LDBAH, - SaveP => SaveP, - Write => Write - ); + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); - alu : entity work.T65_ALU - port map( - Mode => Mode_r, - Op => ALU_Op_r, - BusA => BusA_r, - BusB => BusB, - P_In => P, - P_Out => P_Out, - Q => ALU_Q - ); + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); - -- the 65xx design requires at least two clock cycles before - -- starting its reset sequence (according to datasheet) - process (Res_n, Clk) - begin - if Res_n = '0' then - Res_n_i <= '0'; - Res_n_d <= '0'; - elsif Clk'event and Clk = '1' then - Res_n_i <= Res_n_d; - Res_n_d <= '1'; - end if; - end process; + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; - process (Res_n_i, Clk) - begin - if Res_n_i = '0' then - PC <= (others => '0'); -- Program Counter - IR <= "00000000"; - S <= (others => '0'); -- Dummy - PBR <= (others => '0'); - DBR <= (others => '0'); + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; - Mode_r <= (others => '0'); - ALU_Op_r <= ALU_OP_BIT; - Write_Data_r <= Write_Data_DL; - Set_Addr_To_r <= Set_Addr_To_PBR; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; - WRn_i <= '1'; - EF_i <= '1'; - MF_i <= '1'; - XF_i <= '1'; + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - WRn_i <= not Write or RstCycle; + if MCycle = "000" then + Mode_r <= Mode; - PBR <= (others => '1'); -- Dummy - DBR <= (others => '1'); -- Dummy - EF_i <= '0'; -- Dummy - MF_i <= '0'; -- Dummy - XF_i <= '0'; -- Dummy + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; - if MCycle = "000" then - Mode_r <= Mode; + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; - if IRQCycle = '0' and NMICycle = '0' then - PC <= PC + 1; - end if; + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; - if IRQCycle = '1' or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DI; - end if; + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; - if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0 - S(7 downto 0) <= unsigned(ALU_Q); - end if; - end if; + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; - ALU_Op_r <= ALU_Op; - Write_Data_r <= Write_Data; - if Break = '1' then - Set_Addr_To_r <= Set_Addr_To_PBR; - else - Set_Addr_To_r <= Set_Addr_To; - end if; + when "10" => + PC <= unsigned(DI & DL); - if Inc_S = '1' then - S <= S + 1; - end if; - if Dec_S = '1' and RstCycle = '0' then - S <= S - 1; - end if; + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); - if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then - PC <= PC + 1; - end if; - -- - -- jump control logic - -- - case Jump is - when "01" => - PC <= PC + 1; - when "10" => - PC <= unsigned(DI & DL); - when "11" => - if PCAdder(8) = '1' then - if DL(7) = '0' then - PC(15 downto 8) <= PC(15 downto 8) + 1; - else - PC(15 downto 8) <= PC(15 downto 8) - 1; - end if; - end if; - PC(7 downto 0) <= PCAdder(7 downto 0); - when others => null; - end case; - end if; - end if; - end if; - end process; + when others => null; + end case; + end if; + end if; + end if; + end process; - PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' - else "0" & PC(7 downto 0); + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); - process (Res_n_i, Clk) - variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle - begin - if Res_n_i = '0' then - P <= x"00"; -- ensure we have nothing set on reset - elsif Clk'event and Clk = '1' then - tmpP:=P; - if (Enable = '1') then - if (really_rdy = '1') then - if MCycle = "000" then - if LDA = '1' then - ABC(7 downto 0) <= ALU_Q; - end if; - if LDX = '1' then - X(7 downto 0) <= ALU_Q; - end if; - if LDY = '1' then - Y(7 downto 0) <= ALU_Q; - end if; - if (LDA or LDX or LDY) = '1' then - tmpP:=P_Out; - end if; - end if; - if SaveP = '1' then - tmpP:=P_Out; - end if; - if LDP = '1' then - tmpP:=ALU_Q; - end if; - if IR(4 downto 0) = "11000" then - case IR(7 downto 5) is - when "000" =>--0x18(clc) - tmpP(Flag_C) := '0'; - when "001" =>--0x38(sec) - tmpP(Flag_C) := '1'; - when "010" =>--0x58(cli) - tmpP(Flag_I) := '0'; - when "011" =>--0x78(sei) - tmpP(Flag_I) := '1'; - when "101" =>--0xb8(clv) - tmpP(Flag_V) := '0'; - when "110" =>--0xd8(cld) - tmpP(Flag_D) := '0'; - when "111" =>--0xf8(sed) - tmpP(Flag_D) := '1'; - when others => - end case; - end if; - tmpP(Flag_B) := '1'; - if IR = "00000000" and MCycle = "100" and RstCycle = '0' then - --This should happen after P has been pushed to stack - tmpP(Flag_I) := '1'; - end if; - if RstCycle = '1' then - tmpP(Flag_I) := '1'; - tmpP(Flag_D) := '0'; - end if; - tmpP(Flag_1) := '1'; + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + -- assert false report "Chargement A" severity warning; + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + P(Flag_B) <= '1'; + end if; + if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + P(Flag_I) <= '1'; + P(Flag_B) <= B_o; + end if; + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; - P<=tmpP;--new way - - if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works... - IRQ_n_o <= IRQ_n; - end if; - end if; - -- detect nmi even if not rdy - if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works... - NMI_n_o <= NMI_n; - end if; - end if; - -- act immediately on SO pin change - -- The signal is sampled on the trailing edge of phi1 and must be externally synchronized (from datasheet) - SO_n_o <= SO_n; - if SO_n_o = '1' and SO_n = '0' then - P(Flag_V) <= '1'; - end if; - - end if; - end process; + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; --------------------------------------------------------------------------- -- @@ -499,133 +404,109 @@ begin -- --------------------------------------------------------------------------- - process (Res_n_i, Clk) - begin - if Res_n_i = '0' then - BusA_r <= (others => '0'); - BusB <= (others => '0'); - BusB_r <= (others => '0'); - AD <= (others => '0'); - BAL <= (others => '0'); - BAH <= (others => '0'); - DL <= (others => '0'); - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - NMI_entered <= '0'; - BusA_r <= BusA; - BusB <= DI; + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; - -- not really nice, but no better way found yet ! - if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then - BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA - end if; + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; - case BAAdd is - when "01" => - -- BA Inc - AD <= std_logic_vector(unsigned(AD) + 1); - BAL <= std_logic_vector(unsigned(BAL) + 1); - when "10" => - -- BA Add - BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); - when "11" => - -- BA Adj - if BAL(8) = '1' then - BAH <= std_logic_vector(unsigned(BAH) + 1); - end if; - when others => - end case; + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; - -- modified to use Y register as well - if ADAdd = '1' then - if (AddY = '1') then - AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); - else - AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); - end if; - end if; + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; - if IR = "00000000" then - BAL <= (others => '1'); - BAH <= (others => '1'); - if RstCycle = '1' then - BAL(2 downto 0) <= "100"; - elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then - BAL(2 downto 0) <= "010"; - if MCycle="100" then - NMI_entered <= '1'; - end if; - else - BAL(2 downto 0) <= "110"; - end if; - if Set_addr_To_r = Set_Addr_To_BA then - BAL(0) <= '1'; - end if; - end if; - if LDDI = '1' then - DL <= DI; - end if; - if LDALU = '1' then - DL <= ALU_Q; - end if; - if LDAD = '1' then - AD <= DI; - end if; - if LDBAL = '1' then - BAL(7 downto 0) <= DI; - end if; - if LDBAH = '1' then - BAH <= DI; - end if; - end if; - end if; - end if; - end process; + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; - Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); - with Set_BusA_To select - BusA <= - DI when Set_BusA_To_DI, - ABC(7 downto 0) when Set_BusA_To_ABC, - X(7 downto 0) when Set_BusA_To_X, - Y(7 downto 0) when Set_BusA_To_Y, - std_logic_vector(S(7 downto 0)) when Set_BusA_To_S, - P when Set_BusA_To_P, - ABC(7 downto 0) and DI when Set_BusA_To_DA, - (ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics - (ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics - ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA - (others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this - with Set_Addr_To_r select - A <= - "0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP, - DBR & "00000000" & AD when Set_Addr_To_ZPG, - "00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA, - PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR; + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; - -- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does. - PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P; - - with Write_Data_r select - DO <= - DL when Write_Data_DL, - ABC(7 downto 0) when Write_Data_ABC, - X(7 downto 0) when Write_Data_X, - Y(7 downto 0) when Write_Data_Y, - std_logic_vector(S(7 downto 0)) when Write_Data_S, - PwithB when Write_Data_P, - std_logic_vector(PC(7 downto 0)) when Write_Data_PCL, - std_logic_vector(PC(15 downto 8)) when Write_Data_PCH, - ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX, - ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet... - X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet... - Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet... - (others=>'-') when Write_Data_DONTCARE;--Can probably remove this + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; ------------------------------------------------------------------------- -- @@ -633,42 +514,40 @@ begin -- ------------------------------------------------------------------------- - process (Res_n_i, Clk) - begin - if Res_n_i = '0' then - MCycle <= "001"; - RstCycle <= '1'; - IRQCycle <= '0'; - NMICycle <= '0'; - NMIAct <= '0'; - elsif Clk'event and Clk = '1' then - if (Enable = '1') then - if (really_rdy = '1') then - if MCycle = LCycle or Break = '1' then - MCycle <= "000"; - RstCycle <= '0'; - IRQCycle <= '0'; - NMICycle <= '0'; - if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK - NMICycle <= '1'; - NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI - elsif IRQ_n_o = '0' and P(Flag_I) = '0' then - IRQCycle <= '1'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - --detect NMI even if not rdy - if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...) - NMIAct <= '1'; - end if; - -- we entered NMI during BRK instruction - if NMI_entered='1' then - NMIAct <= '0'; - end if; - end if; - end if; - end process; + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; end; diff --git a/common/CPU/T65/T65_ALU.vhd b/common/CPU/T65/T65_ALU.vhd index c58d7a13..38b84a06 100644 --- a/common/CPU/T65/T65_ALU.vhd +++ b/common/CPU/T65/T65_ALU.vhd @@ -1,18 +1,18 @@ -- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- --- See list of changes in T65 top file (T65.vhd)... +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- **** --- 65xx compatible microprocessor core -- --- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $ +-- 6502 compatible microprocessor core -- --- Copyright (c) 2002...2015 --- Daniel Wallner (jesus opencores org) --- Mike Johnson (mikej fpgaarcade com) --- Wolfgang Scherr (WoS pin4 at> --- Morten Leikvoll () +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) -- -- All rights reserved -- @@ -42,252 +42,220 @@ -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- --- Please report bugs to the author(s), but before you do so, please +-- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- -- Limitations : --- See in T65 top file (T65.vhd)... +-- +-- File history : +-- +-- 0245 : First version +-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.T65_Pack.all; +library work; +use work.pack_t65.all; entity T65_ALU is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 - Op : in T_ALU_OP; - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - P_In : in std_logic_vector(7 downto 0); - P_Out : out std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0) - ); + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); end T65_ALU; architecture rtl of T65_ALU is - -- AddSub variables (temporary signals) - signal ADC_Z : std_logic; - signal ADC_C : std_logic; - signal ADC_V : std_logic; - signal ADC_N : std_logic; - signal ADC_Q : std_logic_vector(7 downto 0); - signal SBC_Z : std_logic; - signal SBC_C : std_logic; - signal SBC_V : std_logic; - signal SBC_N : std_logic; - signal SBC_Q : std_logic_vector(7 downto 0); - signal SBX_Q : std_logic_vector(7 downto 0); + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); begin - process (P_In, BusA, BusB) - variable AL : unsigned(6 downto 0); - variable AH : unsigned(6 downto 0); - variable C : std_logic; - begin - AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); - AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); -- pragma translate_off - if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; - if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on - if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then - ADC_Z <= '1'; - else - ADC_Z <= '0'; - end if; + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; - if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then - AL(6 downto 1) := AL(6 downto 1) + 6; - end if; + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; - C := AL(6) or AL(5); - AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); - ADC_N <= AH(4); - ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); -- pragma translate_off - if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on - if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then - AH(6 downto 1) := AH(6 downto 1) + 6; - end if; + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; - ADC_C <= AH(6) or AH(5); + ADC_C <= AH(6) or AH(5); - ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); - end process; + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; - process (Op, P_In, BusA, BusB) - variable AL : unsigned(6 downto 0); - variable AH : unsigned(5 downto 0); - variable C : std_logic; - variable CT : std_logic; - begin - CT:='0'; - if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set - Op=ALU_OP_ADC or --"0011" - Op=ALU_OP_EQ2 or --"0101" - Op=ALU_OP_SBC or --"0111" - Op=ALU_OP_ROL or --"1001" - Op=ALU_OP_ROR or --"1011" --- Op=ALU_OP_EQ3 or --"1101" - Op=ALU_OP_INC --"1111" - ) then - CT:='1'; - end if; + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); - C := P_In(Flag_C) or not CT;--was: or not Op(0); - AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); - AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on - -- pragma translate_off - if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; - if is_x(std_logic_vector(AH)) then AH := "000000"; end if; - -- pragma translate_on + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; - if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then - SBC_Z <= '1'; - else - SBC_Z <= '0'; - end if; + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); - SBC_C <= not AH(5); - SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); - SBC_N <= AH(4); + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; - SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; - if P_In(Flag_D) = '1' then - if AL(5) = '1' then - AL(5 downto 1) := AL(5 downto 1) - 6; - end if; - AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); - if AH(5) = '1' then - AH(5 downto 1) := AH(5 downto 1) - 6; - end if; - end if; + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; - SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); - end process; + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; - process (Op, P_In, BusA, BusB, - ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, - SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q, - SBX_Q) - variable Q_t : std_logic_vector(7 downto 0); - variable Q2_t : std_logic_vector(7 downto 0); - begin - -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC - -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC - P_Out <= P_In; - Q_t := BusA; - Q2_t := BusA; - case Op is - when ALU_OP_OR=> - Q_t := BusA or BusB; - when ALU_OP_AND=> - Q_t := BusA and BusB; - when ALU_OP_EOR=> - Q_t := BusA xor BusB; - when ALU_OP_ADC=> - P_Out(Flag_V) <= ADC_V; - P_Out(Flag_C) <= ADC_C; - Q_t := ADC_Q; - when ALU_OP_CMP=> - P_Out(Flag_C) <= SBC_C; - when ALU_OP_SAX=> - P_Out(Flag_C) <= SBC_C; - Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate) - when ALU_OP_SBC=> - P_Out(Flag_V) <= SBC_V; - P_Out(Flag_C) <= SBC_C; - Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction - when ALU_OP_ASL=> - Q_t := BusA(6 downto 0) & "0"; - P_Out(Flag_C) <= BusA(7); - when ALU_OP_ROL=> - Q_t := BusA(6 downto 0) & P_In(Flag_C); - P_Out(Flag_C) <= BusA(7); - when ALU_OP_LSR=> - Q_t := "0" & BusA(7 downto 1); - P_Out(Flag_C) <= BusA(0); - when ALU_OP_ROR=> - Q_t := P_In(Flag_C) & BusA(7 downto 1); - P_Out(Flag_C) <= BusA(0); - when ALU_OP_ARR=> - Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1)); - P_Out(Flag_V) <= Q_t(5) xor Q_t(6); - Q2_t := Q_t; - if P_In(Flag_D)='1' then - if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then - Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6"); - end if; - if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then - Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6"); - P_Out(Flag_C) <= '1'; - else - P_Out(Flag_C) <= '0'; - end if; - else - P_Out(Flag_C) <= Q_t(6); - end if; - when ALU_OP_BIT=> - P_Out(Flag_V) <= BusB(6); - when ALU_OP_DEC=> - Q_t := std_logic_vector(unsigned(BusA) - 1); - when ALU_OP_INC=> - Q_t := std_logic_vector(unsigned(BusA) + 1); - when others => - null; - --EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out - end case; - - case Op is - when ALU_OP_ADC=> - P_Out(Flag_N) <= ADC_N; - P_Out(Flag_Z) <= ADC_Z; - when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=> - P_Out(Flag_N) <= SBC_N; - P_Out(Flag_Z) <= SBC_Z; - when ALU_OP_EQ1=>--dont touch P - when ALU_OP_BIT=> - P_Out(Flag_N) <= BusB(7); - if (BusA and BusB) = "00000000" then - P_Out(Flag_Z) <= '1'; - else - P_Out(Flag_Z) <= '0'; - end if; - when ALU_OP_ANC=> - P_Out(Flag_N) <= Q_t(7); - P_Out(Flag_C) <= Q_t(7); - if Q_t = "00000000" then - P_Out(Flag_Z) <= '1'; - else - P_Out(Flag_Z) <= '0'; - end if; - when others => - P_Out(Flag_N) <= Q_t(7); - if Q_t = "00000000" then - P_Out(Flag_Z) <= '1'; - else - P_Out(Flag_Z) <= '0'; - end if; - end case; - - if Op=ALU_OP_ARR then - -- handled above in ARR code - Q <= Q2_t; - else - Q <= Q_t; - end if; - end process; + Q <= Q_t; + end process; end; diff --git a/common/CPU/T65/T65_MCode.vhd b/common/CPU/T65/T65_MCode.vhd index 7af12a31..68f9323e 100644 --- a/common/CPU/T65/T65_MCode.vhd +++ b/common/CPU/T65/T65_MCode.vhd @@ -1,18 +1,19 @@ -- **** -- T65(b) core. In an effort to merge and maintain bug fixes .... -- --- See list of changes in T65 top file (T65.vhd)... +-- +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- **** +-- -- 65xx compatible microprocessor core -- --- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $ +-- Version : 0246 + fix -- --- Copyright (c) 2002...2015 --- Daniel Wallner (jesus opencores org) --- Mike Johnson (mikej fpgaarcade com) --- Wolfgang Scherr (WoS pin4 at> --- Morten Leikvoll () +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) -- -- All rights reserved -- @@ -42,1198 +43,1005 @@ -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- --- Please report bugs to the author(s), but before you do so, please +-- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- -- Limitations : --- See in T65 top file (T65.vhd)... +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use ieee.std_logic_unsigned.all; -use work.T65_Pack.all; +library work; +use work.pack_t65.all; entity T65_MCode is - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 - IR : in std_logic_vector(7 downto 0); - MCycle : in T_Lcycle; - P : in std_logic_vector(7 downto 0); - LCycle : out T_Lcycle; - ALU_Op : out T_ALU_Op; - Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX - Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA - Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB - Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel - BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj - BreakAtNA : out std_logic; - ADAdd : out std_logic; - AddY : out std_logic; - PCAdd : out std_logic; - Inc_S : out std_logic; - Dec_S : out std_logic; - LDA : out std_logic; - LDP : out std_logic; - LDX : out std_logic; - LDY : out std_logic; - LDS : out std_logic; - LDDI : out std_logic; - LDALU : out std_logic; - LDAD : out std_logic; - LDBAL : out std_logic; - LDBAH : out std_logic; - SaveP : out std_logic; - Write : out std_logic - ); + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); end T65_MCode; architecture rtl of T65_MCode is - signal Branch : std_logic; - signal ALUmore:std_logic; + signal Branch : std_logic; begin - with IR(7 downto 5) select - Branch <= not P(Flag_N) when "000", - P(Flag_N) when "001", - not P(Flag_V) when "010", - P(Flag_V) when "011", - not P(Flag_C) when "100", - P(Flag_C) when "101", - not P(Flag_Z) when "110", - P(Flag_Z) when others; + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; - process (IR, MCycle, P, Branch, Mode) - begin - lCycle <= Cycle_1; - Set_BusA_To <= Set_BusA_To_ABC; - Set_Addr_To <= Set_Addr_To_PBR; - Write_Data <= Write_Data_DL; - Jump <= (others => '0'); - BAAdd <= "00"; - BreakAtNA <= '0'; - ADAdd <= '0'; - PCAdd <= '0'; - Inc_S <= '0'; - Dec_S <= '0'; - LDA <= '0'; - LDP <= '0'; - LDX <= '0'; - LDY <= '0'; - LDS <= '0'; - LDDI <= '0'; - LDALU <= '0'; - LDAD <= '0'; - LDBAL <= '0'; - LDBAH <= '0'; - SaveP <= '0'; - Write <= '0'; - AddY <= '0'; - ALUmore <= '0'; + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; - case IR(7 downto 5) is - when "100" => -- covers $8x,$9x - case IR(1 downto 0) is - when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C - Set_BusA_To <= Set_BusA_To_Y; - if IR(4 downto 2)="111" then -- SYA ($9C) - Write_Data <= Write_Data_YB; - else - Write_Data <= Write_Data_Y; - end if; - when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E - Set_BusA_To <= Set_BusA_To_X; - if IR(4 downto 2)="111" then -- SXA ($9E) - Write_Data <= Write_Data_XB; - else - Write_Data <= Write_Data_X; - end if; - when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F - if IR(4 downto 2)="110" then -- SHS ($9B) - Set_BusA_To <= Set_BusA_To_AAX; - LDS <= '1'; - else - Set_BusA_To <= Set_BusA_To_ABC; - end if; - if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B) - Write_Data <= Write_Data_AXB; - else - Write_Data <= Write_Data_AX; - end if; - when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D - Write_Data <= Write_Data_ABC; - end case; - when "101" => -- covers $Ax,$Bx - Set_BusA_To <= Set_BusA_To_DI; - case IR(1 downto 0) is - when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC - if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC - LDY <= '1'; - end if; - when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD - LDA <= '1'; - when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE - LDX <= '1'; - when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc) - LDX <= '1'; - LDA <= '1'; - if IR(4 downto 2)="110" then -- LAS (BB) - Set_BusA_To <= Set_BusA_To_S; - LDS <= '1'; - end if; - end case; - when "110" => -- covers $Cx,$Dx - case IR(1 downto 0) is - when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC - if IR(4) = '0' then--only for $Cx - LDY <= '1'; - end if; - Set_BusA_To <= Set_BusA_To_Y; - when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF - Set_BusA_To <= Set_BusA_To_ABC; - end case; - when "111" => -- covers $Ex,$Fx - case IR(1 downto 0) is - when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC - if IR(4) = '0' then -- only $Ex - LDX <= '1'; - end if; - Set_BusA_To <= Set_BusA_To_X; - when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF - Set_BusA_To <= Set_BusA_To_ABC; - end case; - when others => - end case; + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; - if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs - if IR=x"eb" then - Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB) - else - Set_BusA_To <= Set_BusA_To_DI; - end if; - end if; + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; - case IR(4 downto 0) is - -- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0 - -- $08,$28,$48,$68,$88,$A8,$C8,$E8 - -- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA - -- $18,$38,$58,$78,$98,$B8,$D8,$F8 - -- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA - when "00000" | "01000" | "01010" | "11000" | "11010" => - -- Implied - case IR is - when x"00" => - -- BRK ($00) - lCycle <= Cycle_6; - case MCycle is - when Cycle_1 => - Set_Addr_To <= Set_Addr_To_SP; - Write_Data <= Write_Data_PCH; - Write <= '1'; - when Cycle_2 => - Dec_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - Write_Data <= Write_Data_PCL; - Write <= '1'; - when Cycle_3 => - Dec_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - Write_Data <= Write_Data_P; - Write <= '1'; - when Cycle_4 => - Dec_S <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_5 => - LDDI <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_6 => - Jump <= "10"; - when others => - end case; - when x"20" => -- JSR ($20) - lCycle <= Cycle_5; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDDI <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_2 => - Set_Addr_To <= Set_Addr_To_SP; - Write_Data <= Write_Data_PCH; - Write <= '1'; - when Cycle_3 => - Dec_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - Write_Data <= Write_Data_PCL; - Write <= '1'; - when Cycle_4 => - Dec_S <= '1'; - when Cycle_5 => - Jump <= "10"; - when others => - end case; - when x"40" => -- RTI ($40) - lCycle <= Cycle_5; - case MCycle is - when Cycle_1 => - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_2 => - Inc_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_3 => - Inc_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - Set_BusA_To <= Set_BusA_To_DI; - when Cycle_4 => - LDP <= '1'; - Inc_S <= '1'; - LDDI <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_5 => - Jump <= "10"; - when others => - end case; - when x"60" => -- RTS ($60) - lCycle <= Cycle_5; - case MCycle is - when Cycle_1 => - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_2 => - Inc_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_3 => - Inc_S <= '1'; - LDDI <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - when Cycle_4 => - Jump <= "10"; - when Cycle_5 => - Jump <= "01"; - when others => - end case; - when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA) - lCycle <= Cycle_2; - if Mode = "00" and IR(1) = '1' then--2 cycle nop - lCycle <= Cycle_1; - end if; - case MCycle is - when Cycle_1 => - if mode/="00" or IR(1)='0' then --wrong on 6502 - Write <= '1'; - case IR(7 downto 4) is - when "0000" => - Write_Data <= Write_Data_P; - when "0100" => - Write_Data <= Write_Data_ABC; - when "0101" => - if Mode /= "00" then - Write_Data <= Write_Data_Y; - else - Write <= '0'; - end if; - when "1101" => - if Mode /= "00" then - Write_Data <= Write_Data_X; - else - Write <= '0'; - end if; - when others => - end case; - Set_Addr_To <= Set_Addr_To_SP; - end if; - when Cycle_2 => - Dec_S <= '1'; - when others => - end case; - when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA) - lCycle <= Cycle_3; - if Mode = "00" and IR(1) = '1' then--2 cycle nop - lCycle <= Cycle_1; - end if; - case IR(7 downto 4) is - when "0010" =>--plp - LDP <= '1'; - when "0110" =>--pla - LDA <= '1'; - when "0111" =>--ply not for 6502 - if Mode /= "00" then - LDY <= '1'; - end if; - when "1111" =>--plx not for 6502 - if Mode /= "00" then - LDX <= '1'; - end if; - when others => - end case; - case MCycle is - when Cycle_sync => - if Mode /= "00" or IR(1) = '0' then--wrong on 6502 - SaveP <= '1'; - end if; - when Cycle_1 => - if Mode /= "00" or IR(1) = '0' then--wrong on 6502 - Set_Addr_To <= Set_Addr_To_SP; - LDP <= '0'; - end if; - when Cycle_2 => - Inc_S <= '1'; - Set_Addr_To <= Set_Addr_To_SP; - LDP <= '0'; - when Cycle_3 => - Set_BusA_To <= Set_BusA_To_DI; - when others => - end case; - when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0) - -- Immediate - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - when others => - end case; - when x"88" => -- DEY ($88) - LDY <= '1'; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Set_BusA_To <= Set_BusA_To_Y; - when others => - end case; - when x"ca" => -- DEX ($CA) - LDX <= '1'; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Set_BusA_To <= Set_BusA_To_X; - when others => - end case; - when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A) - if Mode /= "00" then - LDA <= '1'; -- A - else - lCycle <= Cycle_1;--undoc 2 cycle nop - end if; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Set_BusA_To <= Set_BusA_To_S; - when others => - end case; - when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A) - LDA <= '1'; -- A - Set_BusA_To <= Set_BusA_To_ABC; - case MCycle is - when Cycle_sync => - when Cycle_1 => - when others => - end case; - when x"8a" | x"98" => -- TYA, TXA ($8A,$98) - LDA <= '1'; - case MCycle is - when Cycle_sync => - when Cycle_1 => - when others => - end case; - when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8) - case MCycle is - when Cycle_sync => - when Cycle_1 => - Set_BusA_To <= Set_BusA_To_ABC; - when others => - end case; - when x"9a" => -- TXS ($9A) - LDS <= '1'; -- will be set only in Cycle_sync - when x"ba" => -- TSX ($BA) - LDX <= '1'; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Set_BusA_To <= Set_BusA_To_S; - when others => - end case; - when x"80" => -- undoc: NOP imm2 ($80) - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - when others => - end case; - when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8) - case MCycle is - when Cycle_sync => - when others => - end case; - end case; + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => Write_Data <= "101"; -- P + when "0100" => Write_Data <= "001"; -- A + when "0101" => Write_Data <= "011"; -- Y + when "1101" => Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; - -- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1 - -- $03,$23,$43,$63,$83,$A3,$C3,$E3 - when "00001" | "00011" => - -- Zero Page Indexed Indirect (d,x) - lCycle <= Cycle_5; - if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3) - LDA <= '1'; - if Mode="00" and IR(1)='1' then - lCycle <= Cycle_7; - end if; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - ADAdd <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_3 => - BAAdd <= "01"; - LDBAL <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_4 => - LDBAH <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_5=> - if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then - Set_Addr_To <= Set_Addr_To_BA; - Write <= '1'; - LDDI<='1'; - end if; - when Cycle_6=> - Write <= '1'; - LDALU<='1'; - SaveP<='1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_7 => - ALUmore <= '1'; - Set_BusA_To <= Set_BusA_To_ABC; - when others => - end case; + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} - -- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9 - when "01001" => - -- Immediate - if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89) - LDA <= '1'; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - when others => - end case; + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} - -- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB - when "01011" => - if Mode="00" then - -- Immediate undoc for 6500 - case IR(7 downto 5) is - when "010"|"011"|"000"|"001" =>--ALR,ARR - Set_BusA_To<=Set_BusA_To_DA; - LDA <= '1'; - when "100" =>--XAA - Set_BusA_To<=Set_BusA_To_DAX; - LDA <= '1'; - when "110" =>--SAX (SBX) - Set_BusA_To<=Set_BusA_To_AAX; - LDX <= '1'; - when "101" =>--OAL - Set_BusA_To<=Set_BusA_To_DAO; - LDA <= '1'; - when others=> - LDA <= '1'; - end case; - case MCycle is - when Cycle_1 => - Jump <= "01"; - when others => - end case; - end if; + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; - -- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2 - -- $12,$32,$52,$72,$92,$B2,$D2,$F2 - when "00010" | "10010" => - -- Immediate, SKB, KIL - case MCycle is - when Cycle_sync => - when Cycle_1 => - if IR = "10100010" then - -- LDX ($A2) - Jump <= "01"; - LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx) - elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then - -- undoc: NOP imm2 - Jump <= "01"; - else - -- KIL !!! - end if; - when others => - end case; + --}}} - -- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4 - when "00100" => - -- Zero Page - lCycle <= Cycle_2; - case MCycle is - when Cycle_sync => - if IR(7 downto 5) = "001" then--24=BIT zpg - SaveP <= '1'; - end if; - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group) - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - when others => - end case; + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} - -- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5 - -- $06,$26,$46,$66,$86,$A6,$C6,$E6 - -- $07,$27,$47,$67,$87,$A7,$C7,$E7 - when "00101" | "00110" | "00111" => - -- Zero Page - if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs - -- Read-Modify-Write - lCycle <= Cycle_4; - if Mode="00" and IR(0)='1' then - LDA<='1'; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - LDDI <= '1'; - if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_3 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_4 => - if Mode="00" and IR(0)='1' then - Set_BusA_To<=Set_BusA_To_ABC; - ALUmore <= '1'; -- For undoc DCP/DCM support - LDDI <= '1'; -- requires DIN to reflect DOUT! - end if; - when others => - end case; - else - lCycle <= Cycle_2; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - end if; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - if IR(7 downto 5) = "100" then - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - when others => - end case; - end if; + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} - -- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC - when "01100" => - -- Absolute - if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C) - if IR(5) = '0' then - lCycle <= Cycle_2; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDDI <= '1'; - when Cycle_2 => - Jump <= "10"; - when others => - end case; - else - lCycle <= Cycle_4; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDDI <= '1'; - LDBAL <= '1'; - when Cycle_2 => - LDBAH <= '1'; - if Mode /= "00" then - Jump <= "10"; - end if; - if Mode = "00" then - Set_Addr_To <= Set_Addr_To_BA; - end if; - when Cycle_3 => - LDDI <= '1'; - if Mode = "00" then - Set_Addr_To <= Set_Addr_To_BA; - BAAdd <= "01"; -- DB Inc - else - Jump <= "01"; - end if; - when Cycle_4 => - Jump <= "10"; - when others => - end case; - end if; - else - lCycle <= Cycle_3; - case MCycle is - when Cycle_sync => - if IR(7 downto 5) = "001" then--2c-BIT - SaveP <= '1'; - end if; - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - LDBAH <= '1'; - if IR(7 downto 5) = "100" then--80, sty, the only write in this group - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - when others => - end case; - end if; + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} - -- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED - -- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE - -- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF - when "01101" | "01110" | "01111" => - -- Absolute - if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF) - -- Read-Modify-Write - lCycle <= Cycle_5; - if Mode="00" and IR(0) = '1' then - LDA <= '1'; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - LDBAH <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - LDDI <= '1'; - if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_4 => - Write <= '1'; - LDALU <= '1'; - SaveP <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_5 => - if Mode="00" and IR(0)='1' then - ALUmore <= '1'; -- For undoc DCP/DCM support - Set_BusA_To<=Set_BusA_To_ABC; - end if; - when others => - end case; - else - lCycle <= Cycle_3; - if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement) - LDA <= '1'; - end if; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - LDBAH <= '1'; - if IR(7 downto 5) = "100" then--8d - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - when others => - end case; - end if; + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 3 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 4 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} - -- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0 - when "10000" => - -- Relative - -- This circuit dictates when the last - -- microcycle occurs for the branch depending on - -- whether or not the branch is taken and if a page - -- is crossed... - if (Branch = '1') then - lCycle <= Cycle_3; -- We're done @ T3 if branching...upper - -- level logic will stop at T2 if no page cross - -- (See the Break signal) - else - lCycle <= Cycle_1; - end if; - -- This decodes the current microcycle and takes the - -- proper course of action... - case MCycle is - -- On the T1 microcycle, increment the program counter - -- and instruct the upper level logic to fetch the offset - -- from the Din bus and store it in the data latches. This - -- will be the last microcycle if the branch isn't taken. - when Cycle_1 => - Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) - -- from microcycle T0. - LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route - -- the Din bus to the memory data latch (DL) - -- so that the branch offset is fetched. - -- In microcycle T2, tell the logic in the top level to - -- add the offset. If the most significant byte of the - -- program counter (i.e. the current "page") does not need - -- updating, we are done here...the Break signal at the - -- T65.vhd level takes care of that... - when Cycle_2 => - Jump <= "11"; -- Tell the PC Jump logic to use relative mode. - PCAdd <= '1'; -- This tells the PC adder to update itself with - -- the current offset recently fetched from - -- memory. - -- The following is microcycle T3 : - -- The program counter should be completely updated - -- on this cycle after the page cross is detected. - -- We don't need to do anything here... - when Cycle_3 => - when others => null; -- Do nothing. - end case; + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} - -- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1 - -- $13,$33,$53,$73,$93,$B3,$D3,$F3 - when "10001" | "10011" => - lCycle <= Cycle_5; - if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3) - LDA <= '1'; - if Mode="00" and IR(1)='1' then - lCycle <= Cycle_7; - end if; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - LDBAL <= '1'; - BAAdd <= "01"; -- DB Inc - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_3 => - Set_BusA_To <= Set_BusA_To_Y; - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_4 => - BAAdd <= "11"; -- BA Adj - if IR(7 downto 5) = "100" then - Write <= '1'; - elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests) - BreakAtNA <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_5 => - if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then - Set_Addr_To <= Set_Addr_To_BA; - LDDI<='1'; - Write <= '1'; - end if; - when Cycle_6 => - LDALU<='1'; - SaveP<='1'; - Write <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_7 => - ALUmore <= '1'; - Set_BusA_To<=Set_BusA_To_ABC; - when others => - end case; + when "10000" => + --{{{ + -- Relative - -- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4 - -- $15,$35,$55,$75,$95,$B5,$D5,$F5 - -- $16,$36,$56,$76,$96,$B6,$D6,$F6 - -- $17,$37,$57,$77,$97,$B7,$D7,$F7 - when "10100" | "10101" | "10110" | "10111" => - -- Zero Page, X - if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7) - -- Read-Modify-Write - if Mode="00" and IR(0)='1' then - LDA<='1'; - end if; - lCycle <= Cycle_5; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - ADAdd <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_3 => - LDDI <= '1'; - if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_4 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - if Mode="00" and IR(0)='1' then - LDDI<='1'; - end if; - when Cycle_5 => - if Mode="00" and IR(0)='1' then - ALUmore <= '1'; -- For undoc DCP/DCM support - Set_BusA_To<=Set_BusA_To_ABC; - end if; - when others => - end case; - else - lCycle <= Cycle_3; - if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip - LDA <= '1'; - end if; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - LDAD <= '1'; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_2 => - ADAdd <= '1'; - -- Added this check for Y reg. use, added undocs - if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7) - AddY <= '1'; - end if; - if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_ZPG; - when Cycle_3 => null; - when others => - end case; - end if; + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then - -- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9 - -- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB - when "11001" | "11011" => - -- Absolute Y - lCycle <= Cycle_4; - if IR(7 downto 6) /= "10" then - LDA <= '1'; - if Mode="00" and IR(1)='1' then - lCycle <= Cycle_6; - end if; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - Set_BusA_To <= Set_BusA_To_Y; - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - BAAdd <= "11"; -- BA adj - if IR(7 downto 5) = "100" then--99/9b - Write <= '1'; - elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests) - BreakAtNA <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_4 => -- just for undoc - if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then - Set_Addr_To <= Set_Addr_To_BA; - LDDI<='1'; - Write <= '1'; - end if; - when Cycle_5 => - Write <= '1'; - LDALU<='1'; - Set_Addr_To <= Set_Addr_To_BA; - SaveP<='1'; - when Cycle_6 => - ALUmore <= '1'; - Set_BusA_To <= Set_BusA_To_ABC; - when others => - end case; + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else - -- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC - -- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD - -- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE - -- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF - when "11100" | "11101" | "11110" | "11111" => - -- Absolute X - if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF) - -- Read-Modify-Write - lCycle <= Cycle_6; - if Mode="00" and IR(0)='1' then - LDA <= '1'; - end if; - case MCycle is - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - Set_BusA_To <= Set_BusA_To_X; - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - BAAdd <= "11"; -- BA adj - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_4 => - LDDI <= '1'; - if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read - Write <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_5 => - LDALU <= '1'; - SaveP <= '1'; - Write <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_6 => - if Mode="00" and IR(0)='1' then - ALUmore <= '1'; - Set_BusA_To <= Set_BusA_To_ABC; - end if; - when others => - end case; - else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF) - lCycle <= Cycle_4;--Or 3 if not page crossing - if IR(7 downto 6) /= "10" then - if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then - LDA <= '1'; - end if; - end if; - case MCycle is - when Cycle_sync => - when Cycle_1 => - Jump <= "01"; - LDBAL <= '1'; - when Cycle_2 => - Jump <= "01"; - -- special case $BE which uses Y reg as index!! - if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then - Set_BusA_To <= Set_BusA_To_Y; - else - Set_BusA_To <= Set_BusA_To_X; - end if; - BAAdd <= "10"; -- BA Add - LDBAH <= '1'; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_3 => - BAAdd <= "11"; -- BA adj - if IR(7 downto 5) = "100" then -- ($9E,$9F) - Write <= '1'; - else - BreakAtNA <= '1'; - end if; - Set_Addr_To <= Set_Addr_To_BA; - when Cycle_4 => - when others => - end case; - end if; - when others => - end case; - end process; + LCycle <= "001"; - process (IR, MCycle, Mode,ALUmore) - begin - -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC - -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC - case IR(1 downto 0) is - when "00" => - case IR(4 downto 2) is - -- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0 - -- $04,$24,$44,$64,$84,$A4,$C4,$E4 - -- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC - when "000" | "001" | "011" => - case IR(7 downto 5) is - when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC) - ALU_Op <= ALU_OP_CMP; - when "101" => -- LD ($A0,$A4,$AC) - ALU_Op <= ALU_OP_EQ2; - when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp) - ALU_Op <= ALU_OP_BIT; - when others => -- other, NOP/ST ($x0,$x4,$xC) - ALU_Op <= ALU_OP_EQ1; - end case; + end if; - -- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8 - when "010" => - case IR(7 downto 5) is - when "111" | "110" => -- IN ($C8,$E8) - ALU_Op <= ALU_OP_INC; - when "100" => -- DEY ($88) - ALU_Op <= ALU_OP_DEC; - when others => -- LD - ALU_Op <= ALU_OP_EQ2; - end case; + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is - -- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8 - when "110" => - case IR(7 downto 5) is - when "100" => -- TYA ($98) - ALU_Op <= ALU_OP_EQ2; - when others => - ALU_Op <= ALU_OP_EQ1; - end case; + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => - -- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0 - -- $14,$34,$54,$74,$94,$B4,$D4,$F4 - -- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC - when others => - case IR(7 downto 5) is - when "101" => -- LD ($B0,$B4,$BC) - ALU_Op <= ALU_OP_EQ2; - when others => - ALU_Op <= ALU_OP_EQ1; - end case; - end case; + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. - when "01" => -- OR - case(to_integer(unsigned(IR(7 downto 5)))) is - when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D - ALU_Op<=ALU_OP_OR; - when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D - ALU_Op<=ALU_OP_AND; - when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D - ALU_Op<=ALU_OP_EOR; - when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D - ALU_Op<=ALU_OP_ADC; - when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D - ALU_Op<=ALU_OP_EQ1; -- STA - when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD - ALU_Op<=ALU_OP_EQ2; -- LDA - when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD - ALU_Op<=ALU_OP_CMP; - when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD - ALU_Op<=ALU_OP_SBC; - end case; + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. - when "10" => - case(to_integer(unsigned(IR(7 downto 5)))) is - when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E - ALU_Op<=ALU_OP_ASL; - if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502 - ALU_Op <= ALU_OP_INC; - end if; - when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E - ALU_Op<=ALU_OP_ROL; - if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502 - ALU_Op <= ALU_OP_DEC; - end if; - when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E - ALU_Op<=ALU_OP_LSR; - when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E - ALU_Op<=ALU_OP_ROR; - when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E - ALU_Op<=ALU_OP_BIT; - if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA - ALU_Op <= ALU_OP_EQ2; - else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E - ALU_Op <= ALU_OP_EQ1; - end if; - when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE - ALU_Op<=ALU_OP_EQ2; -- LDX - when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE - ALU_Op<=ALU_OP_DEC; - when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE - ALU_Op<=ALU_OP_INC; - end case; + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => - when others => -- "11" undoc double alu ops - case(to_integer(unsigned(IR(7 downto 5)))) is - -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF - when 5 => - if IR=x"bb" then--LAS - ALU_Op <= ALU_OP_AND; - else - ALU_Op <= ALU_OP_EQ2; - end if; + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. - -- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F - -- $23,$27,$2B,$2F,$33,$37,$3B,$3F - -- $43,$47,$4B,$4F,$53,$57,$5B,$5F - -- $63,$67,$6B,$6F,$73,$77,$7B,$7F - -- $83,$87,$8B,$8F,$93,$97,$9B,$9F - -- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF - -- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF - when others => - if IR=x"6b" then -- ARR - ALU_Op<=ALU_OP_ARR; - elsif IR=x"8b" then -- ARR - ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags... - elsif IR=x"0b" or IR=x"2b" then -- ANC - ALU_Op<=ALU_OP_ANC; - elsif IR=x"eb" then -- alternate SBC - ALU_Op<=ALU_OP_SBC; - elsif ALUmore='1' then - case(to_integer(unsigned(IR(7 downto 5)))) is - when 0=> - ALU_Op<=ALU_OP_OR; - when 1=> - ALU_Op<=ALU_OP_AND; - when 2=> - ALU_Op<=ALU_OP_EOR; - when 3=> - ALU_Op<=ALU_OP_ADC; - when 4=> - ALU_Op<=ALU_OP_EQ1; -- STA - when 5=> - ALU_Op<=ALU_OP_EQ2; -- LDA - when 6=> - ALU_Op<=ALU_OP_CMP; - when others=> - ALU_Op<=ALU_OP_SBC; - end case; - else - case(to_integer(unsigned(IR(7 downto 5)))) is - when 0=> - ALU_Op<=ALU_OP_ASL; - when 1=> - ALU_Op<=ALU_OP_ROL; - when 2=> - ALU_Op<=ALU_OP_LSR; - when 3=> - ALU_Op<=ALU_OP_ROR; - when 4=> - ALU_Op<=ALU_OP_BIT; - when 5=> - ALU_Op<=ALU_OP_EQ2; -- LDX - when 6=> - ALU_Op<=ALU_OP_DEC; - if IR(4 downto 2)="010" then -- $6B - ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case - end if; - when others=> - ALU_Op<=ALU_OP_INC; - end case; - end if; - end case; - end case; - end process; + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; end; diff --git a/common/CPU/T65/T65_Pack.vhd b/common/CPU/T65/T65_Pack.vhd deleted file mode 100644 index 92ad4da0..00000000 --- a/common/CPU/T65/T65_Pack.vhd +++ /dev/null @@ -1,180 +0,0 @@ --- **** --- T65(b) core. In an effort to merge and maintain bug fixes .... --- --- See list of changes in T65 top file (T65.vhd)... --- --- **** --- 65xx compatible microprocessor core --- --- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $ --- --- Copyright (c) 2002...2015 --- Daniel Wallner (jesus opencores org) --- Mike Johnson (mikej fpgaarcade com) --- Wolfgang Scherr (WoS pin4 at> --- Morten Leikvoll () --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author(s), but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- Limitations : --- See in T65 top file (T65.vhd)... - -library IEEE; -use IEEE.std_logic_1164.all; - -package T65_Pack is - - constant Flag_C : integer := 0; - constant Flag_Z : integer := 1; - constant Flag_I : integer := 2; - constant Flag_D : integer := 3; - constant Flag_B : integer := 4; - constant Flag_1 : integer := 5; - constant Flag_V : integer := 6; - constant Flag_N : integer := 7; - - subtype T_Lcycle is std_logic_vector(2 downto 0); - constant Cycle_sync :T_Lcycle:="000"; - constant Cycle_1 :T_Lcycle:="001"; - constant Cycle_2 :T_Lcycle:="010"; - constant Cycle_3 :T_Lcycle:="011"; - constant Cycle_4 :T_Lcycle:="100"; - constant Cycle_5 :T_Lcycle:="101"; - constant Cycle_6 :T_Lcycle:="110"; - constant Cycle_7 :T_Lcycle:="111"; - - function CycleNext(c:T_Lcycle) return T_Lcycle; - - type T_Set_BusA_To is - ( - Set_BusA_To_DI, - Set_BusA_To_ABC, - Set_BusA_To_X, - Set_BusA_To_Y, - Set_BusA_To_S, - Set_BusA_To_P, - Set_BusA_To_DA, - Set_BusA_To_DAO, - Set_BusA_To_DAX, - Set_BusA_To_AAX, - Set_BusA_To_DONTCARE - ); - - type T_Set_Addr_To is - ( - Set_Addr_To_PBR, - Set_Addr_To_SP, - Set_Addr_To_ZPG, - Set_Addr_To_BA - ); - - type T_Write_Data is - ( - Write_Data_DL, - Write_Data_ABC, - Write_Data_X, - Write_Data_Y, - Write_Data_S, - Write_Data_P, - Write_Data_PCL, - Write_Data_PCH, - Write_Data_AX, - Write_Data_AXB, - Write_Data_XB, - Write_Data_YB, - Write_Data_DONTCARE - ); - - type T_ALU_OP is - ( - ALU_OP_OR, --"0000" - ALU_OP_AND, --"0001" - ALU_OP_EOR, --"0010" - ALU_OP_ADC, --"0011" - ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does. - ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op - ALU_OP_CMP, --"0110" - ALU_OP_SBC, --"0111" - ALU_OP_ASL, --"1000" - ALU_OP_ROL, --"1001" - ALU_OP_LSR, --"1010" - ALU_OP_ROR, --"1011" - ALU_OP_BIT, --"1100" --- ALU_OP_EQ3, --"1101" - ALU_OP_DEC, --"1110" - ALU_OP_INC, --"1111" - ALU_OP_ARR, - ALU_OP_ANC, - ALU_OP_SAX, - ALU_OP_XAA --- ALU_OP_UNDEF--"----"--may be replaced with any? - ); - - type T_t65_dbg is record - I : std_logic_vector(7 downto 0); -- instruction - A : std_logic_vector(7 downto 0); -- A reg - X : std_logic_vector(7 downto 0); -- X reg - Y : std_logic_vector(7 downto 0); -- Y reg - S : std_logic_vector(7 downto 0); -- stack pointer - P : std_logic_vector(7 downto 0); -- processor flags - end record; - -end; - -package body T65_Pack is - - function CycleNext(c:T_Lcycle) return T_Lcycle is - begin - case(c) is - when Cycle_sync=> - return Cycle_1; - when Cycle_1=> - return Cycle_2; - when Cycle_2=> - return Cycle_3; - when Cycle_3=> - return Cycle_4; - when Cycle_4=> - return Cycle_5; - when Cycle_5=> - return Cycle_6; - when Cycle_6=> - return Cycle_7; - when Cycle_7=> - return Cycle_sync; - when others=> - return Cycle_sync; - end case; - end CycleNext; - -end T65_Pack; diff --git a/common/CPU/T65/pack_t65.vhd b/common/CPU/T65/pack_t65.vhd new file mode 100644 index 00000000..fbe4afe1 --- /dev/null +++ b/common/CPU/T65/pack_t65.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package pack_t65 is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; \ No newline at end of file diff --git a/common/CPU/T80/T80.qip b/common/CPU/T80/T80.qip index 4d071284..d7fc08ba 100644 --- a/common/CPU/T80/T80.qip +++ b/common/CPU/T80/T80.qip @@ -1,10 +1,6 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80se.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80sed.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T8080se.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Pack.vhd ] diff --git a/common/CPU/T80/Z80.vhd b/common/CPU/T80/Z80.vhd new file mode 100644 index 00000000..db1ad947 --- /dev/null +++ b/common/CPU/T80/Z80.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.T80_Pack.all; + +entity Z80 is port + ( + clk : in std_logic; + clk_en : in std_logic; + reset : in std_logic; + + addr : out std_logic_vector(15 downto 0); + datai : in std_logic_vector(7 downto 0); + datao : out std_logic_vector(7 downto 0); + + m1 : out std_logic; + mem_rd : out std_logic; + mem_wr : out std_logic; + io_rd : out std_logic; + io_wr : out std_logic; + + wait_n : in std_logic := '1'; + busrq_n : in std_logic := '1'; + intreq : in std_logic := '0'; + intvec : in std_logic_vector(7 downto 0); + intack : out std_logic; + nmi : in std_logic := '0' + ); +end Z80; + +architecture SYN of Z80 is + + component T80se is + generic + ( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port + ( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); + end component T80se; + + -- Signal Declarations + + signal reset_n : std_logic; + signal int_n : std_logic; + signal nmi_n : std_logic; + + signal z80_m1 : std_logic; + signal z80_memreq : std_logic; + signal z80_ioreq : std_logic; + signal z80_rd : std_logic; + signal z80_wr : std_logic; + signal z80_datai : std_logic_vector(7 downto 0); + + -- derived signals (outputs we need to read) + signal z80_memrd : std_logic; + signal z80_iord : std_logic; + signal fetch : std_logic; + + begin + + -- simple inversions + reset_n <= not reset; + int_n <= not intreq; + nmi_n <= not nmi; + + -- direct-connect (outputs we need to read) + m1 <= z80_m1; + mem_rd <= z80_memrd; + io_rd <= z80_iord; + + -- memory signals + z80_memrd <= z80_memreq nor z80_rd; + mem_wr <= z80_memreq nor z80_wr; + + -- io signals + z80_iord <= z80_ioreq nor z80_rd; + io_wr <= z80_ioreq nor z80_wr; + + -- other signals + fetch <= z80_m1 nor z80_memreq; + intack <= z80_m1 nor z80_ioreq; + + -- data in mux + z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else + datai; + + Z80_uP : T80se + generic map + ( + Mode => 0 -- Z80 + ) + port map + ( + RESET_n => reset_n, + CLK_n => clk, + CLKEN => clk_en, + WAIT_n => wait_n, + INT_n => int_n, + NMI_n => nmi_n, + BUSRQ_n => busrq_n, + M1_n => z80_m1, + MREQ_n => z80_memreq, + IORQ_n => z80_ioreq, + RD_n => z80_rd, + WR_n => z80_wr, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => addr, + DI => z80_datai, + DO => datao + ); + +end architecture SYN; diff --git a/common/mist/cofi.sv b/common/mist/cofi.sv deleted file mode 100644 index adc5c923..00000000 --- a/common/mist/cofi.sv +++ /dev/null @@ -1,55 +0,0 @@ -// Composite-like horizontal blending by Kitrinx - -module cofi ( - input clk, - input pix_ce, - input enable, - - input hblank, - input vblank, - input hs, - input vs, - input [5:0] red, - input [5:0] green, - input [5:0] blue, - - output reg hblank_out, - output reg vblank_out, - output reg hs_out, - output reg vs_out, - output reg [5:0] red_out, - output reg [5:0] green_out, - output reg [5:0] blue_out -); - - function bit [5:0] color_blend ( - input [5:0] color_prev, - input [5:0] color_curr, - input blank_last - ); - begin - color_blend = blank_last ? color_curr : (color_prev >> 1) + (color_curr >> 1); - end - endfunction - -reg [5:0] red_last; -reg [5:0] green_last; -reg [5:0] blue_last; - -wire ce = enable ? pix_ce : 1'b1; -always @(posedge clk) if (ce) begin - hblank_out <= hblank; - vblank_out <= vblank; - vs_out <= vs; - hs_out <= hs; - - red_last <= red; - blue_last <= blue; - green_last <= green; - - red_out <= enable ? color_blend(red_last, red, hblank_out) : red; - blue_out <= enable ? color_blend(blue_last, blue, hblank_out) : blue; - green_out <= enable ? color_blend(green_last, green, hblank_out) : green; -end - -endmodule diff --git a/common/mist/mist.qip b/common/mist/mist.qip index 27f8644d..b5ad8ce4 100644 --- a/common/mist/mist.qip +++ b/common/mist/mist.qip @@ -5,7 +5,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_vi set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd] diff --git a/common/mist/mist.vhd b/common/mist/mist.vhd index f4b57b7a..711d6304 100644 --- a/common/mist/mist.vhd +++ b/common/mist/mist.vhd @@ -84,7 +84,6 @@ component mist_video scandoubler_disable : in std_logic; ypbpr : in std_logic; rotate : in std_logic_vector(1 downto 0); - blend : in std_logic := '0'; HSync : in std_logic; VSync : in std_logic; diff --git a/common/mist/mist_video.v b/common/mist/mist_video.v index 219d78c3..b5eda352 100644 --- a/common/mist/mist_video.v +++ b/common/mist/mist_video.v @@ -20,14 +20,10 @@ module mist_video // 0 = HVSync 31KHz, 1 = CSync 15KHz input scandoubler_disable, - // disable csync without scandoubler - input no_csync, // YPbPr always uses composite sync input ypbpr, // Rotate OSD [0] - rotate [1] - left or right input [1:0] rotate, - // composite-like blending - input blend, // video in input [COLOR_DEPTH-1:0] R, @@ -50,7 +46,6 @@ parameter OSD_X_OFFSET = 10'd0; parameter OSD_Y_OFFSET = 10'd0; parameter SD_HCNT_WIDTH = 9; parameter COLOR_DEPTH = 6; // 1-6 -parameter OSD_AUTO_CE = 1'b1; wire [5:0] SD_R_O; wire [5:0] SD_G_O; @@ -82,35 +77,11 @@ always @(*) begin end end -reg [1:0] i_div; -reg ce_x1, ce_x2; - -always @(posedge clk_sys) begin - reg last_hs_in; - last_hs_in <= HSync; - if(last_hs_in & !HSync) begin - i_div <= 2'b00; - end else begin - i_div <= i_div + 2'd1; - end -end - -always @(*) begin - if (!ce_divider) begin - ce_x1 = (i_div == 2'b01); - ce_x2 = i_div[0]; - end else begin - ce_x1 = i_div[0]; - ce_x2 = 1'b1; - end -end - scandoubler #(SD_HCNT_WIDTH, COLOR_DEPTH) scandoubler ( .clk_sys ( clk_sys ), .scanlines ( scanlines ), - .ce_x1 ( ce_x1 ), - .ce_x2 ( ce_x2 ), + .ce_divider ( ce_divider ), .hs_in ( HSync ), .vs_in ( VSync ), .r_in ( R ), @@ -127,11 +98,10 @@ wire [5:0] osd_r_o; wire [5:0] osd_g_o; wire [5:0] osd_b_o; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR, OSD_AUTO_CE) osd +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd ( .clk_sys ( clk_sys ), .rotate ( rotate ), - .ce ( scandoubler_disable ? ce_x1 : ce_x2 ), .SPI_DI ( SPI_DI ), .SPI_SCK ( SPI_SCK ), .SPI_SS3 ( SPI_SS3 ), @@ -145,49 +115,29 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR, OSD_AUTO_CE) osd .B_out ( osd_b_o ) ); -wire [5:0] cofi_r, cofi_g, cofi_b; -wire cofi_hs, cofi_vs; - -cofi cofi ( - .clk ( clk_sys ), - .pix_ce ( scandoubler_disable ? ce_x1 : ce_x2 ), - .enable ( blend ), - .hblank ( ~(scandoubler_disable ? HSync : SD_HS_O) ), - .hs ( scandoubler_disable ? HSync : SD_HS_O ), - .vs ( scandoubler_disable ? VSync : SD_VS_O ), - .red ( osd_r_o ), - .green ( osd_g_o ), - .blue ( osd_b_o ), - .hs_out ( cofi_hs ), - .vs_out ( cofi_vs ), - .red_out ( cofi_r ), - .green_out( cofi_g ), - .blue_out( cofi_b ) -); - wire [5:0] y, pb, pr; rgb2ypbpr rgb2ypbpr ( - .red ( cofi_r ), - .green ( cofi_g ), - .blue ( cofi_b ), + .red ( osd_r_o ), + .green ( osd_g_o ), + .blue ( osd_b_o ), .y ( y ), .pb ( pb ), .pr ( pr ) ); -assign VGA_R = ypbpr?pr:cofi_r; -assign VGA_G = ypbpr? y:cofi_g; -assign VGA_B = ypbpr?pb:cofi_b; +assign VGA_R = ypbpr?pr:osd_r_o; +assign VGA_G = ypbpr? y:osd_g_o; +assign VGA_B = ypbpr?pb:osd_b_o; -wire cs = ~(cofi_hs ^ cofi_vs); -wire hs = cofi_hs; -wire vs = cofi_vs; +wire cs = scandoubler_disable ? ~(HSync ^ VSync) : ~(SD_HS_O ^ SD_VS_O); +wire hs = scandoubler_disable ? HSync : SD_HS_O; +wire vs = scandoubler_disable ? VSync : SD_VS_O; // a minimig vga->scart cable expects a composite sync signal on the VGA_HS output. // and VCC on VGA_VS (to switch into rgb mode) -assign VGA_HS = ((~no_csync & scandoubler_disable) || ypbpr)? cs : hs; -assign VGA_VS = ((~no_csync & scandoubler_disable) || ypbpr)? 1'b1 : vs; +assign VGA_HS = (scandoubler_disable || ypbpr)? cs : hs; +assign VGA_VS = (scandoubler_disable || ypbpr)? 1'b1 : vs; endmodule diff --git a/common/mist/osd.v b/common/mist/osd.v index 7e41ed27..44ecc713 100644 --- a/common/mist/osd.v +++ b/common/mist/osd.v @@ -5,7 +5,6 @@ module osd ( // OSDs pixel clock, should be synchronous to cores pixel clock to // avoid jitter. input clk_sys, - input ce, // SPI interface input SPI_SCK, @@ -30,7 +29,6 @@ module osd ( parameter OSD_X_OFFSET = 10'd0; parameter OSD_Y_OFFSET = 10'd0; parameter OSD_COLOR = 3'd0; -parameter OSD_AUTO_CE = 1'b1; localparam OSD_WIDTH = 10'd256; localparam OSD_HEIGHT = 10'd128; @@ -97,7 +95,7 @@ wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; wire doublescan = (dsp_height>350); -reg auto_ce_pix; +reg ce_pix; always @(posedge clk_sys) begin integer cnt = 0; integer pixsz, pixcnt; @@ -108,35 +106,34 @@ always @(posedge clk_sys) begin pixcnt <= pixcnt + 1; if(pixcnt == pixsz) pixcnt <= 0; - auto_ce_pix <= !pixcnt; + ce_pix <= !pixcnt; if(hs && ~HSync) begin cnt <= 0; if (cnt <= 512) pixsz = 0; else pixsz <= (cnt >> 9) - 1; pixcnt <= 0; - auto_ce_pix <= 1; + ce_pix <= 1; end end -wire ce_pix = OSD_AUTO_CE ? auto_ce_pix : ce; - always @(posedge clk_sys) begin - reg hsD; - reg vsD; + reg hsD, hsD2; + reg vsD, vsD2; if(ce_pix) begin // bring hsync into local clock domain hsD <= HSync; + hsD2 <= hsD; // falling edge of HSync - if(!HSync && hsD) begin + if(!hsD && hsD2) begin h_cnt <= 0; hs_high <= h_cnt; end // rising edge of HSync - else if(HSync && !hsD) begin + else if(hsD && !hsD2) begin h_cnt <= 0; hs_low <= h_cnt; v_cnt <= v_cnt + 1'd1; @@ -145,15 +142,16 @@ always @(posedge clk_sys) begin end vsD <= VSync; + vsD2 <= vsD; // falling edge of VSync - if(!VSync && vsD) begin + if(!vsD && vsD2) begin v_cnt <= 0; vs_high <= v_cnt; end // rising edge of VSync - else if(VSync && !vsD) begin + else if(vsD && !vsD2) begin v_cnt <= 0; vs_low <= v_cnt; end diff --git a/common/mist/scandoubler.v b/common/mist/scandoubler.v index 05e9286d..120788ca 100644 --- a/common/mist/scandoubler.v +++ b/common/mist/scandoubler.v @@ -25,8 +25,7 @@ module scandoubler // scanlines (00-none 01-25% 10-50% 11-75%) input [1:0] scanlines, - input ce_x1, - input ce_x2, + input ce_divider, // 0 - 4, 1 - 2 // shifter video interface input hs_in, @@ -46,6 +45,34 @@ module scandoubler parameter HCNT_WIDTH = 9; parameter COLOR_DEPTH = 6; +// try to detect changes in input signal and lock input clock gate +// it + +reg [1:0] i_div; + +reg ce_x1, ce_x2; + +always @(*) begin + if (!ce_divider) begin + ce_x1 = (i_div == 2'b01); + ce_x2 = i_div[0]; + end else begin + ce_x1 = i_div[0]; + ce_x2 = 1'b1; + end +end + +always @(posedge clk_sys) begin + reg last_hs_in; + last_hs_in <= hs_in; + if(last_hs_in & !hs_in) begin + i_div <= 2'b00; + end else begin + i_div <= i_div + 2'd1; + end +end + + // --------------------- create output signals ----------------- // latch everything once more to make it glitch free and apply scanline effect reg scanline;