diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qpf b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.qpf similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qpf rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.qpf diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.qsf similarity index 96% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.qsf index bded7b0b..993f6a71 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.qsf @@ -40,7 +40,7 @@ # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files @@ -237,9 +237,9 @@ set_global_assignment -name VERILOG_FILE rtl/z80ip.v set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_array.vhd -set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name VERILOG_FILE rtl/dataselector.v +set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/vol_table_array.vhd +set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/YM2149.vhd +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.sdc similarity index 98% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.sdc index 80fe5371..33ffd42f 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST.sdc @@ -53,7 +53,7 @@ set_time_format -unit ns -decimal_places 3 create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] -set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" #************************************************************** # Create Generated Clock diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector.v deleted file mode 100644 index fd00932a..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector.v +++ /dev/null @@ -1,70 +0,0 @@ -module dataselector_3D_8B -( - output [7:0] out, - input [7:0] df, - - input en0, - input [7:0] dt0, - input en1, - input [7:0] dt1, - input en2, - input [7:0] dt2 -); - -assign out = en0 ? dt0 : - en1 ? dt1 : - en2 ? dt2 : - df; - -endmodule - -module dataselector_5D_8B -( - output [7:0] out, - input en0, - input [7:0] dt0, - input en1, - input [7:0] dt1, - input en2, - input [7:0] dt2, - input en3, - input [7:0] dt3, - input en4, - input [7:0] dt4 -); - -assign out = en0 ? dt0 : - en1 ? dt1 : - en2 ? dt2 : - en3 ? dt3 : - en4 ? dt4 : - 8'hFF; - -endmodule - -module dataselector_4D_9B -( - output [8:0] OUT, - - input EN1, - input [8:0] IN1, - - input EN2, - input [8:0] IN2, - - input EN3, - input [8:0] IN3, - - input EN4, - input [8:0] IN4, - - input [8:0] IND -); - -assign OUT = EN1 ? IN1: - EN2 ? IN2: - EN3 ? IN3: - EN4 ? IN4: - IND; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v deleted file mode 100644 index b5b9977e..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v +++ /dev/null @@ -1,28 +0,0 @@ -module ninjakun_adec -( - input [15:0] CP0AD, - input CP0WR, - - input [15:0] CP1AD, - input CP1WR, - - output CS_IN0, - output CS_IN1, - - output CS_SH0, - output CS_SH1, - - output SYNWR0, - output SYNWR1 -); - -assign CS_IN0 = (CP0AD[15:2] == 14'b1010_0000_0000_00); -assign CS_IN1 = (CP1AD[15:2] == 14'b1010_0000_0000_00); - -assign CS_SH0 = (CP0AD[15:11] == 5'b1110_0); -assign CS_SH1 = (CP1AD[15:11] == 5'b1110_0); - -assign SYNWR0 = CS_IN0 & (CP0AD[1:0]==2) & CP0WR; -assign SYNWR1 = CS_IN1 & (CP1AD[1:0]==2) & CP1WR; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v deleted file mode 100644 index 5bd6fa87..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v +++ /dev/null @@ -1,57 +0,0 @@ -// Copyright (c) 2011 MiSTer-X - -module ninjakun_input -( - input MCLK, - input RESET, - - input [7:0] CTR1i, // Control Panel (Negative Logic) - input [7:0] CTR2i, - - input VBLK, - - input [1:0] AD0, - input [1:0] OD0, - input WR0, - - input [1:0] AD1, - input [1:0] OD1, - input WR1, - - output [7:0] INPD0, - output [7:0] INPD1 -); - -reg [1:0] SYNCFLG; -reg [7:0] CTR1,CTR2; -always @( posedge MCLK or posedge RESET ) begin - if (RESET) begin - SYNCFLG = 0; - end - else begin - CTR1 <= CTR1i; - CTR2 <= CTR2i; - if (WR0) begin - if (OD0[1]) SYNCFLG[0] = 1; - if (OD0[0]) SYNCFLG[1] = 0; - end - if (WR1) begin - if (OD1[1]) SYNCFLG[0] = 0; - if (OD1[0]) SYNCFLG[1] = 1; - end - end -end - -wire [7:0] INPORT0 = CTR1; -wire [7:0] INPORT1 = CTR2; -wire [7:0] INPORT2 = { 4'b0000, SYNCFLG, ~VBLK,1'b0 }; - -assign INPD0 = ( AD0 == 0 ) ? INPORT0 : - ( AD0 == 1 ) ? INPORT1 : - ( AD0 == 2 ) ? INPORT2 : 8'hFF; - -assign INPD1 = ( AD1 == 0 ) ? INPORT0 : - ( AD1 == 1 ) ? INPORT1 : - ( AD1 == 2 ) ? INPORT2 : 8'hFF; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v deleted file mode 100644 index d74a98ce..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v +++ /dev/null @@ -1,93 +0,0 @@ -module ninjakun_psg -( - input MCLK, - input [1:0] ADR, - input CS, - input WR, - input [7:0] ID, - output [7:0] OD, - input RESET, - input RD, - input [7:0] DSW1, - input [7:0] DSW2, - output [7:0] SCRPX, - output [7:0] SCRPY, - output [15:0] SNDO -); - -wire [7:0] OD0, OD1; -assign OD = ADR[1] ? OD1 : OD0; - -reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c; -reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c; - -reg [2:0] encnt; -reg ENA; -always @(posedge MCLK) begin - ENA <= (encnt==0); - encnt <= encnt+1'd1; - case (S0c) - 2'd0: SA0 <= S0x; - 2'd1: SB0 <= S0x; - 2'd2: SC0 <= S0x; - default:; - endcase - case (S1c) - 2'd0: SA1 <= S1x; - 2'd1: SB1 <= S1x; - 2'd2: SC1 <= S1x; - default:; - endcase -end - -wire psgxad = ~ADR[0]; -wire psg0cs = CS & (~ADR[1]); -wire psg0bd = psg0cs & (WR|psgxad); -wire psg0bc = psg0cs & ((~WR)|psgxad); - -wire psg1cs = CS & ADR[1]; -wire psg1bd = psg1cs & (WR|psgxad); -wire psg1bc = psg1cs & ((~WR)|psgxad); - -YM2149 psg0( - .I_DA(ID), - .O_DA(OD0), - .I_A9_L(~psg0cs), - .I_BDIR(psg0bd), - .I_BC1(psg0bc), - .I_A8(1'b1), - .I_BC2(1'b1), - .I_SEL_L(1'b0), - .O_AUDIO(S0x), - .O_CHAN(S0c), - .I_IOA(DSW1), - .I_IOB(DSW2), - .ENA(ENA), - .RESET_L(~RESET), - .CLK(MCLK) -); - -YM2149 psg1( - .I_DA(ID), - .O_DA(OD1), - .I_A9_L(~psg1cs), - .I_BDIR(psg1bd), - .I_BC1(psg1bc), - .I_A8(1'b1), - .I_BC2(1'b1), - .I_SEL_L(1'b0), - .O_AUDIO(S1x), - .O_CHAN(S1c), - .I_IOA(8'd0), - .I_IOB(8'd0), - .O_IOA(SCRPX), - .O_IOB(SCRPY), - .ENA(ENA), - .RESET_L(~RESET), - .CLK(MCLK) -); - -wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1; -assign SNDO = {SND,SND[3:0]}; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v deleted file mode 100644 index 89bd4b14..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright (c) 2011 MiSTer-X - -module ninjakun_sadec -( - input [15:0] CPADR, - output CS_PSG, - output CS_FGV, - output CS_BGV, - output CS_SPA, - output CS_PAL -); - -assign CS_PSG = ( CPADR[15: 2] == 14'b1000_0000_0000_00 ); -assign CS_FGV = ( CPADR[15:11] == 5'b1100_0 ); -assign CS_BGV = ( CPADR[15:11] == 5'b1100_1 ); -assign CS_SPA = ( CPADR[15:11] == 5'b1101_0 ); -assign CS_PAL = ( CPADR[15:11] == 5'b1101_1 ); - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v deleted file mode 100644 index 2632a4d0..00000000 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v +++ /dev/null @@ -1,231 +0,0 @@ -// Copyright (c) 2011,19 MiSTer-X - -module NINJAKUN_VIDEO -( - input RESET, - input MCLK, - input PCLK_EN, - - input [8:0] PH, - input [8:0] PV, - - output [8:0] PALAD, // Pixel Output (Palet Index) - - output [9:0] FGVAD, // FG - input [15:0] FGVDT, - - output [9:0] BGVAD, // BG - input [15:0] BGVDT, - input [7:0] BGSCX, - input [7:0] BGSCY, - - output [10:0] SPAAD, // Sprite - input [7:0] SPADT, - - output VBLK, - input DBGPD, // Palet Display (for Debug) - - output [12:0] sp_rom_addr, - input [31:0] sp_rom_data, - input sp_rdy, - output [12:0] fg_rom_addr, - input [31:0] fg_rom_data, - output [12:0] bg_rom_addr, - input [31:0] bg_rom_data -); - -assign VBLK = (PV>=193); - -// ROMs -wire SPCFT = sp_rdy; -wire [12:0] SPCAD; -wire [31:0] SPCDT; - -wire [12:0] FGCAD; -wire [31:0] FGCDT; - -wire [12:0] BGCAD; -wire [31:0] BGCDT; - -//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN); -//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN); -//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN); - -assign sp_rom_addr = SPCAD; -assign SPCDT = sp_rom_data; -assign fg_rom_addr = FGCAD; -assign FGCDT = fg_rom_data; - -assign bg_rom_addr = BGCAD; -assign BGCDT = bg_rom_data; - -// Fore-Ground Scanline Generator -wire FGPRI; -wire [8:0] FGOUT; -NINJAKUN_FG fg( - MCLK, PCLK_EN, - PH, PV, - FGVAD, FGVDT, - FGCAD, FGCDT, - {FGPRI, FGOUT} -); -wire FGOPQ =(FGOUT[3:0]!=0); -wire FGPPQ = FGOPQ & (~FGPRI); - -// Back-Ground Scanline Generator -wire [8:0] BGOUT; -NINJAKUN_BG bg( - MCLK, PCLK_EN, - PH, PV, - BGSCX, BGSCY, - BGVAD, BGVDT, - BGCAD, BGCDT, - BGOUT -); - -// Sprite Scanline Generator -wire [8:0] SPOUT; -NINJAKUN_SP sp( - MCLK, PCLK_EN, RESET, - PH, PV, - SPAAD, SPADT, - SPCAD, SPCDT, SPCFT, - SPOUT -); -wire SPOPQ = (SPOUT[3:0]!=0); - -// Palet Display (for Debug) -wire [8:0] PDOUT = (PV[7]|PV[8]) ? 9'd0 : {PV[6:2],PH[7:4]}; - -// Color Mixer -DSEL4_9B cmix( PALAD, - DBGPD, PDOUT, - FGPPQ, FGOUT, - SPOPQ, SPOUT, - FGOPQ, FGOUT, - BGOUT -); - -endmodule - -// ForeGround Scanline Generator -module NINJAKUN_FG -( - input MCLK, - input PCLK_EN, - - input [8:0] PH, // CRTC - input [8:0] PV, - - output reg [9:0] FGVAD, // VRAM - input [15:0] FGVDT, - - output reg [12:0] FGCAD, - input [31:0] FGCDT, - - output [9:0] FGOUT // PIXEL OUT : {PRIO,PALNO[8:0]} -); - -wire [8:0] POSH = PH+9'd8+9'd1; -wire [8:0] POSV = PV+9'd32; - -wire [9:0] CHRNO = {1'b0,FGVDT[13],FGVDT[7:0]}; -reg [31:0] CDT; - -reg [4:0] PAL; -reg [3:0] OUT; -always @( posedge MCLK ) begin - if (PCLK_EN) - case(POSH[2:0]) - 0: begin OUT <= CDT[7:4] ; PAL <= FGVDT[12:8]; end - 1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end - 2: begin OUT <= CDT[15:12]; end - 3: begin OUT <= CDT[11:8] ; end - 4: begin OUT <= CDT[23:20]; FGCAD <= {CHRNO,POSV[2:0]}; end - 5: begin OUT <= CDT[19:16]; end - 6: begin OUT <= CDT[31:28]; end - 7: begin OUT <= CDT[27:24]; CDT <= FGCDT; end - endcase -end - -assign FGOUT = { PAL[4], 1'b0, PAL[3:0], OUT }; - -endmodule - - -// BackGround Scanline Generator -module NINJAKUN_BG -( - input MCLK, - input PCLK_EN, - - input [8:0] PH, // CRTC - input [8:0] PV, - - input [7:0] BGSCX, // SCRREG - input [7:0] BGSCY, - - output reg [9:0] BGVAD, // VRAM - input [15:0] BGVDT, - - output reg [12:0] BGCAD, - input [31:0] BGCDT, - - output [8:0] BGOUT // OUTPUT -); - -wire [8:0] POSH = PH+BGSCX+9'd2; -wire [8:0] POSV = PV+BGSCY+9'd32; - -wire [9:0] CHRNO = {BGVDT[15:14],BGVDT[7:0]}; -reg [31:0] CDT; - -reg [3:0] PAL; -reg [3:0] OUT; -always @( posedge MCLK ) begin - if (PCLK_EN) - case(POSH[2:0]) - 0: begin OUT <= CDT[7:4] ; PAL <= BGVDT[11:8]; end - 1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end - 2: begin OUT <= CDT[15:12]; end - 3: begin OUT <= CDT[11:8] ; end - 4: begin OUT <= CDT[23:20]; BGCAD <= {CHRNO,POSV[2:0]}; end - 5: begin OUT <= CDT[19:16]; end - 6: begin OUT <= CDT[31:28]; end - 7: begin OUT <= CDT[27:24]; CDT <= BGCDT; end - endcase -end - -assign BGOUT = { 1'b1, PAL, OUT }; - -endmodule - - -module DSEL4_9B -( - output [8:0] OUT, - - input EN1, - input [8:0] IN1, - - input EN2, - input [8:0] IN2, - - input EN3, - input [8:0] IN3, - - input EN4, - input [8:0] IN4, - - input [8:0] IND -); - -assign OUT = EN1 ? IN1: - EN2 ? IN2: - EN3 ? IN3: - EN4 ? IN4: - IND; - -endmodule - - diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/README.txt b/Arcade_MiST/Nova2001_Hardware/README.txt similarity index 97% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/README.txt rename to Arcade_MiST/Nova2001_Hardware/README.txt index a147acba..d54b6169 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/README.txt +++ b/Arcade_MiST/Nova2001_Hardware/README.txt @@ -2,6 +2,8 @@ -- -- Arcade: Ninja Kun port to MiST by Slingshot -- 29 December 2019 +-- Added Nova 2001, Raiders5 and Penguin-Kun Wars +-- 15 June 2021 -- --------------------------------------------------------------------------------- -- diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/clean.bat b/Arcade_MiST/Nova2001_Hardware/clean.bat similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/clean.bat rename to Arcade_MiST/Nova2001_Hardware/clean.bat diff --git a/Arcade_MiST/Nova2001_Hardware/meta/Ninjakun.mra b/Arcade_MiST/Nova2001_Hardware/meta/Ninjakun.mra new file mode 100644 index 00000000..cd98c373 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/meta/Ninjakun.mra @@ -0,0 +1,82 @@ + + Ninjakun Majou no Bouken + + no + no + + + + + 1984 + UPL + Taito + Platform - Climb + + ninjakun + ninjakun + 0220 + ninjakun + + + 15kHz + horizontal + + + 2 (alternating) + 2-way horizontal + + 2 + + + + + + + + + + + + + + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + 17 00 00 00 00 FF 00 02 00 02 00 01 00 FF 00 00 + 00 00 E0 A3 00 37 00 20 + 00 00 C0 8C 00 07 22 10 + + + + + + + + + 20210430005030 + \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/meta/Nova 2001.mra b/Arcade_MiST/Nova2001_Hardware/meta/Nova 2001.mra new file mode 100644 index 00000000..28e66588 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/meta/Nova 2001.mra @@ -0,0 +1,62 @@ + + Nova 2001 + + no + no + + + + + 1984 + UPL + Taito + Platform - Climb + + nova2001 + ninjakun + 0220 + ninjakun + + 15kHz + horizontal + + + 2 (alternating) + 2-way horizontal + + 2 + + + + + + + + + + + + + + 2 + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/meta/Penguin-Kun Wars (US).mra b/Arcade_MiST/Nova2001_Hardware/meta/Penguin-Kun Wars (US).mra new file mode 100644 index 00000000..fff31bbb --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/meta/Penguin-Kun Wars (US).mra @@ -0,0 +1,53 @@ + + Penguin-Kun Wars (US) + + no + no + + + + + 1984 + UPL + Taito + Ping-Pong + + pkunwar + ninjakun + 0220 + ninjakun + + 15kHz + horizontal + + + 2 (alternating) + 2-way horizontal + + 2 + + + + + + + + + + + 3 + + + + + + + + + + + + AA + + + \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/meta/Raiders5.mra b/Arcade_MiST/Nova2001_Hardware/meta/Raiders5.mra new file mode 100644 index 00000000..376a35e0 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/meta/Raiders5.mra @@ -0,0 +1,58 @@ + + Raiders5 + + no + no + + + + + 1984 + UPL + Taito + Platform - Climb + + raiders5 + ninjakun + 0220 + ninjakun + + 15kHz + horizontal + + + 2 (alternating) + 2-way horizontal + + 2 + + + + + + + + + + + + + + + + 1 + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv b/Arcade_MiST/Nova2001_Hardware/rtl/NinjaKun_MiST.sv similarity index 63% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv rename to Arcade_MiST/Nova2001_Hardware/rtl/NinjaKun_MiST.sv index c3e3287e..ad899248 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv +++ b/Arcade_MiST/Nova2001_Hardware/rtl/NinjaKun_MiST.sv @@ -27,35 +27,57 @@ module NinjaKun_MiST ( output SDRAM_CKE ); -`include "rtl\build_id.v" +`include "rtl/build_id.v" +`include "rtl/defs.v" localparam CONF_STR = { - "NINJAKUN;ROM;", + "NINJAKUN;;", "O2,Rotate Controls,Off,On;", - "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", "O5,Blend,Off,On;", - "O8,Difficulty,Normal,Hard;", - "O9A,Lives,4,3,2,5;", - "OB,1st Extra,30000,40000;", - "OCD,2nd Extra (Every),50000,70000,90000,None;", - "OF,Allow Continue,No,Yes;", - "OG,Free Play,No,Yes;", - "OH,Endless(If Free Play),No,Yes;", - "OE,Demo Sound,Off,On;", - "OI,Name Letters,8,3;", + "O6,Service,Off,On;", + "DIP;", "T0,Reset;", "V,v1.00.",`BUILD_DATE }; assign LED = ~ioctl_downl; assign AUDIO_R = AUDIO_L; -assign SDRAM_CLK = CLOCK_48; +assign SDRAM_CLK = CLOCK_96; assign SDRAM_CKE = 1; -wire CLOCK_48, pll_locked; +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire service = status[6]; + +wire [6:0] core_mod; +wire [1:0] hwtype = core_mod[1:0]; + +reg [7:0] CTR1, CTR2, CTR3; + +always @(*) begin + CTR1 = ~{2'b11, m_one_player, 1'b0, m_fireA, m_fireB, m_right, m_left }; + CTR2 = ~{~(m_coin1 | m_coin2), ~service, m_two_players, 1'b0, m_fire2A, m_fire2B, m_right2, m_left2 }; + CTR3 = 0; + if (hwtype == `HW_RAIDERS5) begin + CTR1 = ~{1'b0, 1'b0, m_one_player, m_fireA, m_up, m_down, m_right, m_left }; + CTR2 = ~{(m_coin1 | m_coin2), service, m_two_players, m_fire2A, m_up2, m_down2, m_right2, m_left2}; + end else if (hwtype == `HW_NOVA2001) begin + CTR1 = ~{m_fireA, m_fireB, 2'b00, m_right, m_left, m_down, m_up}; + CTR2 = ~{m_fire2A, m_fire2B, 2'b00, m_right2, m_left2, m_down2, m_up2}; + CTR3 = ~{5'b00000, m_two_players, m_one_player, m_coin1 | m_coin2}; + end else if (hwtype == `HW_PKUNWAR) begin + CTR1 = ~{2'b00, m_one_player, 2'b00, m_fireA, m_right, m_left }; + CTR2 = ~{(m_coin1 | m_coin2), service, m_two_players, 2'b00, m_fire2A, m_right2, m_left2 }; + end +end + +wire CLOCK_96, CLOCK_48, pll_locked; pll pll( .inclk0(CLOCK_27), - .c0(CLOCK_48), + .c0(CLOCK_96), + .c1(CLOCK_48), .locked(pll_locked) ); @@ -66,6 +88,7 @@ wire [7:0] joystick_0; wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; +wire no_csync; wire [15:0] audio; wire hs, vs; wire [3:0] r, g, b; @@ -102,20 +125,20 @@ data_io data_io( wire [24:0] cpu_ioctl_addr = ioctl_addr - 17'h10000; reg port1_req, port2_req; -wire [14:0] cpu1_rom_addr, cpu2_rom_addr; +wire [15:0] cpu1_rom_addr, cpu2_rom_addr; wire [15:0] cpu1_rom_do, cpu2_rom_do; -wire [12:0] sp_rom_addr; +wire [13:0] sp_rom_addr; wire [31:0] sp_rom_do; wire sp_rdy; wire [12:0] fg_rom_addr; wire [31:0] fg_rom_do; -wire [12:0] bg_rom_addr; +wire [13:0] bg_rom_addr; wire [31:0] bg_rom_do; -sdram sdram( +sdram #(96) sdram( .*, .init_n ( pll_locked ), - .clk ( CLOCK_48 ), + .clk ( CLOCK_96 ), // port1 used for main + aux CPU .port1_req ( port1_req ), @@ -126,9 +149,9 @@ sdram sdram( .port1_d ( {ioctl_dout, ioctl_dout} ), .port1_q ( ), - .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu1_rom_addr[14:1]} ), + .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu1_rom_addr[15:1]} ), .cpu1_q ( cpu1_rom_do ), - .cpu2_addr ( ioctl_downl ? 16'hffff : {1'b1, cpu2_rom_addr[14:1]} ), + .cpu2_addr ( ioctl_downl ? 16'hffff : {2'b01, cpu2_rom_addr[14:1]} ), .cpu2_q ( cpu2_rom_do ), // port2 for graphics @@ -142,10 +165,10 @@ sdram sdram( .fg_addr ( ioctl_downl ? 15'h7fff : {1'b0, fg_rom_addr} ), .fg_q ( fg_rom_do ), - .sp_addr ( ioctl_downl ? 15'h7fff : {1'b0, sp_rom_addr} ), + .sp_addr ( ioctl_downl ? 15'h7fff : sp_rom_addr ), .sp_q ( sp_rom_do ), .sp_rdy ( sp_rdy ), - .bg_addr ( ioctl_downl ? 15'h7fff : {1'b1, bg_rom_addr} ), + .bg_addr ( ioctl_downl ? 15'h7fff : bg_rom_addr ), .bg_q ( bg_rom_do ) ); @@ -178,10 +201,12 @@ wire [11:0] POUT; ninjakun_top ninjakun_top( .RESET(reset), .MCLK(CLOCK_48), - .CTR1(~{2'b11, btn_one_player, 1'b0, m_fire, m_bomb, m_right, m_left }), - .CTR2(~{~btn_coin, 1'b1, btn_two_players, 1'b0, m_fire, m_bomb, m_right, m_left }), - .DSW1({~status[8], ~status[14], ~status[13:12], ~status[11], ~status[10:9], 1'b0}), - .DSW2({~status[17], ~status[16], 1'b0, ~status[15], ~status[18], 3'b111}), + .HWTYPE(hwtype), + .CTR1(CTR1), + .CTR2(CTR2), + .CTR3(CTR3), + .DSW1(status[15:8]), + .DSW2({(hwtype == `HW_NOVA2001 ? ~service : status[23]), status[22:16]}), .PH(HPOS), .PV(VPOS), .PCLK_EN(PCLK_EN), @@ -197,7 +222,11 @@ ninjakun_top ninjakun_top( .fg_rom_addr(fg_rom_addr), .fg_rom_data(fg_rom_do), .bg_rom_addr(bg_rom_addr), - .bg_rom_data(bg_rom_do) + .bg_rom_data(bg_rom_do), + .PALADR(ioctl_addr[4:0]), + .PALWR(ioctl_addr[23:5] == {16'h0180, 3'b000} && ioctl_wr), + .PALDAT(ioctl_dout) + ); wire [7:0] oPIX; @@ -229,12 +258,13 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video( .VGA_B ( VGA_B ), .VGA_VS ( VGA_VS ), .VGA_HS ( VGA_HS ), - .rotate ( {1'b1,status[2]} ), - .ce_divider ( 1'b1 ), - .blend ( status[5] ), + .rotate ( { 1'b1, rotate } ), + .ce_divider ( 1'b1 ), + .blend ( blend ), .scandoubler_disable( scandoublerD ), - .scanlines ( status[4:3] ), - .ypbpr ( ypbpr ) + .scanlines ( scanlines ), + .ypbpr ( ypbpr ), + .no_csync ( no_csync ) ); user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( @@ -246,8 +276,10 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( .SPI_MOSI (SPI_DI ), .buttons (buttons ), .switches (switches ), + .core_mod (core_mod ), .scandoubler_disable (scandoublerD ), .ypbpr (ypbpr ), + .no_csync (no_csync ), .key_strobe (key_strobe ), .key_pressed (key_pressed ), .key_code (key_code ), @@ -262,41 +294,25 @@ dac #(.C_bits(16))dac( .dac_i(audio), .dac_o(AUDIO_L) ); -// Rotated Normal -//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -//reg btn_fire3 = 0; -reg btn_coin = 0; - -always @(posedge CLOCK_48) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 -// 'h14: btn_fire3 <= key_pressed; // ctrl - 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; +arcade_inputs inputs ( + .clk ( CLOCK_48 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( 2'b10 ), + .joyswap ( 1'b0 ), + .oneplayer ( 1'b1 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/build_id.tcl b/Arcade_MiST/Nova2001_Hardware/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/build_id.tcl rename to Arcade_MiST/Nova2001_Hardware/rtl/build_id.tcl diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/defs.v b/Arcade_MiST/Nova2001_Hardware/rtl/defs.v new file mode 100644 index 00000000..975dbdda --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/defs.v @@ -0,0 +1,4 @@ +`define HW_NINJAKUN 2'd0 +`define HW_RAIDERS5 2'd1 +`define HW_NOVA2001 2'd2 +`define HW_PKUNWAR 2'd3 diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd b/Arcade_MiST/Nova2001_Hardware/rtl/dpram.vhd similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd rename to Arcade_MiST/Nova2001_Hardware/rtl/dpram.vhd diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v b/Arcade_MiST/Nova2001_Hardware/rtl/hvgen.v similarity index 94% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v rename to Arcade_MiST/Nova2001_Hardware/rtl/hvgen.v index 8fc63e5d..00f267cd 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/hvgen.v @@ -22,7 +22,7 @@ always @(posedge CLK) begin if (PCLK_EN) begin case (hcnt) 15: begin HBLK <= 0; hcnt <= hcnt+1'd1; end - 272: begin HBLK <= 1; hcnt <= hcnt+1'd1; end + 271: begin HBLK <= 1; hcnt <= hcnt+1'd1; end 311: begin HSYN <= 0; hcnt <= hcnt+1'd1; end 342: begin HSYN <= 1; hcnt <= 471; end 511: begin hcnt <= 0; diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_adec.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_adec.v new file mode 100644 index 00000000..ec0f99e1 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_adec.v @@ -0,0 +1,62 @@ +module ninjakun_adec +( + input [1:0] HWTYPE, + input [15:0] CP0AD, + input CP0WR, + + input [15:0] CP1AD, + input CP1WR, + + output CS_IN0, + output CS_IN1, + + output CS_SH0, + output CS_SH1, + + output SYNWR0, + output SYNWR1 +); + +`include "rtl/defs.v" + +always @(*) begin + CS_IN0 = (CP0AD[15:2] == 14'b1010_0000_0000_00); + CS_IN1 = (CP1AD[15:2] == 14'b1010_0000_0000_00); + + CS_SH0 = (CP0AD[15:11] == 5'b1110_0); + CS_SH1 = (CP1AD[15:11] == 5'b1110_0); + + SYNWR0 = CS_IN0 & (CP0AD[1:0]==2) & CP0WR; + SYNWR1 = CS_IN1 & (CP1AD[1:0]==2) & CP1WR; + + if (HWTYPE == `HW_RAIDERS5) begin + CS_IN0 = 0; + CS_IN1 = 0; + + CS_SH0 = (CP0AD[15:11] == 5'b1110_0); + CS_SH1 = (CP1AD[15:11] == 5'b1010_0); + + SYNWR0 = 0; + SYNWR1 = 0; + end else if (HWTYPE == `HW_NOVA2001) begin + CS_IN0 = (CP0AD[15:4] == 12'hC00 && (CP0AD[3:1] == 3'b011 || CP0AD[3:1] == 3'b111)); + CS_IN1 = 0; + + CS_SH0 = (CP0AD[15:11] == 5'b1110_0); + CS_SH1 = 0; + + SYNWR0 = 0; + SYNWR1 = 0; + end else if (HWTYPE == `HW_PKUNWAR) begin + CS_IN0 = 0; + CS_IN1 = 0; + + CS_SH0 = (CP0AD[15:11] == 5'b1100_0); + CS_SH1 = 0; + + SYNWR0 = 0; + SYNWR1 = 0; + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_cpumux.v similarity index 95% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_cpumux.v index 117e5cb0..6f32333a 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_cpumux.v @@ -6,6 +6,7 @@ module ninjakun_cpumux input [7:0] CPIDT, output CPRED, output CPWRT, + output CPSEL, output reg CP0CL, output reg CP0CE_P, @@ -26,6 +27,7 @@ module ninjakun_cpumux input CP1WR ); +assign CPSEL = CSIDE; reg [7:0] CP0DT, CP1DT; reg [3:0] PHASE; reg CSIDE; diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_input.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_input.v new file mode 100644 index 00000000..b9f9de79 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_input.v @@ -0,0 +1,59 @@ +// Copyright (c) 2011 MiSTer-X + +module ninjakun_input +( + input MCLK, + input RESET, + input [1:0] HWTYPE, + + input [7:0] CTR1i, // Control Panel (Negative Logic) + input [7:0] CTR2i, + input [7:0] CTR3i, + input VBLK, + + input [1:0] AD0, + input [1:0] OD0, + input WR0, + + input [1:0] AD1, + input [1:0] OD1, + input WR1, + + output [7:0] INPD0, + output [7:0] INPD1 +); + +reg [1:0] SYNCFLG; +reg [7:0] CTR1,CTR2,CTR3; +always @( posedge MCLK or posedge RESET ) begin + if (RESET) begin + SYNCFLG = 0; + end + else begin + CTR1 <= CTR1i; + CTR2 <= CTR2i; + CTR3 <= CTR3i; + if (WR0) begin + if (OD0[1]) SYNCFLG[0] = 1; + if (OD0[0]) SYNCFLG[1] = 0; + end + if (WR1) begin + if (OD1[1]) SYNCFLG[0] = 0; + if (OD1[0]) SYNCFLG[1] = 1; + end + end +end + +wire [7:0] INPORT0 = CTR1; +wire [7:0] INPORT1 = CTR2; +wire [7:0] INPORT2 = HWTYPE[1] ? {~VBLK, CTR3[6:0]} : { 4'b0000, SYNCFLG, ~VBLK,1'b0 }; + +assign INPD0 = ( AD0 == 0 ) ? INPORT0 : + ( AD0 == 1 ) ? INPORT1 : + ( AD0 == 2 ) ? INPORT2 : 8'hFF; + +assign INPD1 = ( AD1 == 0 ) ? INPORT0 : + ( AD1 == 1 ) ? INPORT1 : + ( AD1 == 2 ) ? INPORT2 : 8'hFF; + +endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_io_video.v similarity index 54% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_io_video.v index 9dea211e..88af16e6 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_io_video.v @@ -2,42 +2,56 @@ module ninjakun_io_video ( - input MCLK, - input PCLK_EN, - input RESET, - input [8:0] PH, - input [8:0] PV, - input [15:0] CPADR, - input [7:0] CPODT, - output [7:0] CPIDT, - input CPRED, - input CPWRT, - input [7:0] DSW1, - input [7:0] DSW2, - output VBLK, - output [7:0] POUT, - output [15:0] SNDOUT, - output [12:0] sp_rom_addr, - input [31:0] sp_rom_data, + input MCLK, + input [1:0] HWTYPE, + input PCLK_EN, + input RESET, + input [8:0] PH, + input [8:0] PV, + input [15:0] CPADR, + input [7:0] CPODT, + output [7:0] CPIDT, + input CPRED, + input CPWRT, + input CPSEL, + input [7:0] DSW1, + input [7:0] DSW2, + input [7:0] CTR1, + input [7:0] CTR2, + output VBLK, + output [7:0] POUT, + output [15:0] SNDOUT, + output [13:0] sp_rom_addr, + input [31:0] sp_rom_data, input sp_rdy, - output [12:0] fg_rom_addr, - input [31:0] fg_rom_data, - output [12:0] bg_rom_addr, - input [31:0] bg_rom_data + output [12:0] fg_rom_addr, + input [31:0] fg_rom_data, + output [13:0] bg_rom_addr, + input [31:0] bg_rom_data, + input [4:0] PALADR, + input PALWR, + input [7:0] PALDAT ); +`include "rtl/defs.v" + wire [9:0] FGVAD; wire [15:0] FGVDT; wire [9:0] BGVAD; wire [15:0] BGVDT; wire [10:0] SPAAD; wire [7:0] SPADT; -wire [7:0] SCRPX, SCRPY; +wire RAIDERS5 = HWTYPE == `HW_RAIDERS5; +wire [7:0] SCRPX = RAIDERS5 ? SCRPX_CPU : SCRPX_PSG, SCRPY = RAIDERS5 ? SCRPY_CPU : SCRPY_PSG; +wire [7:0] SCRPX_PSG, SCRPY_PSG; +reg [7:0] SCRPX_CPU, SCRPY_CPU; wire [8:0] PALET; + NINJAKUN_VIDEO video ( .RESET(RESET), .MCLK(MCLK), .PCLK_EN(PCLK_EN), + .HWTYPE(HWTYPE), .PH(PH), .PV(PV), .PALAD(PALET), // Pixel Output (Palet Index) @@ -60,44 +74,51 @@ NINJAKUN_VIDEO video ( .bg_rom_data(bg_rom_data) ); -wire CS_PSG, CS_FGV, CS_BGV, CS_SPA, CS_PAL; +wire CS_SCRX, CS_SCRY, CS_PSG, CS_FGV, CS_BGV, CS_SPA, CS_PAL; ninjakun_sadec sadec( + .HWTYPE(HWTYPE), .CPADR(CPADR), + .CPSEL(CPSEL), + .CS_SCRX(CS_SCRX), + .CS_SCRY(CS_SCRY), .CS_PSG(CS_PSG), .CS_FGV(CS_FGV), .CS_BGV(CS_BGV), .CS_SPA(CS_SPA), .CS_PAL(CS_PAL) ); +always @(posedge MCLK) begin + if (RESET) begin + SCRPX_CPU <= 0; + SCRPY_CPU <= 0; + end else begin + if (CS_SCRX) SCRPX_CPU <= CPODT; + if (CS_SCRY) SCRPY_CPU <= CPODT; + end +end wire [7:0] PSDAT, FGDAT = CPADR[10] ? FGDAT16[15:8] : FGDAT16[7:0], BGDAT = CPADR[10] ? BGDAT16[15:8] : BGDAT16[7:0], SPDAT, PLDAT; wire [15:0] FGDAT16, BGDAT16; wire [9:0] BGOFS = CPADR[9:0]+{SCRPY[7:3],SCRPX[7:3]}; -wire [10:0] BGADR = {CPADR[10],BGOFS}; +wire [10:0] BGADR = HWTYPE[1] ? CPADR[10:0] : {CPADR[10],BGOFS}; dpram #(8,10) fgv_lo(MCLK, CS_FGV & CPWRT & ~CPADR[10], CPADR[9:0], CPODT, FGDAT16[ 7:0], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[ 7:0]); dpram #(8,10) fgv_hi(MCLK, CS_FGV & CPWRT & CPADR[10], CPADR[9:0], CPODT, FGDAT16[15:8], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[15:8]); dpram #(8,10) bgv_lo(MCLK, CS_BGV & CPWRT & ~BGADR[10], BGADR[9:0], CPODT, BGDAT16[ 7:0], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[ 7:0]); dpram #(8,10) bgv_hi(MCLK, CS_BGV & CPWRT & BGADR[10], BGADR[9:0], CPODT, BGDAT16[15:8], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[15:8]); dpram #(8,11) spa (MCLK, CS_SPA & CPWRT, CPADR[10:0], CPODT, SPDAT, ~MCLK, 1'b0, SPAAD, 8'h0, SPADT); -dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, 1'b0, PALET, 8'h0, POUT); +dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, PALWR, PALWR ? PALADR : PALET, PALDAT, POUT); -dataselector_5D_8B cpxdsel( - .out(CPIDT), - .en0(CS_PSG), - .dt0(PSDAT), - .en1(CS_FGV), - .dt1(FGDAT), - .en2(CS_BGV), - .dt2(BGDAT), - .en3(CS_SPA), - .dt3(SPDAT), - .en4(CS_PAL), - .dt4(PLDAT) -); +assign CPIDT = CS_PSG ? PSDAT : + CS_FGV ? FGDAT : + CS_BGV ? BGDAT : + CS_SPA ? SPDAT : + CS_PAL ? PLDAT : + 8'hFF; ninjakun_psg psg( .MCLK(MCLK), + .HWTYPE(HWTYPE), .ADR(CPADR[1:0]), .CS(CS_PSG), .WR(CPWRT), @@ -107,9 +128,12 @@ ninjakun_psg psg( .RD(CPRED), .DSW1(DSW1), .DSW2(DSW2), - .SCRPX(SCRPX), - .SCRPY(SCRPY), + .CTR1(CTR1), + .CTR2(CTR2), + .VBLK(VBLK), + .SCRPX(SCRPX_PSG), + .SCRPY(SCRPY_PSG), .SNDO(SNDOUT) ); -endmodule \ No newline at end of file +endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_irqgen.v similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_irqgen.v diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_main.v similarity index 62% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_main.v index 7271381b..ce5055f5 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_main.v @@ -1,23 +1,27 @@ module ninjakun_main( - input RESET, - input MCLK, - input VBLK, + input RESET, + input MCLK, + input [1:0] HWTYPE, + input VBLK, - input [7:0] CTR1, - input [7:0] CTR2, + input [7:0] CTR1, + input [7:0] CTR2, + input [7:0] CTR3, - output [15:0] CPADR, - output [7:0] CPODT, - input [7:0] CPIDT, - output CPRED, - output CPWRT, + output [15:0] CPADR, + output [7:0] CPODT, + input [7:0] CPIDT, + output CPRED, + output CPWRT, + output CPSEL, - output [14:0] CPU1ADDR, - input [7:0] CPU1DT, - output [14:0] CPU2ADDR, - input [7:0] CPU2DT + output [15:0] CPU1ADDR, + input [7:0] CPU1DT, + output [14:0] CPU2ADDR, + input [7:0] CPU2DT ); +`include "rtl/defs.v" wire CP0IQ, CP0IQA; wire CP1IQ, CP1IQA; @@ -52,7 +56,7 @@ Z80IP cpu0( ); Z80IP cpu1( - .reset_in(RESET), + .reset_in(RESET | HWTYPE[1]), .clk(MCLK), .clken_p(CP1CE_P), .clken_n(CP1CE_N), @@ -72,6 +76,7 @@ ninjakun_cpumux ioshare( .CPIDT(CPIDT), .CPRED(CPRED), .CPWRT(CPWRT), + .CPSEL(CPSEL), .CP0CE_P(CP0CE_P), .CP0CE_N(CP0CE_N), .CP0AD(CP0AD), @@ -91,6 +96,7 @@ ninjakun_cpumux ioshare( wire CS_SH0, CS_SH1, CS_IN0, CS_IN1; wire SYNWR0, SYNWR1; ninjakun_adec adec( + .HWTYPE(HWTYPE), .CP0AD(CP0AD), .CP0WR(CP0WR), .CP1AD(CP1AD), @@ -105,25 +111,29 @@ ninjakun_adec adec( wire [7:0] ROM0D, ROM1D; -assign CPU1ADDR = CP0AD[14:0]; +assign CPU1ADDR = CP0AD; assign ROM0D = CPU1DT; assign CPU2ADDR = CP1AD[14:0]; assign ROM1D = CPU2DT; wire [7:0] SHDT0, SHDT1; +wire RAIDERS5 = HWTYPE == `HW_RAIDERS5; dpram #(8,11) shmem( - MCLK, CS_SH0 & CP0WR, { CP0AD[10] ,CP0AD[9:0]}, CP0OD, SHDT0, - MCLK, CS_SH1 & CP1WR, {~CP1AD[10], CP1AD[9:0]}, CP1OD, SHDT1); + MCLK, CS_SH0 & CP0WR, { CP0AD[10] ,CP0AD[9:0]}, CP0OD, SHDT0, + MCLK, CS_SH1 & CP1WR, {RAIDERS5 ^ ~CP1AD[10], CP1AD[9:0]}, CP1OD, SHDT1); wire [7:0] INPD0, INPD1; ninjakun_input inps( .MCLK(MCLK), .RESET(RESET), + .HWTYPE(HWTYPE), .CTR1i(CTR1), // Control Panel (Negative Logic) .CTR2i(CTR2), + .CTR3i(CTR3), .VBLK(VBLK), - .AD0(CP0AD[1:0]), +// .AD0(CP0AD[1:0]), + .AD0({HWTYPE[1] ? CP0AD[3] : CP0AD[1], CP0AD[0]}), .OD0(CP0OD[7:6]), .WR0(SYNWR0), .AD1(CP1AD[1:0]), @@ -133,26 +143,15 @@ ninjakun_input inps( .INPD1(INPD1) ); -dataselector_3D_8B cdt0( - .out(CP0DT), - .df(CP0ID), - .en0(CS_IN0), - .dt0(INPD0), - .en1(CS_SH0), - .dt1(SHDT0), - .en2(~CP0AD[15]), - .dt2(ROM0D) -); +assign CP0DT = CS_IN0 ? INPD0 : + CS_SH0 ? SHDT0 : + ~CP0AD[15] ? ROM0D : + (HWTYPE == `HW_PKUNWAR && CP0AD[15:13] == 3'b111) ? ROM0D : + CP0ID; -dataselector_3D_8B cdt1( - .out(CP1DT), - .df(CP1ID), - .en0(CS_IN1), - .dt0(INPD1), - .en1(CS_SH1), - .dt1(SHDT1), - .en2(~CP1AD[15]), - .dt2(ROM1D) -); +assign CP1DT = CS_IN1 ? INPD1 : + CS_SH1 ? SHDT1 : + ~CP1AD[15] ? ROM1D : + CP1ID; endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_psg.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_psg.v new file mode 100644 index 00000000..87f10fb3 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_psg.v @@ -0,0 +1,116 @@ +module ninjakun_psg +( + input MCLK, + input [1:0] HWTYPE, + input [1:0] ADR, + input CS, + input WR, + input [7:0] ID, + output [7:0] OD, + input RESET, + input RD, + input [7:0] DSW1, + input [7:0] DSW2, + input [7:0] CTR1, + input [7:0] CTR2, + input VBLK, + output [7:0] SCRPX, + output [7:0] SCRPY, + output [15:0] SNDO +); + +`include "rtl/defs.v" + +wire [7:0] OD0, OD1; +assign OD = psg1cs ? OD1 : OD0; + +reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c; +reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c; + +reg [3:0] encnt; +reg ENA; +always @(posedge MCLK) begin + ENA <= (encnt==0); + encnt <= encnt+1'd1; + case (HWTYPE) + `HW_NINJAKUN, `HW_RAIDERS5: + if (encnt == 7) encnt <= 0; // 6 MHz + `HW_NOVA2001: + if (encnt == 11) encnt <= 0; // 4 MHz + default: ; // 3 MHz + endcase + + case (S0c) + 2'd0: SA0 <= S0x; + 2'd1: SB0 <= S0x; + 2'd2: SC0 <= S0x; + default:; + endcase + case (S1c) + 2'd0: SA1 <= S1x; + 2'd1: SB1 <= S1x; + 2'd2: SC1 <= S1x; + default:; + endcase +end + +wire psgxad = HWTYPE == `HW_NOVA2001 ? ADR[1] : ~ADR[0]; +wire psg0cs = CS & (HWTYPE == `HW_NOVA2001 ? ~ADR[0] : ~ADR[1]); +wire psg0bd = psg0cs & (WR|psgxad); +wire psg0bc = psg0cs & ((~WR)|psgxad); + +wire psg1cs = CS & (HWTYPE == `HW_NOVA2001 ? ADR[0] : ADR[1]); +wire psg1bd = psg1cs & (WR|psgxad); +wire psg1bc = psg1cs & ((~WR)|psgxad); + +wire [7:0] IOA_PSG0, IOB_PSG0; +wire [7:0] IOA_PSG1, IOB_PSG1; +assign SCRPX = HWTYPE == `HW_NOVA2001 ? IOA_PSG0 : IOA_PSG1; +assign SCRPY = HWTYPE == `HW_NOVA2001 ? IOB_PSG0 : IOB_PSG1; + +wire IO_TYPE = HWTYPE == `HW_RAIDERS5 || HWTYPE == `HW_PKUNWAR; + +YM2149 psg0( + .I_DA(ID), + .O_DA(OD0), + .I_A9_L(~psg0cs), + .I_BDIR(psg0bd), + .I_BC1(psg0bc), + .I_A8(1'b1), + .I_BC2(1'b1), + .I_SEL_L(1'b0), + .O_AUDIO(S0x), + .O_CHAN(S0c), + .I_IOA(IO_TYPE ? {~VBLK, CTR1[6:0]} : DSW1), + .I_IOB(IO_TYPE ? CTR2 : DSW2), + .O_IOA(IOA_PSG0), + .O_IOB(IOB_PSG0), + .ENA(ENA), + .RESET_L(~RESET), + .CLK(MCLK) +); + +YM2149 psg1( + .I_DA(ID), + .O_DA(OD1), + .I_A9_L(~psg1cs), + .I_BDIR(psg1bd), + .I_BC1(psg1bc), + .I_A8(1'b1), + .I_BC2(1'b1), + .I_SEL_L(1'b0), + .O_AUDIO(S1x), + .O_CHAN(S1c), + .I_IOA(HWTYPE == `HW_NINJAKUN ? 8'd0 : DSW1), + .I_IOB(HWTYPE == `HW_NINJAKUN ? 8'd0 : DSW2), + .O_IOA(IOA_PSG1), + .O_IOB(IOB_PSG1), + .ENA(ENA), + .RESET_L(~RESET), + .CLK(MCLK) +); + +wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1; +assign SNDO = {SND,SND[3:0]}; + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sadec.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sadec.v new file mode 100644 index 00000000..868c84d8 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sadec.v @@ -0,0 +1,78 @@ +// Copyright (c) 2011 MiSTer-X + +module ninjakun_sadec +( + input [1:0] HWTYPE, + input [15:0] CPADR, + input CPSEL, + output CS_SCRX, + output CS_SCRY, + output CS_PSG, + output CS_FGV, + output CS_BGV, + output CS_SPA, + output CS_PAL +); + +`include "rtl/defs.v" + +always @(*) begin + CS_PSG = ( CPADR[15: 2] == 14'b1000_0000_0000_00 ); + CS_FGV = ( CPADR[15:11] == 5'b1100_0 ); + CS_BGV = ( CPADR[15:11] == 5'b1100_1 ); + CS_SPA = ( CPADR[15:11] == 5'b1101_0 ); + CS_PAL = ( CPADR[15:11] == 5'b1101_1 ); + CS_SCRX = 0; + CS_SCRY = 0; + + if (HWTYPE == `HW_RAIDERS5) begin + if (CPSEL) begin + CS_SCRX = ( CPADR == 16'he000 ); + CS_SCRY = ( CPADR == 16'he001 ); + CS_PSG = ( CPADR[15: 2] == 14'b1000_0000_0000_00 ); + CS_FGV = 0; + CS_BGV = 0; + CS_SPA = 0; + CS_PAL = 0; + end else begin + CS_SCRX = ( CPADR == 16'ha000 ); + CS_SCRY = ( CPADR == 16'ha001 ); + CS_PSG = ( CPADR[15: 2] == 14'b1100_0000_0000_00 ); + CS_FGV = ( CPADR[15:11] == 5'b1000_1 ); + CS_BGV = ( CPADR[15:11] == 5'b1001_0 ); + CS_SPA = ( CPADR[15:11] == 5'b1000_0 ); + CS_PAL = ( CPADR[15:11] == 5'b1101_0 ); + end + end else if (HWTYPE == `HW_NOVA2001) begin + CS_SCRX = 0; + CS_SCRY = 0; + CS_PAL = 0; + if (CPSEL) begin + CS_PSG = 0; + CS_FGV = 0; + CS_BGV = 0; + CS_SPA = 0; + end else begin + CS_PSG = ( CPADR[15: 2] == 14'b1100_0000_0000_00 ); + CS_FGV = ( CPADR[15:11] == 5'b1010_0 ); + CS_BGV = ( CPADR[15:11] == 5'b1010_1 ); + CS_SPA = ( CPADR[15:11] == 5'b1011_0 ); + end + end else if (HWTYPE == `HW_PKUNWAR) begin + CS_SCRX = 0; + CS_SCRY = 0; + CS_PAL = 0; + CS_FGV = 0; + if (CPSEL) begin + CS_PSG = 0; + CS_BGV = 0; + CS_SPA = 0; + end else begin + CS_PSG = ( CPADR[15: 2] == 14'b1010_0000_0000_00 ); + CS_BGV = ( CPADR[15:11] == 5'b1000_1 ); + CS_SPA = ( CPADR[15:11] == 5'b1000_0 ); + end + end +end + +endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sprite.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sprite.v similarity index 62% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sprite.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sprite.v index b31ec920..53773ae2 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sprite.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_sprite.v @@ -2,25 +2,26 @@ module NINJAKUN_SP ( - input MCLK, - input PCLK_EN, - input RESET, + input MCLK, + input PCLK_EN, + input RESET, + input RAIDERS5, - input [8:0] PH, - input [8:0] PV, + input [8:0] PH, + input [8:0] PV, - output [10:0] SPAAD, - input [7:0] SPADT, + output [10:0] SPAAD, + input [7:0] SPADT, - output [12:0] SPCAD, - input [31:0] SPCDT, - input SPCFT, + output [13:0] SPCAD, + input [31:0] SPCDT, + input SPCFT, - output [8:0] SPOUT + output [8:0] SPOUT ); -wire WPEN; -wire [8:0] WPAD; +wire WPEN; +wire [7:0] WPAD; wire [7:0] WPIX; reg [7:0] POUT; @@ -30,7 +31,7 @@ reg [9:0] radr0=0,radr1=1; wire [7:0] POUTi; dpram #(8,10) ldbuf( - MCLK, WPEN, {PV[0], WPAD}, WPIX, 8'd0, + MCLK, WPEN, {PV[0], 1'b0, WPAD}, WPIX, 8'd0, MCLK, (radr0==radr1), radr0, 8'd0, POUTi); always @(posedge MCLK) begin @@ -42,7 +43,7 @@ always @(posedge MCLK) begin end NINJAKUN_SPENG eng ( - MCLK, RESET, PH, PV, + MCLK, RESET, RAIDERS5, PH, PV, SPAAD, SPADT, SPCAD, SPCDT, SPCFT, WPAD, WPIX, WPEN @@ -55,34 +56,34 @@ endmodule module NINJAKUN_SPENG ( - input MCLK, - input RESET, + input MCLK, + input RESET, + input RAIDERS5, - input [8:0] PH, - input [8:0] PV, + input [8:0] PH, + input [8:0] PV, - output [10:0] SPAAD, - input [7:0] SPADT, + output [10:0] SPAAD, + input [7:0] SPADT, - output reg [12:0] SPCAD, - input [31:0] SPCDT, - input SPCFT, + output reg [13:0] SPCAD, + input [31:0] SPCDT, + input SPCFT, - output [8:0] WPAD, - output [7:0] WPIX, - output WPEN + output [7:0] WPAD, + output [7:0] WPIX, + output WPEN ); reg [5:0] SPRNO; reg [1:0] SPRIX; -assign SPAAD = {SPRNO, 3'h0, SPRIX}; +assign SPAAD = {SPRNO, 3'h0, SPRIX}; -reg [7:0] ATTR; -wire [3:0] PALNO = ATTR[3:0]; -wire FLIPH = ATTR[4]; -wire FLIPV = ATTR[5]; -wire XPOSH = ATTR[6]; -wire DSABL = ATTR[7]; +reg [3:0] PALNO; +reg FLIPH; +reg FLIPV; +reg XPOSH; +reg DSABL; reg [7:0] YPOS; reg [7:0] NV; @@ -93,11 +94,11 @@ wire YHIT = (HV[7:4]==4'b1111) & (~DSABL); reg [7:0] XPOS; reg [4:0] WP; wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]); -assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1'd1; -assign WPEN = ~(WP[4]|(WPIX[3:0]==0)); +assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1'd1; +assign WPEN = ~(WP[4]|(WPIX[3:0]==0)); -reg [7:0] PTNO; -reg CRS; +reg [8:0] PTNO; +reg CRS; function [3:0] XOUT; input [2:0] N; @@ -127,16 +128,18 @@ assign WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)}; `define NEXT 7 reg [2:0] STATE; +reg PH8_D; always @( posedge MCLK ) begin if (RESET) begin STATE <= `WAIT; - SPCAD <= 13'h1fff; + SPCAD <= 14'h3fff; end else case (STATE) `WAIT: begin + PH8_D <= PH[8]; WP <= 16; - if (~PH[8]) begin + if (PH8_D & ~PH[8]) begin NV <= PV+5'd17; SPRNO <= 0; SPRIX <= 2; @@ -150,13 +153,28 @@ always @( posedge MCLK ) begin STATE <= `FETCH1; end `FETCH1: begin - ATTR = SPADT; /* ATTR must block assign */ + if (!RAIDERS5) begin + PALNO <= SPADT[3:0]; + FLIPH <= SPADT[4]; + FLIPV <= SPADT[5]; + XPOSH <= SPADT[6]; + DSABL <= SPADT[7]; + end else begin + PALNO <= SPADT[7:4]; + DSABL <= SPADT[3]; + XPOSH <= 0; + PTNO[8:6] <= SPADT[2:0]; + end SPRIX <= 0; STATE <= YHIT ? `FETCH2 : `NEXT; end `FETCH2: begin - PTNO <= SPADT; + if (RAIDERS5) begin + FLIPH <= SPADT[0]; + FLIPV <= SPADT[1]; + end + PTNO <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT; SPRIX <= 1; STATE <= `FETCH3; end @@ -183,7 +201,7 @@ always @( posedge MCLK ) begin `DRAW: begin WP <= WP+1'd1; - if (WP[4]) STATE <= `NEXT; + if (&WP[3:0]) STATE <= `NEXT; end `NEXT: begin diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_top.v similarity index 55% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v rename to Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_top.v index 2e6366e1..49f43917 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_top.v @@ -9,28 +9,33 @@ module ninjakun_top ( - input RESET, // RESET - input MCLK, // Master Clock (48.0MHz) - input [7:0] CTR1, // Control Panel - input [7:0] CTR2, - input [7:0] DSW1, // DipSW - input [7:0] DSW2, - input [8:0] PH, // PIXEL H - input [8:0] PV, // PIXEL V - output PCLK_EN, // PIXEL CLOCK ENABLE - output [7:0] POUT, // PIXEL OUT - output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits) - output [14:0] CPU1ADDR, - input [7:0] CPU1DT, - output [14:0] CPU2ADDR, - input [7:0] CPU2DT, - output [12:0] sp_rom_addr, - input [31:0] sp_rom_data, + input RESET, // RESET + input MCLK, // Master Clock (48.0MHz) + input [1:0] HWTYPE, + input [7:0] CTR1, // Control Panel + input [7:0] CTR2, + input [7:0] CTR3, + input [7:0] DSW1, // DipSW + input [7:0] DSW2, + input [8:0] PH, // PIXEL H + input [8:0] PV, // PIXEL V + output PCLK_EN, // PIXEL CLOCK ENABLE + output [7:0] POUT, // PIXEL OUT + output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits) + output [15:0] CPU1ADDR, + input [7:0] CPU1DT, + output [14:0] CPU2ADDR, + input [7:0] CPU2DT, + output [13:0] sp_rom_addr, + input [31:0] sp_rom_data, input sp_rdy, - output [12:0] fg_rom_addr, - input [31:0] fg_rom_data, - output [12:0] bg_rom_addr, - input [31:0] bg_rom_data + output [12:0] fg_rom_addr, + input [31:0] fg_rom_data, + output [13:0] bg_rom_addr, + input [31:0] bg_rom_data, + input [4:0] PALADR, + input PALWR, + input [7:0] PALDAT ); reg [3:0] CLKDIV; @@ -40,19 +45,23 @@ assign PCLK_EN = CLKDIV[2:0] == 3'b111; wire [15:0] CPADR; wire [7:0] CPODT, CPIDT; +wire CPSEL; wire CPRED, CPWRT, VBLK; ninjakun_main ninjakun_main( .RESET(RESET), .MCLK(MCLK), + .HWTYPE(HWTYPE), .VBLK(VBLK), .CTR1(CTR1), .CTR2(CTR2), + .CTR3(CTR3), .CPADR(CPADR), .CPODT(CPODT), .CPIDT(CPIDT), .CPRED(CPRED), .CPWRT(CPWRT), + .CPSEL(CPSEL), .CPU1ADDR(CPU1ADDR), .CPU1DT(CPU1DT), .CPU2ADDR(CPU2ADDR), @@ -68,6 +77,7 @@ wire [8:0] PALET; wire [7:0] SCRPX, SCRPY; ninjakun_io_video ninjakun_io_video( .MCLK(MCLK), + .HWTYPE(HWTYPE), .PCLK_EN(PCLK_EN), .RESET(RESET), .PH(PH), @@ -77,8 +87,11 @@ ninjakun_io_video ninjakun_io_video( .CPIDT(CPIDT), .CPRED(CPRED), .CPWRT(CPWRT), + .CPSEL(CPSEL), .DSW1(DSW1), .DSW2(DSW2), + .CTR1(CTR1), + .CTR2(CTR2), .VBLK(VBLK), .POUT(POUT), .SNDOUT(SNDOUT), @@ -88,7 +101,10 @@ ninjakun_io_video ninjakun_io_video( .fg_rom_addr(fg_rom_addr), .fg_rom_data(fg_rom_data), .bg_rom_addr(bg_rom_addr), - .bg_rom_data(bg_rom_data) + .bg_rom_data(bg_rom_data), + .PALADR(PALADR), + .PALWR(PALWR), + .PALDAT(PALDAT) ); endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_video.v b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_video.v new file mode 100644 index 00000000..89f96486 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/rtl/ninjakun_video.v @@ -0,0 +1,216 @@ +// Copyright (c) 2011,19 MiSTer-X + +module NINJAKUN_VIDEO +( + input RESET, + input MCLK, + input PCLK_EN, + input [1:0] HWTYPE, + + input [8:0] PH, + input [8:0] PV, + + output [8:0] PALAD, // Pixel Output (Palet Index) + + output [9:0] FGVAD, // FG + input [15:0] FGVDT, + + output [9:0] BGVAD, // BG + input [15:0] BGVDT, + input [7:0] BGSCX, + input [7:0] BGSCY, + + output [10:0] SPAAD, // Sprite + input [7:0] SPADT, + + output VBLK, + input DBGPD, // Palet Display (for Debug) + + output [13:0] sp_rom_addr, + input [31:0] sp_rom_data, + input sp_rdy, + output [12:0] fg_rom_addr, + input [31:0] fg_rom_data, + output [13:0] bg_rom_addr, + input [31:0] bg_rom_data +); + +`include "rtl/defs.v" + +assign VBLK = (PV>=193); + +// ROMs +wire SPCFT = sp_rdy; +wire [13:0] SPCAD; +wire [31:0] SPCDT; + +wire [12:0] FGCAD; +wire [31:0] FGCDT; + +wire [13:0] BGCAD; +wire [31:0] BGCDT; + +//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN); +//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN); +//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN); + +assign sp_rom_addr = SPCAD; +assign SPCDT = sp_rom_data; +assign fg_rom_addr = FGCAD; +assign FGCDT = fg_rom_data; + +assign bg_rom_addr = BGCAD; +assign BGCDT = bg_rom_data; + +// Fore-Ground Scanline Generator +wire FGPRI; +wire [8:0] FGOUT; +NINJAKUN_FG fg( + MCLK, PCLK_EN, HWTYPE, + PH, PV, + FGVAD, FGVDT, + FGCAD, FGCDT, + {FGPRI, FGOUT} +); +wire FGOPQ = HWTYPE != `HW_PKUNWAR & (FGOUT[3:0]!=0); +wire FGPPQ = HWTYPE != `HW_PKUNWAR & FGOPQ & (~FGPRI); + +// Back-Ground Scanline Generator +wire [8:0] BGOUT, BGPRI; + +NINJAKUN_BG bg( + MCLK, PCLK_EN, HWTYPE, + PH, PV, + BGSCX, BGSCY, + BGVAD, BGVDT, + BGCAD, BGCDT, + BGOUT, BGPRI +); + +wire BGFRC = BGPRI && BGOUT[3:0] != 0; + +// Sprite Scanline Generator +wire [8:0] SPOUT; + +NINJAKUN_SP sp( + MCLK, PCLK_EN, RESET, (HWTYPE == `HW_PKUNWAR || HWTYPE == `HW_RAIDERS5), + PH, PV, + SPAAD, SPADT, + SPCAD, SPCDT, SPCFT, + SPOUT +); +wire SPOPQ = (SPOUT[3:0]!=0); + +// Palet Display (for Debug) +wire [8:0] PDOUT = (PV[7]|PV[8]) ? 9'd0 : {PV[6:2],PH[7:4]}; + +// Color Mixer +assign PALAD = DBGPD ? PDOUT : + BGFRC ? BGOUT : + FGPPQ ? FGOUT : + SPOPQ ? SPOUT : + FGOPQ ? FGOUT : + BGOUT; + +endmodule + +// ForeGround Scanline Generator +module NINJAKUN_FG +( + input MCLK, + input PCLK_EN, + input [1:0] HWTYPE, + + input [8:0] PH, // CRTC + input [8:0] PV, + + output reg [9:0] FGVAD, // VRAM + input [15:0] FGVDT, + + output reg [12:0] FGCAD, + input [31:0] FGCDT, + + output [9:0] FGOUT // PIXEL OUT : {PRIO,PALNO[8:0]} +); + +wire [8:0] POSH = PH+9'd8+9'd1; +wire [8:0] POSV = PV+9'd32; + +wire [9:0] CHRNO = (HWTYPE == `HW_RAIDERS5 || HWTYPE == `HW_NOVA2001) ? {2'b00, FGVDT[7:0]} : {1'b0,FGVDT[13],FGVDT[7:0]}; +reg [31:0] CDT; + +reg [4:0] PAL; +reg [3:0] OUT; +always @( posedge MCLK ) begin + if (PCLK_EN) + case(POSH[2:0]) + 0: begin OUT <= CDT[7:4] ; PAL <= HWTYPE == `HW_RAIDERS5 ? {1'b0, FGVDT[15:12]} : FGVDT[12:8]; end + 1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end + 2: begin OUT <= CDT[15:12]; end + 3: begin OUT <= CDT[11:8] ; end + 4: begin OUT <= CDT[23:20]; FGCAD <= {CHRNO,POSV[2:0]}; end + 5: begin OUT <= CDT[19:16]; end + 6: begin OUT <= CDT[31:28]; end + 7: begin OUT <= CDT[27:24]; CDT <= FGCDT; end + endcase +end + +assign FGOUT = HWTYPE == `HW_NOVA2001 ? (OUT == 4'h1 ? PAL : { PAL[4], OUT }) : { PAL[4], 1'b0, PAL[3:0], OUT }; + +endmodule + + +// BackGround Scanline Generator +module NINJAKUN_BG +( + input MCLK, + input PCLK_EN, + input [1:0] HWTYPE, + + input [8:0] PH, // CRTC + input [8:0] PV, + + input [7:0] BGSCX, // SCRREG + input [7:0] BGSCY, + + output reg [9:0] BGVAD, // VRAM + input [15:0] BGVDT, + + output reg [13:0] BGCAD, + input [31:0] BGCDT, + + output [8:0] BGOUT, // OUTPUT + output reg BGPRI +); + +wire [8:0] POSH = PH+BGSCX+((HWTYPE == `HW_NOVA2001 || HWTYPE == `HW_PKUNWAR) ? 9'd9 : 9'd2) /* synthesis keep */; +wire [8:0] POSV = PV+BGSCY+9'd32; + +wire [10:0] CHRNO = HWTYPE == `HW_RAIDERS5 ? {2'b10, BGVDT[8:0]} : + HWTYPE == `HW_NOVA2001 ? {3'b110, BGVDT[7:0]}: + HWTYPE == `HW_PKUNWAR ? BGVDT[10:0]: + {1'b1,BGVDT[15:14],BGVDT[7:0]}; +reg [31:0] CDT; + +reg [3:0] PAL; +reg [3:0] OUT; +always @( posedge MCLK ) begin + if (PCLK_EN) + case(POSH[2:0]) + 0: begin OUT <= CDT[7:4] ; + PAL <= (HWTYPE == `HW_RAIDERS5 || HWTYPE == `HW_PKUNWAR) ? BGVDT[15:12] : BGVDT[11:8]; + BGPRI <= HWTYPE == `HW_PKUNWAR && BGVDT[11]; + end + 1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end + 2: begin OUT <= CDT[15:12]; end + 3: begin OUT <= CDT[11:8] ; end + 4: begin OUT <= CDT[23:20]; BGCAD <= {CHRNO,POSV[2:0]}; end + 5: begin OUT <= CDT[19:16]; end + 6: begin OUT <= CDT[31:28]; end + 7: begin OUT <= CDT[27:24]; CDT <= BGCDT; end + endcase +end + +assign BGOUT = HWTYPE[1] ? {1'b1, (OUT == 4'h1 ? PAL : OUT)} : { 1'b1, PAL, OUT }; + +endmodule diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.qip b/Arcade_MiST/Nova2001_Hardware/rtl/pll.qip similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.qip rename to Arcade_MiST/Nova2001_Hardware/rtl/pll.qip diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v b/Arcade_MiST/Nova2001_Hardware/rtl/pll.v similarity index 88% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v rename to Arcade_MiST/Nova2001_Hardware/rtl/pll.v index 2ce015c4..fb6269e6 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v +++ b/Arcade_MiST/Nova2001_Hardware/rtl/pll.v @@ -39,23 +39,27 @@ module pll ( inclk0, c0, + c1, locked); input inclk0; output c0; + output c1; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire5 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; wire locked = sub_wire2; - wire sub_wire3 = inclk0; - wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( - .inclk (sub_wire4), + .inclk (sub_wire5), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -96,8 +100,12 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 16, + altpll_component.clk0_multiply_by = 32, altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 16, + altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -131,7 +139,7 @@ module pll ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", @@ -172,8 +180,11 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -194,18 +205,26 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -228,19 +247,26 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -273,7 +299,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" @@ -292,11 +318,13 @@ endmodule // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv b/Arcade_MiST/Nova2001_Hardware/rtl/sdram.sv similarity index 97% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv rename to Arcade_MiST/Nova2001_Hardware/rtl/sdram.sv index ed64b325..60ad31c7 100644 --- a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Nova2001_Hardware/rtl/sdram.sv @@ -65,9 +65,11 @@ module sdram ( output reg [31:0] fg_q, input [16:2] sp_addr, output reg [31:0] sp_q, - output reg sp_rdy + output sp_rdy ); +parameter MHZ = 80; // 80 MHz default clock, adjust to calculate the refresh rate correctly + localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved @@ -78,7 +80,7 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; // 64ms/8192 rows = 7.8us -> 842 cycles@108MHz -localparam RFRSH_CYCLES = 10'd842; +localparam RFRSH_CYCLES = 16'd78*MHZ/10; // --------------------------------------------------------------------- // ------------------------ cycle state machine ------------------------ @@ -222,6 +224,9 @@ always @(*) begin end end +assign sp_rdy = |sp_rdy_r; +reg [1:0] sp_rdy_r; + always @(posedge clk) begin // permanently latch ram data to reduce delays @@ -231,7 +236,7 @@ always @(posedge clk) begin sd_cmd <= CMD_NOP; // default: idle refresh_cnt <= refresh_cnt + 1'd1; - sp_rdy <= 0; + sp_rdy_r <= {sp_rdy_r[0], 1'b0}; if(init) begin // initialization takes place at the end of the reset phase @@ -357,7 +362,7 @@ always @(posedge clk) begin PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end PORT_FG : begin fg_q[31:16] <= sd_din; end PORT_BG : begin bg_q[31:16] <= sd_din; end - PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy <= 1; end + PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy_r <= 2'b11; end default: ; endcase; end diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/spram.vhd b/Arcade_MiST/Nova2001_Hardware/rtl/spram.vhd similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/spram.vhd rename to Arcade_MiST/Nova2001_Hardware/rtl/spram.vhd diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v b/Arcade_MiST/Nova2001_Hardware/rtl/z80ip.v similarity index 100% rename from Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v rename to Arcade_MiST/Nova2001_Hardware/rtl/z80ip.v diff --git a/common/mist/mist.qip b/common/mist/mist.qip index 46cde4bc..de360210 100644 --- a/common/mist/mist.qip +++ b/common/mist/mist.qip @@ -5,6 +5,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_vi set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_inputs.v] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.v] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd] diff --git a/common/mist/mist_video.v b/common/mist/mist_video.v index a0142aba..39774525 100644 --- a/common/mist/mist_video.v +++ b/common/mist/mist_video.v @@ -166,25 +166,26 @@ cofi cofi ( .blue_out( cofi_b ) ); -wire [5:0] y, pb, pr; +wire hs, vs; -rgb2ypbpr rgb2ypbpr +RGBtoYPbPr #(6) rgb2ypbpr ( - .red ( cofi_r ), - .green ( cofi_g ), - .blue ( cofi_b ), - .y ( y ), - .pb ( pb ), - .pr ( pr ) + .clk ( clk_sys ), + .ena ( ypbpr ), + + .red_in ( cofi_r ), + .green_in ( cofi_g ), + .blue_in ( cofi_b ), + .hs_in ( cofi_hs ), + .vs_in ( cofi_vs ), + .red_out ( VGA_R ), + .green_out ( VGA_G ), + .blue_out ( VGA_B ), + .hs_out ( hs ), + .vs_out ( vs ) ); -assign VGA_R = ypbpr?pr:cofi_r; -assign VGA_G = ypbpr? y:cofi_g; -assign VGA_B = ypbpr?pb:cofi_b; - -wire cs = SYNC_AND ? (cofi_hs & cofi_vs) : ~(cofi_hs ^ cofi_vs); -wire hs = cofi_hs; -wire vs = cofi_vs; +wire cs = SYNC_AND ? (hs & vs) : ~(hs ^ vs); // a minimig vga->scart cable expects a composite sync signal on the VGA_HS output. // and VCC on VGA_VS (to switch into rgb mode) diff --git a/common/mist/rgb2ypbpr.sv b/common/mist/rgb2ypbpr.sv deleted file mode 100644 index 1e1662e8..00000000 --- a/common/mist/rgb2ypbpr.sv +++ /dev/null @@ -1,55 +0,0 @@ -module rgb2ypbpr ( - input [5:0] red, - input [5:0] green, - input [5:0] blue, - - output [5:0] y, - output [5:0] pb, - output [5:0] pr -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign pr = yuv_full[pr_i - 8'd16]; -assign y = yuv_full[y_i - 8'd16]; -assign pb = yuv_full[pb_i - 8'd16]; - -endmodule diff --git a/common/mist/rgb2ypbpr.v b/common/mist/rgb2ypbpr.v new file mode 100644 index 00000000..ee3afc1a --- /dev/null +++ b/common/mist/rgb2ypbpr.v @@ -0,0 +1,103 @@ +// Multiplier-based RGB -> YPbPr conversion + +// Copyright 2020/2021 by Alastair M. Robinson + +module RGBtoYPbPr +( + input clk, + input ena, + + input [WIDTH-1:0] red_in, + input [WIDTH-1:0] green_in, + input [WIDTH-1:0] blue_in, + input hs_in, + input vs_in, + input cs_in, + input pixel_in, + + output [WIDTH-1:0] red_out, + output [WIDTH-1:0] green_out, + output [WIDTH-1:0] blue_out, + output reg hs_out, + output reg vs_out, + output reg cs_out, + output reg pixel_out +); + +parameter WIDTH = 8; + +reg [8+WIDTH-1:0] r_y; +reg [8+WIDTH-1:0] g_y; +reg [8+WIDTH-1:0] b_y; + +reg [8+WIDTH-1:0] r_b; +reg [8+WIDTH-1:0] g_b; +reg [8+WIDTH-1:0] b_b; + +reg [8+WIDTH-1:0] r_r; +reg [8+WIDTH-1:0] g_r; +reg [8+WIDTH-1:0] b_r; + +reg [8+WIDTH-1:0] y; +reg [8+WIDTH-1:0] b; +reg [8+WIDTH-1:0] r; + +reg hs_d; +reg vs_d; +reg cs_d; +reg pixel_d; + +assign red_out = r[8+WIDTH-1:8]; +assign green_out = y[8+WIDTH-1:8]; +assign blue_out = b[8+WIDTH-1:8]; + +// Multiply in the first stage... +always @(posedge clk) begin + hs_d <= hs_in; // Register sync, pixel clock, etc + vs_d <= vs_in; // so they're delayed the same amount as the incoming video + cs_d <= cs_in; + pixel_d <= pixel_in; + + if(ena) begin + // (Y = 0.299*R + 0.587*G + 0.114*B) + r_y <= red_in * 8'd76; + g_y <= green_in * 8'd150; + b_y <= blue_in * 8'd29; + + // (Pb = -0.169*R - 0.331*G + 0.500*B) + r_b <= red_in * 8'd43; + g_b <= green_in * 8'd84; + b_b <= blue_in * 8'd128; + + // (Pr = 0.500*R - 0.419*G - 0.081*B) + r_r <= red_in * 8'd128; + g_r <= green_in * 8'd107; + b_r <= blue_in * 8'd20; + end else begin + r_r[8+WIDTH-1:8] <= red_in; // Passthrough + g_y[8+WIDTH-1:8] <= green_in; + b_b[8+WIDTH-1:8] <= blue_in; + end + +end + +// Second stage - adding + +always @(posedge clk) begin + hs_out <= hs_d; + vs_out <= vs_d; + cs_out <= cs_d; + pixel_out <= pixel_d; + + if(ena) begin + y <= r_y + g_y + b_y; + b <= 2'd2**(8+WIDTH-1) + b_b - r_b - g_b; + r <= 2'd2**(8+WIDTH-1) + r_r - g_r - b_r; + end else begin + y <= g_y; // Passthrough + b <= b_b; + r <= r_r; + end +end + +endmodule