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https://github.com/Gehstock/Mist_FPGA.git
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Update ToaplanV1_Top.sv
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Marcel
@@ -53,14 +53,20 @@ module ToaplanV1_Top(
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output SDRAM_nWE
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);
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//// INPUT
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//
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//
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//
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//wire tile_priority_type;
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// CoreMod Game
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// 0 Demons World
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// 1 Rally Bike
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// 2 Vimana
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// 3 Same! Same! Same!
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// 4 Zerowing
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// 5 Truxton
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// 6 Out Zone
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// 7 Out Zone Conversation
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// 8 HellFire
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wire tile_priority_type;
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wire [15:0] scroll_y_offset;
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wire [15:0] scroll_x_offset = 30;
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reg [7:0] p1;
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reg [7:0] p2;
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reg [7:0] z80_dswa;
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@@ -73,7 +79,8 @@ always @ (posedge clk_sys ) begin
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p1 <= { 1'b0, p1_in[6:4], p1_in[3], p1_in[2], p1_in[1], p1_in[0] };
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p2 <= { 1'b0, p2_in[6:4], p2_in[3], p2_in[2], p2_in[1], p2_in[0] };
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case (core_mod)
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0,1: begin
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0,1: begin //Demons World, Rally Bike
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z80_dswa <= sw0;
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z80_dswb <= sw1;
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z80_tjump <= sw2;
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@@ -83,8 +90,7 @@ case (core_mod)
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system <= { vblank, start[1], start[0], coin[1], coin[0], service, key_tilt, key_service };
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end
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end
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2,3: begin
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2,3: begin //Vimana, Same Same Same
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z80_dswa <= sw0;
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z80_tjump <= sw2;
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if ( scrollDBG == 1 ) begin
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@@ -95,7 +101,7 @@ case (core_mod)
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system <= { vblank, start[1], start[0], coin[1], coin[0], service, key_tilt, key_service };
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end
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end
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4,5,6,7,8: begin
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4,5,6,7,8: begin
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z80_tjump <= sw2;
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if ( core_mod == 4 || core_mod == 6 || core_mod == 7 || core_mod == 8 && scrollDBG == 1 ) begin
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// zerowing, hellfire, outzone, outzone conversion debug options
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@@ -118,7 +124,7 @@ endcase
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end
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//demon
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reg clk_3_5M, clk_7M, clk_10M, clk_14M, clk_14M_N;
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reg [5:0] clk14_count;
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@@ -210,8 +216,6 @@ wire flip = 0;
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reg tile_flip;
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reg sprite_flip;
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//assign vc = vcx - vs_offset;
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// ===============================================================
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// 68000 CPU
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// ===============================================================
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@@ -244,7 +248,7 @@ reg [15:0] cpu_din;
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// CPU inputs
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reg dtack_n; // Data transfer ack (always ready)
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reg ipl2_n;
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reg ipl1_n, ipl2_n;
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wire reset_n;
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wire vpa_n = ~ ( cpu_lds_n == 0 && cpu_fc == 3'b111 ); // from outzone schematic
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@@ -287,7 +291,8 @@ fx68k fx68k (
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.BGACKn(1'b1),
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.IPL0n(1'b1),
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.IPL1n(1'b1),
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// .IPL1n(1'b1),
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.IPL1n((core_mod == 2 | core_mod == 3) ? ipl1_n : 1'b1),
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.IPL2n(ipl2_n),
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// busses
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@@ -296,30 +301,52 @@ fx68k fx68k (
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.eab(cpu_a[23:1])
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);
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////////////////////////////////////////////////////
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//Progress here
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//todo
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//
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//add Vimana HW
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////////////////////////////////////////////////////
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always @ (posedge clk_sys) begin
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if ( clk_10M == 1 ) begin
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// tell 68k to wait for valid data. 0=ready 1=wait
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// always ack when it's not program rom
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dtack_n <= prog_rom_cs ? !prog_rom_data_valid : 0;
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// add dsp_ctrl_cs to cpu_din
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// select cpu data input based on what is active
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cpu_din <= prog_rom_cs ? prog_rom_data :
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ram_cs ? ram_dout :
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if (core_mod == 1) begin
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cpu_din <= prog_rom_cs ? prog_rom_data :
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m68k_ram_cs ? ram_dout :// ram_cs
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tile_palette_cs ? tile_palette_cpu_dout :
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sprite_palette_cs ? sprite_palette_cpu_dout :
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shared_ram_cs ? cpu_shared_dout :
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tile_ofs_cs ? curr_tile_ofs :
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sprite_ofs_cs ? curr_sprite_ofs :
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tile_attr_cs ? cpu_tile_dout_attr :
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tile_num_cs ? cpu_tile_dout_num :
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sprite_0_cs ? sprite_0_dout :
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sprite_1_cs ? sprite_1_dout :
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sprite_2_cs ? sprite_2_dout :
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sprite_3_cs ? sprite_3_dout :
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sprite_size_cs ? sprite_size_cpu_dout :
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frame_done_cs ? { 16 { vblank } } : // get vblank state
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vblank_cs ? { 15'b0, vblank } :
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int_en_cs ? 16'hffff :
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16'd0;
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vblank_cs ? { 15'b0, vblank } :
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tile_attr_cs ? ( cpu_tile_dout_attr | { 4'b0, cpu_tile_dout_attr[15:12], cpu_tile_dout_attr[5:4], 6'b0 } ) :
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sprite_ram_cs ? sprite_ram_dout :
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int_en_cs ? { 15'b0, int_en } : 16'hffff;
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end else begin
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cpu_din <= prog_rom_cs ? prog_rom_data :
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m68k_ram_cs ? ram_dout :
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tile_palette_cs ? tile_palette_cpu_dout :
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sprite_palette_cs ? sprite_palette_cpu_dout :
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shared_ram_cs ? cpu_shared_dout :
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tile_ofs_cs ? curr_tile_ofs :
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sprite_ofs_cs ? curr_sprite_ofs :
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tile_attr_cs ? cpu_tile_dout_attr :
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vblank_cs ? { 15'b0, vblank } :
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tile_num_cs ? cpu_tile_dout_num :
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sprite_0_cs ? sprite_0_dout :
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sprite_1_cs ? sprite_1_dout :
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sprite_2_cs ? sprite_2_dout :
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sprite_3_cs ? sprite_3_dout :
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sprite_size_cs ? sprite_size_cpu_dout :
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frame_done_cs ? { 16 { vblank } } : // get vblank state
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int_en_cs ? 16'hffff : 16'hffff;
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end
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end
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end
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