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Marcel
2020-08-19 16:39:15 +02:00
parent 1a359b445a
commit 8661efc57a
26 changed files with 350 additions and 3 deletions
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1
common/CPU/MC6809/mc6809.qip
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@@ -1,4 +1,5 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu09.vhd ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809i.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809e.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809is.v ]

48
common/CPU/MC6809/mc6809e.v Normal file
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@@ -0,0 +1,48 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:11:34 09/23/2016
// Design Name:
// Module Name: mc6809e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809e(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
input E,
input Q,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
output AVMA,
output BUSY,
output LIC,
input nHALT,
input nRESET
);
mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1)
);
endmodule