From 86e1134ddd11b598f2ffe5b5e675fc8c0118a71f Mon Sep 17 00:00:00 2001 From: Marcel Date: Sun, 18 Aug 2019 12:19:00 +0200 Subject: [PATCH] Some Work on King & Balloon --- .../Z80 Based/KingBaloon_MiST/KingBaloon.qsf | 86 +- .../Z80 Based/KingBaloon_MiST/README.txt | 2 +- .../KingBaloon_MiST/Release/KingBaloon.rbf | Bin 307181 -> 333436 bytes .../KingBaloon_MiST/rtl/KingBalloon_MiST.sv | 19 +- .../Z80 Based/KingBaloon_MiST/rtl/ROM/col.hex | 3 - .../Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd | 24 + .../Z80 Based/KingBaloon_MiST/rtl/ROM/h.hex | 129 --- .../Z80 Based/KingBaloon_MiST/rtl/ROM/k.hex | 129 --- .../KingBaloon_MiST/rtl/ROM/kbe1-4.vhd | 150 +++ .../KingBaloon_MiST/rtl/ROM/kbe1.ic4 | Bin 0 -> 2048 bytes .../KingBaloon_MiST/rtl/ROM/kbe2-5.vhd | 150 +++ .../KingBaloon_MiST/rtl/ROM/kbe2.ic5 | Bin 0 -> 2048 bytes .../KingBaloon_MiST/rtl/ROM/kbe2.ic7 | Bin 0 -> 2048 bytes .../KingBaloon_MiST/rtl/ROM/kbe3-6.vhd | 150 +++ .../KingBaloon_MiST/rtl/ROM/kbe3.ic6 | Bin 0 -> 2048 bytes .../KingBaloon_MiST/rtl/ROM/prog.hex | 769 -------------- .../KingBaloon_MiST/rtl/ROM/prog.vhd | 790 ++++++++++++++ .../KingBaloon_MiST/rtl/ROM/rom_h.vhd | 278 +++++ .../KingBaloon_MiST/rtl/ROM/rom_k.vhd | 278 +++++ .../KingBaloon_MiST/rtl/ROM/sound.vhd | 534 ++++++++++ .../KingBaloon_MiST/rtl/kb_synth.vhd | 160 +++ .../KingBaloon_MiST/rtl/kingballon.vhd | 71 +- .../KingBaloon_MiST/rtl/mc_col_pal.vhd | 12 +- .../KingBaloon_MiST/rtl/mc_video.vhd | 28 +- .../Z80 Based/KingBaloon_MiST/rtl/sprom.vhd | 82 -- .../KingBaloon_MiST/rtl/ttl_74138.vhd | 48 + .../KingBaloon_MiST/rtl/ttl_74273.vhd | 136 +++ .../KingBaloon_MiST/rtl/ttl_74367.vhd | 122 +++ Computer_MiST/Laser310_MiST/Laser310_MiST.qsf | 1 + .../Laser310_MiST/rtl/LASER310_TOP.v | 136 ++- .../Laser310_MiST/rtl/Laser310_MiST.sv | 2 +- Computer_MiST/Laser310_MiST/rtl/fdc.v | 967 ++++++++++++++++++ 32 files changed, 4012 insertions(+), 1244 deletions(-) delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.hex create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/h.hex delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/k.hex create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1.ic4 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2-5.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2.ic5 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2.ic7 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3.ic6 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.hex create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sprom.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd create mode 100644 Computer_MiST/Laser310_MiST/rtl/fdc.v diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf index 77aee543..0dd7647f 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf @@ -18,7 +18,7 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:42:52 March 10, 2019 +# Date created = 21:14:56 August 16, 2019 # # -------------------------------------------------------------------------- # # @@ -46,41 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/KingBalloon_MiST.sv -set_global_assignment -name VHDL_FILE rtl/kingballon.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd # Pin & Location Assignments # ========================== @@ -175,10 +140,55 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(KingBalloon_MiST) -# ---------------------------- \ No newline at end of file +# ---------------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/KingBalloon_MiST.sv +set_global_assignment -name VHDL_FILE rtl/kingballon.vhd +set_global_assignment -name VHDL_FILE rtl/kb_synth.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_h.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_k.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd +set_global_assignment -name VHDL_FILE "rtl/ROM/kbe1-4.vhd" +set_global_assignment -name VHDL_FILE "rtl/ROM/kbe2-5.vhd" +set_global_assignment -name VHDL_FILE "rtl/ROM/kbe3-6.vhd" +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_74138.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_74273.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_74367.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt index d3a83bb6..7c62e33e 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt @@ -23,4 +23,4 @@ --------------------------------------------------------------------------------- -ToDo: Change Sound and add Speech \ No newline at end of file +ToDo: add Speech \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf index 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localparam CONF_STR = { "King and Ball.;;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", + "T5,Reset;", + "V,v1.20.",`BUILD_DATE }; @@ -69,8 +70,8 @@ wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; +wire [7:0] audio_a, audio_b, audio_c; +wire [10:0] audio = {audio_c, 3'b0} + {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); @@ -80,7 +81,7 @@ kingballoon kingballoon( .W_CLK_18M(clk_18), .W_CLK_12M(clk_12), .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), + .I_RESET(status[0] | status[5] | buttons[1]), .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_down,m_up,m_left,m_right}), .P2_CSJUDLR({status[1],btn_two_players,m_fire,m_down,m_up,m_left,m_right}), .W_R(r), @@ -89,9 +90,10 @@ kingballoon kingballoon( .W_H_SYNC(hs), .W_V_SYNC(vs), .HBLANK(hb), - .VBLANK(vb), + .VBLANK(vb), .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) + .W_SDAT_B(audio_b), + .W_SDAT_C(audio_c) ); video_mixer video_mixer( @@ -156,7 +158,7 @@ wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; +//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; reg btn_one_player = 0; reg btn_two_players = 0; @@ -166,7 +168,7 @@ reg btn_down = 0; reg btn_up = 0; reg btn_fire1 = 0; reg btn_fire2 = 0; -reg btn_fire3 = 0; +//reg btn_fire3 = 0; reg btn_coin = 0; wire pressed = ps2_key[9]; wire [7:0] code = ps2_key[7:0]; @@ -183,7 +185,6 @@ always @(posedge clk_24) begin 'h76: btn_coin <= pressed; // ESC 'h05: btn_one_player <= pressed; // F1 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl 'h11: btn_fire2 <= pressed; // alt 'h29: btn_fire1 <= pressed; // Space endcase diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.hex deleted file mode 100644 index 76f86dc6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.hex +++ /dev/null @@ -1,3 +0,0 @@ -:100000000017C7F60017C03F0007C03F00C0C40775 -:1000100000C731170031C73F00F607F0003F07C4A3 -:00000001FF diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd new file mode 100644 index 00000000..be83394e --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity col is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of col is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"D8",X"F0",X"07",X"00",X"3F",X"F6",X"07",X"00",X"F6",X"38",X"07",X"00",X"3F",X"38",X"2F", + X"00",X"2F",X"38",X"3F",X"00",X"07",X"38",X"F6",X"00",X"3F",X"16",X"F0",X"00",X"38",X"2F",X"F0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/h.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/h.hex deleted file mode 100644 index 9d1685a7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000387CC282867C38000202FEFE420200007A -:1000100062F2BA9A9ECE46008CDEF2B2928604005C -:1000200008FEFEC8683818001CBEA2A2A2E6E400C2 -:100030000C9E9292D27E3C00C0E0B09E8EC0C0006A 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/dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity kbe1_IC4 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of kbe1_IC4 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"FF",X"FF",X"2D",X"20",X"FD",X"25",X"20",X"FA",X"DB",X"00",X"FE",X"F0",X"28",X"FA",X"3E", + X"10",X"3D",X"20",X"FD",X"DB",X"00",X"FE",X"F0",X"28",X"EF",X"FE",X"F1",X"20",X"25",X"21",X"80", + X"01",X"01",X"4F",X"06",X"DD",X"21",X"2A",X"00",X"18",X"4C",X"06",X"02",X"21",X"FF",X"FF",X"2D", + X"20",X"FD",X"25",X"20",X"05",X"05",X"20",X"02",X"18",X"CF",X"DB",X"00",X"FE",X"F1",X"28",X"EF", + X"C3",X"09",X"00",X"FE",X"F2",X"C2",X"5B",X"00",X"21",X"50",X"06",X"01",X"8F",X"10",X"DD",X"21", + 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X"6B",X"03",X"12",X"A9",X"FC",X"F5",X"90",X"31",X"3A",X"BF",X"DF",X"69",X"12",X"02",X"9B",X"FD", + X"F7",X"A1",X"30",X"57",X"DF",X"FF",X"8A",X"03",X"05",X"8E",X"FF",X"D9",X"60",X"10",X"78",X"FF", + X"F9",X"A3",X"20",X"09",X"9F",X"DF",X"5B",X"03",X"02",X"7C",X"06",X"F8",X"90",X"20",X"06",X"EF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1.ic4 b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1.ic4 new file mode 100644 index 0000000000000000000000000000000000000000..d44b09ac702745789de7bfcd37c8a8a286298951 GIT binary patch literal 2048 zcmd^9jZYlc5nmu225~%UMTw(S^<5GYk|?!_Q(Gc&aARY|u0Mzq4u7?07qbV{4mb_B zyCgBF4)@+JxS-nRcGn-A6$ftjoKUqz!AA*BsA^-Hp4BL>QimL>QpZ)=@D4B>2Y0Wt z*s9dOp>xu2XJ&uzH?#LN<7Dh9N3y_?xWT1pVdDAxwT|SXJCTYx3Y^VpY1?gM&L_BK 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kbe2_IC5 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"97",X"01",X"05",X"8F",X"FF",X"DB",X"30",X"00",X"68",X"FF",X"FB",X"C2",X"30",X"36",X"AF", + X"FE",X"C8",X"42",X"03",X"5D",X"DF",X"CF",X"55",X"02",X"37",X"ED",X"FC",X"E3",X"30",X"14",X"BF", + X"FF",X"E8",X"50",X"00",X"5D",X"EF",X"CF",X"45",X"01",X"27",X"EE",X"FC",X"C4",X"40",X"14",X"AF", + X"FF",X"F6",X"60",X"11",X"6C",X"EF",X"EC",X"63",X"11",X"39",X"DF",X"FF",X"67",X"02",X"07",X"CF", + X"FF",X"C5",X"30",X"13",X"9C",X"FE",X"F5",X"60",X"11",X"7D",X"FF",X"FB",X"61",X"00",X"4A",X"EF", + X"FF",X"44",X"01",X"38",X"DF",X"FF",X"85",X"00",X"06",X"CF",X"FF",X"E4",X"20",X"02",X"9F",X"FF", + X"F7",X"60",X"00",X"6C",X"FF",X"FE",X"52",X"00",X"27",X"FF",X"FF",X"77",X"00",X"05",X"CF",X"FF", + X"E6",X"10",X"03",X"8F",X"FF",X"F6",X"50",X"00",X"5C",X"FF",X"FB",X"60",X"00",X"5A",X"FF",X"FF", + X"45",X"01",X"27",X"DF",X"FF",X"85",X"00",X"05",X"BF",X"FF",X"F5",X"20",X"02",X"8E",X"FF",X"F9", + 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X"66",X"67",X"78",X"AB",X"BA",X"A8",X"76",X"66",X"66",X"78",X"87",X"77",X"79",X"CD",X"DC",X"DA", + X"85",X"56",X"67",X"8B",X"BB",X"A9",X"76",X"55",X"77",X"9B",X"DC",X"BA",X"87",X"55",X"56",X"67", + X"89",X"98",X"87",X"8B",X"CC",X"BC",X"B8",X"65",X"66",X"78",X"BC",X"BA",X"98",X"66",X"57",X"89", + X"9B",X"CB",X"A8",X"87",X"66",X"67",X"77",X"78",X"78",X"77",X"AC",X"DC",X"CC",X"A8",X"56",X"67", + X"78",X"BB",X"A8",X"87",X"76",X"78",X"99",X"9B",X"BA",X"87",X"77",X"66",X"78",X"88",X"78",X"87", + X"66",X"8C",X"DC",X"BC",X"B9",X"65",X"67",X"88",X"AB",X"A9",X"87",X"77",X"67",X"89",X"AA",X"AA", + X"A8",X"88",X"87",X"67",X"77",X"66",X"78",X"88",X"79",X"CD",X"CA",X"BA",X"96",X"56",X"78",X"79", + X"AA",X"98",X"88",X"87",X"77",X"88",X"89",X"9A",X"AA",X"99",X"87",X"66",X"66",X"66",X"78",X"99", + X"89",X"AB",X"BB",X"AA",X"98",X"66",X"77",X"88",X"9A",X"A9",X"88",X"88",X"77",X"89",X"99",X"99"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2.ic5 b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2.ic5 new file mode 100644 index 0000000000000000000000000000000000000000..9e3c161bc257073e3c1a0969de926383f075c0d5 GIT binary patch literal 2048 zcmb7ETTmNS7!EMiS19;SfznqB2~?jfY=G)Zh22e|b_OYXp{+Ao%;`CO94pBtz>Cw8O@JA#mE6da(-sJMP^(<`sa443cy`muILTh^2z-3p0XPt^MUCd4Io9Q(!gnYEeU?EEWQhV?=f8g`3}&lw%SpCP21`%zm(n{sP0PU zhN{|=y31_-fzE!~3_05utNYX0p{lmU{DXSSN49QKzybQ(#Vr~K-3`d7C$`cOSan7$w3@6KiAj%TUc@#(${VGpVo{*0x zAplW0B?#~{IIQUL@vPwS8FYzdMWrwnSV7i_2Kyf!i~y&NPFFGvfrn(d;AcdEx`&)Y zi2~p7DLCp1dZ?F@1>4{Yq5&8B!cq#7dZ1Ty-O*^G-oF$&G@&KxWMj+v|GzXt{#B@d zcQB&JBstL^(%(b@QY98ztgM7oeHJ?SL#o%!^MWA=WuP=9)2>h~ zsN+!7F%by)1fJ&^hLuAxRpwxW;bk=%lz0K!Fj^=YoHkS_9iP_~Ik+-8wizeeiXe+mx z+5Z}E6M~UxqM_--rQOG0UZh6Ck+F*n?W4(!>8mYtARZa&sOq|#&OQ97nTutgI2(?( z1#$&F}hf zX*=ey;gt2bpn;eZX&Q{J!R*Ewj>`b7+0Biv)Vhzstccm8!Ev?4lS=s*D~6&YNs!?i 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Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd new file mode 100644 index 00000000..e4647eaf --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity kbe3_IC6 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of kbe3_IC6 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"A9",X"99",X"98",X"87",X"76",X"66",X"66",X"78",X"9A",X"BC",X"CB",X"A9",X"87",X"66",X"68",X"99", + X"AA",X"A9",X"87",X"77",X"77",X"89",X"AA",X"99",X"98",X"88",X"99",X"88",X"77",X"66",X"67",X"78", + X"89",X"AB",X"CB",X"AA",X"98",X"77",X"78",X"89",X"9A",X"99",X"88",X"88",X"88",X"89",X"99",X"98", + X"88",X"88",X"88",X"99",X"99",X"87",X"76",X"66",X"77",X"89",X"AA",X"BB",X"B9",X"98",X"77",X"77", + X"89",X"9A",X"99",X"98",X"77",X"78",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"87",X"66", + X"77",X"78",X"99",X"9A",X"AA",X"A9",X"98",X"88",X"78",X"88",X"99",X"99",X"98",X"88",X"88",X"89", + X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",X"87",X"77",X"78",X"88",X"88",X"99",X"9A",X"AA", + X"99",X"88",X"77",X"78",X"99",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"88", + X"89",X"99",X"99",X"98",X"87",X"77",X"77",X"78",X"89",X"99",X"AA",X"AA",X"98",X"87",X"77",X"78", + X"88",X"88",X"88",X"98",X"88",X"88",X"99",X"98",X"88",X"87",X"89",X"AA",X"A9",X"76",X"66",X"8C", + X"EC",X"96",X"44",X"68",X"DF",X"D8",X"63",X"46",X"8D",X"FC",X"76",X"43",X"7A",X"9D",X"D9",X"67", + X"44",X"8A",X"8D",X"D9",X"66",X"35",X"A9",X"BE",X"B6",X"65",X"48",X"B8",X"DC",X"96",X"64",X"69", + X"9A",X"EC",X"86",X"54",X"8B",X"8D",X"D8",X"56",X"46",X"A9",X"BE",X"A6",X"64",X"5A",X"A7",X"EB", + X"77",X"64",X"7B",X"7D",X"E8",X"57",X"37",X"C8",X"AF",X"95",X"74",X"4A",X"A9",X"FA",X"46",X"64", + X"BB",X"5F",X"D5",X"58",X"37",X"C6",X"EF",X"63",X"84",X"7D",X"6A",X"F9",X"37",X"56",X"B7",X"BF", + X"83",X"66",X"8D",X"59",X"F9",X"45",X"78",X"C5",X"BF",X"75",X"65",X"9C",X"3A",X"F7",X"47",X"6A", + X"C2",X"CF",X"63",X"84",X"AC",X"3D",X"F4",X"27",X"7B",X"A4",X"FE",X"42",X"68",X"BA",X"9F",X"93", + X"26",X"BD",X"4B",X"F8",X"33",X"5B",X"C6",X"FC",X"44",X"56",X"E7",X"5F",X"C4",X"35",X"7C",X"5C", + X"F7",X"46",X"4A",X"B2",X"FE",X"54",X"77",X"B5",X"7F",X"95",X"56",X"9B",X"2F",X"D5",X"47",X"9D", + X"55",X"F8",X"25",X"8A",X"B5",X"FA",X"43",X"69",X"E6",X"9F",X"73",X"47",X"DA",X"4F",X"A5",X"52", + X"5F",X"8E",X"E3",X"47",X"5B",X"78",X"F8",X"35",X"48",X"D5",X"FF",X"54",X"44",X"B9",X"CF",X"42", + X"87",X"97",X"7F",X"B3",X"45",X"6D",X"7F",X"C5",X"75",X"4A",X"6F",X"F4",X"17",X"88",X"47",X"FA", + X"35",X"48",X"B6",X"FC",X"55",X"78",X"93",X"FE",X"64",X"67",X"B5",X"CF",X"48",X"55",X"B9",X"6F", + X"64",X"57",X"9A",X"5F",X"91",X"64",X"6D",X"3F",X"F0",X"34",X"7C",X"58",X"F6",X"53",X"2A",X"A4", + X"F8",X"37",X"49",X"A1",X"FF",X"46",X"47",X"C5",X"AF",X"67",X"47",X"C6",X"5F",X"96",X"54",X"BB", + X"0F",X"F2",X"81",X"3F",X"82",X"F9",X"64",X"1C",X"D1",X"AF",X"7E",X"00",X"FE",X"1F",X"A7",X"D0", + X"4F",X"4A",X"F2",X"D0",X"0F",X"90",X"F8",X"CC",X"08",X"E3",X"FF",X"2F",X"00",X"F9",X"2F",X"8E", + X"D0",X"8B",X"5B",X"F2",X"F0",X"2E",X"83",X"F8",X"F6",X"0A",X"A6",X"FF",X"3F",X"02",X"EB",X"4F", + X"9E",X"A0",X"89",X"5F",X"F1",X"F0",X"0C",X"B5",X"FB",X"8E",X"08",X"95",X"BF",X"6E",X"60",X"9A", + X"5F",X"F3",X"F0",X"28",X"4E",X"F6",X"9B",X"0A",X"87",X"8F",X"8F",X"10",X"95",X"BF",X"F2",X"F1", + X"0B",X"8C",X"8D",X"AF",X"05",X"78",X"CF",X"99",X"60",X"DA",X"C5",X"C8",X"F0",X"08",X"4D",X"DF", + X"8C",X"07",X"8F",X"48",X"DC",X"D0",X"90",X"D5",X"FE",X"64",X"0A",X"DA",X"2F",X"5F",X"40",X"83", + X"6C",X"FF",X"C0",X"0F",X"79",X"DB",X"4F",X"07",X"60",X"BF",X"F3",X"F0",X"97",X"DA",X"D5",X"CB", + X"0F",X"0D",X"6F",X"9E",X"40",X"77",X"F3",X"F7",X"F3",X"37",X"4B",X"5F",X"5F",X"00",X"9B",X"87", + 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Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd new file mode 100644 index 00000000..8f7b15f4 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd @@ -0,0 +1,790 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prog is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"22",X"13",X"00",X"3A",X"2F",X"43",X"11",X"30",X"43",X"18",X"3B", + X"4F",X"EB",X"21",X"60",X"40",X"C3",X"EF",X"01",X"E1",X"5E",X"23",X"56",X"23",X"C3",X"5D",X"00", + X"85",X"6F",X"30",X"01",X"24",X"7E",X"C9",X"00",X"87",X"E3",X"E7",X"5F",X"23",X"56",X"EB",X"E9", + X"E1",X"5E",X"23",X"56",X"23",X"4E",X"23",X"3E",X"C7",X"46",X"23",X"C6",X"59",X"91",X"C5",X"06", + X"00",X"ED",X"B0",X"4F",X"EB",X"09",X"EB",X"C1",X"10",X"F4",X"E9",X"EB",X"85",X"6F",X"D6",X"2C", + X"E6",X"7F",X"32",X"2F",X"43",X"71",X"2C",X"70",X"2C",X"73",X"2C",X"72",X"C9",X"ED",X"53",X"00", + X"43",X"E9",X"2A",X"00",X"43",X"E9",X"08",X"D9",X"DD",X"E5",X"FD",X"E5",X"3A",X"00",X"78",X"AF", + X"32",X"01",X"70",X"32",X"3E",X"58",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"21",X"C8", + X"42",X"11",X"06",X"58",X"06",X"04",X"AF",X"96",X"12",X"1C",X"1C",X"12",X"1C",X"1C",X"2C",X"10", + X"F5",X"3A",X"D7",X"42",X"ED",X"44",X"11",X"36",X"58",X"06",X"03",X"12",X"1C",X"1C",X"10",X"FB", + X"3A",X"08",X"43",X"4F",X"3A",X"03",X"43",X"A1",X"4F",X"21",X"70",X"42",X"11",X"40",X"58",X"06", + X"08",X"2C",X"78",X"FE",X"06",X"3E",X"F0",X"38",X"07",X"3C",X"CB",X"41",X"20",X"02",X"3E",X"EF", + X"96",X"12",X"1C",X"1C",X"1C",X"2D",X"7E",X"12",X"2C",X"2C",X"1C",X"10",X"E4",X"DD",X"21",X"B0", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd new file mode 100644 index 00000000..a9b2202b --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_h is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_h is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd new file mode 100644 index 00000000..b6a9c509 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_k is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_k is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", 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X"00",X"00",X"0E",X"3F",X"7F",X"7F",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F", + X"FF",X"FF",X"7F",X"7F",X"3F",X"0E",X"00",X"00",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"01",X"07",X"0E",X"18",X"20",X"07",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"80", + X"FF",X"07",X"20",X"18",X"0E",X"07",X"01",X"00",X"FF",X"81",X"03",X"00",X"00",X"80",X"C0",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd new file mode 100644 index 00000000..39532f82 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity sound is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of sound is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"FF",X"FF",X"2D",X"20",X"FD",X"25",X"20",X"FA",X"DB",X"00",X"FE",X"F0",X"28",X"FA",X"3E", + X"10",X"3D",X"20",X"FD",X"DB",X"00",X"FE",X"F0",X"28",X"EF",X"FE",X"F1",X"20",X"25",X"21",X"80", + X"01",X"01",X"4F",X"06",X"DD",X"21",X"2A",X"00",X"18",X"4C",X"06",X"02",X"21",X"FF",X"FF",X"2D", + X"20",X"FD",X"25",X"20",X"05",X"05",X"20",X"02",X"18",X"CF",X"DB",X"00",X"FE",X"F1",X"28",X"EF", + X"C3",X"09",X"00",X"FE",X"F2",X"C2",X"5B",X"00",X"21",X"50",X"06",X"01",X"8F",X"10",X"DD",X"21", + X"55",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE",X"F2",X"28",X"FA",X"FE",X"F3",X"C2",X"09",X"00", + X"21",X"90",X"10",X"01",X"FF",X"17",X"DD",X"21",X"6D",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE", + 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ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity kb_synth is + port ( + reset_n : in std_logic; + clk : in std_logic; + in0 : in std_logic; + in1 : in std_logic; + in2 : in std_logic; + in3 : in std_logic; + speech_out : out std_logic_vector(7 downto 0) + ); +end kb_synth; + +architecture RTL of kb_synth is + +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_di : std_logic_vector(7 downto 0); +signal cpu_do : std_logic_vector(7 downto 0); +signal ram_do : std_logic_vector(7 downto 0); +signal rom4_do : std_logic_vector(7 downto 0); +signal rom5_do : std_logic_vector(7 downto 0); +signal rom6_do : std_logic_vector(7 downto 0); +signal mreq_n : std_logic; +signal iorq_n : std_logic; +signal rd_n : std_logic; +signal wr_n : std_logic; + +signal ram_ce : std_logic; +signal rom4_ce : std_logic; +signal rom5_ce : std_logic; +signal rom6_ce : std_logic; +signal ic3_out : std_logic_vector(7 downto 0); +signal buf_do : std_logic_vector(7 downto 0); +signal buf_ce : std_logic; +signal A13n : std_logic; +begin + +cpu_di <= ram_do when ram_ce = '1' else + rom4_do when rom4_ce = '1' else + rom5_do when rom5_ce = '1' else + rom6_do when rom6_ce = '1' else + buf_do when buf_ce = '0' else + "00000000"; + + + cpu : entity work.T80as + port map ( + RESET_n => reset_n, + CLK_n => clk, + WAIT_n => '1', + INT_n => '1', + NMI_n => '1', + BUSRQ_n => '1', + MREQ_n => mreq_n, + IORQ_n => iorq_n, + RD_n => rd_n, + WR_n => wr_n, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do + ); + +A13n <= not cpu_addr(13); +ram_ce <= not (A13n or mreq_n); + ram_inst : entity work.spram generic map(10,8) + port map ( + address => cpu_addr(9 downto 0), + clock => clk, + data => cpu_do, + wren => not wr_n, + q => ram_do + ); + +rom4_ce <= ic3_out(0); + rom4_inst : entity work.kbe1_IC4 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom4_do + ); + +rom5_ce <= ic3_out(1); + rom5_inst : entity work.kbe2_IC5 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom5_do + ); + +rom6_ce <= ic3_out(2); + rom6_inst : entity work.kbe3_IC6 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom6_do + ); + + ls138 : entity work.ttl_74138 + port map ( + a => cpu_addr(11), + b => cpu_addr(12), + c => '0', + g1 => A13n, + g2a_n => rd_n, + g2b_n => mreq_n, + y_n => ic3_out + ); + + ls273 : entity work.ttl_74273 + port map ( + CLRN => reset_n, + CLK => not (wr_n or iorq_n), + D8 => cpu_do(0), + D7 => cpu_do(1), + D6 => cpu_do(2), + D5 => cpu_do(3), + D4 => cpu_do(4), + D3 => cpu_do(5), + D2 => cpu_do(6), + D1 => cpu_do(7), + Q1 => speech_out(0), + Q2 => speech_out(1), + Q3 => speech_out(2), + Q4 => speech_out(3), + Q5 => speech_out(4), + Q6 => speech_out(5), + Q7 => speech_out(6), + Q8 => speech_out(7) + ); + +buf_ce <= rd_n or iorq_n; +--buf_do(6) <= '0'; +--buf_do(7) <= '0'; + ls367 : entity work.ttl_74367 + port map ( + p2GN => buf_ce,--15 + + p2A1 => '1',--12 + p2A2 => '1',--14 + + p1A4 => '0',--in3,--10 + p1A3 => '0',--in2,--6 + p1A2 => in1,--4 + p1A1 => in0,--2 + + p1GN => buf_ce,--1 + + p2Y1 => buf_do(4),--11 + p2Y2 => buf_do(5),--13 + + p1Y4 => buf_do(3),--9 + p1Y3 => buf_do(2),--7 + p1Y2 => buf_do(1),--5 + p1Y1 => buf_do(0)--3 + ); + +end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd index 3bfa76cb..91831325 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd @@ -23,24 +23,25 @@ library ieee; entity kingballoon is port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + W_SDAT_C : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic ); end; @@ -140,15 +141,6 @@ architecture RTL of kingballoon is signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - - COMPONENT SoundBoard - PORT( - reset_n : in std_logic; - clk : in std_logic; - audio : out std_logic_vector(7 downto 0) - ); - END COMPONENT; - begin mc_vid : entity work.MC_VIDEO @@ -311,7 +303,7 @@ begin I_256HnX => W_256HnX, I_1VF => W_1VF, I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, + I_STARS_ON => '0',--No Stars on this Game I_STARS_OFFn => W_STARS_OFFn, O_R => W_STARS_R, O_G => W_STARS_G, @@ -333,7 +325,7 @@ begin ); vmc_sound_b : entity work.MC_SOUND_B -port map( + port map( I_CLK1 => W_CLK_6M, I_RSTn => rst_count(3), I_SW => new_sw, @@ -341,16 +333,23 @@ port map( I_FS => W_FS, O_SDAT => W_SDAT_B ); - - mc_roms : entity work.sprom - generic map ( - init_file => "./ROM/prog.hex", - widthad_a => 14, - width_a => 8) + + speech : entity work.kb_synth + port map( + reset_n => W_RESETn, + clk => W_CLK_6M, + in0 => '0',--DIP + in1 => '0',--DIP + in2 => '0',--DIP + in3 => '0',--DIP + speech_out => W_SDAT_C + ); + + mc_roms : entity work.prog port map ( - address => W_A(13 downto 0), - clock => W_CLK_12M, - q => W_CPU_ROM_DO + clk => W_CLK_12M, + addr => W_A(13 downto 0), + data => W_CPU_ROM_DO ); -------- VIDEO ----------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd index 0b4ac592..c0edf061 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd @@ -63,15 +63,11 @@ begin --- COL ROM -------------------------------------------------------- --wire W_COL_ROM_OEn = W_6M_DO[1]; - galaxian_6l : entity work.sprom - generic map ( - init_file => "./ROM/col.hex", - widthad_a => 5, - width_a => 8) + galaxian_6l : entity work.col port map ( - address => W_6M_DO(6 downto 2), - clock => I_CLK_12M, - q => W_COL_ROM_DO + clk => I_CLK_12M, + addr => W_6M_DO(6 downto 2), + data => W_COL_ROM_DO ); --- VID OUT -------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd index 11ce2940..95911cec 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd @@ -219,27 +219,19 @@ begin O_DB => W_VID_RAM_DOB ); - k_rom : entity work.sprom - generic map ( - init_file => "./ROM/k.hex", - widthad_a => 11, - width_a => 8) + k_rom : entity work.rom_k port map ( - address => W_O_OBJ_ROM_A, - clock => I_CLK_12M, - q => W_1K_D + clk => I_CLK_12M, + addr => '0' & W_O_OBJ_ROM_A, + data => W_1K_D ); - - h_rom : entity work.sprom - generic map ( - init_file => "./ROM/h.hex", - widthad_a => 11, - width_a => 8) + + h_rom : entity work.rom_h port map ( - address => W_O_OBJ_ROM_A, - clock => I_CLK_12M, - q => W_1H_D - ); + clk => I_CLK_12M, + addr => '0' & W_O_OBJ_ROM_A, + data => W_1H_D + ); ----------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sprom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd new file mode 100644 index 00000000..e16bd235 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd @@ -0,0 +1,48 @@ +library IEEE; +use IEEE.std_logic_1164.all; +Use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity ttl_74138 is + port + ( + -- input + a : in std_logic; + b : in std_logic; + c : in std_logic; + + g1 : in std_logic; + g2a_n : in std_logic; + g2b_n : in std_logic; + + -- output + y_n : out std_logic_vector(7 downto 0) + ); +end ttl_74138; + +architecture SYN of ttl_74138 is + + signal enabled : std_logic; + +begin + + enabled <= g1 and not g2a_n and not g2b_n; + + y_n(0) <= '1' when enabled = '0' else + not (not a and not b and not c); + y_n(1) <= '1' when enabled = '0' else + not (a and not b and not c); + y_n(2) <= '1' when enabled = '0' else + not (not a and b and not c); + y_n(3) <= '1' when enabled = '0' else + not (a and b and not c); + y_n(4) <= '1' when enabled = '0' else + not (not a and not b and c); + y_n(5) <= '1' when enabled = '0' else + not (a and not b and c); + y_n(6) <= '1' when enabled = '0' else + not (not a and b and c); + y_n(7) <= '1' when enabled = '0' else + not (a and b and c); + +end SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd new file mode 100644 index 00000000..9f60ae57 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd @@ -0,0 +1,136 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Sun Aug 18 11:45:39 2019" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY work; + +ENTITY ttl_74273 IS + PORT + ( + CLRN : IN STD_LOGIC; + CLK : IN STD_LOGIC; + D8 : IN STD_LOGIC; + D7 : IN STD_LOGIC; + D6 : IN STD_LOGIC; + D5 : IN STD_LOGIC; + D4 : IN STD_LOGIC; + D3 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q1 : OUT STD_LOGIC; + Q2 : OUT STD_LOGIC; + Q3 : OUT STD_LOGIC; + Q4 : OUT STD_LOGIC; + Q5 : OUT STD_LOGIC; + Q6 : OUT STD_LOGIC; + Q7 : OUT STD_LOGIC; + Q8 : OUT STD_LOGIC + ); +END ttl_74273; + +ARCHITECTURE bdf_type OF ttl_74273 IS + + + +BEGIN + + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q8 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q8 <= D8; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q7 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q7 <= D7; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q6 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q6 <= D6; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q5 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q5 <= D5; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q4 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q4 <= D4; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q3 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q3 <= D3; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q2 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q2 <= D2; +END IF; +END PROCESS; + + +PROCESS(CLK,CLRN) +BEGIN +IF (CLRN = '0') THEN + Q1 <= '0'; +ELSIF (RISING_EDGE(CLK)) THEN + Q1 <= D1; +END IF; +END PROCESS; + + +END bdf_type; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd new file mode 100644 index 00000000..161c44b2 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd @@ -0,0 +1,122 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Fri Aug 16 22:43:02 2019" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY work; + +ENTITY ttl_74367 IS + PORT + ( + p2GN : IN STD_LOGIC; + p2A1 : IN STD_LOGIC; + p2A2 : IN STD_LOGIC; + p1A4 : IN STD_LOGIC; + p1A3 : IN STD_LOGIC; + p1A2 : IN STD_LOGIC; + p1A1 : IN STD_LOGIC; + p1GN : IN STD_LOGIC; + p2Y1 : OUT STD_LOGIC; + p2Y2 : OUT STD_LOGIC; + p1Y4 : OUT STD_LOGIC; + p1Y3 : OUT STD_LOGIC; + p1Y2 : OUT STD_LOGIC; + p1Y1 : OUT STD_LOGIC + ); +END ttl_74367; + +ARCHITECTURE bdf_type OF ttl_74367 IS + +SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; + + +BEGIN + + + +PROCESS(p1A4,SYNTHESIZED_WIRE_6) +BEGIN +if (SYNTHESIZED_WIRE_6 = '1') THEN + p1Y4 <= p1A4; +ELSE + p1Y4 <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(p2A2,SYNTHESIZED_WIRE_7) +BEGIN +if (SYNTHESIZED_WIRE_7 = '1') THEN + p2Y2 <= p2A2; +ELSE + p2Y2 <= 'Z'; +END IF; +END PROCESS; + + +SYNTHESIZED_WIRE_6 <= NOT(p1GN); + + + +PROCESS(p2A1,SYNTHESIZED_WIRE_7) +BEGIN +if (SYNTHESIZED_WIRE_7 = '1') THEN + p2Y1 <= p2A1; +ELSE + p2Y1 <= 'Z'; +END IF; +END PROCESS; + + +SYNTHESIZED_WIRE_7 <= NOT(p2GN); + + + +PROCESS(p1A1,SYNTHESIZED_WIRE_6) +BEGIN +if (SYNTHESIZED_WIRE_6 = '1') THEN + p1Y1 <= p1A1; +ELSE + p1Y1 <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(p1A2,SYNTHESIZED_WIRE_6) +BEGIN +if (SYNTHESIZED_WIRE_6 = '1') THEN + p1Y2 <= p1A2; +ELSE + p1Y2 <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(p1A3,SYNTHESIZED_WIRE_6) +BEGIN +if (SYNTHESIZED_WIRE_6 = '1') THEN + p1Y3 <= p1A3; +ELSE + p1Y3 <= 'Z'; +END IF; +END PROCESS; + + +END bdf_type; \ No newline at end of file diff --git a/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf b/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf index 3c7e7668..d112c6a2 100644 --- a/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf +++ b/Computer_MiST/Laser310_MiST/Laser310_MiST.qsf @@ -429,4 +429,5 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(Laser310_MiST) # ------------------------- +set_global_assignment -name VERILOG_FILE rtl/fdc.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v b/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v index 9f7eb03f..6754c1ab 100644 --- a/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v +++ b/Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v @@ -47,7 +47,7 @@ input [7:0] key_code, input [9:0] SWITCH, input UART_RXD, output UART_TXD -); + reg [3:0] CLK; @@ -56,45 +56,38 @@ reg MEM_OP_WR; (*keep*)reg GPIO_CPU_CLK; // Processor (*keep*)reg CPU_CLK; -(*keep*)wire [15:0] CPU_A; -(*keep*)wire [7:0] CPU_DI; -(*keep*)wire [7:0] CPU_DO; +(*keep*)wire[15:0] CPU_A; +(*keep*)wire [7:0] CPU_DI; +(*keep*)wire [7:0] CPU_DO; (*keep*)wire CPU_RESET; (*keep*)wire CPU_HALT; - (*keep*)wire CPU_MREQ; (*keep*)wire CPU_RD; (*keep*)wire CPU_WR; (*keep*)wire CPU_IORQ; (*keep*)reg CPU_INT; - (*keep*)wire CPU_M1; -wire CPU_BUSRQ; -wire CPU_BUSAK; -wire CPU_RFSH; - +wire CPU_BUSRQ; +wire CPU_BUSAK; +wire CPU_RFSH; (*keep*)wire CPU_RESET_N; (*keep*)wire CPU_HALT_N; - (*keep*)wire CPU_MREQ_N; (*keep*)wire CPU_RD_N; (*keep*)wire CPU_WR_N; (*keep*)wire CPU_IORQ_N; (*keep*)wire CPU_INT_N; - (*keep*)wire CPU_M1_N; -wire CPU_BUSRQ_N; -wire CPU_BUSAK_N; -wire CPU_RFSH_N; +wire CPU_BUSRQ_N; +wire CPU_BUSAK_N; +wire CPU_RFSH_N; // VRAM -(*keep*)wire [12:0] VRAM_ADDRESS; +(*keep*)wire[12:0] VRAM_ADDRESS; (*keep*)wire VRAM_WR; -(*keep*)wire [7:0] VRAM_DATA_OUT; - +(*keep*)wire [7:0] VRAM_DATA_OUT; (*keep*)wire VDG_RD; -(*keep*)wire [12:0] VDG_ADDRESS; -(*keep*)wire [7:0] VDG_DATA; - +(*keep*)wire[12:0] VDG_ADDRESS; +(*keep*)wire [7:0] VDG_DATA; // ROM IO RAM reg LATCHED_DOSROM_EN; reg LATCHED_BOOTROM_EN; @@ -1082,4 +1075,105 @@ assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0}; (*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0); assign AUD_ADCDAT = {LATCHED_IO_DATA_WR[0],LATCHED_IO_DATA_WR[5]}; + + +// floppy +wire ADDRESS_IO_FDC; +wire ADDRESS_IO_FDC_CT; +wire ADDRESS_IO_FDC_DATA; +wire ADDRESS_IO_FDC_POLL; +wire ADDRESS_IO_FDC_WP; +reg [7:0] LATCHED_IO_FDC; +reg [7:0] LATCHED_IO_FDC_CT; +reg [7:0] LATCHED_RAM_DATA_FDC; + +// floppy +(*keep*)wire FDC_RAM_R; +(*keep*)wire FDC_RAM_W; +(*keep*)wire [17:0] FDC_RAM_ADDR_R; +(*keep*)wire [17:0] FDC_RAM_ADDR_W; +reg [7:0] LAST_WRITE_DATA; +(*keep*)wire [7:0] FDC_RAM_DATA_W; + +(*keep*)wire [7:0] FLOPPY_RD_DATA; +(*keep*)wire [7:0] FLOPPY_DATA; + +// FDC +// if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_FDC_CT}==4'b1011) +// LATCHED_IO_FDC_CT <= CPU_DO; + +// if({CPU_IORQ,CPU_RD,CPU_WR}==3'b110) +// LATCHED_IO_FDC <= ADDRESS_IO_FDC_POLL ? {FDC_POLL, 7'h7F} : +// ADDRESS_IO_FDC_DATA ? FDC_DATA : +// ADDRESS_IO_FDC_WP ? {FDC_WP, 7'h7F} : +// 8'hFF; +wire FLOPPY_WP_READ = 1'b0; +wire RAM_ADDRESS_FD_R = FDC_RAM_ADDR_R; +wire RAM_ADDRESS_FD_W = FDC_RAM_ADDR_W; + +assign ADDRESS_IO_FDC = (CPU_A[7:2] == 6'b000100)?1'b1:1'b0; + +assign ADDRESS_IO_FDC_CT = (CPU_A[7:0] == 8'h10)?1'b1:1'b0; +assign ADDRESS_IO_FDC_DATA = (CPU_A[7:0] == 8'h11)?1'b1:1'b0; +assign ADDRESS_IO_FDC_POLL = (CPU_A[7:0] == 8'h12)?1'b1:1'b0; +assign ADDRESS_IO_FDC_WP = (CPU_A[7:0] == 8'h13)?1'b1:1'b0; + + +wire [7:0] FDC_DATA; +wire FDC_POLL; +wire FDC_WP; + +wire [7:0] SECTOR_BYTE; +wire [7:0] TRACK1_NO; +wire [7:0] TRACK2_NO; +wire DRIVE1; +wire DRIVE2; +wire MOTOR; + +wire FDC_IO_R; +wire FDC_IO_W; + +wire FDC_SIG; +wire FDC_SIG_CLK; + +wire FDC_IO = (CPU_IORQ&ADDRESS_IO_FDC); +wire FDC_IO_POLL = (CPU_IORQ&ADDRESS_IO_FDC_POLL); +wire FDC_IO_DATA = (CPU_IORQ&ADDRESS_IO_FDC_DATA); +wire FDC_IO_CT = (CPU_IORQ&ADDRESS_IO_FDC_CT); + +FDC_IF FDC_U ( + .FDC_CLK(CPU_CLK), + .RESET_N(RESET_N), + .SW(SWITCH[3:2]), + .DBG(SWITCH[9:6]), + + .FDC_RAM_R(FDC_RAM_R), + .FDC_RAM_W(FDC_RAM_W), + .FDC_RAM_ADDR_R(FDC_RAM_ADDR_R), + .FDC_RAM_ADDR_W(FDC_RAM_ADDR_W), + .FDC_RAM_DATA_R(LATCHED_RAM_DATA_FDC), + .FDC_RAM_DATA_W(FDC_RAM_DATA_W), + + .FDC_IO(FDC_IO), + .FDC_IO_POLL(FDC_IO_POLL), + .FDC_IO_DATA(FDC_IO_DATA), + .FDC_IO_CT(FDC_IO_CT), + + .FDC_SIG(FDC_SIG), + .FDC_SIG_CLK(FDC_SIG_CLK), + + .FDC_CT(LATCHED_IO_FDC_CT), + .FDC_DATA(FDC_DATA), + .FDC_POLL(FDC_POLL), + .FDC_WP(FDC_WP), + + .FLOPPY_SECTOR_BYTE(SECTOR_BYTE), + .TRACK1_NO(TRACK1_NO), + .TRACK2_NO(TRACK2_NO), + .DRIVE1(DRIVE1), + .DRIVE2(DRIVE2), + .MOTOR(MOTOR) +); + + endmodule diff --git a/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv b/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv index 15896c09..9b9eeb12 100644 --- a/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv +++ b/Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv @@ -96,7 +96,7 @@ mist_video #(.COLOR_DEPTH(6)) mist_video( .VGA_B(VGA_B), .VGA_VS(VGA_VS), .VGA_HS(VGA_HS), - .scandoubler_disable(scandoublerD), + .scandoubler_disable(1'b1),//scandoublerD), .scanlines(status[4:3]), .ypbpr(ypbpr) ); diff --git a/Computer_MiST/Laser310_MiST/rtl/fdc.v b/Computer_MiST/Laser310_MiST/rtl/fdc.v new file mode 100644 index 00000000..b63ae324 --- /dev/null +++ b/Computer_MiST/Laser310_MiST/rtl/fdc.v @@ -0,0 +1,967 @@ +/***************************************************************************** +* Floppy +******************************************************************************/ + +// POLLING after Clock + +// vz dsk Parameter +// 154 * 16 * 40 = 98560 = 0x18100 +// 154 * 16 = 2464 = 0x9A0 = 0x4D0 * 2 +`define FD_MAX_LEN 17'h18100 +`define FD_TRACK_LEN 12'h9A0 +`define FD_TRACK_STEP 8'h4D + +// 40*2 0 --- 78 +`define FD_MAX_TRACK_NO 8'd78 + + +module FDC_IF ( + FDC_CLK, + RESET_N, + SW, + DBG, + + FDC_RAM_R, + FDC_RAM_W, + FDC_RAM_ADDR_R, + FDC_RAM_ADDR_W, + FDC_RAM_DATA_R, + FDC_RAM_DATA_W, + + FDC_IO, + FDC_IO_POLL, + FDC_IO_DATA, + FDC_IO_CT, + + FDC_SIG, + FDC_SIG_CLK, + + FDC_CT, + FDC_DATA, + FDC_POLL, + FDC_WP, + + FLOPPY_SECTOR_BYTE, + TRACK1_NO, + TRACK2_NO, + DRIVE1, + DRIVE2, + MOTOR +); + + +input FDC_CLK; +input RESET_N; +input [1:0] SW; +input [3:0] DBG; + +output [17:0] FDC_RAM_ADDR_R; +output [17:0] FDC_RAM_ADDR_W; +output reg FDC_RAM_R; +output reg FDC_RAM_W; +input [7:0] FDC_RAM_DATA_R; +output [7:0] FDC_RAM_DATA_W; + + +input FDC_IO; +input FDC_IO_POLL; +input FDC_IO_DATA; +input FDC_IO_CT; + +output FDC_SIG; +output reg FDC_SIG_CLK; + +input [7:0] FDC_CT; + +output [7:0] FDC_DATA; +output FDC_POLL; +output FDC_WP; + + +reg [11:0] FLOPPY_BYTE; +output reg [7:0] FLOPPY_SECTOR_BYTE; // Count Sector Bytes + +reg [6:0] CLK_CNT; +reg [6:0] CLK_CNT_W; + +reg [18:0] SYNC_CNT; +reg [7:0] FLOPPY_SECTOR_DELAY; // Delay on Sector End + + +reg FD_REC1; +reg FDC_POLL1; +reg FDC_REC_DATA_BIT1; +reg FDC_DATA_BIT1; +reg [7:0] FDC_DATA1; +reg [7:0] LATCHED_FDC_DATA1; +reg FDC_DATA_SET1; + +reg FD_REC2; +reg FDC_POLL2; +reg FDC_REC_DATA_BIT2; +reg FDC_DATA_BIT2; +reg [7:0] FDC_DATA2; +reg [7:0] LATCHED_FDC_DATA2; + +reg [3:0] BIT_CNT_W; +reg [2:0] BIT_CNT; + +wire FDC_RAM_DATA_R_BIT; + + +reg [1:0] STEPPER1; +reg [1:0] STEPPER2; +output reg [7:0] TRACK1_NO; +output reg [7:0] TRACK2_NO; +reg [12:0] TRACK1; +reg [12:0] TRACK2; +(*keep*)wire [13:0] TRACK; +wire [12:0] TRACK1_UP; +wire [12:0] TRACK1_DOWN; +wire [12:0] TRACK2_UP; +wire [12:0] TRACK2_DOWN; +reg [17:0] FLOPPY_ADDRESS_R; +reg [17:0] FLOPPY_ADDRESS_W; +//reg [7:0] FLOPPY_WRITE_DATA; + +reg WRITE_WAIT_FIRST_OP; +reg WRITE_DATA_BIT_VAL; + +reg [7:0] WRITE_DATA1; +reg WRITE_DATA_MODI1; +reg [7:0] WRITE_DATA2; +reg WRITE_DATA2_MODI; + + +(*keep*)wire [7:0] FLOPPY_RD_DATA; +(*keep*)wire [7:0] FLOPPY_DATA; +(*keep*)wire FLOPPY_READ; +(*keep*)wire FLOPPY_WRITE; +wire FLOPPY_WP_READ; +reg PHASE0; +reg PHASE0_1; +reg PHASE0_2; +reg PHASE1; +reg PHASE1_1; +reg PHASE1_2; +reg PHASE2; +reg PHASE2_1; +reg PHASE2_2; +reg PHASE3; +reg PHASE3_1; +reg PHASE3_2; +output reg DRIVE1; +output reg DRIVE2; +output reg MOTOR; + +reg WRITE_REQUEST_N; +reg WRITE_DATA_BIT; + +reg Q6; +reg Q7; +wire DRIVE1_EN; +wire DRIVE2_EN; +wire DRIVE1_X; +wire DRIVE2_X; +wire DRIVE_SWAP; +wire DRIVE1_FLOPPY_WP; +wire DRIVE2_FLOPPY_WP; + +reg MODIFY_DRIVE1; +reg MODIFY_DRIVE2; + +assign FDC_RAM_ADDR_R = FLOPPY_ADDRESS_R; +assign FDC_RAM_ADDR_W = FLOPPY_ADDRESS_W; + + +(*preserve*)reg [7:0] FDC_CNT; +(*preserve*)reg [7:0] FDC_CNT_POLL; +(*preserve*)reg [7:0] FDC_CNT_DATA; +(*preserve*)reg [19:0] FDC_CNT_CT; + +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + FDC_CNT <= 8'hFF; + FDC_CNT_POLL <= 8'hFF; + FDC_CNT_DATA <= 8'hFF; + FDC_CNT_CT <= 20'hFFFFF; + end + else + begin + if(FDC_IO) + FDC_CNT <= 0; + else if(~FDC_CNT[7]) + FDC_CNT <= FDC_CNT + 1; + + if(FDC_IO_POLL) + FDC_CNT_POLL <= 0; + else if(~FDC_CNT_POLL[7]) + FDC_CNT_POLL <= FDC_CNT_POLL + 1; + + if(FDC_IO_DATA) + FDC_CNT_DATA <= 0; + else if(~FDC_CNT_DATA[7]) + FDC_CNT_DATA <= FDC_CNT_DATA + 1; + + if(FDC_IO_CT) + FDC_CNT_CT <= 0; + else if(~FDC_CNT_CT[19]) + FDC_CNT_CT <= FDC_CNT_CT + 1; + end +end + + + +assign FDC_POLL = (DRIVE1_EN)?FDC_POLL1: + (DRIVE2_EN)?FDC_POLL2: + 1'b0; + + +assign FDC_DATA = (DRIVE1_EN)?FDC_DATA1: + (DRIVE2_EN)?FDC_DATA2: + 8'hFF; + + + +assign FDC_RAM_DATA_R_BIT = (BIT_CNT==3'd7)?FDC_RAM_DATA_R[7]: + (BIT_CNT==3'd6)?FDC_RAM_DATA_R[6]: + (BIT_CNT==3'd5)?FDC_RAM_DATA_R[5]: + (BIT_CNT==3'd4)?FDC_RAM_DATA_R[4]: + (BIT_CNT==3'd3)?FDC_RAM_DATA_R[3]: + (BIT_CNT==3'd2)?FDC_RAM_DATA_R[2]: + (BIT_CNT==3'd1)?FDC_RAM_DATA_R[1]: + FDC_RAM_DATA_R[0]; + + +// 读取 + +reg LATCHED_FD_REC1; +reg LATCHED_FDC_IO_DATA1; +reg GET_FDC_POLLING; + +reg [5:0] FDC_POLL1_CNT; + +reg [5:0] GET_FDC_POLL1_CNT; + + +always @(posedge FDC_CLK or negedge RESET_N) + if(~RESET_N) + begin + FDC_DATA_BIT1 <= 1'b0; + + LATCHED_FD_REC1 <= 1'b0; + LATCHED_FDC_IO_DATA1 <= 1'b0; + end + else + begin + // 磁道记录信号上沿，翻转 DATA_BIT + if({LATCHED_FD_REC1, FD_REC1}==2'b01) + begin + FDC_DATA_BIT1 <= FDC_POLL1; + end + + if(FDC_DATA_SET1) + LATCHED_FDC_DATA1 <= {LATCHED_FDC_DATA1[6:0], FDC_DATA_BIT1}; + + // 读取DATA信号上沿 + if({LATCHED_FDC_IO_DATA1, FDC_IO_DATA}==2'b01) + begin + FDC_DATA1 <= LATCHED_FDC_DATA1; + end + + LATCHED_FD_REC1 <= FD_REC1; + LATCHED_FDC_IO_DATA1 <= FDC_IO_DATA; + end + +//////////////////////////////////////// +// 物理软驱模拟 +//////////////////////////////////////// + +//WRITE_REQUEST_N +(*preserve*)reg [9:0] WRITE_DATA_CNT; + +assign FDC_RAM_DATA_W = WRITE_DATA1; + +// 对写入操作计数 +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + WRITE_DATA_CNT <= 0; + end + else + begin + if( (~FDC_CT[6]) && (FDC_CT[5]==LATCHED_FDC_CT[5]) ) + begin + if(~WRITE_DATA_CNT[9]) + WRITE_DATA_CNT <= WRITE_DATA_CNT+1; + end + else + begin + WRITE_DATA_CNT <= 0; + end + end +end + + +// 模拟磁道信号 + +// 等待第1个写入数据变化 +always @(posedge FDC_CLK or negedge RESET_N) + if(~RESET_N) + begin + WRITE_WAIT_FIRST_OP <= 1'b0; + end + else + begin + if( LATCHED_FDC_CT[6]!=FDC_CT[6] ) + begin + // 信号下拉，开始写入，并等待第1个写入数据变化。 + WRITE_WAIT_FIRST_OP <= ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b10); + end + else + begin + // 找到第1个写入数据变化 + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) ) + WRITE_WAIT_FIRST_OP <= 1'b0; + end + end + +// 判断是否有写入数据产生 +always @(posedge FDC_CLK or negedge RESET_N) + if(~RESET_N) + begin + WRITE_DATA_MODI1 <= 1'b0; + end + else + begin + // 写入信号变化 + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) ) + begin + WRITE_DATA_MODI1 <= 1'b1; + end + else + begin + if(FDC_RAM_W) + WRITE_DATA_MODI1 <= 1'b0; + end + end + + +// 判断写入的值 +always @(posedge FDC_CLK or negedge RESET_N) + if(~RESET_N) + begin + WRITE_DATA_BIT_VAL <= 1'b0; + end + else + begin + // 写入信号变化 + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) ) + begin + // 9'h01B 9'h056 9'h072 + if(WRITE_DATA_CNT==10'h01B) + begin + WRITE_DATA_BIT_VAL <= 1'b1; + end + else + begin + WRITE_DATA_BIT_VAL <= 1'b0; + end + end + end + + +// 模拟磁盘数据位 +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + SYNC_CNT <= 19'b0; + + BIT_CNT <= 3'd0; + + FDC_RAM_R <= 1'b0; + FDC_RAM_W <= 1'b0; + + FDC_DATA_SET1 <= 1'b0; + + FDC_POLL1 <= 1'b0; + FDC_POLL2 <= 1'b0; + + FLOPPY_BYTE <= 12'h000; + FLOPPY_SECTOR_BYTE <= 8'h00; + FLOPPY_SECTOR_DELAY <= 8'h00; + FLOPPY_ADDRESS_R <= 18'b0; + FLOPPY_ADDRESS_W <= 18'b0; + + WRITE_DATA1 <= 8'b0; + + FD_REC1 <= 1'b0; + CLK_CNT <= 7'h00; + end + else + begin + begin + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT[9] ) + begin + // INIT 磁道空白区，约1/10圈空白。 + // 找到第1个时钟位 + BIT_CNT <= 3'd7; + + // 下一个需要读取的位置 + FLOPPY_BYTE <= 12'h001; + FLOPPY_SECTOR_BYTE <= 8'h00; + + FLOPPY_ADDRESS_R <= {TRACK, 4'b0}; + SYNC_CNT <= 19'b0; + FDC_RAM_R <= 1'b1; + + FDC_RAM_W <= 1'b0; + + FDC_DATA_SET1 <= 1'b0; + + FD_REC1 <= 1'b1; + FDC_POLL1 <= 1'b0; + FDC_POLL2 <= 1'b0; + CLK_CNT <= 7'h03; + end + else + begin + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT==10'h02F ) + begin + // 格式化时，数据区之前无空白。数据存盘时，写入数据区留有50个左右的时钟周期空白。 + // 写入扇区定位，写入扇区前有约0x28个时钟周期的空白。 + FDC_RAM_W <= 1'b0; + + FDC_DATA_SET1 <= 1'b0; + + FD_REC1 <= 1'b1; + FDC_POLL1 <= 1'b0; + FDC_POLL2 <= 1'b0; + CLK_CNT <= 7'h03; + end + else + begin + case(CLK_CNT) + 7'h00: // 同步信号 324 * 8 * 0x70 = 290304 + begin + FD_REC1 <= 1'b0; + SYNC_CNT <= SYNC_CNT+1; + + FDC_RAM_R <= 1'b0; + FDC_RAM_W <= 1'b0; + + if(SYNC_CNT[18]) + //if(SYNC_CNT[10]) + begin + CLK_CNT <= CLK_CNT + 1; + end + end + + 7'h01: + begin + FDC_RAM_R <= 1'b0; + FDC_RAM_W <= 1'b0; + + // 如果是写入，等待时钟沿的变化 + if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && ({LATCHED_FDC_CT[5],FDC_CT[5]}==2'b01) ) + begin + CLK_CNT <= CLK_CNT; + end + else + begin + CLK_CNT <= CLK_CNT + 1; + end + end + + // CLOCK DOMAIN + 7'h02: + begin + BIT_CNT <= BIT_CNT-1; + + // 读取 + if(BIT_CNT==3'd0) + begin + begin + FLOPPY_BYTE <= FLOPPY_BYTE + 1'b1; + + FLOPPY_ADDRESS_R <= {TRACK, 4'b0} + {6'b000000, FLOPPY_BYTE}; + end + + FDC_RAM_R <= 1'b1; + end + + FD_REC1 <= 1'b1; + + CLK_CNT <= CLK_CNT + 1; + end + + + // POOLING + // 从读取POLLING成功（值为1），到读取DATA中间间隔了0x43 个时钟周期。 + 7'h03: + begin + FDC_RAM_R <= 1'b0; + FDC_RAM_W <= 1'b0; + + FDC_POLL1 <= 1'b1; + FDC_POLL2 <= 1'b1; + CLK_CNT <= CLK_CNT + 1; + end + + 7'h06: // 1us + begin + FD_REC1 <= 1'b0; + CLK_CNT <= CLK_CNT + 1; + end + + // DATA DOMAIN + 7'h1E: + begin + FD_REC1 <= FDC_RAM_DATA_R_BIT; + CLK_CNT <= CLK_CNT + 1; + end + + 7'h1F: + begin + FDC_DATA_SET1 <= 1'b1; + CLK_CNT <= CLK_CNT + 1; + end + + 7'h20: + begin + FDC_DATA_SET1 <= 1'b0; + CLK_CNT <= CLK_CNT + 1; + end + + 7'h22: + begin + FD_REC1 <= 1'b0; + CLK_CNT <= CLK_CNT + 1; + end + + 7'h25: + begin + FDC_POLL1 <= 1'b0; + FDC_POLL2 <= 1'b0; + CLK_CNT <= CLK_CNT + 1; + end + + // 扇区结束延时 + 7'h70: + begin + // 写入 + WRITE_DATA1 <= {WRITE_DATA1[6:0],WRITE_DATA_BIT_VAL}; + + if(BIT_CNT==3'd0) + begin + FLOPPY_ADDRESS_W <= FLOPPY_ADDRESS_R; + FDC_RAM_W <= WRITE_DATA_MODI1; + end + + CLK_CNT <= CLK_CNT + 1; + end + + 7'h71: + begin + // 写入结束 + FDC_RAM_W <= 1'b0; + + FDC_SIG_CLK <= WRITE_DATA_MODI1; + + // 扇区结束时的延时 + if(BIT_CNT==3'd0 && FLOPPY_SECTOR_BYTE==8'h99) + begin + FLOPPY_SECTOR_DELAY <= 8'hA5; + end + else + begin + FLOPPY_SECTOR_DELAY <= 8'h00; + end + + CLK_CNT <= CLK_CNT + 1; + end + + // 扇区结束时的延时 + 7'h72: + begin + FDC_SIG_CLK <= 1'b0; + + // 扇区结束时的延时 + if(FLOPPY_SECTOR_DELAY==8'h00) + begin + CLK_CNT <= CLK_CNT + 1; + end + else + begin + FLOPPY_SECTOR_DELAY <= FLOPPY_SECTOR_DELAY-1; + end + end + + 7'h73: + begin + if(BIT_CNT==3'd0) + begin + if(FLOPPY_BYTE==`FD_TRACK_LEN||FLOPPY_SECTOR_BYTE==8'h99) + begin + FLOPPY_SECTOR_BYTE <= 8'h00; + end + else + begin + FLOPPY_SECTOR_BYTE <= FLOPPY_SECTOR_BYTE+1; + end + end + + if(BIT_CNT==3'd0 && FLOPPY_BYTE==`FD_TRACK_LEN) + begin + FLOPPY_BYTE <= 12'h000; + //FLOPPY_SECTOR_BYTE <= 8'h00; + + FLOPPY_ADDRESS_R <= {TRACK, 4'b0}; + SYNC_CNT <= 19'b0; + + CLK_CNT <= 7'h00; + end + else + begin + CLK_CNT <= 7'h01; + end + end + + default: + begin + FDC_RAM_R <= 1'b0; + FDC_RAM_W <= 1'b0; + CLK_CNT <= CLK_CNT + 1; + end + endcase + end + end + end + end +end + + +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + PHASE0 <= 1'b0; + PHASE1 <= 1'b0; + PHASE2 <= 1'b0; + PHASE3 <= 1'b0; + MOTOR <= 1'b0; + DRIVE1 <= 1'b0; + DRIVE2 <= 1'b0; + WRITE_REQUEST_N <= 1'b1; + WRITE_DATA_BIT <= 1'b0; + end + else + begin + PHASE0 <= FDC_CT[0]; + PHASE1 <= FDC_CT[1]; + PHASE2 <= FDC_CT[2]; + PHASE3 <= FDC_CT[3]; + DRIVE1 <= FDC_CT[4]; + DRIVE2 <= FDC_CT[7]; + MOTOR <= (FDC_CT[4])|(FDC_CT[7]); + WRITE_REQUEST_N <= FDC_CT[6]; + WRITE_DATA_BIT <= FDC_CT[5]; + end +end + +//assign DRIVE1_X = DRIVE1 & MOTOR; +//assign DRIVE2_X = !DRIVE1 & MOTOR; + +assign DRIVE1_X = DRIVE1 & MOTOR; +assign DRIVE2_X = DRIVE2 & MOTOR; + +assign DRIVE1_FLOPPY_WP = ~SW[0]; +assign DRIVE2_FLOPPY_WP = ~SW[1]; + +assign FDC_WP = DRIVE1?DRIVE1_FLOPPY_WP: + DRIVE2?DRIVE2_FLOPPY_WP: + 1'b1; + + +assign DRIVE1_EN = (DRIVE1) & MOTOR; +assign DRIVE2_EN = (DRIVE2) & MOTOR; + + +assign TRACK = (DRIVE1_EN) ? {1'b0,TRACK1}: + (DRIVE2_EN) ? {1'b1,TRACK2}: + 14'b0; + +assign TRACK1_UP = TRACK1 + `FD_TRACK_STEP; +assign TRACK1_DOWN = TRACK1 - `FD_TRACK_STEP; +assign TRACK2_UP = TRACK2 + `FD_TRACK_STEP; +assign TRACK2_DOWN = TRACK2 - `FD_TRACK_STEP; + + +//assign FLOPPY_ADDRESS_R = {TRACK, 4'b0} + {5'b00000, FLOPPY_BYTE}; + + +//always @ (posedge PH_2) +always @(negedge FDC_CLK) +begin + PHASE0_1 <= PHASE0; + PHASE0_2 <= PHASE0_1; // Delay 2 clock cycles + PHASE1_1 <= PHASE1; + PHASE1_2 <= PHASE1_1; // Delay 2 clock cycles + PHASE2_1 <= PHASE2; + PHASE2_2 <= PHASE2_1; // Delay 2 clock cycles + PHASE3_1 <= PHASE3; + PHASE3_2 <= PHASE3_1; // Delay 2 clock cycles +end + +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + STEPPER1 <= 2'b00; + STEPPER2 <= 2'b00; + TRACK1 <= 13'd0; + TRACK2 <= 13'd0; + + TRACK1_NO <= 8'd0; + TRACK2_NO <= 8'd0; + end + else + begin +// if(DRIVE1^DRIVE_SWAP) + if(DRIVE1) + begin + case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2}) + 4'b1000: + begin + if(STEPPER1 == 2'b11) + begin + //if(TRACK1 != `FD_MAX_LEN) + if(TRACK1_NO != `FD_MAX_TRACK_NO) + begin + TRACK1 <= TRACK1_UP; + TRACK1_NO <= TRACK1_NO+1; + STEPPER1 <= 2'b00; + end + end + else + if(STEPPER1 == 2'b01) + begin + //if(TRACK1 != 17'h0) + if(TRACK1_NO != 8'd0) + begin + TRACK1 <= TRACK1_DOWN; + TRACK1_NO <= TRACK1_NO-1; + STEPPER1 <= 2'b00; + end + end + end + 4'b0100: + begin + if(STEPPER1 == 2'b00) + begin + //if(TRACK1 != `FD_MAX_LEN) + if(TRACK1_NO != `FD_MAX_TRACK_NO) + begin + TRACK1 <= TRACK1_UP; + TRACK1_NO <= TRACK1_NO+1; + STEPPER1 <= 2'b01; + end + end + else + if(STEPPER1 == 2'b10) + begin + //if(TRACK1 != 17'h0) + if(TRACK1_NO != 8'd0) + begin + TRACK1 <= TRACK1_DOWN; + TRACK1_NO <= TRACK1_NO-1; + STEPPER1 <= 2'b01; + end + end + end + 4'b0010: + begin + if(STEPPER1 == 2'b01) + begin + //if(TRACK1 != `FD_MAX_LEN) + if(TRACK1_NO != `FD_MAX_TRACK_NO) + begin + TRACK1 <= TRACK1_UP; + TRACK1_NO <= TRACK1_NO+1; + STEPPER1 <= 2'b10; + end + end + else + if(STEPPER1 == 2'b11) + begin + //if(TRACK1 != 17'h0) + if(TRACK1_NO != 8'd0) + begin + TRACK1 <= TRACK1_DOWN; + TRACK1_NO <= TRACK1_NO-1; + STEPPER1 <= 2'b10; + end + end + end + 4'b0001: + begin + if(STEPPER1 == 2'b10) + begin + //if(TRACK1 != `FD_MAX_LEN) + if(TRACK1_NO != `FD_MAX_TRACK_NO) + begin + TRACK1 <= TRACK1_UP; + TRACK1_NO <= TRACK1_NO+1; + STEPPER1 <= 2'b11; + end + end + else + if(STEPPER1 == 2'b00) + begin + //if(TRACK1 != 17'h0) + if(TRACK1_NO != 8'd0) + begin + TRACK1 <= TRACK1_DOWN; + TRACK1_NO <= TRACK1_NO-1; + STEPPER1 <= 2'b11; + end + end + end + endcase + end + + else + + begin + case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2}) + 4'b1000: + begin + if(STEPPER2 == 2'b11) + begin + //if(TRACK2 != `FD_MAX_LEN) + if(TRACK2_NO != `FD_MAX_TRACK_NO) + begin + TRACK2 <= TRACK2_UP; + TRACK2_NO <= TRACK2_NO+1; + STEPPER2 <= 2'b00; + end + end + else + if(STEPPER2 == 2'b01) + begin + //if(TRACK2 != 17'h0) + if(TRACK2_NO != 8'd0) + begin + TRACK2 <= TRACK2_DOWN; + TRACK2_NO <= TRACK2_NO-1; + STEPPER2 <= 2'b00; + end + end + end + 4'b0100: + begin + if(STEPPER2 == 2'b00) + begin + //if(TRACK2 != `FD_MAX_LEN) + if(TRACK2_NO != `FD_MAX_TRACK_NO) + begin + TRACK2 <= TRACK2_UP; + TRACK2_NO <= TRACK2_NO+1; + STEPPER2 <= 2'b01; + end + end + else + if(STEPPER2 == 2'b10) + begin + //if(TRACK2 != 17'h0) + if(TRACK2_NO != 8'd0) + begin + TRACK2 <= TRACK2_DOWN; + TRACK2_NO <= TRACK2_NO-1; + STEPPER2 <= 2'b01; + end + end + end + 4'b0010: + begin + if(STEPPER2 == 2'b01) + begin + //if(TRACK2 != `FD_MAX_LEN) + if(TRACK2_NO != `FD_MAX_TRACK_NO) + begin + TRACK2 <= TRACK2_UP; + TRACK2_NO <= TRACK2_NO+1; + STEPPER2 <= 2'b10; + end + end + else + if(STEPPER2 == 2'b11) + begin + //if(TRACK2 != 17'h0) + if(TRACK2_NO != 8'd0) + begin + TRACK2 <= TRACK2_DOWN; + TRACK2_NO <= TRACK2_NO-1; + STEPPER2 <= 2'b10; + end + end + end + 4'b0001: + begin + if(STEPPER2 == 2'b10) + begin + //if(TRACK2 != `FD_MAX_LEN) + if(TRACK2_NO != `FD_MAX_TRACK_NO) + begin + TRACK2 <= TRACK2_UP; + TRACK2_NO <= TRACK2_NO+1; + STEPPER2 <= 2'b11; + end + end + else + if(STEPPER2 == 2'b00) + begin + //if(TRACK2 != 17'h0) + if(TRACK2_NO != 8'd0) + begin + TRACK2 <= TRACK2_DOWN; + TRACK2_NO <= TRACK2_NO-1; + STEPPER2 <= 2'b11; + end + end + end + endcase + end + end +end + + + +reg [19:0] LATCHED_FDC_CNT_CT; +reg [7:0] LATCHED_FDC_CT; + + +always @(posedge FDC_CLK or negedge RESET_N) +begin + if(~RESET_N) + begin + LATCHED_FDC_CT <= 8'hFF; + //FDC_SIG_CLK <= 1'b0; + LATCHED_FDC_CNT_CT <= 20'hFFFFF; + end + else + begin + LATCHED_FDC_CT <= FDC_CT; + LATCHED_FDC_CNT_CT <= FDC_CNT_CT; + //FDC_SIG_CLK <= (LATCHED_FDC_CT!=FDC_CT); + end +end + +assign FDC_SIG = (FDC_CNT[7]|FDC_CNT_POLL[7]|FDC_CNT_DATA[7]|FDC_CNT_CT[19]|(LATCHED_FDC_CNT_CT==0)); + + +endmodule