diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf deleted file mode 100644 index 43a9e280..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "Azurian" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf deleted file mode 100644 index 3fc9a82a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf +++ /dev/null @@ -1,186 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:34:10 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Azurian_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Azurian.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Azurian -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# --------------------- -# start ENTITY(Azurian) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Azurian) -# ------------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt deleted file mode 100644 index 49293e17..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Azurian Attack port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf deleted file mode 100644 index f46206f2..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv deleted file mode 100644 index 1579c63b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Azurian -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Azurian( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Azurian Att.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian azurian( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", - X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", - X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", - X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", - X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", - X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", - X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", - X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", - X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", - X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", - X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", - X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", - X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", - X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", - X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", - X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", - X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", - X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", - X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE", - X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93", - X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B", - X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2", - X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87", - X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29", - X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9", - X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC", - X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE", - X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9", - X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83", - X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0", - X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37", - X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D", - X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd deleted file mode 100644 index 5f8a3a74..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(3), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(2), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 677a03d1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_2P_SH & I_1P_SH & I_COIN1 & I_1P_LE & I_1P_RI & I_2P_LE & I_2P_RI; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "10" & I_1P_LE & I_1P_RI & I_2P_LE & I_2P_RI & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd deleted file mode 100644 index e924e09e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd deleted file mode 100644 index dbe0d0d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip deleted file mode 100644 index 68624e41..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd deleted file mode 100644 index 37a2b849..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf deleted file mode 100644 index fd1b9b51..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "BlackHole" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf deleted file mode 100644 index 4a93cae8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:33:56 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# BlackHole_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlackHole.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY BlackHole - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ----------------------- -# start ENTITY(BlackHole) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(BlackHole) -# --------------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf deleted file mode 100644 index 063fa14d..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf +++ /dev/null @@ -1,52 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt deleted file mode 100644 index 4767d316..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Black Hole port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf deleted file mode 100644 index 403b2565..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv deleted file mode 100644 index b9ff9f01..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: BlackHole -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module BlackHole( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "BlackHole;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian blackhole( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_down,m_up}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd deleted file mode 100644 index b881e738..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 014e6f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library unisim; - use unisim.vcomponents.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 1d61cf9c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,72 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - -signal W_TABLE : std_logic := '1'; -- UP TYPE = 1; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else "000" & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000110"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd deleted file mode 100644 index dbe0d0d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v deleted file mode 100644 index eba1d598..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf deleted file mode 100644 index 3b0d4109..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "Catacomb" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf deleted file mode 100644 index 3b0a5c72..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 17:57:46 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Catacomb_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Catacomb.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Catacomb -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------- -# start ENTITY(Catacomb) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Catacomb) -# -------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt deleted file mode 100644 index 43f4d04c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Catacomb port to MiST by Gehstock --- 19 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf deleted file mode 100644 index 04069438..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv deleted file mode 100644 index 2ce725e5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Catacomb( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Catacomb;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian catacomb( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd deleted file mode 100644 index 08fc21b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 87a5b3b1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd deleted file mode 100644 index d06e75ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1H VID-Rom - k_rom : entity work.GALAXIAN_1H - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - - -- 1K VID-Rom - h_rom : entity work.GALAXIAN_1K - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf deleted file mode 100644 index 48fab33d..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:51:58 January 08, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:51:58 January 08, 2018" - -# Revisions - -PROJECT_REVISION = "ChewingGum" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf deleted file mode 100644 index 8543d295..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf +++ /dev/null @@ -1,187 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 09:12:33 May 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# ChewingGum_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY ChewingGum_MiST -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ----------------------------- -# start ENTITY(ChewingGum_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(ChewingGum_MiST) -# --------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ChewingGum_MiST.sv -set_global_assignment -name VHDL_FILE rtl/tripledrawpoker.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/k.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/h.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf deleted file mode 100644 index 4ecca971..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf +++ /dev/null @@ -1,57 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 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"" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt deleted file mode 100644 index 233da2d4..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: ChewingGum port to MiST by Gehstock --- 16 Mar 2019 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : add 1 Coin --- Up : add 10 Coin --- Left : increase Bet --- Right : decrease Bet --- SPACE/Fire : Start --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf deleted file mode 100644 index ce29a396..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv deleted file mode 100644 index ba86b690..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module ChewingGum_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "ChewingGum;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -tripledrawpoker tripledrawpoker( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}), - .P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv deleted file mode 100644 index 13aa31aa..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Pisces -( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Pisces;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian catacomb( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv deleted file mode 100644 index 214a4eff..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module TripleDrawPoker_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "TriDraPo;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -tripledrawpoker tripledrawpoker( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}), - .P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd deleted file mode 100644 index a44c4a1e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,442 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.sprom - generic map ( - init_file => "./ROM/prog.hex", - widthad_a => 14, - width_a => 8) - port map ( - address => W_A(13 downto 0), - clock => W_CLK_12M, - q => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index 49d7d7a8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,75 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- - crom : entity work.col - port map ( - clk => I_CLK_12M, - addr => W_6M_DO(6 downto 2), - data => W_COL_ROM_DO -); - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 841b2407..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,86 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_UP : in std_logic; -- active high - I_1P_DW : in std_logic; -- active high - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & "0" & I_1P_DW & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010000" & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - - - --- W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1; --- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & "0" & "0" & "0" & "0" & I_2P_START & I_1P_START; --- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; --- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - --- W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; --- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; --- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; --- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd deleted file mode 100644 index 555d96c4..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,430 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - I_BANK : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - k_rom : entity work.k_rom - port map ( - clk => I_CLK_12M, - addr => W_O_OBJ_ROM_A, - data => W_1K_D - ); - - h_rom : entity work.h_rom - port map ( - clk => I_CLK_12M, - addr => W_O_OBJ_ROM_A, - data => W_1H_D - ); ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ----------------------------------------------------------------------------------- - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd deleted file mode 100644 index 0b95e2fc..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd +++ /dev/null @@ -1,443 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA TripleDrawPoker --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity tripledrawpoker is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(7 downto 0); - P2_CSJUDLR : in std_logic_vector(7 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of tripledrawpoker is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(7), - I_COIN2 => P1_CSJUDLR(6), - I_1P_START => P2_CSJUDLR(0), - I_2P_START => P2_CSJUDLR(1), - I_1P_SH => P1_CSJUDLR(3), --- I_2P_SH => P2_CSJUDLR(4), - I_1P_UP => P1_CSJUDLR(0), --- I_2P_UP => P2_CSJUDLR(3), - I_1P_DW => P1_CSJUDLR(2), --- I_2P_DW => P2_CSJUDLR(2), - I_1P_LE => P1_CSJUDLR(5), --- I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(4), --- I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.prog - port map ( - clk => W_CLK_12M, - addr => W_A(13 downto 0), - data => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf deleted file mode 100644 index 7fbf41ef..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 11:56:24 October 19, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "11:56:24 October 19, 2019" - -# Revisions -PROJECT_REVISION = "DevilFish" diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf deleted file mode 100644 index 9a670612..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf +++ /dev/null @@ -1,185 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 01:03:05 October 23, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# DevilFish_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/DevilFish.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY DevilFish - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ----------------------- -# start ENTITY(DevilFish) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(DevilFish) -# --------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf deleted file mode 100644 index a455f0f5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf +++ /dev/null @@ -1,51 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt deleted file mode 100644 index c7b5b73f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Devil Fish port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf deleted file mode 100644 index ae2be577..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv deleted file mode 100644 index ded58af1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv +++ /dev/null @@ -1,187 +0,0 @@ -//============================================================================ -// Arcade: Devil Fish -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module DevilFish( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "DevilFish;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian devilfish( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -mist_video #(.COLOR_DEPTH(3)) mist_video( - .clk_sys(clk_24), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : 0), - .G(blankn ? g : 0), - .B(blankn ? b : 0), - .HSync(~hs), - .VSync(~vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), -// .ce_devide(1), - .scandoubler_disable(scandoublerD), - .scanlines(status[4:3]), - .ypbpr(ypbpr) - ); - -user_io #( - .STRLEN(($size(CONF_STR)>>3))) -user_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .C_bits(11)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -// Normal Rotated -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -//reg btn_fire2 = 0; -//reg btn_fire3 = 0; -reg btn_coin = 0; -wire key_pressed; -wire [7:0] key_code; -wire key_strobe; - -always @(posedge clk_24) begin - if(key_strobe) begin - case(key_code) - 'h75: btn_up <= key_pressed; // up - 'h72: btn_down <= key_pressed; // down - 'h6B: btn_left <= key_pressed; // left - 'h74: btn_right <= key_pressed; // right - 'h76: btn_coin <= key_pressed; // ESC - 'h05: btn_one_player <= key_pressed; // F1 - 'h06: btn_two_players <= key_pressed; // F2 -// 'h14: btn_fire3 <= key_pressed; // ctrl -// 'h11: btn_fire2 <= key_pressed; // alt - 'h29: btn_fire1 <= key_pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", - X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", - X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", - X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", - X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", - X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", - X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", - X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", - X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", - X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", - X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", - X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", - X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", - X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", - X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", - X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", - X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", - X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", - X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE", - X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93", - X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B", - X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2", - X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87", - X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29", - X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9", - X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC", - X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE", - X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9", - X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83", - X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0", - X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37", - X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D", - X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd deleted file mode 100644 index 05956ffa..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,452 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => W_CPU_NMIn, - NMI_n => '1', - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(10 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - - I_1P_UP => P1_CSJUDLR(3), - I_2P_UP => P2_CSJUDLR(3), - I_1P_DN => P1_CSJUDLR(2), - I_2P_DN => P2_CSJUDLR(2), - - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 51676803..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd deleted file mode 100644 index ca6808bf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(10 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(11,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 014e6f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library unisim; - use unisim.vcomponents.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 4c47368c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,78 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_UP : in std_logic; - I_2P_UP : in std_logic; - I_1P_DN : in std_logic; - I_2P_DN : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP & I_1P_DN & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & I_2P_DN & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd deleted file mode 100644 index 27a8432b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,434 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_BANK : std_logic; - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - W_OBJ_ROM_BANK<= not I_H_CNT(8); - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf index 8af2e72b..379b72eb 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf @@ -40,50 +40,12 @@ # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian_MiST.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd # Pin & Location Assignments # ========================== @@ -186,4 +148,105 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(Galaxian_MiST) # ------------------------- +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/kb.stp +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian_MiST.sv +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/kb_synth.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv +set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../../common/CPU/T80/T80.qip +set_global_assignment -name VHDL_FILE rtl/ROM/ROMS.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/rom_k.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/rom_h.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/prog.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/col.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/victory/prog.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/victory/k_rom.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/victory/h_rom.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/victory/col.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/pisces/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/omega/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/rom_k.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/rom_h.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/prog.vhd +set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe3-6.vhd" +set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe2-5.vhd" +set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe1-4.vhd" +set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/col.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/prog.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/k.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/h.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/col.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/azurian/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/ROM_PGM_0.vhd -hdl_version VHDL_2008 +set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc new file mode 100644 index 00000000..81d47ca9 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc @@ -0,0 +1,126 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf deleted file mode 100644 index 5f2094c1..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh new file mode 100755 index 00000000..e195513a --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +PROJECTS=" \ +GALAXIAN \ +MOONCR \ +AZURIAN \ +BLACKHOLE \ +CATACOMB \ +CHEWINGG \ +DEVILFSH \ +KINGBAL \ +MRDONIGH \ +OMEGA \ +ORBITRON \ +PISCES \ +UNIWARS \ +VICTORY \ +WAROFBUG \ +TRIPLEDR" + +for PROJECT in $PROJECTS; do + echo "Compiling $PROJECT" + sed -i "s/^.define NAME.*/\`define NAME \"$PROJECT\"/" rtl/Galaxian_MiST.sv + quartus_sh --flow compile Galaxian.qsf && cp output_files/Galaxian.rbf Releases/$PROJECT.rbf +done \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv index 4fd067af..263dacc0 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv @@ -1,8 +1,7 @@ //============================================================================ // Arcade: Galaxian // -// Port to MiSTer -// Copyright (C) 2017 Sorgelig +// Port to MiST // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free @@ -39,24 +38,59 @@ module Galaxian_MiST( `include "rtl\build_id.v" +// Choose one for name/built-in ROMset/features +`define NAME "GALAXIAN" +//`define NAME "MOONCR" +//`define NAME "AZURIAN" +//`define NAME "BLACKHOLE" +//`define NAME "CATACOMB" +//`define NAME "CHEWINGG" +//`define NAME "DEVILFSH" +//`define NAME "KINGBAL" +//`define NAME "MRDONIGH" +//`define NAME "OMEGA" +//`define NAME "ORBITRON" +//`define NAME "PISCES" +//`define NAME "UNIWARS" +//`define NAME "VICTORY" +//`define NAME "WAROFBUG" +//`define NAME "ZIGZAG" -- doesn't work, video gen issues +//`define NAME "TRIPLEDR" + +reg rotate_dir; + +always @(*) begin + if (`NAME == "MOONCR" || + `NAME == "DEVILFSH" || + `NAME == "KINGBAL" || + `NAME == "OMEGA" || + `NAME == "ORBITRON" || + `NAME == "VICTORY") + begin + rotate_dir = 1'b0; + end else begin + rotate_dir = 1'b1; + end +end + localparam CONF_STR = { - "Galaxian;;", + `NAME,";;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.55.",`BUILD_DATE + "O5,Blend,Off,On;", + "T0,Reset;", + "V,v2.00.",`BUILD_DATE }; assign LED = 1; assign AUDIO_R = AUDIO_L; -wire clk_24, clk_18, clk_12, clk_6; +wire clk_24, clk_12, clk_6; wire pll_locked; pll pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_24), - .c1(clk_18), .c2(clk_12), .c3(clk_6) ); @@ -68,20 +102,18 @@ wire [7:0] joystick_0; wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; +wire [7:0] audio_a, audio_b, audio_c; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a} + {2'b00, audio_c, 1'b0}; wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); wire [2:0] r,g,b; -galaxian galaxian +galaxian #(.name(`NAME)) galaxian ( - .W_CLK_18M(clk_18), .W_CLK_12M(clk_12), .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), + .I_RESET(status[0] | buttons[1]), .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), .W_R(r), @@ -92,19 +124,18 @@ galaxian galaxian .HBLANK(hb), .VBLANK(vb), .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) + .W_SDAT_B(audio_b), + .W_SDAT_C(audio_c) ); -video_mixer video_mixer( +mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video( .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), + .R(blankn ? r : 0), + .G(blankn ? g : 0), + .B(blankn ? b : 0), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), @@ -112,49 +143,48 @@ video_mixer video_mixer( .VGA_B(VGA_B), .VGA_VS(VGA_VS), .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) + .ce_divider(1'b1), + .rotate({rotate_dir,status[2]}), + .scandoubler_disable(scandoublerD), + .scanlines(status[4:3]), + .blend(status[5]), + .ypbpr(ypbpr) ); - -mist_io #( + +user_io #( .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), +user_io( + .clk_sys (clk_12 ), .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), .joystick_1 (joystick_1 ), .status (status ) ); - -dac #( - .msbi_g(15)) + +dac #(11) dac( - .clk_i(clk_24), + .clk_i(clk_12), .res_n_i(1), - .dac_i({audio,5'd0}), + .dac_i(audio), .dac_o(AUDIO_L) ); -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; +// Rotated Normal +wire m_up = ~status[2] ? (rotate_dir ? btn_left | joystick_0[1] | joystick_1[1] : btn_right | joystick_0[0] | joystick_1[0] ) : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? (rotate_dir ? btn_right | joystick_0[0] | joystick_1[0] : btn_left | joystick_0[1] | joystick_1[1] ) : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? (rotate_dir ? btn_down | joystick_0[2] | joystick_1[2] : btn_up | joystick_0[3] | joystick_1[3] ) : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? (rotate_dir ? btn_up | joystick_0[3] | joystick_1[3] : btn_down | joystick_0[2] | joystick_1[2] ) : btn_right | joystick_0[0] | joystick_1[0]; wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; @@ -168,24 +198,23 @@ reg btn_fire1 = 0; reg btn_fire2 = 0; reg btn_fire3 = 0; reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space +always @(posedge clk_12) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space endcase end end diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd new file mode 100644 index 00000000..6ee75692 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd @@ -0,0 +1,292 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +generic ( + name : string := "GALAXIAN" +); +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is +begin + +rom_pgm: if name="GALAXIAN" generate + mc_roms : entity work.GALAXIAN_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="MOONCR" generate + mc_roms : entity work.MOONCR_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="AZURIAN" generate + mc_roms : entity work.AZURIAN_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="BLACKHOLE" generate + mc_roms : entity work.BLACKHOLE_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="CATACOMB" generate + mc_roms : entity work.CATACOMB_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="CHEWINGG" generate + mc_roms : entity work.CHEWINGGUM_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="DEVILFSH" generate + mc_roms : entity work.DEVILFISH_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="KINGBAL" generate + mc_roms : entity work.kb_prog + port map (clk => clk, addr => addr, data => data ); + elsif name="MRDONIGH" generate + mc_roms : entity work.MRDONIGHTMARE_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="OMEGA" generate + mc_roms : entity work.OMEGA_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="ORBITRON" generate + mc_roms : entity work.ORBITRON_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="PISCES" generate + mc_roms : entity work.PISCES_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="UNIWARS" generate + mc_roms : entity work.UNIWARS_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="VICTORY" generate + mc_roms : entity work.VICTORY_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="WAROFBUG" generate + mc_roms : entity work.WAROFBUGS_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="ZIGZAG" generate + mc_roms : entity work.ZIGZAG_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); + elsif name="TRIPLEDR" generate + mc_roms : entity work.TRIPLEDRAWPOKER_ROM_PGM_0 + port map (clk => clk, addr => addr, data => data ); +end generate; + +end architecture; + +------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_1K is +generic ( + name : string := "GALAXIAN" +); +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_1K is +begin + +rom_pgm: if name="GALAXIAN" generate + mc_roms : entity work.GALAXIAN_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="MOONCR" generate + mc_roms : entity work.MOONCR_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="AZURIAN" generate + mc_roms : entity work.AZURIAN_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="BLACKHOLE" generate + mc_roms : entity work.BLACKHOLE_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="CATACOMB" generate + mc_roms : entity work.CATACOMB_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="CHEWINGG" generate + mc_roms : entity work.CHEWINGGUM_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="DEVILFSH" generate + mc_roms : entity work.DEVILFISH_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="KINGBAL" generate + mc_roms : entity work.KB_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="MRDONIGH" generate + mc_roms : entity work.MRDONIGHTMARE_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="OMEGA" generate + mc_roms : entity work.OMEGA_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="ORBITRON" generate + mc_roms : entity work.ORBITRON_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="PISCES" generate + mc_roms : entity work.PISCES_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="UNIWARS" generate + mc_roms : entity work.UNIWARS_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="VICTORY" generate + mc_roms : entity work.VICTORY_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="WAROFBUG" generate + mc_roms : entity work.WAROFBUGS_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="ZIGZAG" generate + mc_roms : entity work.ZIGZAG_1K + port map (clk => clk, addr => addr, data => data ); + elsif name="TRIPLEDR" generate + mc_roms : entity work.TRIPLEDRAWPOKER_1K + port map (clk => clk, addr => addr(10 downto 0), data => data ); +end generate; + +end architecture; + +------------------------- + +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_1H is +generic ( + name : string := "GALAXIAN" +); +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_1H is +begin + +rom_pgm: if name="GALAXIAN" generate + mc_roms : entity work.GALAXIAN_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="MOONCR" generate + mc_roms : entity work.MOONCR_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="AZURIAN" generate + mc_roms : entity work.AZURIAN_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="BLACKHOLE" generate + mc_roms : entity work.BLACKHOLE_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="CATACOMB" generate + mc_roms : entity work.CATACOMB_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="CHEWINGG" generate + mc_roms : entity work.CHEWINGGUM_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="DEVILFSH" generate + mc_roms : entity work.DEVILFISH_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="KINGBAL" generate + mc_roms : entity work.KB_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="MRDONIGH" generate + mc_roms : entity work.MRDONIGHTMARE_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="OMEGA" generate + mc_roms : entity work.OMEGA_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="ORBITRON" generate + mc_roms : entity work.ORBITRON_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="PISCES" generate + mc_roms : entity work.PISCES_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="UNIWARS" generate + mc_roms : entity work.UNIWARS_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="VICTORY" generate + mc_roms : entity work.VICTORY_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="WAROFBUG" generate + mc_roms : entity work.WAROFBUGS_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); + elsif name="ZIGZAG" generate + mc_roms : entity work.ZIGZAG_1H + port map (clk => clk, addr => addr, data => data ); + elsif name="TRIPLEDR" generate + mc_roms : entity work.TRIPLEDRAWPOKER_1H + port map (clk => clk, addr => addr(10 downto 0), data => data ); +end generate; + +end architecture; + +------------------------- + +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_6L is +generic ( + name : string := "GALAXIAN" +); +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_6L is +begin + +rom_pgm: if name="GALAXIAN" generate + mc_roms : entity work.GALAXIAN_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="MOONCR" generate + mc_roms : entity work.MOONCR_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="AZURIAN" generate + mc_roms : entity work.AZURIAN_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="BLACKHOLE" generate + mc_roms : entity work.BLACKHOLE_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="CATACOMB" generate + mc_roms : entity work.CATACOMB_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="CHEWINGG" generate + mc_roms : entity work.CHEWINGGUM_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="DEVILFSH" generate + mc_roms : entity work.DEVILFISH_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="KINGBAL" generate + mc_roms : entity work.KB_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="MRDONIGH" generate + mc_roms : entity work.MRDONIGHTMARE_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="OMEGA" generate + mc_roms : entity work.OMEGA_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="ORBITRON" generate + mc_roms : entity work.ORBITRON_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="PISCES" generate + mc_roms : entity work.PISCES_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="UNIWARS" generate + mc_roms : entity work.UNIWARS_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="VICTORY" generate + mc_roms : entity work.VICTORY_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="WAROFBUG" generate + mc_roms : entity work.WAROFBUGS_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="ZIGZAG" generate + mc_roms : entity work.ZIGZAG_6L + port map (clk => clk, addr => addr, data => data ); + elsif name="TRIPLEDR" generate + mc_roms : entity work.TRIPLEDRAWPOKER_6L + port map (clk => clk, addr => addr, data => data ); +end generate; + +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd index 6f39d31b..6f23af28 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity AZURIAN_1H is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ entity GALAXIAN_1H is ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of AZURIAN_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd index 942316be..3e2ac497 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity AZURIAN_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of AZURIAN_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd similarity index 92% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd index 69425a6e..55ee53d7 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity AZURIAN_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of AZURIAN_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( x"00",x"7A",x"36",x"07",x"00",x"F0",x"38",x"1F", -- 0x0000 diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd index 5a0cf5cd..fbbad63c 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity AZURIAN_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of AZURIAN_ROM_PGM_0 is type rom is array(0 to 12287) of std_logic_vector(7 downto 0); signal rom_data: rom := ( x"00",x"AF",x"32",x"01",x"70",x"C3",x"C8",x"00", -- 0x0000 diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd index 73af8474..e9fb62b7 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity BLACKHOLE_1H is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of BLACKHOLE_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd index b5bcbc4e..dd80c0ea 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity BLACKHOLE_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of BLACKHOLE_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd index 2f811f7d..0b62b833 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity BLACKHOLE_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of BLACKHOLE_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd index 3ca80bee..63a5f7a1 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity BLACKHOLE_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of BLACKHOLE_ROM_PGM_0 is type rom is array(0 to 12287) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"50",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd index dec55c15..d4d2f2b6 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1H is +entity CATACOMB_1H is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1H is ); end; -architecture RTL of GALAXIAN_1H is +architecture RTL of CATACOMB_1H is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd index 4ed5bb4c..4b3dbb2d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1K is +entity CATACOMB_1K is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1K is ); end; -architecture RTL of GALAXIAN_1K is +architecture RTL of CATACOMB_1K is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd similarity index 93% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd index e989225e..b160e0df 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_6L is +entity CATACOMB_6L is port ( CLK : in std_logic; ADDR : in std_logic_vector(4 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_6L is ); end; -architecture RTL of GALAXIAN_6L is +architecture RTL of CATACOMB_6L is type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd index 8b3669d9..8e4a78c4 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity ROM_PGM_0 is +entity CATACOMB_ROM_PGM_0 is port ( CLK : in std_logic; ADDR : in std_logic_vector(13 downto 0); @@ -12,7 +12,7 @@ entity ROM_PGM_0 is ); end; -architecture RTL of ROM_PGM_0 is +architecture RTL of CATACOMB_ROM_PGM_0 is type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd similarity index 90% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd index e4323869..635b1893 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity col is +entity CHEWINGGUM_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of col is +architecture prom of CHEWINGGUM_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd index a14e3a66..96927b51 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity h_rom is +entity CHEWINGGUM_1H is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of h_rom is +architecture prom of CHEWINGGUM_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd index 794537b6..1107bf5d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity k_rom is +entity CHEWINGGUM_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of k_rom is +architecture prom of CHEWINGGUM_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd index b4dc5a23..8c2b8807 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity prog is +entity CHEWINGGUM_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of prog is +architecture prom of CHEWINGGUM_ROM_PGM_0 is type rom is array(0 to 10239) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"C3",X"4A",X"00",X"BA",X"CA",X"69",X"B5",X"6E",X"C3",X"00",X"06",X"54",X"16",X"2A",X"6E",X"3A", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd index 9a0ffdb7..9fad8ef9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity DEVILFISH_1H is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of DEVILFISH_1H is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"1F",X"00",X"30",X"34",X"6C",X"18",X"13",X"8F",X"8E", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd index 50436b22..7e5eb71f 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity DEVILFISH_1K is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of DEVILFISH_1K is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"00",X"0E",X"3F",X"7F",X"73",X"E3",X"E3",X"00",X"00",X"00",X"80",X"E0",X"E0",X"F0",X"F0", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd index 7432acf2..71db70e1 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity DEVILFISH_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of DEVILFISH_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"17",X"C7",X"F6",X"00",X"17",X"C0",X"3F",X"00",X"07",X"C0",X"3F",X"00",X"C0",X"C4",X"07", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd index 84f3475d..bd8eb669 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity DEVILFISH_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of DEVILFISH_ROM_PGM_0 is type rom is array(0 to 16383) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"8E",X"00",X"FF",X"C3",X"73",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1H.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1H.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1K.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1K.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_6L.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_6L.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd index ee7591a2..6bb49253 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity GALAXIAN_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of GALAXIAN_ROM_PGM_0 is type rom is array(0 to 10239) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"55",X"1A",X"FF",X"3A",X"07",X"40",X"0F",X"D0",X"33",X"33",X"C9", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd similarity index 93% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd index be83394e..f305ab52 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity col is +entity kb_6l is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of col is +architecture prom of kb_6l is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"D8",X"F0",X"07",X"00",X"3F",X"F6",X"07",X"00",X"F6",X"38",X"07",X"00",X"3F",X"38",X"2F", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe1-4.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe1-4.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2-5.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe2-5.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2-5.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe2-5.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe3-6.vhd similarity index 100% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe3-6.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd index 8f7b15f4..e6c4325d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity prog is +entity kb_prog is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of prog is +architecture prom of kb_prog is type rom is array(0 to 12287) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"22",X"13",X"00",X"3A",X"2F",X"43",X"11",X"30",X"43",X"18",X"3B", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd index a9b2202b..c4f0a4d9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity rom_h is +entity kb_1h is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of rom_h is +architecture prom of kb_1h is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd index b6a9c509..751080e9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity rom_k is +entity kb_1k is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of rom_k is +architecture prom of kb_1k is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd index b9ce0580..7cbd2290 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity MOONCR_1H is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of MOONCR_1H is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd index 75eca2cc..0e9f18d7 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity MOONCR_1K is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of MOONCR_1K is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd index 9cf7380a..eb484000 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity MOONCR_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of MOONCR_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd index 742f9975..510c6a3d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity MOONCR_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of MOONCR_ROM_PGM_0 is type rom is array(0 to 16383) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"AD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd index df224504..8948e31d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity MRDONIGHTMARE_1H is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of MRDONIGHTMARE_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd index 25afe613..20c69ec9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity MRDONIGHTMARE_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of MRDONIGHTMARE_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd similarity index 90% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd index 9d5c2fdc..9b3f5843 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity MRDONIGHTMARE_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of MRDONIGHTMARE_6L is type rom is array(31 downto 0) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"C6",X"07",X"76",X"00",X"C0",X"80",X"1E",X"00",X"80",X"C0",X"1E",X"00",X"76",X"C0",X"F6",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd index 1b828ed1..bc8150b0 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity MRDONIGHTMARE_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of MRDONIGHTMARE_ROM_PGM_0 is type rom is array(0 to 10239) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"D0",X"00",X"3A",X"36",X"40",X"3C",X"E6",X"07",X"32",X"36",X"40", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd index f7d8d13f..21a028d8 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1H is +entity OMEGA_1H is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1H is ); end; -architecture RTL of GALAXIAN_1H is +architecture RTL of OMEGA_1H is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd index cb6701eb..957bead1 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1K is +entity OMEGA_1K is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1K is ); end; -architecture RTL of GALAXIAN_1K is +architecture RTL of OMEGA_1K is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd similarity index 93% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd index e989225e..0f72c46c 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_6L is +entity OMEGA_6L is port ( CLK : in std_logic; ADDR : in std_logic_vector(4 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_6L is ); end; -architecture RTL of GALAXIAN_6L is +architecture RTL of OMEGA_6L is type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd index 33721787..19fe3086 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity ROM_PGM_0 is +entity OMEGA_ROM_PGM_0 is port ( CLK : in std_logic; ADDR : in std_logic_vector(13 downto 0); @@ -12,7 +12,7 @@ entity ROM_PGM_0 is ); end; -architecture RTL of ROM_PGM_0 is +architecture RTL of OMEGA_ROM_PGM_0 is type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd index dacb0a04..a813db5b 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity ORBITRON_1H is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of ORBITRON_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd index fd77d08e..ae3bd9dc 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity ORBITRON_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of ORBITRON_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd index 9cf7380a..ac18266d 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity ORBITRON_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of ORBITRON_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd index 401c50ae..c13d7bde 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity ORBITRON_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of ORBITRON_ROM_PGM_0 is type rom is array(0 to 10239) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"31",X"00",X"44",X"C3",X"41",X"02",X"00",X"FF",X"FF",X"FF",X"FF",X"20",X"20",X"20",X"20",X"20", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd index 787ca26f..25d7b89c 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1H is +entity PISCES_1H is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1H is ); end; -architecture RTL of GALAXIAN_1H is +architecture RTL of PISCES_1H is type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd index 693ba290..c6553365 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1K is +entity PISCES_1K is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1K is ); end; -architecture RTL of GALAXIAN_1K is +architecture RTL of PISCES_1K is type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd similarity index 93% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd index 222709ac..19e98de8 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_6L is +entity PISCES_6L is port ( CLK : in std_logic; ADDR : in std_logic_vector(4 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_6L is ); end; -architecture RTL of GALAXIAN_6L is +architecture RTL of PISCES_6L is type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd index f49d198b..55a5db3b 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity ROM_PGM_0 is +entity PISCES_ROM_PGM_0 is port ( CLK : in std_logic; ADDR : in std_logic_vector(13 downto 0); @@ -12,7 +12,7 @@ entity ROM_PGM_0 is ); end; -architecture RTL of ROM_PGM_0 is +architecture RTL of PISCES_ROM_PGM_0 is type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd new file mode 100644 index 00000000..a74a2d51 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity TRIPLEDRAWPOKER_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of TRIPLEDRAWPOKER_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00", + X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"0F",X"07",X"03",X"03",X"03",X"07",X"0F",X"1F", + X"1F",X"0F",X"07",X"03",X"03",X"03",X"07",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"91",X"98", + X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"81",X"80",X"FF",X"FF",X"E3",X"E1",X"E0",X"F0",X"F8",X"F8", + X"80",X"88",X"8C",X"8E",X"8F",X"8F",X"8F",X"FF",X"78",X"38",X"18",X"00",X"00",X"81",X"C3",X"FF", + X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"81",X"80",X"FF",X"FF",X"E3",X"E1",X"E0",X"F0",X"F8",X"F8", + X"80",X"88",X"8C",X"8E",X"8F",X"8F",X"8F",X"FF",X"78",X"38",X"18",X"00",X"00",X"81",X"C3",X"FF", + X"FF",X"FF",X"E7",X"C7",X"87",X"8F",X"8F",X"8E",X"FF",X"FF",X"F3",X"F1",X"F0",X"F8",X"F8",X"38", + X"C0",X"9F",X"1F",X"01",X"01",X"01",X"1F",X"1F",X"03",X"F9",X"F8",X"80",X"80",X"80",X"F8",X"F8", + X"FF",X"FF",X"E7",X"C7",X"87",X"8F",X"8F",X"8E",X"FF",X"FF",X"F3",X"F1",X"F0",X"F8",X"F8",X"38", + X"00",X"1F",X"1F",X"19",X"19",X"19",X"18",X"18",X"00",X"F8",X"F8",X"98",X"98",X"98",X"18",X"18", + X"FF",X"F1",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"87", + X"91",X"91",X"80",X"80",X"80",X"91",X"91",X"FF",X"C3",X"E1",X"00",X"00",X"00",X"FF",X"FF",X"FF", + X"FF",X"F1",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"87", + X"91",X"91",X"80",X"80",X"80",X"91",X"91",X"FF",X"C3",X"E1",X"00",X"00",X"00",X"FF",X"FF",X"FF", + X"FF",X"FF",X"E7",X"C6",X"86",X"86",X"8E",X"8E",X"FF",X"FF",X"00",X"00",X"00",X"38",X"38",X"38", + X"00",X"1F",X"1F",X"18",X"18",X"18",X"18",X"00",X"38",X"38",X"38",X"38",X"38",X"78",X"FF",X"FF", + X"FF",X"FF",X"E7",X"C6",X"86",X"86",X"8E",X"8E",X"FF",X"FF",X"00",X"00",X"00",X"38",X"38",X"38", + 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Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd new file mode 100644 index 00000000..bbfbe2d1 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity TRIPLEDRAWPOKER_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of TRIPLEDRAWPOKER_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF", + X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"F0",X"F8",X"FC",X"FC",X"FC",X"F8",X"F0",X"E0", + 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X"FF",X"E7",X"E7",X"07",X"07",X"E7",X"E7",X"FF",X"FF",X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8", + X"FF",X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0", + X"FF",X"0F",X"07",X"67",X"67",X"67",X"07",X"0F",X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"FF", + X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd new file mode 100644 index 00000000..bf710e68 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity TRIPLEDRAWPOKER_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of TRIPLEDRAWPOKER_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C0",X"07",X"FF",X"00",X"00",X"07",X"FF",X"C0",X"00",X"3F",X"07",X"C0",X"00",X"17",X"3F",X"C0", + X"00",X"C7",X"3F",X"C0",X"00",X"38",X"3F",X"C0",X"00",X"3F",X"17",X"C0",X"00",X"07",X"F8",X"C0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd new file mode 100644 index 00000000..a9eb6f48 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd @@ -0,0 +1,790 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity TRIPLEDRAWPOKER_ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of TRIPLEDRAWPOKER_ROM_PGM_0 is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"ED",X"56",X"31",X"00",X"44",X"C3",X"7B",X"00",X"E5",X"C5",X"F5",X"04",X"0C",X"C3",X"71",X"00", + X"85",X"6F",X"30",X"01",X"24",X"7E",X"C9",X"FF",X"E5",X"B7",X"ED",X"52",X"E1",X"C9",X"28",X"28", + X"E5",X"77",X"23",X"10",X"FC",X"E1",X"C9",X"AD",X"E1",X"87",X"85",X"6F",X"30",X"3C",X"18",X"39", + X"47",X"00",X"FD",X"36",X"41",X"00",X"28",X"E1",X"C3",X"29",X"0B",X"D5",X"F5",X"BE",X"30",X"05", + X"16",X"00",X"5F",X"19",X"19",X"23",X"5E",X"23",X"56",X"EB",X"F1",X"D1",X"E9",X"A7",X"C8",X"E5", + X"D5",X"C5",X"06",X"00",X"4F",X"09",X"EB",X"09",X"41",X"1B",X"2B",X"1A",X"BE",X"20",X"02",X"10", + X"F8",X"79",X"C1",X"D1",X"E1",X"C9",X"C3",X"27",X"08",X"24",X"7E",X"23",X"66",X"6F",X"E9",X"77", + X"23",X"0D",X"C2",X"6F",X"00",X"10",X"F8",X"F1",X"C1",X"E1",X"C9",X"FD",X"21",X"8E",X"40",X"21", + X"84",X"00",X"18",X"04",X"CD",X"BC",X"00",X"E9",X"F3",X"CD",X"6C",X"0A",X"01",X"00",X"04",X"11", + X"00",X"40",X"AF",X"CD",X"7B",X"0A",X"12",X"13",X"0D",X"20",X"FB",X"10",X"F6",X"CD",X"35",X"07", + X"CD",X"DD",X"02",X"CD",X"8E",X"04",X"CD",X"2E",X"06",X"CD",X"FC",X"15",X"CD",X"C2",X"02",X"28", + X"07",X"38",X"05",X"CD",X"C1",X"08",X"18",X"03",X"CD",X"BA",X"08",X"E9",X"F5",X"18",X"1C",X"D5", + X"E5",X"FD",X"E5",X"D1",X"21",X"02",X"00",X"7D",X"21",X"00",X"00",X"19",X"36",X"00",X"21",X"48", + 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X"C3",X"24",X"2E",X"F5",X"FD",X"7E",X"38",X"3C",X"CA",X"A3",X"2C",X"3E",X"00",X"32",X"89",X"40", + X"C3",X"D6",X"2C",X"FD",X"7E",X"02",X"E6",X"0F",X"C2",X"D6",X"2C",X"3A",X"89",X"40",X"E6",X"01", + X"CA",X"D6",X"2C",X"FD",X"7E",X"02",X"E6",X"F0",X"C2",X"F4",X"2C",X"3A",X"89",X"40",X"E6",X"02", + X"CA",X"F4",X"2C",X"FD",X"7E",X"03",X"E6",X"0F",X"C2",X"3A",X"2D",X"3A",X"89",X"40",X"E6",X"04", + X"CA",X"3A",X"2D",X"C3",X"80",X"2D",X"3A",X"89",X"40",X"F6",X"01",X"32",X"89",X"40",X"21",X"EF", + X"2C",X"CD",X"E9",X"2D",X"21",X"03",X"17",X"CD",X"BE",X"2D",X"CD",X"59",X"1C",X"F1",X"C9",X"01", + X"00",X"00",X"00",X"C9",X"3A",X"89",X"40",X"F6",X"02",X"32",X"89",X"40",X"3E",X"0A",X"CD",X"FA", + X"26",X"21",X"12",X"2D",X"CD",X"E9",X"2D",X"21",X"16",X"2D",X"CD",X"BE",X"2D",X"CD",X"74",X"1C", + X"F1",X"C9",X"10",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"40",X"00", + X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"04", + X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"20",X"00",X"00",X"3A",X"89",X"40",X"F6",X"04",X"32", + X"89",X"40",X"3E",X"0A",X"CD",X"FA",X"26",X"21",X"58",X"2D",X"CD",X"E9",X"2D",X"21",X"5C",X"2D", + X"CD",X"BE",X"2D",X"CD",X"8F",X"1C",X"F1",X"C9",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00", + X"00",X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"10",X"00",X"00", + X"00",X"20",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"02",X"00", + X"3E",X"0A",X"CD",X"FA",X"26",X"21",X"96",X"2D",X"CD",X"E9",X"2D",X"21",X"9A",X"2D",X"CD",X"BE", + X"2D",X"CD",X"AA",X"1C",X"F1",X"C9",X"00",X"10",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"20", + X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00", + X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"20",X"00",X"E5",X"D5", + X"C5",X"F5",X"E5",X"FD",X"E5",X"E1",X"11",X"06",X"00",X"19",X"EB",X"6B",X"62",X"C1",X"3E",X"09", + X"F5",X"3E",X"04",X"CD",X"C1",X"03",X"03",X"03",X"03",X"03",X"23",X"23",X"23",X"23",X"5D",X"54", + X"F1",X"3D",X"20",X"EC",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"E5",X"FD",X"E5", + X"E1",X"01",X"02",X"00",X"09",X"EB",X"42",X"4B",X"E1",X"3E",X"04",X"CD",X"09",X"2E",X"FD",X"7E", + X"37",X"CD",X"33",X"04",X"F1",X"C1",X"D1",X"E1",X"C9",X"A7",X"C8",X"E5",X"D5",X"C5",X"F5",X"F5", + X"97",X"0A",X"9E",X"27",X"12",X"03",X"13",X"23",X"E3",X"25",X"E3",X"20",X"F4",X"E1",X"E1",X"7C", + X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"21",X"5F",X"40",X"3A",X"8D",X"40",X"87",X"4F", + X"06",X"00",X"09",X"11",X"35",X"00",X"73",X"23",X"72",X"CD",X"4F",X"2A",X"3E",X"00",X"CD",X"27", + X"17",X"FD",X"36",X"36",X"FF",X"CD",X"59",X"2E",X"CD",X"77",X"2E",X"CD",X"A0",X"2E",X"CD",X"FE", + X"1C",X"CD",X"58",X"18",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD", + X"E5",X"E1",X"01",X"2B",X"00",X"09",X"06",X"05",X"0F",X"38",X"02",X"36",X"00",X"23",X"10",X"F8", + X"CD",X"58",X"18",X"F1",X"C1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",X"E5",X"E1", + X"01",X"2B",X"00",X"09",X"06",X"05",X"0F",X"38",X"10",X"36",X"0E",X"CD",X"58",X"18",X"CD",X"E5", + X"1C",X"0E",X"1E",X"CD",X"15",X"08",X"0D",X"20",X"FA",X"23",X"10",X"EA",X"F1",X"C1",X"E1",X"C9", + X"E5",X"D5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",X"E5",X"E1",X"01",X"2B",X"00",X"09",X"5D",X"54", + X"06",X"05",X"0F",X"F5",X"38",X"15",X"CD",X"2C",X"05",X"4F",X"E6",X"0F",X"28",X"F8",X"FE",X"0E", + X"30",X"F4",X"79",X"E6",X"3F",X"CD",X"D4",X"2E",X"28",X"EC",X"12",X"13",X"F1",X"10",X"E3",X"F1", + X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"F5",X"21",X"4D",X"40",X"06",X"0E",X"BE",X"23",X"28",X"0D", + X"10",X"FA",X"2A",X"5D",X"40",X"77",X"23",X"22",X"5D",X"40",X"3E",X"01",X"B7",X"C1",X"78",X"C1", + X"E1",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"FF",X"FF",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F", + X"3F",X"7F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F", + X"7F",X"FF",X"FF",X"3F",X"FF",X"FF",X"FF",X"3F",X"3F",X"3F",X"FF",X"FF",X"FF",X"7F",X"3F",X"3F", + X"FF",X"3F",X"BF",X"FF",X"BF",X"3F",X"3F",X"3F",X"3F",X"3F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd index 8cbdb31c..a560a391 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity ROM_PGM_0 is +entity UNIWARS_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of ROM_PGM_0 is +architecture prom of UNIWARS_ROM_PGM_0 is type rom is array(0 to 16383) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"AF",X"32",X"01",X"70",X"C3",X"59",X"1A",X"FF",X"3A",X"07",X"40",X"0F",X"D0",X"33",X"33",X"C9", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd index 68faa089..f5dcbba9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1H is +entity UNIWARS_1H is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1H is +architecture prom of UNIWARS_1H is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd index 479fc3d9..40a985b7 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_1K is +entity UNIWARS_1K is port ( clk : in std_logic; addr : in std_logic_vector(11 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_1K is +architecture prom of UNIWARS_1K is type rom is array(0 to 4095) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd index 3c34489f..f8909bd7 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity GALAXIAN_6L is +entity UNIWARS_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of GALAXIAN_6L is +architecture prom of UNIWARS_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"E8",X"17",X"3F",X"00",X"2F",X"87",X"20",X"00",X"FF",X"3F",X"38",X"00",X"83",X"3F",X"06", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd similarity index 91% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd index fa425023..386b59eb 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity col is +entity VICTORY_6L is port ( clk : in std_logic; addr : in std_logic_vector(4 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of col is +architecture prom of VICTORY_6L is type rom is array(0 to 31) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"07",X"15",X"E4",X"00",X"BC",X"6C",X"6C",X"00",X"38",X"00",X"A7",X"00",X"00",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd index f4d82a16..343a0b65 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity h_rom is +entity VICTORY_1H is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of h_rom is +architecture prom of VICTORY_1H is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd index cd100cb3..59fcdb19 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity k_rom is +entity VICTORY_1K is port ( clk : in std_logic; addr : in std_logic_vector(10 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of k_rom is +architecture prom of VICTORY_1K is type rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd index c8fdb367..ef448913 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all,ieee.numeric_std.all; -entity prog is +entity VICTORY_ROM_PGM_0 is port ( clk : in std_logic; addr : in std_logic_vector(13 downto 0); @@ -9,7 +9,7 @@ port ( ); end entity; -architecture prom of prog is +architecture prom of VICTORY_ROM_PGM_0 is type rom is array(0 to 10239) of std_logic_vector(7 downto 0); signal rom_data: rom := ( X"31",X"00",X"44",X"C3",X"40",X"02",X"00",X"FF",X"FF",X"FF",X"FF",X"20",X"20",X"20",X"20",X"20", diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd index c5c2e037..6e7dde14 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd @@ -1,10 +1,9 @@ -- generated with romgen v3.0 by MikeJ library ieee; use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity ROM_PGM_0 is +entity WAROFBUGS_ROM_PGM_0 is port ( CLK : in std_logic; ADDR : in std_logic_vector(13 downto 0); @@ -12,11 +11,11 @@ entity ROM_PGM_0 is ); end; -architecture RTL of ROM_PGM_0 is +architecture prom of WAROFBUGS_ROM_PGM_0 is type ROM_ARRAY is array(0 to 10087) of std_logic_vector(7 downto 0); - constant ROM : ROM_ARRAY := ( + signal ROM : ROM_ARRAY := ( x"31",x"00",x"44",x"AF",x"C3",x"00",x"03",x"C3", -- 0x0000 x"46",x"0B",x"55",x"50",x"4F",x"00",x"84",x"54", -- 0x0008 x"77",x"23",x"10",x"FC",x"C9",x"06",x"C2",x"4C", -- 0x0010 @@ -1281,10 +1280,12 @@ architecture RTL of ROM_PGM_0 is ); begin +process(clk) +begin + if rising_edge(clk) then + data <= ROM(to_integer(unsigned(addr))); + end if; - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; +end process; + +end prom; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd index a6558456..1fea1ba6 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1H is +entity WAROFBUGS_1H is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1H is ); end; -architecture RTL of GALAXIAN_1H is +architecture RTL of WAROFBUGS_1H is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd similarity index 99% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd index 25f4acf1..3daf8157 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_1K is +entity WAROFBUGS_1K is port ( CLK : in std_logic; ADDR : in std_logic_vector(10 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_1K is ); end; -architecture RTL of GALAXIAN_1K is +architecture RTL of WAROFBUGS_1K is type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd similarity index 93% rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd index 7eb01da4..64471aa9 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd @@ -4,7 +4,7 @@ library ieee; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity GALAXIAN_6L is +entity WAROFBUGS_6L is port ( CLK : in std_logic; ADDR : in std_logic_vector(4 downto 0); @@ -12,7 +12,7 @@ entity GALAXIAN_6L is ); end; -architecture RTL of GALAXIAN_6L is +architecture RTL of WAROFBUGS_6L is type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd new file mode 100644 index 00000000..c491b15e --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ZIGZAG_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ZIGZAG_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",X"00",X"F0",X"15",X"1F",X"00",X"F6",X"06",X"07", + X"00",X"91",X"07",X"F6",X"00",X"F0",X"FE",X"07",X"00",X"38",X"07",X"FE",X"00",X"07",X"3F",X"FE"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd new file mode 100644 index 00000000..57565562 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ZIGZAG_ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ZIGZAG_ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"32",X"01",X"70",X"C3",X"82",X"01",X"84",X"AF",X"21",X"06",X"70",X"77",X"23",X"77",X"C9", + X"F5",X"C5",X"D5",X"E5",X"5E",X"23",X"56",X"23",X"E5",X"C1",X"EB",X"11",X"20",X"00",X"0A",X"FE", + X"FF",X"28",X"07",X"D6",X"30",X"77",X"03",X"19",X"18",X"F4",X"E1",X"D1",X"C1",X"F1",X"C9",X"67", + X"21",X"07",X"42",X"06",X"1B",X"71",X"23",X"23",X"10",X"FB",X"3A",X"00",X"78",X"21",X"00",X"42", + X"11",X"40",X"42",X"06",X"20",X"AF",X"77",X"12",X"13",X"23",X"23",X"10",X"F9",X"06",X"20",X"12", + X"13",X"10",X"FC",X"C9",X"DB",X"28",X"0C",X"D9",X"CD",X"12",X"DA",X"D9",X"28",X"0A",X"CD",X"3A", + X"84",X"18",X"DF",X"CD",X"35",X"84",X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"AF",X"32", + X"01",X"70",X"3A",X"00",X"78",X"21",X"00",X"42",X"01",X"60",X"00",X"11",X"00",X"58",X"ED",X"B0", + X"21",X"BB",X"42",X"34",X"21",X"84",X"42",X"CD",X"E2",X"00",X"CD",X"2F",X"31",X"21",X"60",X"42", + X"01",X"20",X"00",X"11",X"60",X"58",X"ED",X"B0",X"CD",X"1F",X"34",X"3A",X"CE",X"42",X"B7",X"C4", + X"F4",X"00",X"CD",X"0B",X"01",X"CD",X"67",X"01",X"CD",X"8A",X"36",X"21",X"02",X"70",X"3E",X"FF", + X"77",X"00",X"00",X"C3",X"97",X"20",X"AF",X"21",X"02",X"70",X"77",X"7A",X"B7",X"28",X"0E",X"31", + X"00",X"48",X"21",X"22",X"04",X"E5",X"3E",X"01",X"32",X"01",X"70",X"ED",X"45",X"FD",X"E1",X"DD", + X"E1",X"E1",X"D1",X"C1",X"3E",X"01",X"32",X"01",X"70",X"F1",X"ED",X"45",X"3A",X"00",X"60",X"CB", + X"47",X"C9",X"34",X"7E",X"FE",X"3C",X"C0",X"36",X"00",X"23",X"34",X"C9",X"3A",X"86",X"42",X"E6", + X"03",X"FE",X"03",X"C9",X"3A",X"BB",X"42",X"CB",X"5F",X"20",X"08",X"FD",X"66",X"0B",X"FD",X"6E", + X"0A",X"D7",X"C9",X"FD",X"66",X"0D",X"FD",X"6E",X"0C",X"D7",X"C9",X"3A",X"84",X"42",X"B7",X"C0", + X"3A",X"BD",X"42",X"CB",X"47",X"28",X"0D",X"21",X"BC",X"42",X"35",X"20",X"07",X"21",X"8F",X"42", + X"CB",X"9E",X"CB",X"87",X"CB",X"4F",X"28",X"08",X"21",X"A5",X"42",X"35",X"20",X"02",X"CB",X"8F", + X"CB",X"57",X"28",X"08",X"21",X"A4",X"42",X"35",X"20",X"02",X"CB",X"97",X"CB",X"5F",X"28",X"23", + X"21",X"A6",X"42",X"35",X"20",X"1D",X"4F",X"21",X"9E",X"42",X"CB",X"3E",X"7E",X"CB",X"3E",X"86", + X"77",X"21",X"9F",X"42",X"CB",X"3E",X"7E",X"CB",X"3E",X"86",X"77",X"21",X"CA",X"42",X"CB",X"D6", + X"79",X"CB",X"9F",X"32",X"BD",X"42",X"C9",X"3A",X"8B",X"42",X"B7",X"C8",X"21",X"CA",X"42",X"CB", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd new file mode 100644 index 00000000..12e8a1f4 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ZIGZAG_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ZIGZAG_1H is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ZIGZAG_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ZIGZAG_1K is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd index dafe8385..fec08f5f 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd @@ -16,7 +16,7 @@ entity dpram is clock_a : IN STD_LOGIC := '1'; clock_b : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); enable_a : IN STD_LOGIC := '1'; enable_b : IN STD_LOGIC := '1'; wren_a : IN STD_LOGIC := '0'; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd index b881e738..f384af19 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd @@ -15,6 +15,26 @@ -- 2004- 5- 6 first release. -- 2004- 8-23 Improvement with T80-IP. -- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-- +-- 2019-12 Multi-machine support added +-- "GALAXIAN" +-- "MOONCR" +-- "AZURIAN" +-- "BLACKHOLE" +-- "CATACOMB" +-- "CHEWINGG" +-- "DEVILFSH" +-- "KINGBAL" +-- "MRDONIGH" +-- "OMEGA" +-- "ORBITRON" +-- "PISCES" +-- "UNIWARS" +-- "VICTORY" +-- "WAROFBUG" +-- "ZIGZAG" -- doesn't work yet +-- "TRIPLEDR" + ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; @@ -24,8 +44,10 @@ library ieee; --use work.pkg_galaxian.all; entity galaxian is + generic ( + name : string := "GALAXIAN" + ); port( - W_CLK_18M : in std_logic; W_CLK_12M : in std_logic; W_CLK_6M : in std_logic; @@ -40,8 +62,9 @@ entity galaxian is VBLANK : out std_logic; W_H_SYNC : out std_logic; W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); + W_SDAT_A : out std_logic_vector( 7 downto 0) := (others => '0'); + W_SDAT_B : out std_logic_vector( 7 downto 0) := (others => '0'); + W_SDAT_C : out std_logic_vector( 7 downto 0) := (others => '0'); O_CMPBL : out std_logic ); end; @@ -50,7 +73,7 @@ architecture RTL of galaxian is -- CPU ADDRESS BUS signal W_A : std_logic_vector(15 downto 0) := (others => '0'); -- CPU IF - signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_CLK_EN : std_logic := '0'; signal W_CPU_MREQn : std_logic := '0'; signal W_CPU_NMIn : std_logic := '0'; signal W_CPU_RDn : std_logic := '0'; @@ -59,9 +82,15 @@ architecture RTL of galaxian is signal W_CPU_WRn : std_logic := '0'; signal W_CPU_WR : std_logic := '0'; signal W_RESETn : std_logic := '0'; + signal CPU_INT_n : std_logic; + signal CPU_NMI_n : std_logic; + -------- H and V COUNTER ------------------------- signal W_C_BLn : std_logic := '0'; signal W_C_BLnX : std_logic := '0'; + signal W_H_BLn : std_logic := '0'; + signal W_H_BLnX : std_logic := '0'; + signal W_H_BLXn : std_logic := '0'; signal W_C_BLXn : std_logic := '0'; signal W_H_BL : std_logic := '0'; signal W_H_SYNC_int : std_logic := '0'; @@ -76,6 +105,7 @@ architecture RTL of galaxian is signal W_BD_G : std_logic := '0'; signal W_CPU_RAM_CS : std_logic := '0'; signal W_CPU_RAM_RD : std_logic := '0'; + signal W_CPU_ROM_ADDR : std_logic_vector(13 downto 0); -- signal W_CPU_RAM_WR : std_logic := '0'; signal W_CPU_ROM_CS : std_logic := '0'; signal W_DIP_OE : std_logic := '0'; @@ -86,7 +116,10 @@ architecture RTL of galaxian is signal W_OBJ_RAM_WR : std_logic := '0'; signal W_PITCH : std_logic := '0'; signal W_SOUND_WE : std_logic := '0'; + signal W_MISC_WE : std_logic := '0'; + signal W_SPEECH_IN : std_logic_vector(1 downto 0); signal W_STARS_ON : std_logic := '0'; + signal W_STARS_ON_ADJ : std_logic := '0'; signal W_STARS_OFFn : std_logic := '0'; signal W_SW0_OE : std_logic := '0'; signal W_SW1_OE : std_logic := '0'; @@ -101,9 +134,9 @@ architecture RTL of galaxian is ----- DATA I/F ------------------------------------- signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_ROM_SWP : std_logic := '0'; -- ZigZag signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; signal W_VOL1 : std_logic := '0'; signal W_VOL2 : std_logic := '0'; signal W_FIRE : std_logic := '0'; @@ -142,11 +175,34 @@ architecture RTL of galaxian is signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + + signal PSG_EN : std_logic; + signal PSG_D : std_logic_vector(7 downto 0); + signal PSG_A,PSG_B,PSG_C : std_logic_vector(7 downto 0); + signal PSG_OUT : std_logic_vector(9 downto 0); + + component ym2149 + port ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A : out std_logic_vector(7 downto 0); + CHANNEL_B : out std_logic_vector(7 downto 0); + CHANNEL_C : out std_logic_vector(7 downto 0) + ); + end component; begin + mc_vid : entity work.MC_VIDEO + generic map( + name => name + ) port map( - I_CLK_18M => W_CLK_18M, I_CLK_12M => W_CLK_12M, I_CLK_6M => W_CLK_6M, I_H_CNT => W_H_CNT, @@ -155,6 +211,7 @@ begin I_V_FLIP => W_V_FLIP, I_V_BLn => W_V_BLn, I_C_BLn => W_C_BLn, + I_H_BLn => W_H_BLn, I_A => W_A(9 downto 0), I_OBJ_SUB_A => "000", I_BD => W_BDI, @@ -165,6 +222,7 @@ begin I_VID_RAM_WR => W_VID_RAM_WR, I_DRIVER_WR => W_DRIVER_WE, O_C_BLnX => W_C_BLnX, + O_H_BLnX => W_H_BLnX, O_8HF => W_8HF, O_256HnX => W_256HnX, O_1VF => W_1VF, @@ -175,13 +233,22 @@ begin O_COL => W_COL ); - cpu : entity work.T80as + int_gen: if name = "DEVILFSH" generate + CPU_INT_n <= W_CPU_NMIn; + CPU_NMI_n <= '1'; + else generate + CPU_INT_n <= '1'; + CPU_NMI_n <= W_CPU_NMIn; + end generate; + + cpu : entity work.T80se port map ( RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, + CLK_n => W_CLK_6M, + CLKEN => W_CPU_CLK_EN, WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, + INT_n => CPU_INT_n, + NMI_n => CPU_NMI_n, BUSRQ_n => '1', MREQ_n => W_CPU_MREQn, RD_n => W_CPU_RDn, @@ -193,13 +260,14 @@ begin M1_n => open, IORQ_n => open, HALT_n => open, - BUSAK_n => open, - DOE => open + BUSAK_n => open--, +-- DOE => open ); mc_cpu_ram : entity work.MC_CPU_RAM port map ( - I_CLK => W_CPU_RAM_CLK, + I_CLK => W_CLK_12M, + I_CS => W_CPU_RAM_CS, I_ADDR => W_A(9 downto 0), I_D => W_BDI, I_WE => W_CPU_WR, @@ -211,7 +279,6 @@ begin port map( I_CLK_12M => W_CLK_12M, I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, I_RSTn => W_RESETn, I_CPU_A => W_A, @@ -240,15 +307,21 @@ begin O_WDR_OE => W_WDR_OE, O_DRIVER_WE => W_DRIVER_WE, O_SOUND_WE => W_SOUND_WE, + O_MISC_WE => W_MISC_WE, O_PITCH => W_PITCH, O_H_FLIP => W_H_FLIP, O_V_FLIP => W_V_FLIP, + O_SPEECH => W_SPEECH_IN, O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON + O_STARS_ON => W_STARS_ON, + O_ROM_SWP => W_ROM_SWP ); -- active high buttons mc_inport : entity work.MC_INPORT + generic map( + name => name + ) port map ( I_COIN1 => P1_CSJUDLR(6), I_COIN2 => P2_CSJUDLR(6), @@ -260,6 +333,10 @@ begin I_2P_LE => P2_CSJUDLR(1), I_1P_RI => P1_CSJUDLR(0), I_2P_RI => P2_CSJUDLR(0), + I_1P_UP => P1_CSJUDLR(3), + I_2P_UP => P2_CSJUDLR(3), + I_1P_DN => P1_CSJUDLR(2), + I_2P_DN => P2_CSJUDLR(2), I_SW0_OE => W_SW0_OE, I_SW1_OE => W_SW1_OE, I_DIP_OE => W_DIP_OE, @@ -273,6 +350,7 @@ begin O_H_CNT => W_H_CNT, O_H_SYNC => W_H_SYNC_int, O_H_BL => W_H_BL, + O_H_BLn => W_H_BLn, O_V_CNT => W_V_CNT, O_V_SYNC => W_V_SYNC_int, O_V_BL2n => W_V_BL2n, @@ -281,22 +359,29 @@ begin ); mc_col_pal : entity work.MC_COL_PAL + generic map( + name => name + ) port map( I_CLK_12M => W_CLK_12M, I_CLK_6M => W_CLK_6M, I_VID => W_VID, I_COL => W_COL, I_C_BLnX => W_C_BLnX, + I_H_BLnX => W_H_BLnX, O_C_BLXn => W_C_BLXn, + O_H_BLXn => W_H_BLXn, O_STARS_OFFn => W_STARS_OFFn, O_R => W_VIDEO_R, O_G => W_VIDEO_G, O_B => W_VIDEO_B ); + comps: if name /= "ZIGZAG" generate + mc_stars : entity work.MC_STARS port map ( - I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, I_CLK_6M => W_CLK_6M, I_H_FLIP => W_H_FLIP, I_V_SYNC => W_V_SYNC_int, @@ -304,7 +389,7 @@ begin I_256HnX => W_256HnX, I_1VF => W_1VF, I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, + I_STARS_ON => W_STARS_ON_ADJ, I_STARS_OFFn => W_STARS_OFFn, O_R => W_STARS_R, O_G => W_STARS_G, @@ -334,15 +419,25 @@ begin I_FS => W_FS, O_SDAT => W_SDAT_B ); +end generate; --------- ROM ------------------------------------------------------- mc_roms : entity work.ROM_PGM_0 + generic map ( + name => name + ) port map ( CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), + ADDR => W_CPU_ROM_ADDR, DATA => W_CPU_ROM_DO ); + romaddr: if name = "ZIGZAG" generate + W_CPU_ROM_ADDR <= W_A(13) & (W_A(12) xor (W_ROM_SWP and W_A(13))) & W_A(11 downto 0); + else generate + W_CPU_ROM_ADDR <= W_A(13 downto 0); + end generate; + -------- VIDEO ----------------------------- blx_comb <= not ( W_C_BLXn and W_V_BL2n ); W_V_SYNC <= not W_V_SYNC_int; @@ -363,7 +458,7 @@ begin process(W_CLK_6M) begin if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; + HBLANK <= not W_H_BLXn; VBLANK <= not W_V_BL2n; end if; end process; @@ -371,8 +466,8 @@ begin ----- CPU I/F ------------------------------------- - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + W_CPU_CLK_EN <= not W_H_CNT(0); -- CPU clock enable in the 6MHz domain +-- W_CPU_CLK <= W_H_CNT(0); W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); @@ -382,12 +477,12 @@ begin new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - process(W_CPU_CLK, I_RESET) + process(W_CLK_6M, I_RESET) begin if (I_RESET = '1') then rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then + elsif rising_edge( W_CLK_6M) then + if ( W_CPU_CLK_EN = '1' and rst_count /= x"f") then rst_count <= rst_count + 1; end if; end if; @@ -443,4 +538,54 @@ begin end process; ------------------------------------------------------------------------------- +-- King & Balloon speech board +kb_speech: if name = "KINGBAL" generate + speech : entity work.kb_synth + port map( + reset_n => W_RESETn, + clk => W_CLK_12M, + in0 => W_SPEECH_IN(0), + in1 => W_SPEECH_IN(1), + in2 => '0', -- GND + in3 => '0', -- GND + speech_out => W_SDAT_C + ); + + W_STARS_ON_ADJ <= '0'; -- no stars in this game +else generate + W_STARS_ON_ADJ <= W_STARS_ON; +end generate; + +-- AY8910 for ZigZag +psg: if name = "ZIGZAG" generate + PSG_EN <= '1' when W_A(15 downto 11) = "01001" and W_A(9) = '0' and W_CPU_MREQn = '0' and W_CPU_WRn = '0' else '0'; + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + if PSG_EN = '1' and W_A(8) = '1' then + PSG_D <= W_A(7 downto 0); + end if; + end if; + end process; + + PSG_OUT <= ("00" & PSG_A) + ("00" & PSG_B) + ("00" & PSG_C); + W_SDAT_C <= PSG_OUT(9 downto 2); + + psg : ym2149 + port map ( + CLK => W_CLK_6M, + CE => W_CPU_CLK_EN, + RESET => I_RESET, + + BDIR => PSG_EN and W_A(0) and not W_A(8), + BC => W_A(1), + DI => PSG_D, + + CHANNEL_A => PSG_A, + CHANNEL_B => PSG_B, + CHANNEL_C => PSG_C + ); +end generate; + end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd new file mode 100644 index 00000000..350eed5c --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd @@ -0,0 +1,136 @@ +-- Sound synth board for King & Balloon + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity kb_synth is + port ( + reset_n : in std_logic; + clk : in std_logic; + in0 : in std_logic; + in1 : in std_logic; + in2 : in std_logic; + in3 : in std_logic; + speech_out : out std_logic_vector(7 downto 0) + ); +end kb_synth; + +architecture RTL of kb_synth is + +signal cpu_ce : std_logic; +signal cpu_ce_cnt : unsigned(2 downto 0); +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_di : std_logic_vector(7 downto 0); +signal cpu_do : std_logic_vector(7 downto 0); +signal ram_do : std_logic_vector(7 downto 0); +signal rom4_do : std_logic_vector(7 downto 0); +signal rom5_do : std_logic_vector(7 downto 0); +signal rom6_do : std_logic_vector(7 downto 0); +signal mreq_n : std_logic; +signal iorq_n : std_logic; +signal rd_n : std_logic; +signal wr_n : std_logic; + +signal ram_ce : std_logic; +signal ram_wr : std_logic; +signal rom4_ce : std_logic; +signal rom5_ce : std_logic; +signal rom6_ce : std_logic; +signal buf_do : std_logic_vector(7 downto 0); +signal buf_ce_n : std_logic; + +begin + + cpu_di <= ram_do when ram_ce = '1' else + rom4_do when rom4_ce = '1' else + rom5_do when rom5_ce = '1' else + rom6_do when rom6_ce = '1' else + buf_do when buf_ce_n = '0' else + "00000000"; + + -- clk/5 = 12MHz/5 = 2.4MHz (originally 5MHz/2) + process(clk, reset_n) + begin + if reset_n = '0' then + cpu_ce <= '0'; + cpu_ce_cnt <= (others => '0'); + elsif rising_edge(clk) then + cpu_ce_cnt <= cpu_ce_cnt + 1; + cpu_ce <= '0'; + if cpu_ce_cnt = 4 then + cpu_ce <= '1'; + cpu_ce_cnt <= (others => '0'); + end if; + end if; + end process; + + cpu : entity work.T80se + port map ( + RESET_n => reset_n, + CLK_n => clk, + CLKEN => cpu_ce, + WAIT_n => '1', + INT_n => '1', + NMI_n => '1', + BUSRQ_n => '1', + MREQ_n => mreq_n, + IORQ_n => iorq_n, + RD_n => rd_n, + WR_n => wr_n, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do + ); + + ram_ce <= cpu_addr(13) and not mreq_n; + ram_wr <= not wr_n and ram_ce; + + ram_inst : entity work.spram generic map(10,8) + port map ( + address => cpu_addr(9 downto 0), + clock => clk, + data => cpu_do, + wren => ram_wr, + q => ram_do + ); + + rom4_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "000" else '0'; + rom4_inst : entity work.kbe1_IC4 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom4_do + ); + + rom5_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "001" else '0'; + rom5_inst : entity work.kbe2_IC5 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom5_do + ); + + rom6_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "010" else '0'; + rom6_inst : entity work.kbe3_IC6 + port map ( + clk => clk, + addr => cpu_addr(10 downto 0), + data => rom6_do + ); + + process(clk, reset_n) + begin + if reset_n = '0' then + speech_out <= (others => '0'); + elsif rising_edge(clk) then + if iorq_n = '0' and wr_n = '0' then + speech_out <= cpu_do; + end if; + end if; + end process; + + buf_ce_n <= rd_n or iorq_n; + buf_do <= "1111"&in3&in2&in1&in0; + +end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd index 7245ce8c..2a35d496 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd @@ -57,7 +57,6 @@ entity MC_ADEC is port ( I_CLK_12M : in std_logic; I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; I_RSTn : in std_logic; I_CPU_A : in std_logic_vector(15 downto 0); @@ -86,11 +85,14 @@ entity MC_ADEC is O_WDR_OE : out std_logic; O_DRIVER_WE : out std_logic; O_SOUND_WE : out std_logic; + O_MISC_WE : out std_logic; O_PITCH : out std_logic; O_H_FLIP : out std_logic; O_V_FLIP : out std_logic; + O_SPEECH : out std_logic_vector(1 downto 0); -- kingballoon O_BD_G : out std_logic; - O_STARS_ON : out std_logic + O_STARS_ON : out std_logic; + O_ROM_SWP : out std_logic -- ZigZag ); end; @@ -115,12 +117,12 @@ begin -- O_WAITn <= '1' ; -- No Wait O_WAITn <= W_6S1_Qn; - process(I_CPU_CLK, I_V_BLn) + process(I_CLK_6M, I_V_BLn) begin if (I_V_BLn = '0') then -- W_6S1_Q <= '0'; W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then + elsif rising_edge(I_CLK_6M) then -- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); W_6S1_Qn <= I_H_BL or W_8P_Q(2); end if; @@ -213,7 +215,7 @@ begin O_CPU_RAM_RD <= not W_8N_Q(0); O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); + O_MISC_WE <= not W_8M_Q(6); O_SOUND_WE <= not W_8M_Q(5); O_DRIVER_WE <= not W_8M_Q(4); O_OBJ_RAM_WR <= not W_8M_Q(3); @@ -247,5 +249,7 @@ begin O_STARS_ON <= W_9N_Q(4); O_H_FLIP <= W_9N_Q(6); O_V_FLIP <= W_9N_Q(7); + O_SPEECH <= W_9N_Q(2)&W_9N_Q(0); -- King & Balloon + O_ROM_SWP <= W_9N_Q(2); -- ZigZag end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd index a6df1ce1..5bafe7aa 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd @@ -27,6 +27,7 @@ library ieee; entity MC_CPU_RAM is port ( I_CLK : in std_logic; + I_CS : in std_logic; I_ADDR : in std_logic_vector(9 downto 0); I_D : in std_logic_vector(7 downto 0); I_WE : in std_logic; @@ -46,7 +47,7 @@ begin address => I_ADDR, clock => I_CLK, data => I_D, - wren => I_WE, + wren => I_WE and I_CS, q => W_D ); end RTL; @@ -150,32 +151,29 @@ library ieee; -- mc_video.v use entity MC_LRAM is port ( - I_CLK : in std_logic; + I_WCLK : in std_logic; + I_RCLK : in std_logic; I_ADDR : in std_logic_vector(7 downto 0); I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; O_Dn : out std_logic_vector(4 downto 0) ); end; architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); begin - O_Dn <= not W_D; - ram_inst : work.dpram generic map(8,5) port map ( - clock_a => I_CLK, + clock_a => I_WCLK, address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, + data_a => not I_D, + wren_a => '1', - clock_b => not I_CLK, + clock_b => not I_RCLK, address_b => I_ADDR, data_b => (others => '0'), - q_b => W_D, + q_b => O_Dn, enable_b => '1', wren_b => '0' ); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd index c4dc06ad..eda4677e 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd @@ -22,14 +22,19 @@ library ieee; -- use UNISIM.Vcomponents.all; entity MC_COL_PAL is +generic ( + name : string +); port ( I_CLK_12M : in std_logic; I_CLK_6M : in std_logic; I_VID : in std_logic_vector(1 downto 0); I_COL : in std_logic_vector(2 downto 0); I_C_BLnX : in std_logic; + I_H_BLnX : in std_logic; O_C_BLXn : out std_logic; + O_H_BLXn : out std_logic; O_STARS_OFFn : out std_logic; O_R : out std_logic_vector(2 downto 0); O_G : out std_logic_vector(2 downto 0); @@ -43,6 +48,8 @@ architecture RTL of MC_COL_PAL is signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); signal W_6M_CLR : std_logic := '0'; + signal W_6M_HBL : std_logic := '0'; + signal W_6M_HBLCLR : std_logic := '0'; begin W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; @@ -50,6 +57,9 @@ begin O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); O_STARS_OFFn <= W_6M_DO(1); + W_6M_HBLCLR <= I_H_BLnX or W_6M_HBL; + O_H_BLXn <= I_H_BLnX or W_6M_HBL; + --always@(posedge I_CLK_6M or negedge W_6M_CLR) process(I_CLK_6M, W_6M_CLR) begin @@ -60,10 +70,19 @@ begin end if; end process; - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; + process(I_CLK_6M, W_6M_HBLCLR) + begin + if (W_6M_HBLCLR = '0') then + W_6M_HBL <= '0'; + elsif rising_edge(I_CLK_6M) then + W_6M_HBL <= I_H_BLnX; + end if; + end process; - galaxian_6l : entity work.GALAXIAN_6L + clut : entity work.ROM_6L + generic map ( + name => name + ) port map ( CLK => I_CLK_12M, ADDR => W_6M_DO(6 downto 2), diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd index f310321b..3ead8849 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd @@ -35,6 +35,7 @@ entity MC_HV_COUNT is O_H_CNT : out std_logic_vector(8 downto 0); O_H_SYNC : out std_logic; O_H_BL : out std_logic; + O_H_BLn : out std_logic; O_V_BL2n : out std_logic; O_V_CNT : out std_logic_vector(7 downto 0); O_V_SYNC : out std_logic; @@ -47,7 +48,10 @@ architecture RTL of MC_HV_COUNT is signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); signal H_SYNC : std_logic := '0'; + signal H_SYNC_NEXT : std_logic := '0'; + signal H_SYNC_EN : std_logic := '0'; signal H_CLK : std_logic := '0'; + signal H_CLK_EN : std_logic := '0'; signal H_BL : std_logic := '0'; signal V_BLn : std_logic := '0'; signal V_BL2n : std_logic := '0'; @@ -69,13 +73,19 @@ begin O_H_CNT <= H_CNT; --------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) +-- H_CLK <= H_CNT(4); + H_CLK_EN <= '1' when H_CNT(4 downto 0) = "01111" else '0'; + H_SYNC_NEXT <= (not H_CNT(6) ) and H_CNT(5); + H_SYNC_EN <= '1' when H_CLK_EN = '1' and H_CNT(8) = '1' and H_SYNC = '0' and H_SYNC_NEXT = '1' else '0'; + + process(I_CLK, H_CNT(8)) begin if (H_CNT(8) = '0') then H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + elsif rising_edge(I_CLK) then + if H_CLK_EN = '1' then + H_SYNC <= H_SYNC_NEXT; + end if; end if; end process; @@ -97,15 +107,17 @@ begin O_H_BL <= H_BL; --------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) + process(I_CLK, I_RSTn) begin if (I_RSTn = '0') then V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; + elsif rising_edge(I_CLK) then + if H_SYNC_EN = '1' then -- rising_edge(HSYNC) + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; end if; end if; end process; @@ -115,24 +127,28 @@ begin --------- V_BLn ------------------------------------------ - process(H_SYNC) + process(I_CLK) begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; + if rising_edge(I_CLK) then + if H_SYNC_EN = '1' then -- rising_edge(HSYNC) + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; end if; end if; end process; - process(H_SYNC) + process(I_CLK) begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; + if rising_edge(I_CLK) then + if H_SYNC_EN = '1' then -- rising_edge(HSYNC) + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; end if; end if; end process; @@ -141,5 +157,6 @@ begin O_V_BL2n <= V_BL2n; ------- C_BLn ------------------------------------------ O_C_BLn <= V_BLn and (not H_CNT(8)); + O_H_BLn <= not H_CNT(8); end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd index 69a20cbe..c10bbf64 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd @@ -35,14 +35,21 @@ library ieee; use ieee.numeric_std.all; entity MC_INPORT is +generic ( + name : in string +); port ( I_COIN1 : in std_logic; -- active high I_COIN2 : in std_logic; -- active high I_1P_LE : in std_logic; -- active high I_1P_RI : in std_logic; -- active high + I_1P_UP : in std_logic; -- active high + I_1P_DN : in std_logic; -- active high I_1P_SH : in std_logic; -- active high I_2P_LE : in std_logic; I_2P_RI : in std_logic; + I_2P_UP : in std_logic; + I_2P_DN : in std_logic; I_2P_SH : in std_logic; I_1P_START : in std_logic; -- active high I_2P_START : in std_logic; -- active high @@ -66,9 +73,31 @@ architecture RTL of MC_INPORT is begin - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + ioports: if name = "AZURIAN" generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_1P_SH & I_1P_SH & I_COIN1 & I_1P_LE & I_1P_RI & I_1P_UP & I_1P_DN; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "10" & I_1P_LE & I_1P_RI & I_2P_UP & I_2P_DN & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + elsif name = "DEVILFSH" or name = "TRIPLEDR" generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP & I_1P_DN & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & I_2P_DN & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + elsif name = "MRDONIGH" generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_1P_SH & I_1P_DN & I_1P_UP & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + elsif name = "ORBITRON" or name = "VICTORY" or name = "WAROFBUG" generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DN & I_2P_DN & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else I_2P_UP & "1" & "0" & I_1P_SH & I_1P_RI & I_1P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001000"; + elsif name = "ZIGZAG" generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_1P_DN & I_1P_UP & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000000" & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000011"; + else generate + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + end generate; O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd index c5aa6633..1971b9e0 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd @@ -21,7 +21,6 @@ library ieee; entity MC_MISSILE is port( I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; I_C_BLn_X : in std_logic; I_MLDn : in std_logic; I_SLDn : in std_logic; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd index b91197b3..1c01f7ae 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd @@ -18,7 +18,7 @@ library ieee; entity MC_STARS is port ( - I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; I_CLK_6M : in std_logic; I_H_FLIP : in std_logic; I_V_SYNC : in std_logic; @@ -52,7 +52,7 @@ begin O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1C <= not (I_CLK_12M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); W_3B <= W_2D_Qn xor W_1AB_Q(4); diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd index dbe0d0d8..7c10aba4 100644 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd @@ -30,8 +30,10 @@ library ieee; use ieee.numeric_std.all; entity MC_VIDEO is + generic ( + name : string + ); port( - I_CLK_18M : in std_logic; I_CLK_12M : in std_logic; I_CLK_6M : in std_logic; I_H_CNT : in std_logic_vector(8 downto 0); @@ -40,6 +42,7 @@ entity MC_VIDEO is I_V_FLIP : in std_logic; I_V_BLn : in std_logic; I_C_BLn : in std_logic; + I_H_BLn : in std_logic; I_A : in std_logic_vector(9 downto 0); I_BD : in std_logic_vector(7 downto 0); @@ -52,6 +55,7 @@ entity MC_VIDEO is I_DRIVER_WR : in std_logic; O_C_BLnX : out std_logic; + O_H_BLnX : out std_logic; O_8HF : out std_logic; O_256HnX : out std_logic; O_1VF : out std_logic; @@ -97,7 +101,7 @@ architecture RTL of MC_VIDEO is signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_O_OBJ_ROM_A : std_logic_vector(11 downto 0) := (others => '0'); signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); @@ -145,9 +149,13 @@ architecture RTL of MC_VIDEO is signal W_SRCLK : std_logic := '0'; signal W_SRLD : std_logic := '0'; signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; + + type bank_a is array(0 to 3) of std_logic_vector(7 downto 0); + signal bank : bank_a; + signal pisces_gfxbank : std_logic; begin + ld_pls : entity work.MC_LD_PLS port map( I_CLK_6M => I_CLK_6M, @@ -183,16 +191,15 @@ begin lram : entity work.MC_LRAM port map( - I_CLK => I_CLK_18M, + I_WCLK => I_CLK_6M, + I_RCLK => I_CLK_12M, I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, I_D => W_LRAM_DI, O_Dn => W_LRAM_DO ); missile : entity work.MC_MISSILE port map( - I_CLK_18M => I_CLK_18M, I_CLK_6M => I_CLK_6M, I_C_BLn_X => W_C_BLnX, I_MLDn => W_MLDn, @@ -220,7 +227,10 @@ begin ); -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K + k_rom : entity work.ROM_1K + generic map ( + name => name + ) port map ( CLK => I_CLK_12M, ADDR => W_O_OBJ_ROM_A, @@ -228,7 +238,10 @@ begin ); -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H + h_rom : entity work.ROM_1H + generic map ( + name => name + ) port map( CLK => I_CLK_12M, ADDR => W_O_OBJ_ROM_A, @@ -251,8 +264,6 @@ begin end if; end process; - W_CLK_6Mn <= not I_CLK_6M; - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; @@ -299,7 +310,19 @@ begin W_2M_Q <= W_45N_Q; end if; end process; - + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + if I_DRIVER_WR = '1' and I_A(2) = '0' then + bank(to_integer(unsigned(I_A(1 downto 0)))) <= I_BD; + end if; + if I_DRIVER_WR = '1' and I_A(2 downto 0) = "010" then + pisces_gfxbank <= I_BD(0); + end if; + end if; + end process; + W_2N <= I_H_CNT(8) and W_OBJ_D(7); W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; @@ -315,7 +338,20 @@ begin W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + + rom_a : if name = "MOONCR" generate + W_O_OBJ_ROM_A <= '1' & bank(0)(0) & bank(1)(0) & W_OBJ_ROM_A(5 downto 0) & W_1M(2 downto 0) + when (bank(2) /= X"00" and W_OBJ_ROM_A(7 downto 6) = "10") else + '0' & W_OBJ_ROM_A & W_1M(2 downto 0); + elsif name = "DEVILFSH" generate + W_O_OBJ_ROM_A <= not I_H_CNT(8) & W_OBJ_ROM_A & W_1M(2 downto 0); + elsif name = "ZIGZAG" generate + W_O_OBJ_ROM_A <= I_H_CNT(8) & W_OBJ_ROM_A & W_1M(2 downto 0); + elsif name = "PISCES" or name = "UNIWARS" generate + W_O_OBJ_ROM_A <= pisces_gfxbank & W_OBJ_ROM_A & W_1M(2 downto 0); + else generate + W_O_OBJ_ROM_A <= '0' & W_OBJ_ROM_A & W_1M(2 downto 0); + end generate; ----------------------------------------------------------------------------------- @@ -374,8 +410,7 @@ begin if rising_edge(I_CLK_6M) then if (W_LDn = '0') then W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; + O_H_BLnX <= I_H_BLn; end if; end if; end process; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv new file mode 100644 index 00000000..1aa73ff8 --- /dev/null +++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv @@ -0,0 +1,331 @@ +// +// Copyright (c) MikeJ - Jan 2005 +// Copyright (c) 2016-2018 Sorgelig +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + + +// BDIR BC MODE +// 0 0 inactive +// 0 1 read value +// 1 0 write value +// 1 1 set address +// + +module ym2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + output [5:0] ACTIVE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign ACTIVE = ~ymreg[7][5:0]; +assign IOA_out = ymreg[14]; +assign IOB_out = ymreg[15]; + +reg [7:0] addr; +reg [7:0] ymreg[16]; + +// Write to PSG +reg env_reset; +always @(posedge CLK) begin + if(RESET) begin + ymreg <= '{default:0}; + ymreg[7] <= '1; + addr <= '0; + env_reset <= 0; + end else begin + env_reset <= 0; + if(BDIR) begin + if(BC) addr <= DI; + else if(!addr[7:4]) begin + ymreg[addr[3:0]] <= DI; + env_reset <= (addr == 13); + end + end + end +end + +// Read from PSG +assign DO = dout; +reg [7:0] dout; +always_comb begin + dout = 8'hFF; + if(~BDIR & BC & !addr[7:4]) begin + case(addr[3:0]) + 0: dout = ymreg[0]; + 1: dout = ymreg[1][3:0]; + 2: dout = ymreg[2]; + 3: dout = ymreg[3][3:0]; + 4: dout = ymreg[4]; + 5: dout = ymreg[5][3:0]; + 6: dout = ymreg[6][4:0]; + 7: dout = ymreg[7]; + 8: dout = ymreg[8][4:0]; + 9: dout = ymreg[9][4:0]; + 10: dout = ymreg[10][4:0]; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = ymreg[13][3:0]; + 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; + 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; + endcase + end +end + +reg ena_div; +reg ena_div_noise; + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [2:0] noise_gen_op; + +// p_noise_gen +always @(posedge CLK) begin + reg [16:0] poly17; + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if(ymreg[6][4:0]) begin + if (noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + noise_gen_op <= {3{poly17[0]}}; + end else begin + noise_gen_op <= ymreg[7][5:3]; + noise_gen_cnt <= 0; + end + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_freq[i]) begin + if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= ~tone_gen_op[i]; + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end else begin + tone_gen_op[i] <= ymreg[7][i]; + tone_gen_cnt[i] <= 0; + end + end + end + end +end + +reg env_ena; +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +reg [4:0] env_vol; + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(env_reset | RESET) begin + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end + else if(CE) begin + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end +end + +reg [5:0] A,B,C; +always @(posedge CLK) begin + A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; + B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; + C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; +end + +wire [7:0] volTable[64] = '{ + //YM2149 + 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, + + //AY8910 + 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, + 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, + 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, + 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff +}; + +assign CHANNEL_A = volTable[A]; +assign CHANNEL_B = volTable[B]; +assign CHANNEL_C = volTable[C]; + +endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf deleted file mode 100644 index 38cc2338..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 17:34:44 October 10, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "17:34:44 October 10, 2018" - -# Revisions - -PROJECT_REVISION = "KingBaloon" -PROJECT_REVISION = "Galaxian" diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf deleted file mode 100644 index 0dd7647f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf +++ /dev/null @@ -1,194 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 21:14:56 August 16, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# KingBaloon_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY KingBalloon_MiST -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------------------ -# start ENTITY(KingBalloon_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(KingBalloon_MiST) -# ---------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/KingBalloon_MiST.sv -set_global_assignment -name VHDL_FILE rtl/kingballon.vhd -set_global_assignment -name VHDL_FILE rtl/kb_synth.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/rom_h.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/rom_k.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd -set_global_assignment -name VHDL_FILE "rtl/ROM/kbe1-4.vhd" -set_global_assignment -name VHDL_FILE "rtl/ROM/kbe2-5.vhd" -set_global_assignment -name VHDL_FILE "rtl/ROM/kbe3-6.vhd" -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/ttl_74138.vhd -set_global_assignment -name VHDL_FILE rtl/ttl_74273.vhd -set_global_assignment -name VHDL_FILE rtl/ttl_74367.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf deleted file mode 100644 index f79ee3f7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf +++ /dev/null @@ -1,56 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt deleted file mode 100644 index 7c62e33e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: King and Balloon port to MiST by Gehstock --- 22 October 2018 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- - - -ToDo: add Speech \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf deleted file mode 100644 index d409f213..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv deleted file mode 100644 index b6867af1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv +++ /dev/null @@ -1,194 +0,0 @@ -//============================================================================ -// Arcade: King & Balloon -// -// Port to MiST -// Copyright (C) 2018 Gehstock -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module KingBalloon_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "King and Ball.;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T5,Reset;", - - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b, audio_c; -wire [10:0] audio = {audio_c, 3'b0} + {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -kingballoon kingballoon( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[5] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_down,m_up,m_left,m_right}), - .P2_CSJUDLR({status[1],btn_two_players,m_fire,m_down,m_up,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b), - .W_SDAT_C(audio_c) -); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; - -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -//reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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-entity sound is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of sound is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"21",X"FF",X"FF",X"2D",X"20",X"FD",X"25",X"20",X"FA",X"DB",X"00",X"FE",X"F0",X"28",X"FA",X"3E", - X"10",X"3D",X"20",X"FD",X"DB",X"00",X"FE",X"F0",X"28",X"EF",X"FE",X"F1",X"20",X"25",X"21",X"80", - X"01",X"01",X"4F",X"06",X"DD",X"21",X"2A",X"00",X"18",X"4C",X"06",X"02",X"21",X"FF",X"FF",X"2D", - X"20",X"FD",X"25",X"20",X"05",X"05",X"20",X"02",X"18",X"CF",X"DB",X"00",X"FE",X"F1",X"28",X"EF", - X"C3",X"09",X"00",X"FE",X"F2",X"C2",X"5B",X"00",X"21",X"50",X"06",X"01",X"8F",X"10",X"DD",X"21", - X"55",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE",X"F2",X"28",X"FA",X"FE",X"F3",X"C2",X"09",X"00", - X"21",X"90",X"10",X"01",X"FF",X"17",X"DD",X"21",X"6D",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE", - X"F3",X"28",X"FA",X"C3",X"09",X"00",X"50",X"59",X"7E",X"E6",X"F0",X"D3",X"00",X"3E",X"1B",X"3D", - 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8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd deleted file mode 100644 index 91f7e809..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 10 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd deleted file mode 100644 index c90cf9c0..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd +++ /dev/null @@ -1,160 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity kb_synth is - port ( - reset_n : in std_logic; - clk : in std_logic; - in0 : in std_logic; - in1 : in std_logic; - in2 : in std_logic; - in3 : in std_logic; - speech_out : out std_logic_vector(7 downto 0) - ); -end kb_synth; - -architecture RTL of kb_synth is - -signal cpu_addr : std_logic_vector(15 downto 0); -signal cpu_di : std_logic_vector(7 downto 0); -signal cpu_do : std_logic_vector(7 downto 0); -signal ram_do : std_logic_vector(7 downto 0); -signal rom4_do : std_logic_vector(7 downto 0); -signal rom5_do : std_logic_vector(7 downto 0); -signal rom6_do : std_logic_vector(7 downto 0); -signal mreq_n : std_logic; -signal iorq_n : std_logic; -signal rd_n : std_logic; -signal wr_n : std_logic; - -signal ram_ce : std_logic; -signal rom4_ce : std_logic; -signal rom5_ce : std_logic; -signal rom6_ce : std_logic; -signal ic3_out : std_logic_vector(7 downto 0); -signal buf_do : std_logic_vector(7 downto 0); -signal buf_ce : std_logic; -signal A13n : std_logic; -begin - -cpu_di <= ram_do when ram_ce = '1' else - rom4_do when rom4_ce = '1' else - rom5_do when rom5_ce = '1' else - rom6_do when rom6_ce = '1' else - buf_do when buf_ce = '0' else - "00000000"; - - - cpu : entity work.T80as - port map ( - RESET_n => reset_n, - CLK_n => clk, - WAIT_n => '1', - INT_n => '1', - NMI_n => '1', - BUSRQ_n => '1', - MREQ_n => mreq_n, - IORQ_n => iorq_n, - RD_n => rd_n, - WR_n => wr_n, - A => cpu_addr, - DI => cpu_di, - DO => cpu_do - ); - -A13n <= not cpu_addr(13); -ram_ce <= not (A13n or mreq_n); - ram_inst : entity work.spram generic map(10,8) - port map ( - address => cpu_addr(9 downto 0), - clock => clk, - data => cpu_do, - wren => not wr_n, - q => ram_do - ); - -rom4_ce <= ic3_out(0); - rom4_inst : entity work.kbe1_IC4 - port map ( - clk => clk, - addr => cpu_addr(10 downto 0), - data => rom4_do - ); - -rom5_ce <= ic3_out(1); - rom5_inst : entity work.kbe2_IC5 - port map ( - clk => clk, - addr => cpu_addr(10 downto 0), - data => rom5_do - ); - -rom6_ce <= ic3_out(2); - rom6_inst : entity work.kbe3_IC6 - port map ( - clk => clk, - addr => cpu_addr(10 downto 0), - data => rom6_do - ); - - ls138 : entity work.ttl_74138 - port map ( - a => cpu_addr(11), - b => cpu_addr(12), - c => '0', - g1 => A13n, - g2a_n => rd_n, - g2b_n => mreq_n, - y_n => ic3_out - ); - - ls273 : entity work.ttl_74273 - port map ( - CLRN => reset_n, - CLK => not (wr_n or iorq_n), - D8 => cpu_do(0), - D7 => cpu_do(1), - D6 => cpu_do(2), - D5 => cpu_do(3), - D4 => cpu_do(4), - D3 => cpu_do(5), - D2 => cpu_do(6), - D1 => cpu_do(7), - Q1 => speech_out(0), - Q2 => speech_out(1), - Q3 => speech_out(2), - Q4 => speech_out(3), - Q5 => speech_out(4), - Q6 => speech_out(5), - Q7 => speech_out(6), - Q8 => speech_out(7) - ); - -buf_ce <= rd_n or iorq_n; ---buf_do(6) <= '0'; ---buf_do(7) <= '0'; - ls367 : entity work.ttl_74367 - port map ( - p2GN => buf_ce,--15 - - p2A1 => '1',--12 - p2A2 => '1',--14 - - p1A4 => '0',--in3,--10 - p1A3 => '0',--in2,--6 - p1A2 => in1,--4 - p1A1 => in0,--2 - - p1GN => buf_ce,--1 - - p2Y1 => buf_do(4),--11 - p2Y2 => buf_do(5),--13 - - p1Y4 => buf_do(3),--9 - p1Y3 => buf_do(2),--7 - p1Y2 => buf_do(1),--5 - p1Y1 => buf_do(0)--3 - ); - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd deleted file mode 100644 index 91831325..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd +++ /dev/null @@ -1,455 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA King and Balloon --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity kingballoon is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - W_SDAT_C : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of kingballoon is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => '0',--No Stars on this Game - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - - speech : entity work.kb_synth - port map( - reset_n => W_RESETn, - clk => W_CLK_6M, - in0 => '0',--DIP - in1 => '0',--DIP - in2 => '0',--DIP - in3 => '0',--DIP - speech_out => W_SDAT_C - ); - - mc_roms : entity work.prog - port map ( - clk => W_CLK_12M, - addr => W_A(13 downto 0), - data => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c0edf061..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.col - port map ( - clk => I_CLK_12M, - addr => W_6M_DO(6 downto 2), - data => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 69a20cbe..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd deleted file mode 100644 index 95911cec..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,431 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - k_rom : entity work.rom_k - port map ( - clk => I_CLK_12M, - addr => '0' & W_O_OBJ_ROM_A, - data => W_1K_D - ); - - h_rom : entity work.rom_h - port map ( - clk => I_CLK_12M, - addr => '0' & W_O_OBJ_ROM_A, - data => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd deleted file mode 100644 index d8043481..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd deleted file mode 100644 index e16bd235..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd +++ /dev/null @@ -1,48 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -Use IEEE.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity ttl_74138 is - port - ( - -- input - a : in std_logic; - b : in std_logic; - c : in std_logic; - - g1 : in std_logic; - g2a_n : in std_logic; - g2b_n : in std_logic; - - -- output - y_n : out std_logic_vector(7 downto 0) - ); -end ttl_74138; - -architecture SYN of ttl_74138 is - - signal enabled : std_logic; - -begin - - enabled <= g1 and not g2a_n and not g2b_n; - - y_n(0) <= '1' when enabled = '0' else - not (not a and not b and not c); - y_n(1) <= '1' when enabled = '0' else - not (a and not b and not c); - y_n(2) <= '1' when enabled = '0' else - not (not a and b and not c); - y_n(3) <= '1' when enabled = '0' else - not (a and b and not c); - y_n(4) <= '1' when enabled = '0' else - not (not a and not b and c); - y_n(5) <= '1' when enabled = '0' else - not (a and not b and c); - y_n(6) <= '1' when enabled = '0' else - not (not a and b and c); - y_n(7) <= '1' when enabled = '0' else - not (a and b and c); - -end SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd deleted file mode 100644 index 9f60ae57..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd +++ /dev/null @@ -1,136 +0,0 @@ --- Copyright (C) 1991-2014 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - --- PROGRAM "Quartus II 64-Bit" --- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" --- CREATED "Sun Aug 18 11:45:39 2019" - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY work; - -ENTITY ttl_74273 IS - PORT - ( - CLRN : IN STD_LOGIC; - CLK : IN STD_LOGIC; - D8 : IN STD_LOGIC; - D7 : IN STD_LOGIC; - D6 : IN STD_LOGIC; - D5 : IN STD_LOGIC; - D4 : IN STD_LOGIC; - D3 : IN STD_LOGIC; - D2 : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q1 : OUT STD_LOGIC; - Q2 : OUT STD_LOGIC; - Q3 : OUT STD_LOGIC; - Q4 : OUT STD_LOGIC; - Q5 : OUT STD_LOGIC; - Q6 : OUT STD_LOGIC; - Q7 : OUT STD_LOGIC; - Q8 : OUT STD_LOGIC - ); -END ttl_74273; - -ARCHITECTURE bdf_type OF ttl_74273 IS - - - -BEGIN - - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q8 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q8 <= D8; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q7 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q7 <= D7; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q6 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q6 <= D6; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q5 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q5 <= D5; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q4 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q4 <= D4; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q3 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q3 <= D3; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q2 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q2 <= D2; -END IF; -END PROCESS; - - -PROCESS(CLK,CLRN) -BEGIN -IF (CLRN = '0') THEN - Q1 <= '0'; -ELSIF (RISING_EDGE(CLK)) THEN - Q1 <= D1; -END IF; -END PROCESS; - - -END bdf_type; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd deleted file mode 100644 index 161c44b2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd +++ /dev/null @@ -1,122 +0,0 @@ --- Copyright (C) 1991-2014 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - --- PROGRAM "Quartus II 64-Bit" --- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" --- CREATED "Fri Aug 16 22:43:02 2019" - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY work; - -ENTITY ttl_74367 IS - PORT - ( - p2GN : IN STD_LOGIC; - p2A1 : IN STD_LOGIC; - p2A2 : IN STD_LOGIC; - p1A4 : IN STD_LOGIC; - p1A3 : IN STD_LOGIC; - p1A2 : IN STD_LOGIC; - p1A1 : IN STD_LOGIC; - p1GN : IN STD_LOGIC; - p2Y1 : OUT STD_LOGIC; - p2Y2 : OUT STD_LOGIC; - p1Y4 : OUT STD_LOGIC; - p1Y3 : OUT STD_LOGIC; - p1Y2 : OUT STD_LOGIC; - p1Y1 : OUT STD_LOGIC - ); -END ttl_74367; - -ARCHITECTURE bdf_type OF ttl_74367 IS - -SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC; - - -BEGIN - - - -PROCESS(p1A4,SYNTHESIZED_WIRE_6) -BEGIN -if (SYNTHESIZED_WIRE_6 = '1') THEN - p1Y4 <= p1A4; -ELSE - p1Y4 <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(p2A2,SYNTHESIZED_WIRE_7) -BEGIN -if (SYNTHESIZED_WIRE_7 = '1') THEN - p2Y2 <= p2A2; -ELSE - p2Y2 <= 'Z'; -END IF; -END PROCESS; - - -SYNTHESIZED_WIRE_6 <= NOT(p1GN); - - - -PROCESS(p2A1,SYNTHESIZED_WIRE_7) -BEGIN -if (SYNTHESIZED_WIRE_7 = '1') THEN - p2Y1 <= p2A1; -ELSE - p2Y1 <= 'Z'; -END IF; -END PROCESS; - - -SYNTHESIZED_WIRE_7 <= NOT(p2GN); - - - -PROCESS(p1A1,SYNTHESIZED_WIRE_6) -BEGIN -if (SYNTHESIZED_WIRE_6 = '1') THEN - p1Y1 <= p1A1; -ELSE - p1Y1 <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(p1A2,SYNTHESIZED_WIRE_6) -BEGIN -if (SYNTHESIZED_WIRE_6 = '1') THEN - p1Y2 <= p1A2; -ELSE - p1Y2 <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(p1A3,SYNTHESIZED_WIRE_6) -BEGIN -if (SYNTHESIZED_WIRE_6 = '1') THEN - p1Y3 <= p1A3; -ELSE - p1Y3 <= 'Z'; -END IF; -END PROCESS; - - -END bdf_type; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf deleted file mode 100644 index 35d49f9b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "MoonCresta" -PROJECT_REVISION = "Arcade-MoonCresta" diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf deleted file mode 100644 index 5fb26b29..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:56:24 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# MoonCresta_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonCresta.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY MoonCresta - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------------ -# start ENTITY(MoonCresta) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(MoonCresta) -# ---------------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf deleted file mode 100644 index a455f0f5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf +++ /dev/null @@ -1,51 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt deleted file mode 100644 index 846fd542..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Moon Cresta port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf deleted file mode 100644 index cb89a4ec..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv deleted file mode 100644 index f9a4938a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Moon Cresta -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module MoonCresta( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "MoonCresta;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian mooncresta( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule - \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd deleted file mode 100644 index b881e738..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 014e6f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library unisim; - use unisim.vcomponents.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 69a20cbe..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd deleted file mode 100644 index 6c7c3250..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,447 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - - type bank_a is array(0 to 3) of std_logic_vector(7 downto 0); - signal bank : bank_a; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - if I_DRIVER_WR = '1' and I_A(2) = '0' then - bank(to_integer(unsigned(I_A(1 downto 0)))) <= I_BD; - end if; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= '1' & bank(0)(0) & bank(1)(0) & W_OBJ_ROM_A(5 downto 0) & W_1M(2 downto 0) - when (bank(2) /= X"00" and W_OBJ_ROM_A(7 downto 6) = "10") else - '0' & W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v deleted file mode 100644 index 2a921604..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,195 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf deleted file mode 100644 index 842b51ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "MrDoNightmare" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf deleted file mode 100644 index 916a3e5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 16:59:54 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# MrDoNightmare_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDoNightmare.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY MrDoNightmare -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# --------------------------- -# start ENTITY(MrDoNightmare) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(MrDoNightmare) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf deleted file mode 100644 index cdf208db..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No output dependent on input pin \"SPI_SS2\"" { } { } 0 15610 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at MrDoNightmare.sv(86): object \"m_bomb\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt deleted file mode 100644 index af0153f8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Mr. Do´s Nightmare port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf deleted file mode 100644 index ff1dfc16..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv deleted file mode 100644 index ea1623e3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: MrDoNightmare -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module MrDoNightmare( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "MrDoNightmare;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian mrdo( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_up ,m_down }), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", - X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", - X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", - X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", - X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", - X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", - X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", - X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", - X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", - X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", - X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", - X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", - X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", - X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", - X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", - X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", - X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", - X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", - X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE", - X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93", - X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B", - X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd deleted file mode 100644 index b881e738..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 014e6f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library unisim; - use unisim.vcomponents.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 496f01ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,71 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else "00" & '0' & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd deleted file mode 100644 index dbe0d0d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v deleted file mode 100644 index eba1d598..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf deleted file mode 100644 index 12eceeac..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "Omega" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf deleted file mode 100644 index 4dc86db1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 17:11:29 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Omega_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Omega.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY Omega - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------- -# start ENTITY(Omega) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Omega) -# ----------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt deleted file mode 100644 index 60917297..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Omega port to MiST by Gehstock --- 8 Januar 2018 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf deleted file mode 100644 index 4f311a0c..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv deleted file mode 100644 index 788b47d0..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Omega -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Omega( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Omega;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian omega( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd deleted file mode 100644 index 5f8a3a74..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(3), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(2), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 550e610e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd deleted file mode 100644 index e924e09e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd deleted file mode 100644 index dbe0d0d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf deleted file mode 100644 index 258424fc..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "Orbitron" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf deleted file mode 100644 index ace21d2f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 17:16:41 March 10, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Orbitron_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Orbitron.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Orbitron -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------- -# start ENTITY(Orbitron) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Orbitron) -# -------------------- \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf deleted file mode 100644 index a455f0f5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf +++ /dev/null @@ -1,51 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 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0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt deleted file mode 100644 index e07cca59..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Orbitron port to MiST by Gehstock --- 18 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf deleted file mode 100644 index e99fac23..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv deleted file mode 100644 index 5fe19f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Orbitron -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Orbitron( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Orbitron;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian orbitron( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_right,m_left}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_up ,m_down}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule - diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd deleted file mode 100644 index b881e738..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,446 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 014e6f7a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library unisim; - use unisim.vcomponents.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 596db956..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '1'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_2P_LE & I_2P_RI & I_2P_RI & I_1P_SH & I_1P_LE & I_1P_RI & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else I_2P_LE & "1" & "0" & I_1P_SH & I_1P_LE & I_1P_RI & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "0000" & W_TABLE & "000"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd deleted file mode 100644 index dbe0d0d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1K VID-Rom - k_rom : entity work.GALAXIAN_1K - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - -- 1H VID-Rom - h_rom : entity work.GALAXIAN_1H - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v deleted file mode 100644 index 2a921604..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,195 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf deleted file mode 100644 index 02128464..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:51:58 January 08, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:51:58 January 08, 2018" - -# Revisions - -PROJECT_REVISION = "Pisces" -PROJECT_REVISION = "Catacomb" diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf deleted file mode 100644 index 95b686d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 18:12:35 November 17, 2017 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Galaxian_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Pisces -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------- -# start ENTITY(Galaxian) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Galaxian) -# -------------------- -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pisces.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt deleted file mode 100644 index a402af10..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Pisces port to MiST by Gehstock --- 19 December 2017 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf deleted file mode 100644 index f899cd87..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv deleted file mode 100644 index 13aa31aa..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Pisces -( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Pisces;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian catacomb( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", - X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", - X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", - X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", - X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", - X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", - X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", - X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", - X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", - X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", - X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", - X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", - X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", - X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", - X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", - X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", - X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", - X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", - X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE", - X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93", - X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B", - X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2", - X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87", - X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29", - X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9", - X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC", - X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE", - X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9", - X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83", - X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0", - X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37", - X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D", - X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A", - 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-entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd deleted file mode 100644 index 138d85cb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,448 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 01cee00a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN1 & I_COIN2; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd deleted file mode 100644 index ec46308a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - I_BANK : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1H VID-Rom - k_rom : entity work.GALAXIAN_1H - port map ( - CLK => I_CLK_12M, - ADDR => I_BANK & W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - - -- 1K VID-Rom - h_rom : entity work.GALAXIAN_1K - port map( - CLK => I_CLK_12M, - ADDR => I_BANK & W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ----------------------------------------------------------------------------------- - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt deleted file mode 100644 index f20f8e06..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: TripleDrawPoker port to MiST by Gehstock --- 11 Mar 2019 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F1 : Start 2 player --- SPACE : Select --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf deleted file mode 100644 index 491c0169..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf deleted file mode 100644 index 38d5967a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:51:58 January 08, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:51:58 January 08, 2018" - -# Revisions - -PROJECT_REVISION = "TripleDrawPoker" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf deleted file mode 100644 index 5c521181..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf +++ /dev/null @@ -1,184 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:15:04 March 11, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# TripleDrawPoker_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/TripleDrawPoker_MiST.sv -set_global_assignment -name VHDL_FILE rtl/tripledrawpoker.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY TripleDrawPoker_MiST -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------------------- -# start ENTITY(TripleDrawPoker_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(TripleDrawPoker_MiST) -# -------------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin deleted file mode 100644 index cb5d4b67..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex deleted file mode 100644 index a53b54df..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex +++ /dev/null @@ -1,3 +0,0 @@ -:10000000C007FF000007FFC0003F07C000173FC048 -:1000100000C73FC000383FC0003F17C00007F8C00E -:00000001FF diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin deleted file mode 100644 index df310112..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex deleted file mode 100644 index 98be5089..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex +++ /dev/null @@ -1,129 +0,0 @@ -:1000000000000000000000000103070F1F3F7FFFFA -:10001000FF7F3F1F0F070301F0F8FCFCFCF8F0E046 -:10002000E0F0F8FCFCFCF8F0C080000000000000EC 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Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/swap.exe and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv deleted file mode 100644 index 214a4eff..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module TripleDrawPoker_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "TriDraPo;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -tripledrawpoker tripledrawpoker( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}), - .P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index 7a26ee8e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,83 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - crom : entity work.sprom - generic map ( - init_file => "./ROM/col.hex", - widthad_a => 5, - width_a => 8) - port map ( - address => W_6M_DO(6 downto 2), - clock => I_CLK_12M, - q => W_COL_ROM_DO - ); - - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 841b2407..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,86 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_UP : in std_logic; -- active high - I_1P_DW : in std_logic; -- active high - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & "0" & I_1P_DW & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010000" & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - - - --- W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1; --- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & "0" & "0" & "0" & "0" & I_2P_START & I_1P_START; --- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; --- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - --- W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; --- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; --- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; --- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd deleted file mode 100644 index 30030bb2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,440 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - I_BANK : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - k_rom : entity work.sprom - generic map ( - init_file => "./ROM/h.hex", - widthad_a => 11, - width_a => 8) - port map ( - address => W_O_OBJ_ROM_A, - clock => I_CLK_12M, - q => W_1K_D - ); - - h_rom : entity work.sprom - generic map ( - init_file => "./ROM/k.hex", - widthad_a => 11, - width_a => 8) - port map ( - address => W_O_OBJ_ROM_A, - clock => I_CLK_12M, - q => W_1H_D - ); - - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ----------------------------------------------------------------------------------- - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd deleted file mode 100644 index 327691de..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd +++ /dev/null @@ -1,447 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA TripleDrawPoker --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity tripledrawpoker is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(7 downto 0); - P2_CSJUDLR : in std_logic_vector(7 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of tripledrawpoker is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(7), - I_COIN2 => P1_CSJUDLR(6), - I_1P_START => P2_CSJUDLR(0), - I_2P_START => P2_CSJUDLR(1), - I_1P_SH => P1_CSJUDLR(3), --- I_2P_SH => P2_CSJUDLR(4), - I_1P_UP => P1_CSJUDLR(0), --- I_2P_UP => P2_CSJUDLR(3), - I_1P_DW => P1_CSJUDLR(2), --- I_2P_DW => P2_CSJUDLR(2), - I_1P_LE => P1_CSJUDLR(5), --- I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(4), --- I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.sprom - generic map ( - init_file => "./ROM/prog.hex", - widthad_a => 14, - width_a => 8) - port map ( - address => W_A(13 downto 0), - clock => W_CLK_12M, - q => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt deleted file mode 100644 index d6655423..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt +++ /dev/null @@ -1,24 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Uniwars port to MiST by Gehstock --- 19 June 2019 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf deleted file mode 100644 index d116f76a..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf deleted file mode 100644 index a0bc9d80..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 21:51:58 January 08, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "21:51:58 January 08, 2018" - -# Revisions - -PROJECT_REVISION = "Uniwars" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf deleted file mode 100644 index a25c482a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 18:12:35 November 17, 2017 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Uniwars_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Uniwars -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------- -# start ENTITY(Uniwars) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Uniwars) -# -------------------- -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Uniwars.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", - X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", - X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", - X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", - X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", - X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", - X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", - X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", - X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", - X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", - X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", - X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", - X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", - X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", - X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", - X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", - X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", - X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", - X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", - X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", - X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", - X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", - X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", - X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", - X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", - X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", - X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", - X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", - X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE", - X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93", - 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X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E", - X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82", - X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd deleted file mode 100644 index 7d2fd29c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv deleted file mode 100644 index 6b534bfd..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Uniwars -( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Uniwars;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian catacomb( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd deleted file mode 100644 index 138d85cb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,448 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 01cee00a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN1 & I_COIN2; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd deleted file mode 100644 index ec46308a..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,433 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - I_BANK : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1H VID-Rom - k_rom : entity work.GALAXIAN_1H - port map ( - CLK => I_CLK_12M, - ADDR => I_BANK & W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - - -- 1K VID-Rom - h_rom : entity work.GALAXIAN_1K - port map( - CLK => I_CLK_12M, - ADDR => I_BANK & W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ----------------------------------------------------------------------------------- - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt deleted file mode 100644 index d9a15ff7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt +++ /dev/null @@ -1,23 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Victory port to MiST by Gehstock --- 10 Mai 2019 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- F2 : Coin + Start 2 players --- F1 : Coin + Start 1 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf deleted file mode 100644 index 7a0e9b1d..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf deleted file mode 100644 index 31a2bd33..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "Victory" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf deleted file mode 100644 index d4441ceb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf +++ /dev/null @@ -1,188 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 23:19:48 May 18, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Victory_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Victory_MiST.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/k_rom.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/h_rom.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Victory_MiST -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# -------------------------- -# start ENTITY(Victory_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Victory_MiST) -# ------------------------ -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - 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X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E", - X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82", - X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd deleted file mode 100644 index 7d2fd29c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv deleted file mode 100644 index 8f93252c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv +++ /dev/null @@ -1,189 +0,0 @@ -//============================================================================ -// Arcade: Victory -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Victory_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Victory;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.21.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian galaxian -( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) -); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b0,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; - - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; - -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd deleted file mode 100644 index ff7dc99b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,411 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(10 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_1P_UP => P1_CSJUDLR(3), - I_1P_DN => P1_CSJUDLR(2), - I_2P_UP => P2_CSJUDLR(3), - I_2P_DN => P2_CSJUDLR(2), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.prog - port map ( - clk => W_CLK_12M, - addr => W_A(13 downto 0), - data => W_CPU_ROM_DO - ); --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 346b85ee..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,215 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0));--0x4000, 0x43ff - O_WDR_OE <= not W_8N_Q(7);--7800 - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5);--7000 - O_SW0_OE <= not W_8N_Q(4);--6800 - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0);--4000 - - O_PITCH <= not W_8M_Q(7); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0);--4000 - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd deleted file mode 100644 index ca6808bf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(10 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(11,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index ba7e38b1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- - - - crom : entity work.col - port map ( - clk => I_CLK_12M, - addr => W_6M_DO(6 downto 2), - data => W_COL_ROM_DO - ); - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 8c2df5c1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,78 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_1P_UP : in std_logic; -- active high - I_1P_DN : in std_logic; -- active high - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_2P_UP : in std_logic; -- active high - I_2P_DN : in std_logic; -- active high - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP & I_1P_DN & I_1P_SH & I_1P_RI & I_1P_LE & I_2P_DN & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "00" & I_COIN2 & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd deleted file mode 100644 index 252930ba..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,431 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - h_rom : entity work.h_rom - port map ( - clk => I_CLK_12M, - addr => W_O_OBJ_ROM_A, - data => W_1H_D - ); - - k_rom : entity work.k_rom - port map ( - clk => I_CLK_12M, - addr => W_O_OBJ_ROM_A, - data => W_1K_D - ); - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip deleted file mode 100644 index 48665362..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt deleted file mode 100644 index 9d75bb33..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt +++ /dev/null @@ -1,26 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: War of the Bugs port to MiST by Gehstock --- 3 Januar 2018 --- ---------------------------------------------------------------------------------- --- A simulation model of Galaxian hardware --- Copyright(c) 2004 Katsumi Degawa ---------------------------------------------------------------------------------- --- --- Only controls and OSD are rotated on Video output. --- --- --- Keyboard inputs : --- --- ESC : Coin --- F1 : Start 1 player --- F2 : Start 2 player --- SPACE : Fire --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- - -ToDo: Fix long Compilation Time diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf deleted file mode 100644 index 9fd06bf9..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf deleted file mode 100644 index 323e0052..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 14:59:16 November 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "14:59:16 November 16, 2017" - -# Revisions - -PROJECT_REVISION = "WarOfTheBugs" \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf deleted file mode 100644 index 07be9d62..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf +++ /dev/null @@ -1,190 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 18:12:35 November 17, 2017 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Galaxian_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY WarOfTheBugs -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SAVE_DISK_SPACE OFF - -# Fitter Assignments -# ================== -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ---------------------- -# start ENTITY(Galaxian) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Galaxian) -# -------------------- -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/WarOfTheBugs.sv -set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd -set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd -set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd -set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd -set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd -set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd -set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd -set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd -set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -set_global_assignment -name VHDL_FILE rtl/sine_package.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd -set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf deleted file mode 100644 index 14cddd5e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf +++ /dev/null @@ -1,54 +0,0 @@ -{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd deleted file mode 100644 index 5aff2022..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_FIR is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_FIR is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", - X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", - X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", - X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", - X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", - X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", - X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", - X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", - X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", - 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X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E", - X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82", - X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd deleted file mode 100644 index 7d2fd29c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity GAL_HIT is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of GAL_HIT is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", - X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", - X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", - X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", - X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", - X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", - X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", - X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", - 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X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78", - X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D", - X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D", - X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", - X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", - X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", - X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", - X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", - X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", - X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat deleted file mode 100644 index 8d35a90e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat +++ /dev/null @@ -1,20 +0,0 @@ -@echo off - - -copy /b/y warofbug.1j + warofbug.1k gfx1.bin > NUL -copy /b/y warofbug.u + warofbug.v + warofbug.w + warofbug.y + warofbug.z main.bin > NUL - - - -romgen warofbug.cla GALAXIAN_6L 5 a r e > GALAXIAN_6L.vhd - - -romgen gfx1.bin GFX1 12 a r e > GFX1.vhd -romgen main.bin ROM_PGM_0 14 a r e > ROM_PGM_0.vhd - -romgen warofbug.1j GALAXIAN_1H 11 a r e > GALAXIAN_1H.vhd -romgen warofbug.1k GALAXIAN_1K 11 a r e > GALAXIAN_1K.vhd - - -echo done -pause diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin deleted file mode 100644 index 3593689f..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin deleted file mode 100644 index c5f46697..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe deleted file mode 100644 index ab2427f2..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j deleted file mode 100644 index d8c1edde..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k deleted file mode 100644 index 92d611b2..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla deleted file mode 100644 index 298d9068..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u deleted file mode 100644 index 8f554dec..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v deleted file mode 100644 index ce7f3ea7..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w deleted file mode 100644 index cfe60857..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y deleted file mode 100644 index 03c2e3bf..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z deleted file mode 100644 index d1ed656c..00000000 Binary files a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z and /dev/null differ diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd deleted file mode 100644 index 1b3ce2c4..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd +++ /dev/null @@ -1,547 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library UNISIM; - use UNISIM.Vcomponents.all; - -entity GFX1 is - port ( - CLK : in std_logic; - ENA : in std_logic; - ADDR : in std_logic_vector(11 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of GFX1 is - - - type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 - x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 - x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 - x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 - x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 - x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 - x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 - x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 - x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 - x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 - x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 - x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 - x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 - x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 - x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 - x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 - x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 - x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 - x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 - x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 - x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 - x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 - x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 - x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 - x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 - x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 - x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 - x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 - x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 - x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 - x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 - x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 - x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 - x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 - x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 - x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 - x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 - x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 - x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 - x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 - x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 - x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 - x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0158 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0160 - x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0168 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0170 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0178 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0180 - x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0188 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0190 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0198 - x"00",x"00",x"00",x"03",x"0F",x"1F",x"41",x"00", -- 0x01A0 - x"08",x"3C",x"FE",x"E7",x"8F",x"FE",x"FC",x"00", -- 0x01A8 - x"00",x"41",x"1F",x"0F",x"03",x"00",x"00",x"00", -- 0x01B0 - x"00",x"FC",x"FE",x"8F",x"E7",x"FE",x"3C",x"08", -- 0x01B8 - x"06",x"08",x"03",x"24",x"40",x"10",x"20",x"40", -- 0x01C0 - x"60",x"10",x"00",x"30",x"0A",x"21",x"10",x"00", -- 0x01C8 - x"88",x"A8",x"24",x"08",x"40",x"26",x"10",x"03", -- 0x01D0 - x"15",x"15",x"24",x"80",x"12",x"60",x"04",x"90", -- 0x01D8 - x"00",x"00",x"00",x"00",x"04",x"00",x"08",x"09", -- 0x01E0 - x"00",x"00",x"00",x"00",x"80",x"20",x"80",x"50", -- 0x01E8 - x"00",x"02",x"08",x"04",x"00",x"00",x"00",x"00", -- 0x01F0 - x"90",x"00",x"20",x"40",x"00",x"00",x"00",x"00", -- 0x01F8 - x"00",x"00",x"08",x"08",x"E5",x"15",x"15",x"3A", -- 0x0200 - x"00",x"00",x"80",x"90",x"20",x"4E",x"5F",x"BB", -- 0x0208 - x"3A",x"15",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0210 - x"A3",x"5B",x"4E",x"20",x"90",x"80",x"00",x"00", -- 0x0218 - x"00",x"00",x"01",x"22",x"14",x"15",x"15",x"3A", -- 0x0220 - x"00",x"00",x"20",x"48",x"90",x"2E",x"5F",x"BB", -- 0x0228 - x"3A",x"15",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0230 - x"A3",x"5B",x"2E",x"90",x"48",x"20",x"00",x"00", -- 0x0238 - x"10",x"48",x"2C",x"1C",x"06",x"02",x"00",x"00", -- 0x0240 - x"00",x"02",x"04",x"05",x"8E",x"2C",x"98",x"20", -- 0x0248 - x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0250 - x"00",x"40",x"33",x"8C",x"60",x"1E",x"C0",x"38", -- 0x0258 - x"11",x"0A",x"0E",x"04",x"06",x"02",x"00",x"00", -- 0x0260 - x"10",x"14",x"14",x"1C",x"8C",x"28",x"98",x"20", -- 0x0268 - x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0270 - x"01",x"42",x"3C",x"81",x"7E",x"00",x"84",x"78", -- 0x0278 - x"00",x"00",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x0280 - x"50",x"90",x"24",x"44",x"18",x"00",x"80",x"40", -- 0x0288 - x"00",x"06",x"06",x"00",x"01",x"01",x"00",x"00", -- 0x0290 - x"40",x"80",x"00",x"18",x"44",x"24",x"90",x"50", -- 0x0298 - x"00",x"06",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x02A0 - x"00",x"00",x"3C",x"40",x"1F",x"00",x"80",x"C0", -- 0x02A8 - x"00",x"06",x"06",x"00",x"01",x"01",x"06",x"00", -- 0x02B0 - x"C0",x"80",x"00",x"1F",x"40",x"38",x"00",x"00", -- 0x02B8 - x"00",x"FF",x"00",x"9F",x"CF",x"9F",x"00",x"FF", -- 0x02C0 - x"FF",x"FF",x"FF",x"C1",x"BE",x"BE",x"80",x"FF", -- 0x02C8 - x"88",x"77",x"00",x"FF",x"80",x"77",x"80",x"FF", -- 0x02D0 - x"BF",x"80",x"BF",x"FF",x"FE",x"FE",x"80",x"FF", -- 0x02D8 - x"FF",x"80",x"77",x"80",x"FF",x"7E",x"00",x"7E", -- 0x02E0 - x"FE",x"80",x"DE",x"FF",x"C9",x"B6",x"B6",x"C9", -- 0x02E8 - x"FF",x"00",x"CF",x"9F",x"00",x"FF",x"7E",x"76", -- 0x02F0 - x"FF",x"C1",x"B6",x"B6",x"CF",x"FE",x"80",x"DE", -- 0x02F8 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"7E",x"FF",x"EF",x"E7",x"7D",x"3C",x"1C",x"08", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"80", -- 0x0318 - x"7C",x"FE",x"FE",x"C8",x"C0",x"FE",x"7E",x"3C", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"7E",x"FF",x"9F",x"DD",x"65",x"35",x"1C",x"08", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"7C",x"FE",x"FE",x"E2",x"C0",x"EE",x"7E",x"3C", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"7E",x"FF",x"EF",x"ED",x"79",x"38",x"38",x"10", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0358 - x"7C",x"FE",x"FC",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1C",x"08", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"7E",x"FF",x"EF",x"E5",x"7D",x"3D",x"1C",x"08", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"7E",x"FF",x"9F",x"DD",x"65",x"34",x"1C",x"08", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x04B8 - x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"7E",x"FF",x"EF",x"E5",x"7C",x"3C",x"1C",x"08", -- 0x04D0 - x"00",x"00",x"00",x"00",x"80",x"40",x"40",x"00", -- 0x04D8 - x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1D",x"08", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"7F",x"3F",x"3F",x"1E",x"1C",x"0F",x"0F",x"07", -- 0x0610 - x"C0",x"00",x"E0",x"F0",x"E0",x"C0",x"80",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x0630 - x"7C",x"F0",x"FE",x"EF",x"CE",x"FC",x"F8",x"70", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"1C",x"18",x"18",x"1B",x"1F",x"0F",x"03",x"00", -- 0x0650 - x"18",x"7D",x"FD",x"CD",x"DE",x"DC",x"F8",x"70", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"08",x"1C",x"3D",x"7D",x"E7",x"EF",x"FF",x"7E", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0678 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"3C",x"3E",x"1E",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0690 - x"E0",x"70",x"78",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x06B0 - x"18",x"CC",x"CE",x"DE",x"FE",x"FC",x"F8",x"70", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"1C",x"3E", -- 0x06C8 - x"00",x"00",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x06D0 - x"7F",x"FF",x"FF",x"FF",x"FE",x"FC",x"38",x"80", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"1C",x"3F",x"7F",x"EF",x"E7",x"F3",x"78", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x06F8 - x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0700 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0708 - x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0720 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0728 - x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"46",x"2F",x"1F",x"CF",x"3F",x"0F",x"3F",x"C6", -- 0x0740 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0748 - x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0760 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0768 - x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"09",x"17",x"3C",x"1B",x"3F",x"EF",x"DF",x"BF", -- 0x0780 - x"80",x"E0",x"F8",x"CC",x"F4",x"DE",x"EF",x"FF", -- 0x0788 - x"77",x"57",x"DB",x"77",x"3F",x"19",x"0F",x"04", -- 0x0790 - x"EA",x"EA",x"DB",x"7E",x"EC",x"9C",x"F8",x"40", -- 0x0798 - x"03",x"07",x"1F",x"1F",x"3B",x"3F",x"37",x"36", -- 0x07A0 - x"C0",x"E0",x"F0",x"F8",x"7C",x"DC",x"7C",x"AC", -- 0x07A8 - x"3F",x"3D",x"37",x"1B",x"1F",x"1F",x"0F",x"07", -- 0x07B0 - x"6C",x"FC",x"DC",x"BC",x"F8",x"F8",x"F0",x"E0", -- 0x07B8 - x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C0 - x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C8 - x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D0 - x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D8 - x"1E",x"3F",x"7E",x"00",x"00",x"7E",x"3F",x"1E", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0800 - x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0808 - x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0810 - x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0818 - x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0820 - x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0828 - x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0830 - x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0838 - x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0840 - x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0848 - x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0850 - x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0858 - x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0860 - x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0868 - x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0870 - x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0888 - x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0890 - x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0898 - x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x08A0 - x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x08A8 - x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x08B0 - x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x08B8 - x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x08C0 - x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x08C8 - x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x08D0 - x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x08D8 - x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x08E0 - x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x08E8 - x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x08F0 - x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x08F8 - x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0900 - x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0908 - x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0910 - x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0918 - x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0920 - x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0928 - x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0930 - x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0938 - x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0940 - x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0948 - x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0950 - x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0958 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0960 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0968 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0970 - x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0978 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0980 - x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0988 - x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0990 - x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0998 - x"00",x"00",x"00",x"00",x"01",x"00",x"5E",x"FF", -- 0x09A0 - x"00",x"00",x"18",x"7C",x"F4",x"78",x"00",x"F8", -- 0x09A8 - x"FF",x"5E",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x09B0 - x"F8",x"00",x"78",x"F4",x"7C",x"18",x"00",x"00", -- 0x09B8 - x"00",x"00",x"03",x"04",x"01",x"12",x"22",x"00", -- 0x09C0 - x"00",x"00",x"00",x"30",x"08",x"00",x"00",x"C0", -- 0x09C8 - x"02",x"21",x"20",x"10",x"00",x"06",x"00",x"00", -- 0x09D0 - x"44",x"04",x"04",x"00",x"10",x"60",x"00",x"00", -- 0x09D8 - x"02",x"00",x"00",x"10",x"10",x"20",x"00",x"01", -- 0x09E0 - x"C0",x"00",x"10",x"08",x"00",x"00",x"84",x"40", -- 0x09E8 - x"20",x"22",x"00",x"00",x"10",x"00",x"00",x"06", -- 0x09F0 - x"80",x"04",x"04",x"00",x"00",x"10",x"00",x"40", -- 0x09F8 - x"00",x"00",x"08",x"08",x"E5",x"15",x"42",x"2F", -- 0x0A00 - x"00",x"00",x"80",x"90",x"20",x"40",x"84",x"DE", -- 0x0A08 - x"05",x"42",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0A10 - x"5E",x"84",x"40",x"20",x"90",x"80",x"00",x"00", -- 0x0A18 - x"00",x"00",x"01",x"22",x"14",x"15",x"42",x"2F", -- 0x0A20 - x"00",x"00",x"20",x"48",x"90",x"20",x"84",x"DE", -- 0x0A28 - x"05",x"42",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0A30 - x"5E",x"84",x"20",x"90",x"48",x"20",x"00",x"00", -- 0x0A38 - x"10",x"48",x"2C",x"1C",x"06",x"03",x"01",x"03", -- 0x0A40 - x"00",x"02",x"04",x"05",x"4E",x"CC",x"78",x"E0", -- 0x0A48 - x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A50 - x"E0",x"E0",x"F3",x"CC",x"E0",x"9E",x"C0",x"38", -- 0x0A58 - x"11",x"0A",x"0E",x"04",x"06",x"03",x"01",x"03", -- 0x0A60 - x"10",x"14",x"14",x"1C",x"4C",x"C8",x"78",x"E0", -- 0x0A68 - x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A70 - x"E1",x"E2",x"FC",x"C1",x"FE",x"80",x"84",x"78", -- 0x0A78 - x"00",x"00",x"01",x"01",x"03",x"01",x"0B",x"0F", -- 0x0A80 - x"50",x"90",x"24",x"C4",x"D8",x"E0",x"60",x"B0", -- 0x0A88 - x"0F",x"0B",x"01",x"03",x"01",x"01",x"00",x"00", -- 0x0A90 - x"B0",x"60",x"E0",x"D8",x"C4",x"24",x"90",x"50", -- 0x0A98 - x"00",x"06",x"01",x"01",x"03",x"07",x"0D",x"0F", -- 0x0AA0 - x"00",x"00",x"3C",x"C0",x"DF",x"E0",x"60",x"30", -- 0x0AA8 - x"0F",x"0D",x"07",x"03",x"01",x"01",x"06",x"00", -- 0x0AB0 - x"30",x"60",x"E0",x"DF",x"C0",x"38",x"00",x"00", -- 0x0AB8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF8 - x"70",x"F8",x"FC",x"BE",x"9F",x"CC",x"78",x"30", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0B08 - x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1D",x"09", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"70",x"F8",x"FC",x"BF",x"BF",x"CC",x"78",x"30", -- 0x0B20 - x"00",x"00",x"00",x"00",x"C0",x"00",x"00",x"00", -- 0x0B28 - x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"08", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0B38 - x"70",x"F8",x"CC",x"9C",x"BF",x"DC",x"78",x"30", -- 0x0B40 - x"00",x"00",x"40",x"80",x"00",x"00",x"00",x"00", -- 0x0B48 - x"78",x"FC",x"9E",x"DE",x"6A",x"39",x"39",x"12", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"70",x"F9",x"CE",x"8E",x"9C",x"FC",x"78",x"30", -- 0x0B60 - x"C0",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"09", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B88 - x"70",x"F8",x"FC",x"BE",x"9E",x"CD",x"78",x"30", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B98 - x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BA8 - x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BB8 - x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BC0 - x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BD0 - x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BE0 - x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BF0 - x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"78",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"78",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"78",x"FC",x"9E",x"DE",x"66",x"36",x"1E",x"0A", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"78",x"FC",x"EE",x"E6",x"7E",x"3D",x"1C",x"08", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CB8 - x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1C",x"09", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CD8 - x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1E",x"09", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"70", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"78",x"37",x"3F",x"1F",x"1F",x"0C",x"0D",x"07", -- 0x0E10 - x"00",x"00",x"E0",x"30",x"60",x"C0",x"80",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0E30 - x"00",x"30",x"7E",x"F3",x"F6",x"CC",x"D8",x"70", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"19",x"1F",x"1E",x"1D",x"1F",x"0F",x"07",x"06", -- 0x0E50 - x"18",x"7C",x"FC",x"FC",x"B8",x"B0",x"D0",x"60", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"08",x"1C",x"34",x"64",x"DE",x"9E",x"FC",x"78", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0E78 - x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"32", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"3F",x"3D",x"1D",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0E90 - x"00",x"C0",x"E0",x"30",x"F8",x"F0",x"E0",x"C0", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0EB0 - x"60",x"30",x"7E",x"EE",x"CE",x"FC",x"F8",x"70", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"9C",x"3E", -- 0x0EC8 - x"01",x"03",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x0ED0 - x"FE",x"FE",x"FE",x"FC",x"F8",x"F0",x"E0",x"FC", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"1C",x"3C",x"7E",x"FE",x"DE",x"CC",x"7F", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"71",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0EF8 - x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F00 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F08 - x"1F",x"36",x"6F",x"FF",x"CF",x"C6",x"40",x"40", -- 0x0F10 - x"80",x"C0",x"60",x"F0",x"30",x"30",x"20",x"20", -- 0x0F18 - x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F20 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F28 - x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"20",x"20", -- 0x0F30 - x"80",x"C0",x"60",x"F0",x"30",x"60",x"40",x"40", -- 0x0F38 - x"44",x"2C",x"1C",x"CC",x"3C",x"0C",x"3C",x"C4", -- 0x0F40 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F48 - x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"30",x"10", -- 0x0F50 - x"80",x"C0",x"60",x"F0",x"30",x"60",x"C0",x"80", -- 0x0F58 - x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F60 - x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F68 - x"1F",x"36",x"6F",x"FF",x"FF",x"76",x"19",x"06", -- 0x0F70 - x"80",x"C0",x"60",x"F0",x"F0",x"E0",x"80",x"00", -- 0x0F78 - x"0F",x"1F",x"3C",x"3B",x"7E",x"ED",x"DD",x"FF", -- 0x0F80 - x"E0",x"F0",x"F8",x"CC",x"F6",x"FF",x"FF",x"3F", -- 0x0F88 - x"FD",x"DE",x"DF",x"6F",x"7F",x"39",x"1F",x"07", -- 0x0F90 - x"BB",x"FB",x"FB",x"FE",x"EE",x"9C",x"F8",x"C0", -- 0x0F98 - x"01",x"07",x"1F",x"0F",x"2F",x"1F",x"3F",x"3E", -- 0x0FA0 - x"00",x"E0",x"E0",x"F0",x"FC",x"FC",x"78",x"BC", -- 0x0FA8 - x"1F",x"1D",x"3F",x"1F",x"0F",x"1F",x"0F",x"01", -- 0x0FB0 - x"7C",x"F8",x"F8",x"FC",x"F8",x"E8",x"F0",x"A0", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"24",x"14",x"0C",x"3F",x"3F",x"0C",x"14",x"24", -- 0x0FC8 - x"20",x"90",x"40",x"F0",x"F0",x"40",x"90",x"20", -- 0x0FD0 - x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x0FD8 - x"00",x"0C",x"14",x"FE",x"FE",x"14",x"0C",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - DATA <= ROM(to_integer(unsigned(ADDR))); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv deleted file mode 100644 index a9c1d6ef..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv +++ /dev/null @@ -1,192 +0,0 @@ -//============================================================================ -// Arcade: WarOfTheBugs -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module WarOfTheBugs( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "WarOfTheBugs;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0;# -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian warofbugs( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index c07d2629..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1093 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 6bd576cf..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index ee217402..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index 679730ab..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd deleted file mode 100644 index fe477f50..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd +++ /dev/null @@ -1,283 +0,0 @@ ------------------------------------------------------------------------------- --- t80as.vhd : The non-tristate signal edition of t80a.vhd --- --- 2003.2.7 non-tristate modification by Tatsuyuki Satoh --- --- 1.separate 'D' to 'DO' and 'DI'. --- 2.added 'DOE' to 'DO' enable signal.(data direction) --- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. --- --- There is a mark of "--AS" in all the change points. --- ------------------------------------------------------------------------------- - --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80as is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); ---AS-- D : inout std_logic_vector(7 downto 0) ---AS>> - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - DOE : out std_logic ---< 'Z'); ---AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); ---AS>> - MREQ_n <= MREQ_n_i; - IORQ_n <= IORQ_n_i; - RD_n <= RD_n_i; - WR_n <= WR_n_i; - RFSH_n <= RFSH_n_i; - A <= A_i; - DOE <= Write when BUSAK_n_i = '1' else '0'; ---< Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, --- DInst => D, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then ---AS-- DI_Reg <= to_x01(D); ---AS>> - DI_Reg <= to_x01(DI); ---< 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd deleted file mode 100644 index b1ecdcb7..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 11 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd deleted file mode 100644 index dafe8385..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -entity dpram is - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - enable_a : IN STD_LOGIC := '1'; - enable_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone V", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - numwords_b => 2**addr_width_g, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - widthad_b => addr_width_g, - width_a => data_width_g, - width_b => data_width_g, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - address_a => address_a, - address_b => address_b, - clock0 => clock_a, - clock1 => clock_b, - clocken0 => enable_a, - clocken1 => enable_b, - data_a => data_a, - data_b => data_b, - wren_a => wren_a, - wren_b => wren_b, - q_a => q_a, - q_b => q_b - ); - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd deleted file mode 100644 index a2c66505..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,450 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - - -- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_UP => P1_CSJUDLR(3), - I_2P_UP => P2_CSJUDLR(3), - I_1P_DW => P1_CSJUDLR(2), - I_2P_DW => P2_CSJUDLR(2), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - - vmc_sound_b : entity work.MC_SOUND_B - port map( - I_CLK1 => W_CLK_6M, - I_RSTn => rst_count(3), - I_SW => new_sw, - I_DAC => W_DAC, - I_FS => W_FS, - O_SDAT => W_SDAT_B - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.ROM_PGM_0 - port map ( - CLK => W_CLK_12M, - ADDR => W_A(13 downto 0), - DATA => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); --- when "010" => COIN LOCK <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd deleted file mode 100644 index 7245ce8c..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd +++ /dev/null @@ -1,251 +0,0 @@ ---------------------------------------------------------------------- --- FPGA GALAXIAN ADDRESS DECDER --- --- Version : 2.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. ---------------------------------------------------------------------- --- ---GALAXIAN Address Map --- --- Address Item(R..read-mode W..wight-mode) Parts ---0000 - 1FFF CPU-ROM..R ( 7H or 7K ) ---2000 - 3FFF CPU-ROM..R ( 7L ) ---4000 - 47FF CPU-RAM..RW ( 7N & 7P ) ---5000 - 57FF VID-RAM..RW ---5800 - 5FFF OBJ-RAM..RW ---6000 - SW0..R LAMP......W ---6800 - SW1..R SOUND.....W ---7000 - DIP..R ---7001 NMI_ON....W ---7004 STARS_ON..W ---7006 H_FLIP....W ---7007 V-FLIP....W ---7800 WDR..R PITCH.....W --- ---W MODE ---6000 1P START ---6001 2P START ---6002 COIN LOCKOUT ---6003 COIN COUNTER ---6004 - 6007 SOUND CONTROL(OSC) --- ---6800 SOUND CONTROL(FS1) ---6801 SOUND CONTROL(FS2) ---6802 SOUND CONTROL(FS3) ---6803 SOUND CONTROL(HIT) ---6805 SOUND CONTROL(SHOT) ---6806 SOUND CONTROL(VOL1) ---6807 SOUND CONTROL(VOL2) --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_ADEC is - port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_CPU_CLK : in std_logic; - I_RSTn : in std_logic; - - I_CPU_A : in std_logic_vector(15 downto 0); - I_CPU_D : in std_logic; - I_MREQn : in std_logic; - I_RFSHn : in std_logic; - I_RDn : in std_logic; - I_WRn : in std_logic; - I_H_BL : in std_logic; - I_V_BLn : in std_logic; - - O_WAITn : out std_logic; - O_NMIn : out std_logic; - O_CPU_ROM_CS : out std_logic; - O_CPU_RAM_RD : out std_logic; - O_CPU_RAM_WR : out std_logic; - O_CPU_RAM_CS : out std_logic; - O_OBJ_RAM_RD : out std_logic; - O_OBJ_RAM_WR : out std_logic; - O_OBJ_RAM_RQ : out std_logic; - O_VID_RAM_RD : out std_logic; - O_VID_RAM_WR : out std_logic; - O_SW0_OE : out std_logic; - O_SW1_OE : out std_logic; - O_DIP_OE : out std_logic; - O_WDR_OE : out std_logic; - O_DRIVER_WE : out std_logic; - O_SOUND_WE : out std_logic; - O_PITCH : out std_logic; - O_H_FLIP : out std_logic; - O_V_FLIP : out std_logic; - O_BD_G : out std_logic; - O_STARS_ON : out std_logic - ); -end; - -architecture RTL of MC_ADEC is - signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_NMI_ONn : std_logic := '0'; - -------- CPU WAITn ---------------------------------------------- --- signal W_6S1_Q : std_logic := '0'; - signal W_6S1_Qn : std_logic := '0'; --- signal W_6S2_Qn : std_logic := '0'; - - signal W_V_BL : std_logic := '0'; - -begin - W_NMI_ONn <= W_9N_Q(1); -- galaxian - --- O_WAITn <= '1' ; -- No Wait - O_WAITn <= W_6S1_Qn; - - process(I_CPU_CLK, I_V_BLn) - begin - if (I_V_BLn = '0') then --- W_6S1_Q <= '0'; - W_6S1_Qn <= '1'; - elsif rising_edge(I_CPU_CLK) then --- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); - W_6S1_Qn <= I_H_BL or W_8P_Q(2); - end if; - end process; - --- process(I_CPU_CLK) --- begin --- if falling_edge(I_CPU_CLK) then --- W_6S2_Qn <= not W_6S1_Q; --- end if; --- end process; - --------- CPU NMIn ----------------------------------------------- - W_V_BL <= not I_V_BLn; - process(W_V_BL, W_NMI_ONn) - begin - if (W_NMI_ONn = '0') then - O_NMIn <= '1'; - elsif rising_edge(W_V_BL) then - O_NMIn <= '0'; - end if; - end process; - - ------------------------------------------------------------------- - u_8e1 : entity work.LOGIC_74XX139 - port map ( - I_G => I_MREQn, - I_Sel(1) => I_CPU_A(15), - I_Sel(0) => I_CPU_A(14), - O_Q => W_8E1_Q - ); - - ---------- CPU_ROM CS 0000 - 3FFF --------------------------- - u_8e2 : entity work.LOGIC_74XX139 - port map ( - I_G => I_RDn, - I_Sel(1) => W_8E1_Q(0), - I_Sel(0) => I_CPU_A(13), - O_Q => W_8E2_Q - ); - - O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF - ------------------------------------------------------------------- - -- ADDRESS - -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE - -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 - -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE - -- W_8E1_Q[3] = C000 - FFFF - - u_8p : entity work.LOGIC_74XX138 - port map ( - I_G1 => I_RFSHn, - I_G2a => W_8E1_Q(1), -- <= *1 - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8P_Q - ); - - u_8n : entity work.LOGIC_74XX138 - port map ( - I_G1 => '1', - I_G2a => I_RDn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8N_Q - ); - - u_8m : entity work.LOGIC_74XX138 - port map ( - -- I_G1 => W_6S2_Qn, - I_G1 => '1', -- No Wait - I_G2a => I_WRn, - I_G2b => W_8E1_Q(1), -- <= *1 - I_Sel => I_CPU_A(13 downto 11), - O_Q => W_8M_Q - ); - - O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); - O_OBJ_RAM_RQ <= not W_8P_Q(3); - - O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); - - O_WDR_OE <= not W_8N_Q(7); - O_DIP_OE <= not W_8N_Q(6); - O_SW1_OE <= not W_8N_Q(5); - O_SW0_OE <= not W_8N_Q(4); - O_OBJ_RAM_RD <= not W_8N_Q(3); - O_VID_RAM_RD <= not W_8N_Q(2); --- UNUSED <= not W_8N_Q(1); - O_CPU_RAM_RD <= not W_8N_Q(0); - - O_PITCH <= not W_8M_Q(7); --- STARS_ON_ENA <= not W_8M_Q(6); - O_SOUND_WE <= not W_8M_Q(5); - O_DRIVER_WE <= not W_8M_Q(4); - O_OBJ_RAM_WR <= not W_8M_Q(3); - O_VID_RAM_WR <= not W_8M_Q(2); --- UNUSED <= not W_8M_Q(1); - O_CPU_RAM_WR <= not W_8M_Q(0); - - ----- Parts 9N --------- - - process(I_CLK_12M, I_RSTn) - begin - if (I_RSTn = '0') then - W_9N_Q <= (others => '0'); - elsif rising_edge(I_CLK_12M) then - if (W_8M_Q(6) = '0') then - case I_CPU_A(2 downto 0) is - when "000" => W_9N_Q(0) <= I_CPU_D; - when "001" => W_9N_Q(1) <= I_CPU_D; - when "010" => W_9N_Q(2) <= I_CPU_D; - when "011" => W_9N_Q(3) <= I_CPU_D; - when "100" => W_9N_Q(4) <= I_CPU_D; - when "101" => W_9N_Q(5) <= I_CPU_D; - when "110" => W_9N_Q(6) <= I_CPU_D; - when "111" => W_9N_Q(7) <= I_CPU_D; - when others => null; - end case; - end if; - end if; - end process; - - O_STARS_ON <= W_9N_Q(4); - O_H_FLIP <= W_9N_Q(6); - O_V_FLIP <= W_9N_Q(7); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd deleted file mode 100644 index a6df1ce1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA & GALAXIAN --- FPGA BLOCK RAM I/F (XILINX SPARTAN) --- --- Version : 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- mc_col_rom(6L) added by k.Degawa --- --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. K.Degawa --- 2004- 9-18 added Xilinx Device K.Degawa ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_top.v use -entity MC_CPU_RAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(9 downto 0); - I_D : in std_logic_vector(7 downto 0); - I_WE : in std_logic; - I_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) - ); -end; -architecture RTL of MC_CPU_RAM is - - signal W_D : std_logic_vector(7 downto 0) := (others => '0'); -begin - O_D <= W_D when I_OE ='1' else (others=>'0'); - - ram_inst : work.spram generic map(10,8) - port map - ( - address => I_ADDR, - clock => I_CLK, - data => I_D, - wren => I_WE, - q => W_D - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_OBJ_RAM is - port( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(7 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(7 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); - end; - -architecture RTL of MC_OBJ_RAM is -begin - - ram_inst : work.dpram generic map(8,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_VID_RAM is - port ( - I_CLKA : in std_logic := '0'; - I_WEA : in std_logic := '0'; - I_CEA : in std_logic := '0'; - I_ADDRA : in std_logic_vector(9 downto 0); - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - - I_CLKB : in std_logic := '0'; - I_WEB : in std_logic := '0'; - I_CEB : in std_logic := '0'; - I_ADDRB : in std_logic_vector(9 downto 0); - I_DB : in std_logic_vector(7 downto 0); - O_DB : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of MC_VID_RAM is -begin - ram_inst : work.dpram generic map(10,8) - port map - ( - clock_a => I_CLKA, - address_a => I_ADDRA, - data_a => I_DA, - q_a => O_DA, - enable_a => I_CEA, - wren_a => I_WEA, - - clock_b => I_CLKB, - address_b => I_ADDRB, - data_b => I_DB, - q_b => O_DB, - enable_b => I_CEB, - wren_b => I_WEB - ); -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- mc_video.v use -entity MC_LRAM is - port ( - I_CLK : in std_logic; - I_ADDR : in std_logic_vector(7 downto 0); - I_D : in std_logic_vector(4 downto 0); - I_WE : in std_logic; - O_Dn : out std_logic_vector(4 downto 0) - ); -end; - -architecture RTL of MC_LRAM is - signal W_D : std_logic_vector(4 downto 0) := (others => '0'); -begin - - O_Dn <= not W_D; - - ram_inst : work.dpram generic map(8,5) - port map - ( - clock_a => I_CLK, - address_a => I_ADDR, - data_a => I_D, - wren_a => not I_WE, - - clock_b => not I_CLK, - address_b => I_ADDR, - data_b => (others => '0'), - q_b => W_D, - enable_b => '1', - wren_b => '0' - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd deleted file mode 100644 index 5a4d0094..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA CLOCK GEN --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity CLOCKGEN is -port ( - CLKIN_IN : in std_logic; - RST_IN : in std_logic; - -- - O_CLK_24M : out std_logic; - O_CLK_18M : out std_logic; - O_CLK_12M : out std_logic; - O_CLK_06M : out std_logic -); -end; - -architecture RTL of CLOCKGEN is - signal state : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); - signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); - signal CLKFB_IN : std_logic := '0'; - signal CLK0_BUF : std_logic := '0'; - signal CLKFX_BUF : std_logic := '0'; - signal CLK_72M : std_logic := '0'; - signal I_DCM_LOCKED : std_logic := '0'; - -begin - dcm_inst : DCM_SP - generic map ( - CLKFX_MULTIPLY => 9, - CLKFX_DIVIDE => 4, - CLKIN_PERIOD => 31.25 - ) - port map ( - CLKIN => CLKIN_IN, - CLKFB => CLKFB_IN, - RST => RST_IN, - CLK0 => CLK0_BUF, - CLKFX => CLKFX_BUF, - LOCKED => I_DCM_LOCKED - ); - - BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); - BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); - O_CLK_06M <= ctr2(2); - O_CLK_12M <= ctr2(1); - O_CLK_24M <= ctr2(0); - O_CLK_18M <= ctr1(1); - - -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz - process(CLK_72M) - begin - if rising_edge(CLK_72M) then - if (I_DCM_LOCKED = '0') then - state <= "00"; - ctr1 <= (others=>'0'); - ctr2 <= (others=>'0'); - else - ctr1 <= ctr1 + 1; - case state is - when "00" => state <= "01"; ctr2 <= ctr2 + 1; - when "01" => state <= "10"; ctr2 <= ctr2 + 1; - when "10" => state <= "00"; - when "11" => state <= "00"; - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd deleted file mode 100644 index c4dc06ad..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd +++ /dev/null @@ -1,78 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA COLOR-PALETTE --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-18 added Xilinx Device. K.Degawa -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; --- use ieee.numeric_std.all; - ---library UNISIM; --- use UNISIM.Vcomponents.all; - -entity MC_COL_PAL is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_VID : in std_logic_vector(1 downto 0); - I_COL : in std_logic_vector(2 downto 0); - I_C_BLnX : in std_logic; - - O_C_BLXn : out std_logic; - O_STARS_OFFn : out std_logic; - O_R : out std_logic_vector(2 downto 0); - O_G : out std_logic_vector(2 downto 0); - O_B : out std_logic_vector(2 downto 0) -); -end; - -architecture RTL of MC_COL_PAL is - --- Parts 6M -------------------------------------------------------- - signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); - signal W_6M_CLR : std_logic := '0'; - -begin - W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; - W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); - O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); - O_STARS_OFFn <= W_6M_DO(1); - ---always@(posedge I_CLK_6M or negedge W_6M_CLR) - process(I_CLK_6M, W_6M_CLR) - begin - if (W_6M_CLR = '0') then - W_6M_DO <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - W_6M_DO <= W_6M_DI; - end if; - end process; - - --- COL ROM -------------------------------------------------------- ---wire W_COL_ROM_OEn = W_6M_DO[1]; - - galaxian_6l : entity work.GALAXIAN_6L - port map ( - CLK => I_CLK_12M, - ADDR => W_6M_DO(6 downto 2), - DATA => W_COL_ROM_DO - ); - - --- VID OUT -------------------------------------------------------- - O_R <= W_COL_ROM_DO(2 downto 0); - O_G <= W_COL_ROM_DO(5 downto 3); - O_B <= W_COL_ROM_DO(7 downto 6) & "0"; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd deleted file mode 100644 index f310321b..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd +++ /dev/null @@ -1,145 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA H & V COUNTER --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 ------------------------------------------------------------------------ --- MoonCrest hv_count --- H_CNT 0 - 255 , 384 - 511 Total 384 count --- V_CNT 0 - 255 , 504 - 511 Total 264 count -------------------------------------------------------------------------------------------- --- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], --- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_HV_COUNT is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - O_H_CNT : out std_logic_vector(8 downto 0); - O_H_SYNC : out std_logic; - O_H_BL : out std_logic; - O_V_BL2n : out std_logic; - O_V_CNT : out std_logic_vector(7 downto 0); - O_V_SYNC : out std_logic; - O_V_BLn : out std_logic; - O_C_BLn : out std_logic - ); -end; - -architecture RTL of MC_HV_COUNT is - signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal H_SYNC : std_logic := '0'; - signal H_CLK : std_logic := '0'; - signal H_BL : std_logic := '0'; - signal V_BLn : std_logic := '0'; - signal V_BL2n : std_logic := '0'; - -begin ---------- H_COUNT ---------------------------------------- - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if (H_CNT = 255) then - H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); - else - H_CNT <= H_CNT + 1 ; - end if; - end if; - end process; - - O_H_CNT <= H_CNT; - ---------- H_SYNC ---------------------------------------- - H_CLK <= H_CNT(4); - process(H_CLK, H_CNT(8)) - begin - if (H_CNT(8) = '0') then - H_SYNC <= '0'; - elsif rising_edge(H_CLK) then - H_SYNC <= (not H_CNT(6) ) and H_CNT(5); - end if; - end process; - - O_H_SYNC <= H_SYNC; - ---------- H_BL ------------------------------------------ - - process(I_CLK) - begin - if rising_edge(I_CLK) then - if H_CNT = 387 then - H_BL <= '1'; - elsif H_CNT = 503 then - H_BL <= '0'; - end if; - end if; - end process; - - O_H_BL <= H_BL; - ---------- V_COUNT ---------------------------------------- - process(H_SYNC, I_RSTn) - begin - if (I_RSTn = '0') then - V_CNT <= (others => '0'); - elsif rising_edge(H_SYNC) then - if (V_CNT = 255) then - V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); - else - V_CNT <= V_CNT + 1 ; - end if; - end if; - end process; - - O_V_CNT <= V_CNT(7 downto 0); - O_V_SYNC <= V_CNT(8); - ---------- V_BLn ------------------------------------------ - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BLn <= '0'; - elsif V_CNT(7 downto 0) = 15 then - V_BLn <= '1'; - end if; - end if; - end process; - - process(H_SYNC) - begin - if rising_edge(H_SYNC) then - if V_CNT(7 downto 0) = 239 then - V_BL2n <= '0'; - elsif V_CNT(7 downto 0) = 16 then - V_BL2n <= '1'; - end if; - end if; - end process; - - O_V_BLn <= V_BLn; - O_V_BL2n <= V_BL2n; -------- C_BLn ------------------------------------------ - O_C_BLn <= V_BLn and (not H_CNT(8)); - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd deleted file mode 100644 index 25250c11..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------ --- FPGA MOONCRESTA INPORT --- --- Version : 1.01 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004-4-30 galaxian modify by K.DEGAWA ------------------------------------------------------------------------ - --- DIP SW 0 1 2 3 4 5 ------------------------------------------------------------------ --- COIN CHUTE --- 1 COIN/1 PLAY 1'b0 1'b0 --- 2 COIN/1 PLAY 1'b1 1'b0 --- 1 COIN/2 PLAY 1'b0 1'b1 --- FREE PLAY 1'b1 1'b1 --- BOUNS --- 1'b0 1'b0 --- 1'b1 1'b0 --- 1'b0 1'b1 --- 1'b1 1'b1 --- LIVES --- 2 1'b0 --- 3 1'b1 -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_INPORT is -port ( - I_COIN1 : in std_logic; -- active high - I_COIN2 : in std_logic; -- active high - I_1P_LE : in std_logic; -- active high - I_1P_RI : in std_logic; -- active high - I_1P_SH : in std_logic; -- active high - I_1P_UP : in std_logic; -- active high - I_1P_DW : in std_logic; -- active high - - I_2P_LE : in std_logic; - I_2P_RI : in std_logic; - I_2P_SH : in std_logic; - I_2P_UP : in std_logic; -- active high - I_2P_DW : in std_logic; -- active high - I_1P_START : in std_logic; -- active high - I_2P_START : in std_logic; -- active high - I_SW0_OE : in std_logic; - I_SW1_OE : in std_logic; - I_DIP_OE : in std_logic; - O_D : out std_logic_vector(7 downto 0) -); - -end; - -architecture RTL of MC_INPORT is - - constant W_TABLE : std_logic := '0'; -- UP = 0; - constant W_TEST : std_logic := '0'; - constant W_SERVICE : std_logic := '0'; - - signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); - signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); - -begin - - W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1; - W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & I_2P_DW & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; - W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; - O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - --- W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; --- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; --- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; --- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; - - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd deleted file mode 100644 index 0945fe35..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA VIDEO-LD_PLS_GEN --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. -------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_LD_PLS is - port ( - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_3D_DI : in std_logic; - - O_LDn : out std_logic; - O_CNTRLDn : out std_logic; - O_CNTRCLRn : out std_logic; - O_COLLn : out std_logic; - O_VPLn : out std_logic; - O_OBJDATALn : out std_logic; - O_MLDn : out std_logic; - O_SLDn : out std_logic - ); -end; - -architecture RTL of MC_LD_PLS is - signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4C1_Q3 : std_logic := '0'; - signal W_4C2_B : std_logic := '0'; - signal W_4D1_G : std_logic := '0'; - signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_5C_Q : std_logic := '0'; - signal W_HCNT : std_logic := '0'; -begin - O_LDn <= W_4D1_G; - O_CNTRLDn <= W_4D1_Q(2); - O_CNTRCLRn <= W_4D1_Q(0); - O_COLLn <= W_4D2_Q(2); - O_VPLn <= W_4D2_Q(0); - O_OBJDATALn <= W_4C1_Q(2); - O_MLDn <= W_4C2_Q(0); - O_SLDn <= W_4C2_Q(1); - W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); - W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); - -- Parts 4D - u_4d1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_G, - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q =>W_4D1_Q - ); - - u_4d2 : entity work.LOGIC_74XX139 - port map( - I_G => W_5C_Q, - I_Sel(1) => I_H_CNT(2), - I_Sel(0) => I_H_CNT(1), - O_Q => W_4D2_Q - ); - - -- Parts 4C - u_4c1 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D2_Q(1), - I_Sel(1) => I_H_CNT(8), - I_Sel(0) => I_H_CNT(3), - O_Q => W_4C1_Q - ); - - u_4c2 : entity work.LOGIC_74XX139 - port map( - I_G => W_4D1_Q(3), - I_Sel(1) => W_4C2_B, - I_Sel(0) => W_HCNT, - O_Q => W_4C2_Q - ); - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_5C_Q <= I_H_CNT(0); - end if; - end process; - - -- 2004-9-22 added - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - W_4C1_Q3 <= W_4C1_Q(3); - end if; - end process; - - process(W_4C1_Q3) - begin - if rising_edge(W_4C1_Q3) then - W_4C2_B <= I_3D_DI; - end if; - end process; - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd deleted file mode 100644 index 5dae8a87..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd +++ /dev/null @@ -1,92 +0,0 @@ -------------------------------------------------------------------------------- --- FPGA MOONCRESTA LOGIC IP MODULE --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- -------------------------------------------------------------------------------- - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx138 --- 3-to-8 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX138 is - port ( - I_G1 : in std_logic; - I_G2a : in std_logic; - I_G2b : in std_logic; - I_Sel : in std_logic_vector(2 downto 0); - O_Q : out std_logic_vector(7 downto 0) - ); -end logic_74xx138; - -architecture RTL of LOGIC_74XX138 is - signal I_G : std_logic_vector(2 downto 0) := (others => '0'); - -begin - I_G <= I_G1 & I_G2a & I_G2b; - - xx138 : process(I_G, I_Sel) - begin - if(I_G = "100" ) then - case I_Sel is - when "000" => O_Q <= "11111110"; - when "001" => O_Q <= "11111101"; - when "010" => O_Q <= "11111011"; - when "011" => O_Q <= "11110111"; - when "100" => O_Q <= "11101111"; - when "101" => O_Q <= "11011111"; - when "110" => O_Q <= "10111111"; - when "111" => O_Q <= "01111111"; - when others => null; - end case; - else - O_Q <= (others => '1'); - end if; - end process; -end RTL; - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -------------------------------------------------------------------------------- --- 74xx139 --- 2-to-4 line decoder -------------------------------------------------------------------------------- -entity LOGIC_74XX139 is - port ( - I_G : in std_logic; - I_Sel : in std_logic_vector(1 downto 0); - O_Q : out std_logic_vector(3 downto 0) - ); -end; - -architecture RTL of LOGIC_74XX139 is -begin - xx139 : process (I_G, I_Sel) - begin - if I_G = '0' then - case I_Sel is - when "00" => O_Q <= "1110"; - when "01" => O_Q <= "1101"; - when "10" => O_Q <= "1011"; - when "11" => O_Q <= "0111"; - when others => null; - end case; - else - O_Q <= "1111"; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd deleted file mode 100644 index c5aa6633..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA VIDEO-MISSILE ----- ----- Version : 2.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_MISSILE is - port( - I_CLK_6M : in std_logic; - I_CLK_18M : in std_logic; - I_C_BLn_X : in std_logic; - I_MLDn : in std_logic; - I_SLDn : in std_logic; - I_HPOS : in std_logic_vector (7 downto 0); - - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic - ); -end; - -architecture RTL of MC_MISSILE is - signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); - signal W_5P1_Q : std_logic := '0'; - signal W_5P2_Q : std_logic := '0'; - signal W_5P1_CLK : std_logic := '0'; - signal W_5P2_CLK : std_logic := '0'; -begin - - O_MISSILEn <= W_5P1_CLK; - O_SHELLn <= W_5P2_CLK; - - -- missile counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if (I_MLDn = '0') then - W_45R_Q <= I_HPOS; - else - if (I_C_BLn_X = '1') then - W_45R_Q <= W_45R_Q + 1; - if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then - W_5P1_CLK <= '0'; - else - W_5P1_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- shell counter - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - if(I_SLDn = '0') then - W_45S_Q <= I_HPOS; - else - if(I_C_BLn_X = '1') then - W_45S_Q <= W_45S_Q + 1; - if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then - W_5P2_CLK <= '0'; - else - W_5P2_CLK <= '1'; - end if; - end if; - end if; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) - process(W_5P1_CLK, I_MLDn) - begin - if (I_MLDn = '0') then - W_5P1_Q <= '1'; - elsif rising_edge(W_5P1_CLK) then - W_5P1_Q <= '0'; - end if; - end process; - - -- Standard D-type flip-flop with D input tied low, async active - -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) - process(W_5P2_CLK, I_SLDn) - begin - if (I_SLDn = '0') then - W_5P2_Q <= '1'; - elsif rising_edge(W_5P2_CLK) then - W_5P2_Q <= '0'; - end if; - end process; - -end RTL; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd deleted file mode 100644 index ee0c66be..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA SOUND I/F --- --- Version : 1.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - use IEEE.std_logic_arith.all; - -entity MC_SOUND_A is -port ( - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT1 : in std_logic; - I_BD : in std_logic_vector(7 downto 0); - I_PITCH : in std_logic; - I_VOL1 : in std_logic; - I_VOL2 : in std_logic; - - O_SDAT : out std_logic_vector(7 downto 0); - O_DO : out std_logic_vector(3 downto 0) -); -end; - -architecture RTL of MC_SOUND_A is - signal W_PITCH : std_logic := '0'; - signal W_89K_LDn : std_logic := '0'; - signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); - signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); - signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); - signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); - signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); - -begin - O_DO <= W_6T_Q; - - process (I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_PITCH <= I_PITCH; - if (W_89K_Q = x"ff") then - W_89K_LDn <= '0' ; - else - W_89K_LDn <= '1' ; - end if; - end if; - end process; - - -- Parts 9J - process (W_PITCH) - begin - if falling_edge(W_PITCH) then - W_89K_LDATA <= I_BD; - end if; - end process; - - process (I_H_CNT1) - begin - if rising_edge(I_H_CNT1) then - if (W_89K_LDn = '0') then - W_89K_Q <= W_89K_LDATA; - else - W_89K_Q <= W_89K_Q + 1; - end if; - end if; - end process; - - process (W_89K_LDn) - begin - if falling_edge(W_89K_LDn) then - W_6T_Q <= W_6T_Q + 1; - end if; - end process; - - process (I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); - - if W_6T_Q(0)='1' then - W_SDAT0 <= x"2a"; - else - W_SDAT0 <= (others => '0'); - end if; - - if W_6T_Q(2)='1' then - if I_VOL1 = '1' then - W_SDAT2 <= x"69"; - else - W_SDAT2 <= x"39"; - end if; - else - W_SDAT2 <= (others => '0'); - end if; - - if (W_6T_Q(3)='1') and (I_VOL2 = '1') then - W_SDAT3 <= x"48" ; - else - W_SDAT3 <= (others => '0'); - end if; - - end if; - end process; - -end; \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd deleted file mode 100644 index b74e4bb1..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA MOONCRESTA WAVE SOUND ----- ----- Version : 1.00 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does no guarantee this program. ----- You can use this at your own risk. ----- --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off --- use ieee.std_logic_textio.all; --- use std.textio.all; ---pragma translate_on - -entity MC_SOUND_B is - port( - I_CLK1 : in std_logic; -- 6MHz - I_RSTn : in std_logic; - I_SW : in std_logic_vector( 2 downto 0); - I_DAC : in std_logic_vector( 3 downto 0); - I_FS : in std_logic_vector( 2 downto 0); - O_SDAT : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_B is -constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz -constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; -constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; - -signal sample : std_logic_vector(10 downto 0) := (others => '0'); -signal sample_pls : std_logic := '0'; -signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s0_trg : std_logic := '0'; -signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); -signal s1_trg : std_logic := '0'; -signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); - -signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); -signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - -signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); -signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); - -signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); - -begin - -- ideally we should divide by 5 because this is the sum of 5 channels - -- but in practice we divide by 4 and just clip sounds that are too loud. - O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds - - process(I_CLK1) - begin - if rising_edge(I_CLK1) then - SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - sample <= (others => '0'); - sample_pls <= '0'; - elsif rising_edge(I_CLK1) then - if (sample = sample_time - 1) then - sample <= (others => '0'); - sample_pls <= '1'; - else - sample <= sample + 1; - sample_pls <= '0'; - end if; - end if; - end process; - -------------- FIRE SOUND ------------------------------------------ - mc_roms_fire : entity work.GAL_FIR - port map ( - CLK => I_CLK1, - ADDR => fire_addr(12 downto 0), - DATA => WAV_D0 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s0_trg_ff <= (others => '0'); - s0_trg <= '0'; - elsif rising_edge(I_CLK1) then - s0_trg_ff(0) <= I_SW(0); - s0_trg_ff(1) <= s0_trg_ff(0); - s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - fire_addr <= fire_cnt; - elsif rising_edge(I_CLK1) then - if (s0_trg = '1') then - fire_addr <= (others => '0'); - else - if(sample_pls = '1') then - if(fire_addr <= fire_cnt) then - fire_addr <= fire_addr + 1; - else - fire_addr <= fire_addr ; - end if; - end if; - end if; - end if; - end process; - -------------- HIT SOUND ------------------------------------------ - mc_roms_hit : entity work.GAL_HIT - port map ( - CLK => I_CLK1, - ADDR => hit_addr(12 downto 0), - DATA => WAV_D1 - ); - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - s1_trg_ff <= (others => '0'); - s1_trg <= '0'; - elsif rising_edge(I_CLK1) then - s1_trg_ff(0) <= I_SW(1); - s1_trg_ff(1) <= s1_trg_ff(0); - s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); - end if; - end process; - - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - hit_addr <= hit_cnt; - elsif rising_edge(I_CLK1) then - if (s1_trg = '1') then - hit_addr <= (others => '0'); - else - if (sample_pls = '1') then - if (hit_addr <= hit_cnt) then - hit_addr <= hit_addr + 1 ; - else - hit_addr <= hit_addr ; - end if; - end if; - end if; - end if; - end process; - ---------------- EFFECT SOUND --------------------------------------- - --- 9R modulator voltage generator based on DAC value - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - VCO_CTR <= (others=>'0'); - elsif rising_edge(I_CLK1) then - VCO_CTR <= VCO_CTR + (not I_DAC); - end if; - end process; - - -- modulator frequency lookup tables for the three VCOs - process(I_CLK1, I_RSTn) - begin - if (I_RSTn = '0') then - elsif rising_edge(I_CLK1) then - case VCO_CTR(23 downto 19) is - when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; - when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; - when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; - when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; - when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; - when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; - when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; - when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; - when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; - when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; - when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; - when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; - when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; - when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; - when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; - when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; - when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; - when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; - when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; - when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; - when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; - when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; - when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; - when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; - when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; - when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; - when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; - when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; - when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; - when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; - when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; - when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; - when others => null; - end case; - end if; - end process; - --- 8R VCO 240Hz - 140Hz (8) - mc_vco1 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(0), - I_STEP => W_VCO1_STEP, - O_WAV => W_VCO1_OUT - ); - --- 8S VCO 330Hz - 190Hz (11) - mc_vco2 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(1), - I_STEP => W_VCO2_STEP, - O_WAV => W_VCO2_OUT - ); - --- 8T VCO 480Hz - 270Hz (16) - mc_vco3 : entity work.MC_SOUND_VCO - port map ( - I_CLK => I_CLK1, - I_RSTn => I_RSTn, - I_FS => I_FS(2), - I_STEP => W_VCO3_STEP, - O_WAV => W_VCO3_OUT - ); -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd deleted file mode 100644 index e2a63e85..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd +++ /dev/null @@ -1,49 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA VCO --------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -use work.sine_package.all; - --- O_CLK = (I_CLK / 2^20) * I_STEP -entity MC_SOUND_VCO is - port( - I_CLK : in std_logic; - I_RSTn : in std_logic; - I_FS : in std_logic; - I_STEP : in std_logic_vector( 7 downto 0); - O_WAV : out std_logic_vector( 7 downto 0) - ); -end; - -architecture RTL of MC_SOUND_VCO is - signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); - signal sine : std_logic_vector(14 downto 0) := (others => '0'); - -begin - O_WAV <= sine(14 downto 7); - process(I_CLK, I_RSTn) - begin - if (I_RSTn = '0') then - VCO1_CTR <= (others=>'0'); - elsif rising_edge(I_CLK) then - if I_FS = '1' then - VCO1_CTR <= VCO1_CTR + I_STEP; - case VCO1_CTR(19 downto 18) is - when "00" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "01" => - sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when "10" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); - when "11" => - sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); - when others => null; - end case; - end if; - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd deleted file mode 100644 index b91197b3..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd +++ /dev/null @@ -1,90 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA MOONCRESTA STARS --- --- Version : 2.00 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important ! --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity MC_STARS is - port ( - I_CLK_18M : in std_logic; - I_CLK_6M : in std_logic; - I_H_FLIP : in std_logic; - I_V_SYNC : in std_logic; - I_8HF : in std_logic; - I_256HnX : in std_logic; - I_1VF : in std_logic; - I_2V : in std_logic; - I_STARS_ON : in std_logic; - I_STARS_OFFn : in std_logic; - - O_R : out std_logic_vector(1 downto 0); - O_G : out std_logic_vector(1 downto 0); - O_B : out std_logic_vector(1 downto 0); - O_NOISE : out std_logic - ); -end; - -architecture RTL of MC_STARS is - signal CLK_1C : std_logic := '0'; - signal W_2D_Qn : std_logic := '0'; - - signal W_3B : std_logic := '0'; - signal noise : std_logic := '0'; - signal W_2A : std_logic := '0'; - signal W_4P : std_logic := '0'; - signal CLK_1AB : std_logic := '0'; - signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); - signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); -begin - O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); - - CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); - CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); - W_3B <= W_2D_Qn xor W_1AB_Q(4); - - W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; - W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); - - O_NOISE <= noise ; - - process(I_2V) - begin - if rising_edge(I_2V) then - noise <= W_2D_Qn; - end if; - end process; - - process(CLK_1C, I_V_SYNC) - begin - if(I_V_SYNC = '1') then - W_1C_Q <= (others => '0'); - elsif rising_edge(CLK_1C) then - W_1C_Q <= W_1C_Q(0) & '1'; - end if; - end process; - - process(CLK_1AB, I_STARS_ON) - begin - if(I_STARS_ON = '0') then - W_1AB_Q <= (others => '0'); - W_2D_Qn <= '1'; - elsif rising_edge(CLK_1AB) then - W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; - W_2D_Qn <= not W_1AB_Q(15); - end if; - end process; -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd deleted file mode 100644 index 9642043d..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd +++ /dev/null @@ -1,436 +0,0 @@ --------------------------------------------------------------------------------- ----- FPGA GALAXIAN VIDEO ----- ----- Version : 2.50 ----- ----- Copyright(c) 2004 Katsumi Degawa , All rights reserved ----- ----- Important ! ----- ----- This program is freeware for non-commercial use. ----- The author does not guarantee this program. ----- You can use this at your own risk. ----- ----- 2004- 4-30 galaxian modify by K.DEGAWA ----- 2004- 5- 6 first release. ----- 2004- 8-23 Improvement with T80-IP. ----- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. --------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- --- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), --- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H -------------------------------------------------------------------------------------------- --- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) --- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V -------------------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity MC_VIDEO is - port( - I_CLK_18M : in std_logic; - I_CLK_12M : in std_logic; - I_CLK_6M : in std_logic; - I_H_CNT : in std_logic_vector(8 downto 0); - I_V_CNT : in std_logic_vector(7 downto 0); - I_H_FLIP : in std_logic; - I_V_FLIP : in std_logic; - I_V_BLn : in std_logic; - I_C_BLn : in std_logic; - - I_A : in std_logic_vector(9 downto 0); - I_BD : in std_logic_vector(7 downto 0); - I_OBJ_SUB_A : in std_logic_vector(2 downto 0); - I_OBJ_RAM_RQ : in std_logic; - I_OBJ_RAM_RD : in std_logic; - I_OBJ_RAM_WR : in std_logic; - I_VID_RAM_RD : in std_logic; - I_VID_RAM_WR : in std_logic; - I_DRIVER_WR : in std_logic; - - - O_C_BLnX : out std_logic; - O_8HF : out std_logic; - O_256HnX : out std_logic; - O_1VF : out std_logic; - O_MISSILEn : out std_logic; - O_SHELLn : out std_logic; - - O_BD : out std_logic_vector(7 downto 0); - O_VID : out std_logic_vector(1 downto 0); - O_COL : out std_logic_vector(2 downto 0) - ); -end; - -architecture RTL of MC_VIDEO is - - signal WB_LDn : std_logic := '0'; - signal WB_CNTRLDn : std_logic := '0'; - signal WB_CNTRCLRn : std_logic := '0'; - signal WB_COLLn : std_logic := '0'; - signal WB_VPLn : std_logic := '0'; - signal WB_OBJDATALn : std_logic := '0'; - signal WB_MLDn : std_logic := '0'; - signal WB_SLDn : std_logic := '0'; - signal W_3D : std_logic := '0'; - signal W_LDn : std_logic := '0'; - signal W_CNTRLDn : std_logic := '0'; - signal W_CNTRCLRn : std_logic := '0'; - signal W_COLLn : std_logic := '0'; - signal W_VPLn : std_logic := '0'; - signal W_OBJDATALn : std_logic := '0'; - signal W_MLDn : std_logic := '0'; - signal W_SLDn : std_logic := '0'; - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); - signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); - signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); - - signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); - signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); - signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); - signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); - signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); - signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); --- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_256HnX : std_logic := '0'; - signal W_2N : std_logic := '0'; - signal W_45T_CLR : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_H_FLIP1 : std_logic := '0'; - signal W_H_FLIP2 : std_logic := '0'; - signal W_H_FLIP1X : std_logic := '0'; - signal W_H_FLIP2X : std_logic := '0'; - signal W_LRAM_AND : std_logic := '0'; - signal W_RAW0 : std_logic := '0'; - signal W_RAW1 : std_logic := '0'; - signal W_RAW_OR : std_logic := '0'; - signal W_SRCLK : std_logic := '0'; - signal W_SRLD : std_logic := '0'; - signal W_VID_RAM_CS : std_logic := '0'; - signal W_CLK_6Mn : std_logic := '0'; - -begin - - ld_pls : entity work.MC_LD_PLS - port map( - I_CLK_6M => I_CLK_6M, - I_H_CNT => I_H_CNT, - I_3D_DI => W_3D, - - O_LDn => WB_LDn, - O_CNTRLDn => WB_CNTRLDn, - O_CNTRCLRn => WB_CNTRCLRn, - O_COLLn => WB_COLLn, - O_VPLn => WB_VPLn, - O_OBJDATALn => WB_OBJDATALn, - O_MLDn => WB_MLDn, - O_SLDn => WB_SLDn - ); - - obj_ram : entity work.MC_OBJ_RAM - port map( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(7 downto 0), - I_WEA => I_OBJ_RAM_WR, - I_CEA => I_OBJ_RAM_RQ, - I_DA => I_BD, - O_DA => W_OBJ_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_OBJ_RAM_AB, - I_WEB => '0', - I_CEB => '1', - I_DB => x"00", - O_DB => W_OBJ_RAM_DOB - ); - - lram : entity work.MC_LRAM - port map( - I_CLK => I_CLK_18M, - I_ADDR => W_LRAM_A, - I_WE => W_CLK_6Mn, - I_D => W_LRAM_DI, - O_Dn => W_LRAM_DO - ); - - missile : entity work.MC_MISSILE - port map( - I_CLK_18M => I_CLK_18M, - I_CLK_6M => I_CLK_6M, - I_C_BLn_X => W_C_BLnX, - I_MLDn => W_MLDn, - I_SLDn => W_SLDn, - I_HPOS => W_H_POSI, - O_MISSILEn => O_MISSILEn, - O_SHELLn => O_SHELLn - ); - - vid_ram : entity work.MC_VID_RAM - port map ( - I_CLKA => I_CLK_12M, - I_ADDRA => I_A(9 downto 0), - I_DA => W_VID_RAM_DI, - I_WEA => I_VID_RAM_WR, - I_CEA => W_VID_RAM_CS, - O_DA => W_VID_RAM_DOA, - - I_CLKB => I_CLK_12M, - I_ADDRB => W_VID_RAM_A(9 downto 0), - I_DB => x"00", - I_WEB => '0', - I_CEB => '1', - O_DB => W_VID_RAM_DOB - ); - - -- 1H VID-Rom - k_rom : entity work.GALAXIAN_1H - port map ( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1H_D - ); - - -- 1K VID-Rom - h_rom : entity work.GALAXIAN_1K - port map( - CLK => I_CLK_12M, - ADDR => W_O_OBJ_ROM_A, - DATA => W_1K_D - ); - - ------------------------------------------------------------------------------------ - - process(I_CLK_12M) - begin - if falling_edge(I_CLK_12M) then - W_LDn <= WB_LDn; - W_CNTRLDn <= WB_CNTRLDn; - W_CNTRCLRn <= WB_CNTRCLRn; - W_COLLn <= WB_COLLn; - W_VPLn <= WB_VPLn; - W_OBJDATALn <= WB_OBJDATALn; - W_MLDn <= WB_MLDn; - W_SLDn <= WB_SLDn; - end if; - end process; - - W_CLK_6Mn <= not I_CLK_6M; - - W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); - W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); - W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; - - W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; - - W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); - W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; - - O_8HF <= W_HF_CNT(3); - O_1VF <= W_VF_CNT(0); - W_H_FLIP2 <= W_6J_Q(3); - --- Parts 4F,5F - W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); --- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; - - process(I_CLK_12M) - begin - if rising_edge(I_CLK_12M) then - W_H_POSI <= W_OBJ_RAM_DOB; - end if; - end process; - - W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); - --- Parts 4L - process(W_OBJDATALn) - begin - if rising_edge(W_OBJDATALn) then - W_OBJ_D <= W_H_POSI; - end if; - end process; - --- Parts 4,5N - W_45N_Q <= W_VF_CNT + W_H_POSI; - W_3D <= '0' when W_45N_Q = x"FF" else '1'; - - process(W_VPLn, I_V_BLn) - begin - if (I_V_BLn = '0') then - W_2M_Q <= (others => '0'); - elsif rising_edge(W_VPLn) then - W_2M_Q <= W_45N_Q; - end if; - end process; - - W_2N <= I_H_CNT(8) and W_OBJ_D(7); - W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); - W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; - W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); - W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) - W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); - W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; - W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); - ----- VIDEO DATA OUTPUT -------------- - - O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; - W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); - W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); - W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; - W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); - ------------------------------------------------------------------------------------ - - W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; - W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; - W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 - C_2HJ <= W_3L_Y(1 downto 0); - C_2KL <= W_3L_Y(1 downto 0); - W_RAW0 <= W_3L_Y(2); - W_RAW1 <= W_3L_Y(3); - W_SRCLK <= I_CLK_6M; - --------- PARTS 2KL ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2KL) is - when "00" => reg_2KL <= reg_2KL; - when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; - when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); - when "11" => reg_2KL <= W_1K_D; - when others => null; - end case; - end if; - end process; - --------- PARTS 2HJ ---------------------------------------------- - - process(W_SRCLK) - begin - if rising_edge(W_SRCLK) then - case(C_2HJ) is - when "00" => reg_2HJ <= reg_2HJ; - when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; - when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); - when "11" => reg_2HJ <= W_1H_D; - when others => null; - end case; - end if; - end process; - -------- SHT2 ----------------------------------------------------- - --- Parts 6K - process(W_COLLn) - begin - if rising_edge(W_COLLn) then - W_6K_Q <= W_H_POSI(2 downto 0); - end if; - end process; - --- Parts 6P - process(I_CLK_6M) - begin - if rising_edge(I_CLK_6M) then - if (W_LDn = '0') then - W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); - else - W_6P_Q <= W_6P_Q; - end if; - end if; - end process; - - W_H_FLIP2X <= W_6P_Q(6); - W_H_FLIP1X <= W_6P_Q(5); - W_C_BLnX <= W_6P_Q(4); - W_256HnX <= W_6P_Q(3); - W_CD <= W_6P_Q(2 downto 0); - O_256HnX <= W_256HnX; - O_C_BLnX <= W_C_BLnX; - W_45T_CLR <= W_CNTRCLRn or W_256HnX ; - - process(I_CLK_6M, W_45T_CLR) - begin - if (W_45T_CLR = '0') then - W_45T_Q <= (others => '0'); - elsif rising_edge(I_CLK_6M) then - if (W_CNTRLDn = '0') then - W_45T_Q <= W_H_POSI; - else - W_45T_Q <= W_45T_Q + 1; - end if; - end if; - end process; - - W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; - - process(I_CLK_6M) - begin - if falling_edge(I_CLK_6M) then - W_RV <= W_LRAM_DO(1 downto 0); - W_RC <= W_LRAM_DO(4 downto 2); - end if; - end process; - - W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); - W_RAW_OR <= W_RAW0 or W_RAW1 ; - - W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); - W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); - W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); - W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); - W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); - - O_VID <= W_VID; - O_COL <= W_COL; - - W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); - W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); - W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); - W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); - W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); - -end RTL; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v deleted file mode 100644 index 2f41221f..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v +++ /dev/null @@ -1,530 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, -// output reg [31:0] joystick_2, -// output reg [31:0] joystick_3, -// output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoublerD, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoublerD = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; -// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; -// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -reg rdownload = 0; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index[4:0]) - 1: addr <= 25'h200000; // TRD buffer at 2MB - 2: addr <= 25'h400000; // tape buffer at 4MB - default: addr <= 25'h150000; // boot rom - endcase - rdownload <= 1; - end else begin - addr_w <= addr; - rdownload <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - rclk <= ~rclk; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -// transfer to ioctl_clk domain. -// ioctl_index is set before ioctl_download, so it's stable already -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - if(ioctl_ce) begin - ioctl_download <= rdownload; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD != rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - end -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v deleted file mode 100644 index b9181763..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v +++ /dev/null @@ -1,194 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - input [1:0] rotate, //[0] - rotate [1] - left or right - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [10:0] osd_buffer_addr; -wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; -reg osd_pixel; - -always @(posedge clk_sys) begin - if(ce_pix) begin - osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], - rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : - (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : - {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; - - osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : - osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - end -end - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd deleted file mode 100644 index 2822d752..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd +++ /dev/null @@ -1,451 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 3, - clk1_duty_cycle => 50, - clk1_multiply_by => 2, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "0", - clk3_divide_by => 9, - clk3_duty_cycle => 50, - clk3_multiply_by => 2, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd deleted file mode 100644 index 473caa04..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd +++ /dev/null @@ -1,152 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package sine_package is - - subtype table_value_type is integer range 0 to 16383; - subtype table_index_type is std_logic_vector( 6 downto 0 ); - - function get_table_value (table_index: table_index_type) return table_value_type; - -end; - -package body sine_package is - - function get_table_value (table_index: table_index_type) return table_value_type is - variable table_value: table_value_type; - begin - case table_index is - when "0000000" => table_value := 101; - when "0000001" => table_value := 302; - when "0000010" => table_value := 503; - when "0000011" => table_value := 703; - when "0000100" => table_value := 904; - when "0000101" => table_value := 1105; - when "0000110" => table_value := 1305; - when "0000111" => table_value := 1506; - when "0001000" => table_value := 1706; - when "0001001" => table_value := 1906; - when "0001010" => table_value := 2105; - when "0001011" => table_value := 2304; - when "0001100" => table_value := 2503; - when "0001101" => table_value := 2702; - when "0001110" => table_value := 2900; - when "0001111" => table_value := 3098; - when "0010000" => table_value := 3295; - when "0010001" => table_value := 3491; - when "0010010" => table_value := 3688; - when "0010011" => table_value := 3883; - when "0010100" => table_value := 4078; - when "0010101" => table_value := 4273; - when "0010110" => table_value := 4466; - when "0010111" => table_value := 4659; - when "0011000" => table_value := 4852; - when "0011001" => table_value := 5044; - when "0011010" => table_value := 5234; - when "0011011" => table_value := 5425; - when "0011100" => table_value := 5614; - when "0011101" => table_value := 5802; - when "0011110" => table_value := 5990; - when "0011111" => table_value := 6177; - when "0100000" => table_value := 6362; - when "0100001" => table_value := 6547; - when "0100010" => table_value := 6731; - when "0100011" => table_value := 6914; - when "0100100" => table_value := 7095; - when "0100101" => table_value := 7276; - when "0100110" => table_value := 7456; - when "0100111" => table_value := 7634; - when "0101000" => table_value := 7811; - when "0101001" => table_value := 7988; - when "0101010" => table_value := 8162; - when "0101011" => table_value := 8336; - when "0101100" => table_value := 8509; - when "0101101" => table_value := 8680; - when "0101110" => table_value := 8850; - when "0101111" => table_value := 9018; - when "0110000" => table_value := 9185; - when "0110001" => table_value := 9351; - when "0110010" => table_value := 9515; - when "0110011" => table_value := 9678; - when "0110100" => table_value := 9840; - when "0110101" => table_value := 10000; - when "0110110" => table_value := 10158; - when "0110111" => table_value := 10315; - when "0111000" => table_value := 10471; - when "0111001" => table_value := 10625; - when "0111010" => table_value := 10777; - when "0111011" => table_value := 10927; - when "0111100" => table_value := 11076; - when "0111101" => table_value := 11224; - when "0111110" => table_value := 11369; - when "0111111" => table_value := 11513; - when "1000000" => table_value := 11655; - when "1000001" => table_value := 11796; - when "1000010" => table_value := 11934; - when "1000011" => table_value := 12071; - when "1000100" => table_value := 12206; - when "1000101" => table_value := 12339; - when "1000110" => table_value := 12471; - when "1000111" => table_value := 12600; - when "1001000" => table_value := 12728; - when "1001001" => table_value := 12853; - when "1001010" => table_value := 12977; - when "1001011" => table_value := 13099; - when "1001100" => table_value := 13219; - when "1001101" => table_value := 13336; - when "1001110" => table_value := 13452; - when "1001111" => table_value := 13566; - when "1010000" => table_value := 13678; - when "1010001" => table_value := 13787; - when "1010010" => table_value := 13895; - when "1010011" => table_value := 14000; - when "1010100" => table_value := 14104; - when "1010101" => table_value := 14205; - when "1010110" => table_value := 14304; - when "1010111" => table_value := 14401; - when "1011000" => table_value := 14496; - when "1011001" => table_value := 14588; - when "1011010" => table_value := 14679; - when "1011011" => table_value := 14767; - when "1011100" => table_value := 14853; - when "1011101" => table_value := 14936; - when "1011110" => table_value := 15018; - when "1011111" => table_value := 15097; - when "1100000" => table_value := 15174; - when "1100001" => table_value := 15249; - when "1100010" => table_value := 15321; - when "1100011" => table_value := 15391; - when "1100100" => table_value := 15459; - when "1100101" => table_value := 15524; - when "1100110" => table_value := 15587; - when "1100111" => table_value := 15648; - when "1101000" => table_value := 15706; - when "1101001" => table_value := 15762; - when "1101010" => table_value := 15816; - when "1101011" => table_value := 15867; - when "1101100" => table_value := 15916; - when "1101101" => table_value := 15963; - when "1101110" => table_value := 16007; - when "1101111" => table_value := 16048; - when "1110000" => table_value := 16088; - when "1110001" => table_value := 16124; - when "1110010" => table_value := 16159; - when "1110011" => table_value := 16191; - when "1110100" => table_value := 16220; - when "1110101" => table_value := 16247; - when "1110110" => table_value := 16272; - when "1110111" => table_value := 16294; - when "1111000" => table_value := 16314; - when "1111001" => table_value := 16331; - when "1111010" => table_value := 16346; - when "1111011" => table_value := 16358; - when "1111100" => table_value := 16368; - when "1111101" => table_value := 16375; - when "1111110" => table_value := 16380; - when "1111111" => table_value := 16383; - when others => null; - end case; - return table_value; - end; - -end; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd deleted file mode 100644 index ad6b58b5..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd +++ /dev/null @@ -1,55 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY spram IS - generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); - clken : IN STD_LOGIC := '1'; - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - -BEGIN - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone V", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**addr_width_g, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => addr_width_g, - width_a => data_width_g, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => address, - clock0 => clock, - clocken0 => clken, - data_a => data, - wren_a => wren, - q_a => q - ); - - - -END SYN; diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv deleted file mode 100644 index 79d8ca03..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,243 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 480, - parameter HALF_DEPTH = 1, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoublerD, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - input [1:0] rotate, //[0] - rotate [1] - left or right - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); -wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); -wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoublerD ? HSync : hs_sd); -wire vs = (scandoublerD ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - .rotate(rotate), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule