diff --git a/Arcade_MiST/.gitignore b/Arcade_MiST/.gitignore
new file mode 100644
index 00000000..896db0ea
--- /dev/null
+++ b/Arcade_MiST/.gitignore
@@ -0,0 +1,2 @@
+test/
+
diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/README.txt b/Arcade_MiST/Galaga Hardware/Xevious_MiST/README.txt
deleted file mode 100644
index 701865d0..00000000
--- a/Arcade_MiST/Galaga Hardware/Xevious_MiST/README.txt	
+++ /dev/null
@@ -1,164 +0,0 @@
-Super Bagman Port to Mist FPGA by Gehstock
-
-SBAGMAN.ROM is required at the root of the SD-Card.
-
--------------------------------------------------
-Bagman (STERN) FPGA - (darfpga@aol.fr)
--- http://darfpga.blogspot.fr
--------------------------------------------------
--- Bagman releases
---
--- Release 0.0 - 2014 - Dar
---	External sram required
---
---
--- Release 0.1 - 05/06/2018 - Dar
---      DE10_lite board
---	No external sram required
---	435kbits internal ram
---
--------------------------------------------------
-Educational use only
-Do not redistribute synthetized file with roms
-Do not redistribute roms whatever the form
-Use at your own risk
---------------------------------------------------------------------
-make sure to use bagman.zip roms
--------------------------------------------------------------------------
--- See my previous bagman/ckong release (2014) for some more explanations
--------------------------------------------------------------------------
-The original arcade hardware PCB contains 7 memory regions
-
- cpu addressable space
- 
- - program                  rom  24Kx8, cpu only access
- - working ram              ram   2Kx8, cpu only access
- - color/sprite-data        ram   1Kx8, cpu + (2 access / 8 pixels)
- - background buffer        ram   1Kx8, cpu + (1 access / 8 pixels)
-
- non cpu addressable region   
-
- - background/sprite graphics      rom 8Kx16, (1 access / 8 pixels) 
- - background/sprite color palette rom 64x8 , (1 access / pixels)
- - sound samples                   rom 8Kx8 , low rate
-
-The pixel clock is 6MHz, the cpu clock is 3MHz.
- 
-Background color contains 2 high bits of tile code.
-Sprite color contains horizontal and vertical invert control  
- 
-Video frame is 384 pixels x 264 lines.
-  
-Video display is 256 pixels x 240 lines.
-Each lines contains 8 sprites and 32 background tiles. 
-Each frames contains 28 background tiles height.
-
-Each tile is 8x8 pixels
-Each sprite is 16x16 pixels
-
-Sound is composed of AY-3-8910 music and TMS5110 synthetized speech 
---------------------------------------------------------------------
-
----------------
-VHDL File list 
----------------
-
-bagman_de10_lite.vhd     Top level for de0-nano board
-
-max10_pll_12M.vhd        Pll 12MHz from 50MHz altera mf
-
-bagman.vhd               Main logic
-
-video_gen.vhd            Video scheduler, syncs (h,v and composite)
-line_doubler.vhd         Line doubler 15kHz -> 31kHz
-
-bagman_speech.vhd        prom reader for speech synthetizer
-lpc10_speech_synthetizer speech synthetizer logic (TMS5110) 
-
-bagman_pal16r6           Random generator
-
-kbd_joystick.vhd         Keyboard key to player/coin input
-ram_loader               Load external sram from fpga internal ram
-
-rtl_T80/T80s.vhd         T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-rtl_T80/T80_Reg.vhd
-rtl_T80/T80_Pack.vhd
-rtl_T80/T80_MCode.vhd
-rtl_T80/T80_ALU.vhd
-rtl_T80/T80.vhd
-
-io_ps2_keyboard.vhd      Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-
-ym_2149_linmix.vhd       Copyright (c) MikeJ - Jan 2005
-
-----------------------
-Quartus project files
-----------------------
-de10_lite/bagman_de10_lite.qsf       de10_lite settings (files,pins...) 
-de10_lite/bagman_de10_lite.qpf       de10_lite project
-
------------------------------
-Required ROMs (Not included)
------------------------------
-You need the following 15 ROMs from bagman.zip 
-(MAME Bagman - Valadon Automation)
-
-e9_b05.bin  CRC(e0156191) SHA1(bb5f16d49fbe48f3bac118acd1fea51ec4bc5355)
-f9_b06.bin  CRC(7b758982) SHA1(c8460023b43fed4aca9c6b987faea334832c5e30)
-f9_b07.bin  CRC(302a077b) SHA1(916c4a6ea1e631cc72bdb91ff9d263dcbaf08bb2)
-k9_b08.bin  CRC(f04293cb) SHA1(ce6b0ae4088ce28c75d414f506fad2cf2b6920c2)
-m9_b09s.bin CRC(68e83e4f) SHA1(9454564885a1003cee7107db18bedb387b85e9ab)
-n9_b10.bin  CRC(1d6579f7) SHA1(3ab54329f516156b1c9f68efbe59c95d5240bc8c)
-
-p3.bin      CRC(2a855523) SHA1(91e032233fee397c90b7c1662934aca9e0671482)
-r3.bin      CRC(ae6f1019) SHA1(fd711882b670380cb4bd909c840ba06277b8fbe3)
-
-e1_b02.bin  CRC(4a0a6b55) SHA1(955f8bd4bd9b0fc3c6c359c25ba543ba26c04cbd)
-c1_b01.bin  CRC(705193b2) SHA1(ca9cfd05f9195c2a38e8854012de51b6ee6bb403)
-j1_b04.bin  CRC(c680ef04) SHA1(79406bc786374abfcd9f548268c445b5c8d8858d)
-f1_b03s.bin CRC(dba1eda7) SHA1(26d877028b3a31dd671f9e667316c8a14780ca73)
-
-r9_b11.bin  CRC(2e0057ff) SHA1(33e3ffa6418f86864eb81e5e9bda4bf540c143a6)
-t9_b12.bin  CRC(b2120edd) SHA1(52b89dbcc749b084331fa82b13d0876e911fce52)
-
-r6.bin      CRC(c58a4f6a) SHA1(35ef244b3e94032df2610aa594ea5670b91e1449) (N.U.)
-
-------
-Tools 
-------
-You need to build vhdl ROM image files from the binary file :
- - Unzip the roms file in the tools/bagman_unzip directory
- - Double click (execute) the script tools/make_bagman_proms.bat to get the following files
-
-bagman_program.vhd
-bagman_tile_bit0.vhd
-bagman_tile_bit1.vhd
-bagman_palette.vhd
-bagman_speech1.vhd
-bagman_speech2.vhd
-
-*DO NOT REDISTRIBUTE THESE FILES*
-
-The script make_bagman_proms uses make_vhdl_prom and and duplicate_byte executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
-
-Source code of make_vhdl_prom.c and and duplicate_byte.c is also delivered.
-
----------------------------------
-Compiling for de10_lite
----------------------------------
-You can rebuild the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES.
-4 steps
-
- - put the VHDL rom files into the project directory
- - rebuild bagman_de10_lite project
- - program bagman_de10_lite.sof into the fpga 
-
---------------------
-Keyboard and swicth
---------------------
-Use directional key to move, space to jump, F1/F2 to start player 1/2 and F3 for coins
-de10_lite sw0 allow to switch 15kHz/31kHz
-
-------------------------
-End of file
-------------------------
diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/clean.bat b/Arcade_MiST/Galaga Hardware/Xevious_MiST/clean.bat
deleted file mode 100644
index 59a9a059..00000000
--- a/Arcade_MiST/Galaga Hardware/Xevious_MiST/clean.bat	
+++ /dev/null
@@ -1,38 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-del /s PLLJ_PLLSPE_INFO.txt
-
-pause
diff --git a/Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/rom/XEVIOUS.ROM b/Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/rom/XEVIOUS.ROM
deleted file mode 100644
index c7eb0704..00000000
Binary files a/Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/rom/XEVIOUS.ROM and /dev/null differ
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt
index 34428fbb..9ccdcd8e 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt	
@@ -5,7 +5,7 @@
 -- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX
 -- 
 
-Todo fix Sound
+Todo: wrong Music
 ---------------------------------------------------------------------------------
 -- FPGA New Rally-X for Spartan-3 Starter Board
 ------------------------------------------------
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf
index 2aaaf0fa..09612672 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf	
@@ -18,7 +18,7 @@
 #
 # Quartus II 64-Bit
 # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 18:24:29  September 19, 2019
+# Date created = 16:37:48  September 22, 2019
 #
 # -------------------------------------------------------------------------- #
 #
@@ -45,6 +45,31 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/rallyX_mist.sv
+set_global_assignment -name VERILOG_FILE rtl/fpga_nrx.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_video.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_hvgen.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_sprite.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_sound.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_psg_voice.v
+set_global_assignment -name VERILOG_FILE rtl/nrx_namco.v
+set_global_assignment -name VERILOG_FILE rtl/rams.v
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_wav_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_prg_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_dot_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_chr_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_pal_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_col_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/nrx_nam_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -137,35 +162,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(rallyX_mist)
-# -----------------------
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/rallyX_mist.sv
-set_global_assignment -name VERILOG_FILE rtl/fpga_nrx.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_video.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_hvgen.v
-set_global_assignment -name VERILOG_FILE rtl/LINEBUF.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_sprite.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_sound.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_psg_voice.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_wav2.v
-set_global_assignment -name VERILOG_FILE rtl/rams.v
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_wav_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_prg_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_dot_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_chr_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_pal_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_col_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/nrx_nam_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+# -----------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf
index d0075afd..8b5f796f 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf	
@@ -23,6 +23,7 @@
 { "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "*" {  } {  } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "*" {  } {  } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf
index 35966951..78f1b08f 100644
Binary files a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf and b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/Release/RallyX.rbf differ
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.qip b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.qip
deleted file mode 100644
index c2e90185..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LINEBUF.v"]
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.v
deleted file mode 100644
index 191b7c2b..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/LINEBUF.v	
+++ /dev/null
@@ -1,246 +0,0 @@
-// megafunction wizard: %RAM: 2-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram 
-
-// ============================================================
-// File Name: LINEBUF.v
-// Megafunction Name(s):
-// 			altsyncram
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.4 Build 182 03/12/2014 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2014 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module LINEBUF (
-	address_a,
-	address_b,
-	clock_a,
-	clock_b,
-	data_a,
-	data_b,
-	wren_a,
-	wren_b,
-	q_a,
-	q_b);
-
-	input	[9:0]  address_a;
-	input	[9:0]  address_b;
-	input	  clock_a;
-	input	  clock_b;
-	input	[8:0]  data_a;
-	input	[8:0]  data_b;
-	input	  wren_a;
-	input	  wren_b;
-	output	[8:0]  q_a;
-	output	[8:0]  q_b;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri1	  clock_a;
-	tri0	  wren_a;
-	tri0	  wren_b;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [8:0] sub_wire0;
-	wire [8:0] sub_wire1;
-	wire [8:0] q_a = sub_wire0[8:0];
-	wire [8:0] q_b = sub_wire1[8:0];
-
-	altsyncram	altsyncram_component (
-				.clock0 (clock_a),
-				.wren_a (wren_a),
-				.address_b (address_b),
-				.clock1 (clock_b),
-				.data_b (data_b),
-				.wren_b (wren_b),
-				.address_a (address_a),
-				.data_a (data_a),
-				.q_a (sub_wire0),
-				.q_b (sub_wire1),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.eccstatus (),
-				.rden_a (1'b1),
-				.rden_b (1'b1));
-	defparam
-		altsyncram_component.address_reg_b = "CLOCK1",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_a = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.indata_reg_b = "CLOCK1",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 1024,
-		altsyncram_component.numwords_b = 1024,
-		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
-		altsyncram_component.outdata_aclr_a = "NONE",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_a = "UNREGISTERED",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.ram_block_type = "M9K",
-		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
-		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
-		altsyncram_component.widthad_a = 10,
-		altsyncram_component.widthad_b = 10,
-		altsyncram_component.width_a = 9,
-		altsyncram_component.width_b = 9,
-		altsyncram_component.width_byteena_a = 1,
-		altsyncram_component.width_byteena_b = 1,
-		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "5"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "0"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: REGrren NUMERIC "0"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
-// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
-// Retrieval info: USED_PORT: data_a 0 0 9 0 INPUT NODEFVAL "data_a[8..0]"
-// Retrieval info: USED_PORT: data_b 0 0 9 0 INPUT NODEFVAL "data_b[8..0]"
-// Retrieval info: USED_PORT: q_a 0 0 9 0 OUTPUT NODEFVAL "q_a[8..0]"
-// Retrieval info: USED_PORT: q_b 0 0 9 0 OUTPUT NODEFVAL "q_b[8..0]"
-// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 9 0 data_a 0 0 9 0
-// Retrieval info: CONNECT: @data_b 0 0 9 0 data_b 0 0 9 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-// Retrieval info: CONNECT: q_a 0 0 9 0 @q_a 0 0 9 0
-// Retrieval info: CONNECT: q_b 0 0 9 0 @q_b 0 0 9 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..cda0f3cd
--- /dev/null
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/dpram.vhd	
@@ -0,0 +1,123 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		numwords_a		: natural := 0;   -- not used any more
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_b,
+		power_up_uninitialized => "FALSE",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+END SYN;
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v
index ac1d44fc..476fdb53 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v	
@@ -98,7 +98,7 @@ nrx_prg_rom nrx_prg_rom (
 	.clk(CCLK),
 	.addr(ad[13:0]),
 	.data(romdata)
-);
+	);
 
 // Work RAM (2KB)
 wire [7:0] ramdata;
@@ -157,8 +157,8 @@ wire 				PCLK;
 
 nrx_video video( 
 	.VCLKx4(CLK),  
-	.HPOS(HP+22), 
-	.VPOS(VP-5), 
+	.HPOS(HP+3), 
+	.VPOS(VP+1), 
 	.PCLK(PCLK), 
 	.POUT({b,g,r}), 
 	.CPUCLK(CCLK), 
@@ -188,7 +188,7 @@ nrx_sound sound(
 	.CLK24M(CLK), 
 	.CCLK(CCLK), 
 	.SND(SND),
-	.AD(ad[4:0]), 
+	.AD(ad), 
 	.DI(odt[3:0]),
 	.WR(snd_Wce),
 	.BANG(bang)
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v
index 1bfb1724..0318fa92 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v	
@@ -33,4 +33,4 @@ always @(posedge PCLK) begin
 	endcase
 end
 
-endmodule
\ No newline at end of file
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_wav2.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_namco.v
similarity index 90%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_wav2.v
rename to Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_namco.v
index 9c35a76e..5a40777b 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_wav2.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_namco.v	
@@ -2,7 +2,7 @@
 	FPGA New Rally-X (Sound Part)
 ***************************************************************/
 
-module nrx_wav2
+module nrx_namco
 (
 	input			clk,
 	input [7:0] a0,
@@ -18,10 +18,10 @@ reg  [1:0] ph=0;
 reg  [7:0] ad;
 wire [7:0] dt;
 nrx_nam_rom namrom(
-	.clk(clk),//todo enable signal
+	.clk(clk),
 	.addr(ad), 
 	.data(dt)
-);
+	);
 
 always @(negedge clk) begin
 	case (ph)
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v
index 89141e0d..dcf2ac88 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v	
@@ -8,7 +8,7 @@ module nrx_sound
 	input					CLK24M,
 	input					CCLK,
 	output reg [7:0]	SND,
-	input	 [4:0]	AD,
+	input	 [15:0]	AD,
 	input  [3:0]	DI,
 	input				WR,
 
@@ -24,7 +24,7 @@ wire	SCLK    = ccnt[7];
 
 wire  [7:0]		wa0, wa1, wa2;
 wire  [3:0]		wd0, wd1, wd2;
-nrx_wav2 namco(
+nrx_namco namco(
 	.clk(SCLKx8),
 	.a0(wa0),
 	.a1(wa1),
@@ -32,7 +32,7 @@ nrx_wav2 namco(
 	.d0(wd0),
 	.d1(wd1),
 	.d2(wd2)
-);
+	);
 
 reg		  		bWavPlay = 1'b0;
 reg  [13:0] 	wap = 14'h0000;
@@ -40,10 +40,10 @@ wire  [7:0] 	wdp;
 wire  [7:0]		wo = bWavPlay ? wdp : 8'h80;
 
 nrx_wav_rom nrx_wav_rom (
-	.clk(CLK6K),//todo enable signal
+	.clk(CLK6K),
 	.addr(wap),
 	.data(wdp)
-);
+	);
 
 always @( posedge CLK6K ) begin
 	if ( BANG && (~bWavPlay) ) bWavPlay <= 1'b1;
@@ -66,15 +66,41 @@ wire	[19:0]	f2 = { fq2, 4'b0000 };
 
 wire	[3:0]		o0,  o1,  o2;
 
-nrx_psg_voice voice0( SCLK, o0, f0, v0, n0, wa0, wd0 );
-nrx_psg_voice voice1( SCLK, o1, f1, v1, n1, wa1, wd1 );
-nrx_psg_voice voice2( SCLK, o2, f2, v2, n2, wa2, wd2 );
+nrx_psg_voice voice0( 
+	.clk(SCLK), 
+	.out(o0), 
+	.freq(f0), 
+	.vol(v0), 
+	.vn(n0), 
+	.waveaddr(wa0), 
+	.wavedata(wd0) 
+	);
+	
+nrx_psg_voice voice1( 
+	.clk(SCLK), 
+	.out(o1), 
+	.freq(f1), 
+	.vol(v1), 
+	.vn(n1), 
+	.waveaddr(wa1), 
+	.wavedata(wd1) 
+	);
+
+nrx_psg_voice voice2( 
+	.clk(SCLK), 
+	.out(o2), 
+	.freq(f2), 
+	.vol(v2), 
+	.vn(n2), 
+	.waveaddr(wa2), 
+	.wavedata(wd2) 
+	);	
 
 reg [7:0] wout;
 always @( posedge SCLK ) SND <= ( { 2'b0, wo } ) + ( o0 + o1 + o2 );
 
 always @( posedge CCLK ) begin
-	if ( WR ) case ( AD )
+	if ( WR ) case ( AD[4:0] )
 
 		5'h05:	n0         <= DI[2:0];
 		5'h0A:	n1         <= DI[2:0];
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v
index 00552221..c84dfa33 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v	
@@ -129,10 +129,22 @@ end
 
 reg  [9:0] radr0=0,radr1=1;
 wire [8:0] SPCOLi;
-
-LINEBUF1024_9 linedbuf(VCLKx2,{SIDE,HPOS},(radr0==radr1),SPCOLi, VCLKx2,{~SIDE,HPOSW},(SPWCL[0]|SPWCL[1]),SPWCL);
-//GLINEBUF #(10,9) linedbuf(VCLKx2,{SIDE,HPOS},(radr0==radr1),SPCOLi, VCLKx2,{~SIDE,HPOSW},(SPWCL[0]|SPWCL[1]),SPWCL);
-
+dpram #(
+	.widthad_a(10),
+	.width_a(9))
+linebuffer(
+	.address_a({SIDE,HPOS}),
+	.address_b({~SIDE,HPOSW}),
+	.clock_a(VCLKx2),
+	.clock_b(VCLKx2),
+	.data_a(9'h0),
+	.data_b(SPWCL),
+	.wren_a(radr0==radr1),
+	.wren_b((SPWCL[0]|SPWCL[1])),
+	.q_a(SPCOLi),
+	.q_b()
+	);
+	
 always @(posedge VCLK) radr0 <= {SIDE,HPOS};
 always @(negedge VCLK) begin 
 	if (radr0!=radr1) SPCOL <= SPCOLi;
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v
index 033e4cac..16b51fc4 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v	
@@ -92,9 +92,55 @@ assign			CPUDO = DTV0 | DTV1;
 assign			CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 );
 
 GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO );  
-GDPRAM #(11,8)	vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO );  
+/*dpram #(
+	.widthad_a(11),
+	.width_a(8))
+vram0(
+	.address_a(VRAMADRS),
+	.address_b(CPUADDR[10:0]),
+	.clock_a(VCLKx4),
+	.clock_b(CPUCLK),
+	.data_a(),
+	.data_b(CPUDI),
+	.wren_a(),
+	.wren_b(( CPUWE & CEV0 )),
+	.q_a(CHRC),
+	.q_b(V0DO)
+	);*/
+	
+GDPRAM #(11,8)	vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); 
+/*dpram #(
+	.widthad_a(11),
+	.width_a(8))
+vram1(
+	.address_a(VRAMADRS),
+	.address_b(CPUADDR[10:0]),
+	.clock_a(VCLKx4),
+	.clock_b(CPUCLK),
+	.data_a(),
+	.data_b(CPUDI),
+	.wren_a(),
+	.wren_b(( CPUWE & CEV1 )),
+	.q_a(ATTR),
+	.q_b(V1DO)
+	); */
 GDPRAM #(4,8)	aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0],  ( CPUWE & CEAT ), CPUDI );
-
+/*dpram #(
+	.widthad_a(8),
+	.width_a(4))
+aram0(
+	.address_a(ARAMADRS),
+	.address_b(CPUADDR[3:0]),
+	.clock_a(VCLKx4),
+	.clock_b(CPUCLK),
+	.data_a(),
+	.data_b(CPUDI),
+	.wren_a(),
+	.wren_b(( CPUWE & CEAT )),
+	.q_a(ARDT),
+	.q_b()
+	); */
+	
 wire				BGF = ATTR[5];
 
 
@@ -123,7 +169,7 @@ nrx_dot_rom dotrom(
 	.clk(VCLKx4),
 	.addr(DROMAD), 
 	.data(DROMDT)
-);
+	);
 
 //----------------------------------------
 //  BG/FG scanline generator
@@ -145,7 +191,21 @@ end
 //  Sprite Engine
 //----------------------------------------
 wire [8:0] SPCOL;
-NRX_SPRITE speng( VCLKx4, oHB, HPOS, VPOS, SPRAADRS, { ATTR, CHRC }, ARAMADRS, ARDT, SPCHRADR, CHRO, DROMAD, DROMDT, SPCOL );
+NRX_SPRITE speng( 
+	.VCLKx4(VCLKx4), 
+	.HBLK(oHB), 
+	.HPOS(HPOS), 
+	.VPOS(VPOS), 
+	.SPRAADRS(SPRAADRS), 
+	.SPRADATA({ ATTR, CHRC }), 
+	.ARAMADRS(ARAMADRS), 
+	.ARAMDATA(ARDT), 
+	.SPCHRADR(SPCHRADR), 
+	.SPCHRDAT(CHRO), 
+	.DROMAD(DROMAD), 
+	.DROMDT(DROMDT), 
+	.SPCOL(SPCOL) 
+	);
 
 
 //----------------------------------------
@@ -160,7 +220,7 @@ nrx_col_rom colrom(
 	.clk(~VCLKx4),
 	.addr(OUTCOL), 
 	.data(CLUT)
-);
+	);
 
 wire	[4:0]		PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT };
 wire	[7:0]		PALO;
@@ -169,7 +229,7 @@ nrx_pal_rom palrom(
 	.clk(VCLKx4),
 	.addr(PALA), 
 	.data(PALO)
-);
+	);
 
 //----------------------------------------
 //  Color output
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv
index 8473d0c1..94d36e93 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv	
@@ -34,7 +34,7 @@ assign 		AUDIO_R = AUDIO_L;
 wire clock_24, clock_12;
 pll pll(
 	.inclk0(CLOCK_27),
-	.c0(clock_24)
+	.c0(clock_24)//24.576MHz
 	);
 
 wire [31:0] status;
@@ -63,7 +63,7 @@ wire  [7:0] iCTR2 = ~{ btn_coin, btn_two_players, m_up2, m_down2, m_right2, m_le
 
 fpga_nrx fpga_nrx(
 	.RESET(status[0] | status[6] | buttons[1]),
-	.CLK24M(clock_24),		// Clock 24.576MHz
+	.CLK24M(clock_24),
 	.hsync(hs),
 	.vsync(vs),
 	.hblank(hb),
@@ -71,15 +71,15 @@ fpga_nrx fpga_nrx(
 	.r(r),
 	.g(g),
 	.b(b),
-	.SND(audio),			// Sound (unsigned PCM)
-	.DSW(iDSW),			// DipSW
-	.CTR1(iCTR1),			// Controler (Negative logic)
+	.SND(audio),
+	.DSW(iDSW),
+	.CTR1(iCTR1),
 	.CTR2(iCTR2),
 	.LAMP()
-);
+	);
 
 	
-mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys        ( clock_24         ),
 	.SPI_SCK        ( SPI_SCK          ),
 	.SPI_SS3        ( SPI_SS3          ),
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v
index 6647c62e..4d579578 100644
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v	
+++ b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v	
@@ -1,31 +1,4 @@
 
-module LINEBUF1024_9
-(
-	input				CL0,
-	input	 [9:0]	AD0,
-	input				WE0,
-	output [8:0]	DO0,
-
-	input				CL1,
-	input	 [9:0]	AD1,
-	input				WE1,
-	input	 [8:0]	DI1
-);
-
-LINEBUF lbcore (
-	.clock_a(CL0),
-	.address_a(AD0),
-	.data_a(9'h0),
-	.wren_a(WE0),
-	.q_a(DO0),
-
-	.clock_b(CL1),
-	.address_b(AD1),
-	.data_b(DI1),
-	.wren_b(WE1)
-);
-
-endmodule
 
 
 module GSPRAM #(parameter AW,parameter DW)
@@ -67,7 +40,7 @@ always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end
 
 endmodule
 
-
+/*
 module GLINEBUF #(parameter AW,parameter DW)
 (
 	input							CL0,
@@ -86,26 +59,6 @@ reg [(DW-1):0] core[0:((2**AW)-1)];
 always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end
 always @(posedge CL1) if (WE1) core[AD1] <= DI1;
 
-endmodule
-
-
-module DLROM #(parameter AW,parameter DW)
-(
-	input							CL0,
-	input [(AW-1):0]			AD0,
-	output reg [(DW-1):0]	DO0,
-
-	input							CL1,
-	input [(AW-1):0]			AD1,
-	input	[(DW-1):0]			DI1,
-	input							WE1
-);
-
-reg [DW:0] core[0:((2**AW)-1)];
-
-always @(posedge CL0) DO0 <= core[AD0];
-always @(posedge CL1) if (WE1) core[AD1] <= DI1;
-
-endmodule
+endmodule*/
 
 
diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf
index 362a5b6e..e8b9993e 100644
--- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf	
+++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf	
@@ -58,7 +58,6 @@ set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd
 set_global_assignment -name QIP_FILE rtl/pll_mist.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
 set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf
index d9ac26bf..40caf603 100644
Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf and b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf differ