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NinjaKun: works

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This commit is contained in:
Gyorgy Szombathelyi 2019-12-29 00:26:34 +01:00
parent 56220af6f6
commit 8db29f3f4f
26 changed files with 635 additions and 1985 deletions
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15
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf
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@ -40,7 +40,7 @@
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@ -158,7 +158,7 @@ set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/nk.stp
# Power Estimation Assignments
# ============================
@ -220,34 +220,27 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/ninjakun_sprite.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/NinjaKun_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/ninjakun_top.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_main.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_io_video.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_video.v
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_bg.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_fg.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_sp.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_psg.v
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VERILOG_FILE rtl/ninjakun_cpumux.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_irqgen.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_clkgen.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_input.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_sadec.v
set_global_assignment -name VERILOG_FILE rtl/ninjakun_adec.v
set_global_assignment -name VERILOG_FILE rtl/dataselector_3D_8B.v
set_global_assignment -name VERILOG_FILE rtl/dataselector_4D_9B.v
set_global_assignment -name VERILOG_FILE rtl/dataselector_5D_8B.v
set_global_assignment -name VHDL_FILE rtl/rom/fg4_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/fg3_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/fg2_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/fg1_rom.vhd
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/mems.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

134
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.sdc Normal file
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@ -0,0 +1,134 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

123
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv
View File

@ -25,7 +25,6 @@ module NinjaKun_MiST (
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
@ -33,7 +32,8 @@ module NinjaKun_MiST (
localparam CONF_STR = {
"NINJAKUN;ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O5,Blend,Off,On;",
"O8,Difficulty,Normal,Hard;",
"O9A,Lives,4,3,2,5;",
"OB,1st Extra,30000,40000;",
@ -43,13 +43,13 @@ localparam CONF_STR = {
"OH,Endless(If Free Play),No,Yes;",
"OE,Demo Sound,Off,On;",
"OI,Name Letters,8,3;",
"T6,Reset;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = ~CLOCK_48;
assign SDRAM_CLK = CLOCK_48;
assign SDRAM_CKE = 1;
wire CLOCK_48, pll_locked;
@ -62,33 +62,33 @@ pll pll(
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [11:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [15:0] audio;
wire hs, vs;
wire [15:0] audio;
wire hs, vs;
wire [3:0] r, g, b;
wire [14:0] cpu1_rom_addr, cpu2_rom_addr;
wire [15:0] cpu1_rom_do, cpu2_rom_do;
//wire [12:0] sp_rom_addr;
//wire [31:0] sp_rom_do;
//wire [12:0] fg_rom_addr;
//wire [31:0] fg_rom_do;
wire [12:0] bg_rom_addr;
wire [31:0] bg_rom_do;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
/*
ROM Structure (same as the original)
fg gfx 32k ninja-6.7n ninja-7.7p ninja-8.7s ninja-9.7t
bg gfx 32k ninja-10.2c ninja-11.2d ninja-12.4c ninja-13.4d
cpu1 32k ninja-1.7a ninja-2.7b ninja-3.7d ninja-4.7e
cpu2 32k ninja-5.7h ninja-2.7b ninja-3.7d ninja-4.7e
*/
data_io data_io(
.clk_sys ( CLOCK_48 ),
.clk_sys ( CLOCK_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
@ -99,42 +99,56 @@ data_io data_io(
.ioctl_dout ( ioctl_dout )
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000;
wire [24:0] cpu_ioctl_addr = ioctl_addr - 17'h10000;
reg port1_req, port2_req;
wire [14:0] cpu1_rom_addr, cpu2_rom_addr;
wire [15:0] cpu1_rom_do, cpu2_rom_do;
wire [12:0] sp_rom_addr;
wire [31:0] sp_rom_do;
wire sp_rdy;
wire [12:0] fg_rom_addr;
wire [31:0] fg_rom_do;
wire [12:0] bg_rom_addr;
wire [31:0] bg_rom_do;
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( CLOCK_48 ),
.clk ( CLOCK_48 ),
// port1 used for main + sound CPU
// port1 used for main + aux CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_a ( cpu_ioctl_addr[23:1] ),
.port1_ds ( {cpu_ioctl_addr[0], ~cpu_ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu1_rom_addr[14:1]} ),
.cpu1_q ( cpu1_rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h4000 + cpu2_rom_addr[14:1]) ),
.cpu2_addr ( ioctl_downl ? 16'hffff : {1'b1, cpu2_rom_addr[14:1]} ),
.cpu2_q ( cpu2_rom_do ),
// port2 for sprite graphics
// port2 for graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {sp_ioctl_addr[12:0], sp_ioctl_addr[14]} ),
.port2_ds ( {sp_ioctl_addr[13], ~sp_ioctl_addr[13]} ),
.port2_a ( {ioctl_addr[23:15], ioctl_addr[14], ioctl_addr[12:0]} ),
.port2_ds ( {ioctl_addr[13], ~ioctl_addr[13]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp_addr ( ioctl_downl ? 15'h7fff : bg_rom_addr ),
.sp_q ( bg_rom_do )
.fg_addr ( ioctl_downl ? 15'h7fff : {1'b0, fg_rom_addr} ),
.fg_q ( fg_rom_do ),
.sp_addr ( ioctl_downl ? 15'h7fff : {1'b0, sp_rom_addr} ),
.sp_q ( sp_rom_do ),
.sp_rdy ( sp_rdy ),
.bg_addr ( ioctl_downl ? 15'h7fff : {1'b1, bg_rom_addr} ),
.bg_q ( bg_rom_do )
);
// ROM download controller
always @(posedge CLOCK_48) begin
reg ioctl_wr_last = 0;
@ -148,19 +162,19 @@ always @(posedge CLOCK_48) begin
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge CLOCK_48) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire PCLK;
wire PCLK_EN;
wire [8:0] HPOS,VPOS;
wire [11:0] POUT;
wire [11:0] POUT;
ninjakun_top ninjakun_top(
.RESET(reset),
.MCLK(CLOCK_48),
@ -170,42 +184,44 @@ ninjakun_top ninjakun_top(
.DSW2({~status[17], ~status[16], 1'b0, ~status[15], ~status[18], 3'b111}),
.PH(HPOS),
.PV(VPOS),
.PCLK(PCLK),
.PCLK_EN(PCLK_EN),
.POUT(oPIX),
.SNDOUT(audio),
.CPU1ADDR(cpu1_rom_addr),
.CPU1DT(cpu1_rom_addr[0] ? cpu1_rom_do[15:8] : cpu1_rom_do[7:0]),
.CPU2ADDR(cpu2_rom_addr),
.CPU2DT(cpu2_rom_addr[0] ? cpu2_rom_do[15:8] : cpu2_rom_do[7:0]),
// .sp_rom_addr(sp_rom_addr),
// .sp_rom_data(sp_rom_do),
// .fg_rom_addr(fg_rom_addr),
// .fg_rom_data(sp_rom_do),
.sp_rom_addr(sp_rom_addr),
.sp_rom_data(sp_rom_do),
.sp_rdy(sp_rdy),
.fg_rom_addr(fg_rom_addr),
.fg_rom_data(fg_rom_do),
.bg_rom_addr(bg_rom_addr),
.bg_rom_data(bg_rom_do)
);
wire [7:0] oPIX;
assign POUT = {{oPIX[7:6],oPIX[1:0]},{oPIX[5:4],oPIX[1:0]},{oPIX[3:2],oPIX[1:0]}};
hvgen hvgen(
.CLK(CLOCK_48),
.PCLK_EN(PCLK_EN),
.HPOS(HPOS),
.VPOS(VPOS),
.PCLK(PCLK),
.iRGB(POUT),
.oRGB({r,g,b}),
.oRGB({b,g,r}),
.HSYN(hs),
.VSYN(vs)
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
.clk_sys ( CLOCK_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( r ),
.G ( g ),
.B ( b ),
.R ( r ),
.G ( g ),
.B ( b ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
@ -214,7 +230,8 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( {1'b1,status[2]} ),
.ce_divider (1),
.ce_divider ( 1'b1 ),
.blend ( status[5] ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr )
@ -248,8 +265,8 @@ dac #(.C_bits(16))dac(
// Rotated Normal
//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_left = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
@ -265,9 +282,7 @@ reg btn_fire2 = 0;
reg btn_coin = 0;
always @(posedge CLOCK_48) begin
reg old_state;
old_state <= key_strobe;
if(old_state != key_strobe) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down

193
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd
View File

@ -1,130 +1,81 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
LIBRARY altera_mf;
USE altera_mf.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
END dpram;
end entity;
-- -----------------------------------------------------------------------
ARCHITECTURE SYN OF dpram IS
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

47
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v
View File

@ -1,8 +1,9 @@
module hvgen
(
input CLK,
input PCLK_EN,
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input [11:0] iRGB,
output reg [11:0] oRGB,
output reg HBLK = 1,
@ -14,28 +15,30 @@ module hvgen
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-16;
assign VPOS = vcnt-16;
assign HPOS = hcnt-9'd16;
assign VPOS = vcnt-9'd16;
always @(posedge PCLK) begin
case (hcnt)
15: begin HBLK <= 0; hcnt <= hcnt+1; end
272: begin HBLK <= 1; hcnt <= hcnt+1; end
311: begin HSYN <= 0; hcnt <= hcnt+1; end
342: begin HSYN <= 1; hcnt <= 471; end
511: begin hcnt <= 0;
case (vcnt)
15: begin VBLK <= 0; vcnt <= vcnt+1; end
207: begin VBLK <= 1; vcnt <= vcnt+1; end
226: begin VSYN <= 0; vcnt <= vcnt+1; end
233: begin VSYN <= 1; vcnt <= 483; end
511: begin vcnt <= 0; end
default: vcnt <= vcnt+1;
endcase
end
default: hcnt <= hcnt+1;
endcase
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
always @(posedge CLK) begin
if (PCLK_EN) begin
case (hcnt)
15: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
272: begin HBLK <= 1; hcnt <= hcnt+1'd1; end
311: begin HSYN <= 0; hcnt <= hcnt+1'd1; end
342: begin HSYN <= 1; hcnt <= 471; end
511: begin hcnt <= 0;
case (vcnt)
15: begin VBLK <= 0; vcnt <= vcnt+1'd1; end
207: begin VBLK <= 1; vcnt <= vcnt+1'd1; end
226: begin VSYN <= 0; vcnt <= vcnt+1'd1; end
233: begin VSYN <= 1; vcnt <= 483; end
511: begin vcnt <= 0; end
default: vcnt <= vcnt+1'd1;
endcase
end
default: hcnt <= hcnt+1'd1;
endcase
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end
end
endmodule

305
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/mems.v
View File

@ -1,305 +0,0 @@
// Copyright (c) 2011 MiSTer-X
module VDPRAM400x2
(
input CL0,
input [10:0] AD0,
input WR0,
input [7:0] WD0,
output [7:0] RD0,
input CL1,
input [9:0] AD1,
output [15:0] RD1
);
reg A10;
always @( posedge CL0 ) A10 <= AD0[10];
wire [7:0] RD00, RD01;
DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
assign RD0 = A10 ? RD01 : RD00;
endmodule
module DPRAM800
(
input CL0,
input [10:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [10:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:2047];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM400
(
input CL0,
input [9:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [9:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:1023];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM200
(
input CL0,
input [8:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [8:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:511];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fg_sp_dulport_rom (
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
input [12:0] address_a;
input [12:0] address_b;
input clock_a;
input clock_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_b = sub_wire0[31:0];
wire [31:0] q_a = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (sub_wire2),
.address_b (address_b),
.clock1 (clock_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
`ifdef NO_PLI
altsyncram_component.init_file = "./rom/gfx1.rif"
`else
altsyncram_component.init_file = "./rom/gfx1.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule

44
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_bg.v
View File

@ -1,44 +0,0 @@
// BackGround Scanline Generator
module ninjakun_bg
(
input VCLK,
input [8:0] PH, // CRTC
input [8:0] PV,
input [7:0] BGSCX, // SCRREG
input [7:0] BGSCY,
output reg [9:0] BGVAD, // VRAM
input [15:0] BGVDT,
output reg [12:0] BGCAD,
input [31:0] BGCDT,
output [8:0] BGOUT // OUTPUT
);
wire [8:0] POSH = PH+BGSCX+2;
wire [8:0] POSV = PV+BGSCY+32;
wire [9:0] CHRNO = {BGVDT[15:14],BGVDT[7:0]};
reg [31:0] CDT;
reg [3:0] PAL;
reg [3:0] OUT;
always @( posedge VCLK ) begin
case(POSH[2:0])
0: begin OUT <= CDT[7:4] ; PAL <= BGVDT[11:8]; end
1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end
2: begin OUT <= CDT[15:12]; end
3: begin OUT <= CDT[11:8] ; end
4: begin OUT <= CDT[23:20]; BGCAD <= {CHRNO,POSV[2:0]}; end
5: begin OUT <= CDT[19:16]; end
6: begin OUT <= CDT[31:28]; end
7: begin OUT <= CDT[27:24]; CDT <= BGCDT; end
endcase
end
assign BGOUT = { 1'b1, PAL, OUT };
endmodule

33
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_clkgen.v
View File

@ -1,33 +0,0 @@
// Copyright (c) 2011 MiSTer-X
module ninjakun_clkgen
(
input MCLK, // 48MHz
output VCLKx4,
output VCLK,
output VRAMCL,
output PCLK,
output CLK24M,
output CLK12M,
output CLK6M,
output CLK3M
);
reg [3:0] CLKDIV;
always @( posedge MCLK ) CLKDIV <= CLKDIV+1'b1;
assign VCLKx4 = CLKDIV[0]; // 24MHz
assign VCLK = CLKDIV[2]; // 6MHz
assign CLK24M = CLKDIV[0];
assign CLK12M = CLKDIV[1];
assign CLK6M = CLKDIV[2];
assign CLK3M = CLKDIV[3];
assign VRAMCL = ~VCLKx4;
assign PCLK = ~VCLK;
endmodule

28
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v
View File

@ -1,6 +1,6 @@
module ninjakun_cpumux
(
input SHCLK,
input MCLK,
output [15:0] CPADR,
output [7:0] CPODT,
input [7:0] CPIDT,
@ -8,6 +8,8 @@ module ninjakun_cpumux
output CPWRT,
output reg CP0CL,
output reg CP0CE_P,
output reg CP0CE_N,
input [15:0] CP0AD,
input [7:0] CP0OD,
output [7:0] CP0ID,
@ -15,6 +17,8 @@ module ninjakun_cpumux
input CP0WR,
output reg CP1CL,
output reg CP1CE_P,
output reg CP1CE_N,
input [15:0] CP1AD,
input [7:0] CP1OD,
output [7:0] CP1ID,
@ -23,24 +27,26 @@ module ninjakun_cpumux
);
reg [7:0] CP0DT, CP1DT;
reg [2:0] PHASE;
reg [3:0] PHASE;
reg CSIDE;
always @( posedge SHCLK ) begin // 24MHz
always @( posedge MCLK ) begin // 48MHz
CP0CE_P <= 0; CP0CE_N <= 0;
CP1CE_P <= 0; CP1CE_N <= 0;
case (PHASE)
0: begin CP0DT <= CPIDT; CSIDE <= 1'b0; end
4: begin CP1DT <= CPIDT; CSIDE <= 1'b1; end
0: begin CP0DT <= CPIDT; CP0CE_P <= 1; CP1CE_N <= 1; end
1: CSIDE <= 0;
8: begin CP1DT <= CPIDT; CP1CE_P <= 1; CP0CE_N <= 1; end
9: CSIDE <= 1;
default:;
endcase
end
always @( negedge SHCLK ) begin
always @( posedge MCLK ) begin
case (PHASE)
0: CP0CL <= 1'b1;
2: CP0CL <= 1'b0;
4: CP1CL <= 1'b1;
6: CP1CL <= 1'b0;
1: begin CP0CL <= 1; CP1CL <= 0; end
9: begin CP1CL <= 1; CP0CL <= 0; end
default:;
endcase
PHASE <= PHASE+1;
PHASE <= PHASE+1'd1;
end
assign CPADR = CSIDE ? CP1AD : CP0AD;

41
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_fg.v
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@ -1,41 +0,0 @@
// ForeGround Scanline Generator
module ninjakun_fg
(
input VCLK,
input [8:0] PH, // CRTC
input [8:0] PV,
output reg [9:0] FGVAD, // VRAM
input [15:0] FGVDT,
output reg [12:0] FGCAD,
input [31:0] FGCDT,
output [9:0] FGOUT // PIXEL OUT : {PRIO,PALNO[8:0]}
);
wire [8:0] POSH = PH+8+1;
wire [8:0] POSV = PV+32;
wire [9:0] CHRNO = {1'b0,FGVDT[13],FGVDT[7:0]};
reg [31:0] CDT;
reg [4:0] PAL;
reg [3:0] OUT;
always @( posedge VCLK ) begin
case(POSH[2:0])
0: begin OUT <= CDT[7:4] ; PAL <= FGVDT[12:8]; end
1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end
2: begin OUT <= CDT[15:12]; end
3: begin OUT <= CDT[11:8] ; end
4: begin OUT <= CDT[23:20]; FGCAD <= {CHRNO,POSV[2:0]}; end
5: begin OUT <= CDT[19:16]; end
6: begin OUT <= CDT[31:28]; end
7: begin OUT <= CDT[27:24]; CDT <= FGCDT; end
endcase
end
assign FGOUT = { PAL[4], 1'b0, PAL[3:0], OUT };
endmodule

4
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v
View File

@ -2,7 +2,7 @@
module ninjakun_input
(
input INPCL,
input MCLK,
input RESET,
input [7:0] CTR1i, // Control Panel (Negative Logic)
@ -24,7 +24,7 @@ module ninjakun_input
reg [1:0] SYNCFLG;
reg [7:0] CTR1,CTR2;
always @( posedge INPCL or posedge RESET ) begin
always @( posedge MCLK or posedge RESET ) begin
if (RESET) begin
SYNCFLG = 0;
end

48
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v
View File

@ -2,12 +2,9 @@
module ninjakun_io_video
(
input SHCLK,
input CLK3M,
input MCLK,
input PCLK_EN,
input RESET,
input VRCLK,
input VCLKx4,
input VCLK,
input [8:0] PH,
input [8:0] PV,
input [15:0] CPADR,
@ -20,10 +17,11 @@ module ninjakun_io_video
output VBLK,
output [7:0] POUT,
output [15:0] SNDOUT,
// output [12:0] sp_rom_addr,
// input [31:0] sp_rom_data,
// output [12:0] fg_rom_addr,
// input [31:0] fg_rom_data,
output [12:0] sp_rom_addr,
input [31:0] sp_rom_data,
input sp_rdy,
output [12:0] fg_rom_addr,
input [31:0] fg_rom_data,
output [12:0] bg_rom_addr,
input [31:0] bg_rom_data
);
@ -36,10 +34,10 @@ wire [10:0] SPAAD;
wire [7:0] SPADT;
wire [7:0] SCRPX, SCRPY;
wire [8:0] PALET;
ninjakun_video video (
NINJAKUN_VIDEO video (
.RESET(RESET),
.VCLKx4(VCLKx4),
.VCLK(VCLK),
.MCLK(MCLK),
.PCLK_EN(PCLK_EN),
.PH(PH),
.PV(PV),
.PALAD(PALET), // Pixel Output (Palet Index)
@ -53,10 +51,11 @@ ninjakun_video video (
.SPADT(SPADT),
.VBLK(VBLK),
.DBGPD(1'b0), // Palet Display (for Debug)
// .sp_rom_addr(sp_rom_addr),
// .sp_rom_data(sp_rom_data),
// .fg_rom_addr(fg_rom_addr),
// .fg_rom_data(fg_rom_data),
.sp_rom_addr(sp_rom_addr),
.sp_rom_data(sp_rom_data),
.sp_rdy(sp_rdy),
.fg_rom_addr(fg_rom_addr),
.fg_rom_data(fg_rom_data),
.bg_rom_addr(bg_rom_addr),
.bg_rom_data(bg_rom_data)
);
@ -71,15 +70,17 @@ ninjakun_sadec sadec(
.CS_PAL(CS_PAL)
);
wire [7:0] PSDAT, FGDAT, BGDAT, SPDAT, PLDAT;
wire [7:0] PSDAT, FGDAT = CPADR[10] ? FGDAT16[15:8] : FGDAT16[7:0], BGDAT = CPADR[10] ? BGDAT16[15:8] : BGDAT16[7:0], SPDAT, PLDAT;
wire [15:0] FGDAT16, BGDAT16;
wire [9:0] BGOFS = CPADR[9:0]+{SCRPY[7:3],SCRPX[7:3]};
wire [10:0] BGADR = {CPADR[10],BGOFS};
VDPRAM400x2 fgv( SHCLK, CPADR[10:0], CS_FGV & CPWRT, CPODT, FGDAT, VRCLK, FGVAD, FGVDT );
VDPRAM400x2 bgv( SHCLK, BGADR , CS_BGV & CPWRT, CPODT, BGDAT, VRCLK, BGVAD, BGVDT );
DPRAM800 spa( SHCLK, CPADR[10:0], CS_SPA & CPWRT, CPODT, SPDAT, VRCLK, SPAAD, 1'b0, 8'h0, SPADT );
DPRAM200 pal( SHCLK, CPADR[ 8:0], CS_PAL & CPWRT, CPODT, PLDAT, VCLK, PALET, 1'b0, 8'h0, POUT );
dpram #(8,10) fgv_lo(MCLK, CS_FGV & CPWRT & ~CPADR[10], CPADR[9:0], CPODT, FGDAT16[ 7:0], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[ 7:0]);
dpram #(8,10) fgv_hi(MCLK, CS_FGV & CPWRT & CPADR[10], CPADR[9:0], CPODT, FGDAT16[15:8], MCLK, 1'b0, FGVAD, 8'd0, FGVDT[15:8]);
dpram #(8,10) bgv_lo(MCLK, CS_BGV & CPWRT & ~BGADR[10], BGADR[9:0], CPODT, BGDAT16[ 7:0], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[ 7:0]);
dpram #(8,10) bgv_hi(MCLK, CS_BGV & CPWRT & BGADR[10], BGADR[9:0], CPODT, BGDAT16[15:8], MCLK, 1'b0, BGVAD, 8'd0, BGVDT[15:8]);
dpram #(8,11) spa (MCLK, CS_SPA & CPWRT, CPADR[10:0], CPODT, SPDAT, ~MCLK, 1'b0, SPAAD, 8'h0, SPADT);
dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, 1'b0, PALET, 8'h0, POUT);
dataselector_5D_8B cpxdsel(
.out(CPIDT),
@ -96,8 +97,7 @@ dataselector_5D_8B cpxdsel(
);
ninjakun_psg psg(
.AXSCLK(SHCLK),
.CLK(CLK3M),
.MCLK(MCLK),
.ADR(CPADR[1:0]),
.CS(CS_PSG),
.WR(CPWRT),

10
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v
View File

@ -1,6 +1,6 @@
module ninjakun_irqgen
(
input CLK,
input MCLK,
input VBLK,
input IRQ0_ACK,
@ -10,23 +10,23 @@ module ninjakun_irqgen
output reg IRQ1
);
`define CYCLES 12500 // 1/240sec.
`define CYCLES 18'd200000 // 1/240sec.
reg pVBLK;
wire VBTG = VBLK & (pVBLK^VBLK);
reg [13:0] cnt;
reg [17:0] cnt;
wire IRQ1_ACT = (cnt == 1);
wire CNTR_RST = (cnt == `CYCLES)|VBTG;
always @( posedge CLK ) begin
always @( posedge MCLK ) begin
if (VBTG) IRQ0 <= 1'b1;
if (IRQ1_ACT) IRQ1 <= 1'b1;
if (IRQ0_ACK) IRQ0 <= 1'b0;
if (IRQ1_ACK) IRQ1 <= 1'b0;
cnt <= CNTR_RST ? 0 : (cnt + 1'b1);
cnt <= CNTR_RST ? 18'd0 : (cnt + 1'b1);
pVBLK <= VBLK;
end

36
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v
View File

@ -1,7 +1,6 @@
module ninjakun_main(
input RESET,
input CLK24M,
input CLK3M,
input MCLK,
input VBLK,
input [7:0] CTR1,
@ -12,19 +11,18 @@ module ninjakun_main(
input [7:0] CPIDT,
output CPRED,
output CPWRT,
output [14:0] CPU1ADDR,
input [7:0] CPU1DT,
output [14:0] CPU2ADDR,
input [7:0] CPU2DT
);
wire SHCLK = CLK24M;
wire INPCL = CLK24M;
wire CP0IQ, CP0IQA;
wire CP1IQ, CP1IQA;
ninjakun_irqgen ninjakun_irqgen(
.CLK(CLK3M),
.MCLK(MCLK),
.VBLK(VBLK),
.IRQ0_ACK(CP0IQA),
.IRQ1_ACK(CP1IQA),
@ -32,7 +30,7 @@ ninjakun_irqgen ninjakun_irqgen(
.IRQ1(CP1IQ)
);
wire CP0CL, CP1CL;
wire CP0CE_P, CP0CE_N, CP1CE_P, CP1CE_N;
wire [15:0] CP0AD, CP1AD;
wire [7:0] CP0OD, CP1OD;
wire [7:0] CP0DT, CP1DT;
@ -41,7 +39,9 @@ wire CP0RD, CP1RD;
wire CP0WR, CP1WR;
Z80IP cpu0(
.reset_in(RESET),
.clk(CP0CL),
.clk(MCLK),
.clken_p(CP0CE_P),
.clken_n(CP0CE_N),
.adr(CP0AD),
.data_in(CP0DT),
.data_out(CP0OD),
@ -53,7 +53,9 @@ Z80IP cpu0(
Z80IP cpu1(
.reset_in(RESET),
.clk(CP1CL),
.clk(MCLK),
.clken_p(CP1CE_P),
.clken_n(CP1CE_N),
.adr(CP1AD),
.data_in(CP1DT),
.data_out(CP1OD),
@ -64,19 +66,21 @@ Z80IP cpu1(
);
ninjakun_cpumux ioshare(
.SHCLK(SHCLK),
.MCLK(MCLK),
.CPADR(CPADR),
.CPODT(CPODT),
.CPIDT(CPIDT),
.CPRED(CPRED),
.CPWRT(CPWRT),
.CP0CL(CP0CL),
.CP0CE_P(CP0CE_P),
.CP0CE_N(CP0CE_N),
.CP0AD(CP0AD),
.CP0OD(CP0OD),
.CP0ID(CP0ID),
.CP0RD(CP0RD),
.CP0WR(CP0WR),
.CP1CL(CP1CL),
.CP1CE_P(CP1CE_P),
.CP1CE_N(CP1CE_N),
.CP1AD(CP1AD),
.CP1OD(CP1OD),
.CP1ID(CP1ID),
@ -107,14 +111,14 @@ assign CPU2ADDR = CP1AD[14:0];
assign ROM1D = CPU2DT;
wire [7:0] SHDT0, SHDT1;
DPRAM800 shmem(
SHCLK, { CP0AD[10] ,CP0AD[9:0]}, CS_SH0 & CP0WR, CP0OD, SHDT0,
SHCLK, {(~CP1AD[10]),CP1AD[9:0]}, CS_SH1 & CP1WR, CP1OD, SHDT1
);
dpram #(8,11) shmem(
MCLK, CS_SH0 & CP0WR, { CP0AD[10] ,CP0AD[9:0]}, CP0OD, SHDT0,
MCLK, CS_SH1 & CP1WR, {~CP1AD[10], CP1AD[9:0]}, CP1OD, SHDT1);
wire [7:0] INPD0, INPD1;
ninjakun_input inps(
.INPCL(INPCL),
.MCLK(MCLK),
.RESET(RESET),
.CTR1i(CTR1), // Control Panel (Negative Logic)
.CTR2i(CTR2),

13
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v
View File

@ -1,7 +1,6 @@
module ninjakun_psg
(
input AXSCLK,
input CLK,
input MCLK,
input [1:0] ADR,
input CS,
input WR,
@ -22,11 +21,11 @@ assign OD = ADR[1] ? OD1 : OD0;
reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c;
reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c;
reg [1:0] encnt;
reg [2:0] encnt;
reg ENA;
always @(posedge AXSCLK) begin
always @(posedge MCLK) begin
ENA <= (encnt==0);
encnt <= encnt+1;
encnt <= encnt+1'd1;
case (S0c)
2'd0: SA0 <= S0x;
2'd1: SB0 <= S0x;
@ -65,7 +64,7 @@ YM2149 psg0(
.I_IOB(DSW2),
.ENA(ENA),
.RESET_L(~RESET),
.CLK(AXSCLK)
.CLK(MCLK)
);
YM2149 psg1(
@ -85,7 +84,7 @@ YM2149 psg1(
.O_IOB(SCRPY),
.ENA(ENA),
.RESET_L(~RESET),
.CLK(AXSCLK)
.CLK(MCLK)
);
wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;

83
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sp.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sprite.v
View File

@ -1,9 +1,10 @@
// Copyright (c) 2011,19 MiSTer-X
module ninjakun_sp
module NINJAKUN_SP
(
input VCLKx4,
input VCLK,
input MCLK,
input PCLK_EN,
input RESET,
input [8:0] PH,
input [8:0] PV,
@ -27,18 +28,21 @@ wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];
reg [9:0] radr0=0,radr1=1;
wire [7:0] POUTi;
LineDBuf ldbuf(
VCLKx4, radr0, POUTi, (radr0==radr1),
~VCLKx4, {PV[0],WPAD}, WPIX, WPEN
);
always @(posedge VCLK) radr0 <= {~PV[0],PH};
always @(negedge VCLK) begin
if (radr0!=radr1) POUT <= POUTi;
radr1 <= radr0;
dpram #(8,10) ldbuf(
MCLK, WPEN, {PV[0], WPAD}, WPIX, 8'd0,
MCLK, (radr0==radr1), radr0, 8'd0, POUTi);
always @(posedge MCLK) begin
radr0 <= {~PV[0],PH};
if (PCLK_EN) begin
if (radr0!=radr1) POUT <= POUTi;
radr1 <= radr0;
end
end
NINJAKUN_SPENG eng (
VCLKx4, PH, PV,
MCLK, RESET, PH, PV,
SPAAD, SPADT,
SPCAD, SPCDT, SPCFT,
WPAD, WPIX, WPEN
@ -51,7 +55,8 @@ endmodule
module NINJAKUN_SPENG
(
input VCLKx4,
input MCLK,
input RESET,
input [8:0] PH,
input [8:0] PV,
@ -59,7 +64,7 @@ module NINJAKUN_SPENG
output [10:0] SPAAD,
input [7:0] SPADT,
output [12:0] SPCAD,
output reg [12:0] SPCAD,
input [31:0] SPCDT,
input SPCFT,
@ -88,12 +93,11 @@ wire YHIT = (HV[7:4]==4'b1111) & (~DSABL);
reg [7:0] XPOS;
reg [4:0] WP;
wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]);
assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1;
assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1'd1;
assign WPEN = ~(WP[4]|(WPIX[3:0]==0));
reg [7:0] PTNO;
reg CRS;
assign SPCAD = {PTNO, LV[3], CRS, LV[2:0]};
function [3:0] XOUT;
input [2:0] N;
@ -123,13 +127,17 @@ assign WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)};
`define NEXT 7
reg [2:0] STATE;
always @( posedge VCLKx4 ) begin
always @( posedge MCLK ) begin
if (RESET) begin
STATE <= `WAIT;
SPCAD <= 13'h1fff;
end else
case (STATE)
`WAIT: begin
WP <= 16;
if (~PH[8]) begin
NV <= PV+17;
NV <= PV+5'd17;
SPRNO <= 0;
SPRIX <= 2;
STATE <= `FETCH0;
@ -153,17 +161,17 @@ always @( posedge VCLKx4 ) begin
STATE <= `FETCH3;
end
`FETCH3: begin
if (SPCFT) begin // Wait for CHRROM fetch cycle
XPOS <= SPADT;
CRS <= 0;
STATE <= `FETCH4;
end
XPOS <= SPADT;
CRS <= 0;
STATE <= `FETCH4;
SPCAD <= {PTNO, LV[3], 1'b0, LV[2:0]};
end
`FETCH4: begin
if (SPCFT) begin // Fetch CHRROM data (16pixels)
if (~CRS) begin
CDT0 <= SPCDT;
CRS <= 1;
SPCAD <= {PTNO, LV[3], 1'b1, LV[2:0]};
end
else begin
CDT1 <= SPCDT;
@ -174,13 +182,13 @@ always @( posedge VCLKx4 ) begin
end
`DRAW: begin
WP <= WP+1;
WP <= WP+1'd1;
if (WP[4]) STATE <= `NEXT;
end
`NEXT: begin
CDT0 <= 0; CDT1 <= 0;
SPRNO <= SPRNO+1;
SPRNO <= SPRNO+1'd1;
SPRIX <= 2;
STATE <= (SPRNO==63) ? `WAIT : `FETCH0;
end
@ -189,28 +197,3 @@ always @( posedge VCLKx4 ) begin
end
endmodule
module LineDBuf
(
input rC,
input [9:0] rA,
output [7:0] rD,
input rE,
input wC,
input [9:0] wA,
input [7:0] wD,
input wE
);
DPRAM1024 ram(
rA, wA,
rC, wC,
8'h0, wD,
rE, wE,
rD
);
endmodule

74
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v
View File

@ -2,30 +2,10 @@
"FPGA NinjaKun" for MiSTer
Copyright (c) 2011,19 MiSTer-X
Converted to SDRAM, single clock and
clock-enables for MiST
************************************************/
/*
ROM_START( ninjakun )
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "ninja-1.7a", 0x0000, 0x02000, CRC(1c1dc141) SHA1(423d3ed35e73a8d5bfce075a889b0322b207bd0d) )
ROM_LOAD( "ninja-2.7b", 0x2000, 0x02000, CRC(39cc7d37) SHA1(7f0d0e1e92cb6a57f15eb7fc51a67112f1c5fc8e) )
ROM_LOAD( "ninja-3.7d", 0x4000, 0x02000, CRC(d542bfe3) SHA1(3814d8f5b1acda21438fff4f71670fa653dc7b30) )
ROM_LOAD( "ninja-4.7e", 0x6000, 0x02000, CRC(a57385c6) SHA1(77925a281e64889bfe967c3d42a388529aaf7eb6) )
ROM_REGION( 0x2000, "sub", 0 )
ROM_LOAD( "ninja-5.7h", 0x0000, 0x02000, CRC(164a42c4) SHA1(16b434b33b76b878514f67c23315d4c6da7bfc9e) )
ROM_REGION( 0x08000, "gfx1", 0 )
ROM_LOAD16_BYTE( "ninja-6.7n", 0x0000, 0x02000, CRC(a74c4297) SHA1(87184d14c67331f2c8a2412e28f31427eddae799) )
ROM_LOAD16_BYTE( "ninja-7.7p", 0x0001, 0x02000, CRC(53a72039) SHA1(d77d608ce9388a8956831369badd88a8eda8e102) )
ROM_LOAD16_BYTE( "ninja-8.7s", 0x4000, 0x02000, CRC(4a99d857) SHA1(6aadb6a5c721a161a5c1bef5569c1e323e380cff) )
ROM_LOAD16_BYTE( "ninja-9.7t", 0x4001, 0x02000, CRC(dede49e4) SHA1(8ce4bc02ec583b3885ca63fb5e2d5dad185fe192) )
ROM_REGION( 0x08000, "gfx2", 0 )
ROM_LOAD16_BYTE( "ninja-10.2c", 0x0000, 0x02000, CRC(0d55664a) SHA1(955a607b4401ce9f3f807d53833a766152b0ef9b) )
ROM_LOAD16_BYTE( "ninja-11.2d", 0x0001, 0x02000, CRC(12ff9597) SHA1(10b572844ab32e3ae54abe3600fecc1a811ac713) )
ROM_LOAD16_BYTE( "ninja-12.4c", 0x4000, 0x02000, CRC(e9b75807) SHA1(cf4c8ac962f785e9de5502df58eab9b3725aaa28) )
ROM_LOAD16_BYTE( "ninja-13.4d", 0x4001, 0x02000, CRC(1760ed2c) SHA1(ee4c8efcce483c8051873714856824a1a1e14b61) )
ROM_END*/
module ninjakun_top
(
@ -37,42 +17,34 @@ module ninjakun_top
input [7:0] DSW2,
input [8:0] PH, // PIXEL H
input [8:0] PV, // PIXEL V
output PCLK, // PIXEL CLOCK
output PCLK_EN, // PIXEL CLOCK ENABLE
output [7:0] POUT, // PIXEL OUT
output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits)
output [14:0] CPU1ADDR,
input [7:0] CPU1DT,
output [14:0] CPU2ADDR,
input [7:0] CPU2DT,
// output [12:0] sp_rom_addr,
// input [31:0] sp_rom_data,
// output [12:0] fg_rom_addr,
// input [31:0] fg_rom_data,
output [12:0] sp_rom_addr,
input [31:0] sp_rom_data,
input sp_rdy,
output [12:0] fg_rom_addr,
input [31:0] fg_rom_data,
output [12:0] bg_rom_addr,
input [31:0] bg_rom_data
);
wire VCLKx4, VCLK;
wire VRAMCL, CLK24M, CLK12M, CLK6M, CLK3M;
ninjakun_clkgen ninjakun_clkgen(
.MCLK(MCLK), // 48MHz
.VCLKx4(VCLKx4),
.VCLK(VCLK),
.VRAMCL(VRAMCL),
.PCLK(PCLK),
.CLK24M(CLK24M),
.CLK12M(CLK12M),
.CLK6M(CLK6M),
.CLK3M(CLK3M)
);
reg [3:0] CLKDIV;
always @( posedge MCLK ) CLKDIV <= CLKDIV+1'b1;
assign PCLK_EN = CLKDIV[2:0] == 3'b111;
wire [15:0] CPADR;
wire [7:0] CPODT, CPIDT;
wire CPRED, CPWRT, VBLK;
ninjakun_main ninjakun_main(
.RESET(RESET),
.CLK24M(CLK24M),
.CLK3M(CLK3M),
.MCLK(MCLK),
.VBLK(VBLK),
.CTR1(CTR1),
.CTR2(CTR2),
@ -95,12 +67,9 @@ wire [7:0] SPADT;
wire [8:0] PALET;
wire [7:0] SCRPX, SCRPY;
ninjakun_io_video ninjakun_io_video(
.SHCLK(CLK24M),
.CLK3M(CLK3M),
.MCLK(MCLK),
.PCLK_EN(PCLK_EN),
.RESET(RESET),
.VRCLK(VRAMCL),
.VCLKx4(VCLKx4),
.VCLK(VCLK),
.PH(PH),
.PV(PV),
.CPADR(CPADR),
@ -113,10 +82,11 @@ ninjakun_io_video ninjakun_io_video(
.VBLK(VBLK),
.POUT(POUT),
.SNDOUT(SNDOUT),
// .sp_rom_addr(sp_rom_addr),
// .sp_rom_data(sp_rom_data),
// .fg_rom_addr(fg_rom_addr),
// .fg_rom_data(fg_rom_data),
.sp_rom_addr(sp_rom_addr),
.sp_rom_data(sp_rom_data),
.sp_rdy(sp_rdy),
.fg_rom_addr(fg_rom_addr),
.fg_rom_data(fg_rom_data),
.bg_rom_addr(bg_rom_addr),
.bg_rom_data(bg_rom_data)
);

251
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v
View File

@ -1,10 +1,11 @@
// Copyright (c) 2011,19 MiSTer-X
module ninjakun_video
module NINJAKUN_VIDEO
(
input RESET,
input VCLKx4,
input VCLK,
input MCLK,
input PCLK_EN,
input [8:0] PH,
input [8:0] PV,
@ -23,18 +24,20 @@ module ninjakun_video
output VBLK,
input DBGPD, // Palet Display (for Debug)
// output [12:0] sp_rom_addr,
// input [31:0] sp_rom_data,
// output [12:0] fg_rom_addr,
// input [31:0] fg_rom_data,
output [12:0] bg_rom_addr,
input [31:0] bg_rom_data
output [12:0] sp_rom_addr,
input [31:0] sp_rom_data,
input sp_rdy,
output [12:0] fg_rom_addr,
input [31:0] fg_rom_data,
output [12:0] bg_rom_addr,
input [31:0] bg_rom_data
);
assign VBLK = (PV>=193);
// ROMs
wire SPCFT = 1'b1;
wire SPCFT = sp_rdy;
wire [12:0] SPCAD;
wire [31:0] SPCDT;
@ -47,83 +50,20 @@ wire [31:0] BGCDT;
//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//assign sp_rom_addr = SPCAD;
//assign SPCDT = sp_rom_data;
//assign fg_rom_addr = FGCAD;
//assign FGCDT = fg_rom_data;
/*
static GFXDECODE_START( gfx_ninjakun )
GFXDECODE_ENTRY( "gfx1", 0, layout16x16, 0x200, 16 ) // sprites
GFXDECODE_ENTRY( "gfx1", 0, layout8x8, 0x000, 16 ) // fg tiles
GFXDECODE_ENTRY( "gfx2", 0, layout8x8, 0x100, 16 ) // bg tiles
GFXDECODE_END*/
assign sp_rom_addr = SPCAD;
assign SPCDT = sp_rom_data;
assign fg_rom_addr = FGCAD;
assign FGCDT = fg_rom_data;
assign bg_rom_addr = BGCAD;
assign BGCDT = bg_rom_data;
fg_sp_dulport_rom gfx1_rom(
.address_a(SPCAD),
.address_b(FGCAD),
.clock_a(VCLKx4),
.clock_b(VCLK),
.q_a(SPCDT),
.q_b(FGCDT)
);
/*
fg1_rom fg1_rom (
.clk(~VCLKx4),//if sprite ? ~VCLKx4 : ~VCLK
.addr(SPCAD),//if sprite ? SPCAD : FGCAD
.data(SPCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
);
fg2_rom fg2_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[15:8])
);
fg3_rom fg3_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[23:16])
);
fg4_rom fg4_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[31:24])
);*//*
fg1_rom fg1_rom (
.clk(~VCLK),//if sprite ? ~VCLKx4 : ~VCLK
.addr(FGCAD),//if sprite ? SPCAD : FGCAD
.data(FGCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
);
fg2_rom fg2_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[15:8])
);
fg3_rom fg3_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[23:16])
);
fg4_rom fg4_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[31:24])
);*/
// Fore-Ground Scanline Generator
wire FGPRI;
wire [8:0] FGOUT;
ninjakun_fg fg(
VCLK,
NINJAKUN_FG fg(
MCLK, PCLK_EN,
PH, PV,
FGVAD, FGVDT,
FGCAD, FGCDT,
@ -134,8 +74,8 @@ wire FGPPQ = FGOPQ & (~FGPRI);
// Back-Ground Scanline Generator
wire [8:0] BGOUT;
ninjakun_bg bg(
VCLK,
NINJAKUN_BG bg(
MCLK, PCLK_EN,
PH, PV,
BGSCX, BGSCY,
BGVAD, BGVDT,
@ -145,8 +85,8 @@ ninjakun_bg bg(
// Sprite Scanline Generator
wire [8:0] SPOUT;
ninjakun_sp sp(
VCLKx4, VCLK,
NINJAKUN_SP sp(
MCLK, PCLK_EN, RESET,
PH, PV,
SPAAD, SPADT,
SPCAD, SPCDT, SPCFT,
@ -155,20 +95,137 @@ ninjakun_sp sp(
wire SPOPQ = (SPOUT[3:0]!=0);
// Palet Display (for Debug)
wire [8:0] PDOUT = (PV[7]|PV[8]) ? 0 : {PV[6:2],PH[7:4]};
wire [8:0] PDOUT = (PV[7]|PV[8]) ? 9'd0 : {PV[6:2],PH[7:4]};
// Color Mixer
dataselector_4D_9B dataselector_4D_9B(
.OUT(PALAD),
.EN1(DBGPD),
.IN1(PDOUT),
.EN2(FGPPQ),
.IN2(FGOUT),
.EN3(SPOPQ),
.IN3(SPOUT),
.EN4(FGOPQ),
.IN4(FGOUT),
.IND(BGOUT)
DSEL4_9B cmix( PALAD,
DBGPD, PDOUT,
FGPPQ, FGOUT,
SPOPQ, SPOUT,
FGOPQ, FGOUT,
BGOUT
);
endmodule
endmodule
// ForeGround Scanline Generator
module NINJAKUN_FG
(
input MCLK,
input PCLK_EN,
input [8:0] PH, // CRTC
input [8:0] PV,
output reg [9:0] FGVAD, // VRAM
input [15:0] FGVDT,
output reg [12:0] FGCAD,
input [31:0] FGCDT,
output [9:0] FGOUT // PIXEL OUT : {PRIO,PALNO[8:0]}
);
wire [8:0] POSH = PH+9'd8+9'd1;
wire [8:0] POSV = PV+9'd32;
wire [9:0] CHRNO = {1'b0,FGVDT[13],FGVDT[7:0]};
reg [31:0] CDT;
reg [4:0] PAL;
reg [3:0] OUT;
always @( posedge MCLK ) begin
if (PCLK_EN)
case(POSH[2:0])
0: begin OUT <= CDT[7:4] ; PAL <= FGVDT[12:8]; end
1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end
2: begin OUT <= CDT[15:12]; end
3: begin OUT <= CDT[11:8] ; end
4: begin OUT <= CDT[23:20]; FGCAD <= {CHRNO,POSV[2:0]}; end
5: begin OUT <= CDT[19:16]; end
6: begin OUT <= CDT[31:28]; end
7: begin OUT <= CDT[27:24]; CDT <= FGCDT; end
endcase
end
assign FGOUT = { PAL[4], 1'b0, PAL[3:0], OUT };
endmodule
// BackGround Scanline Generator
module NINJAKUN_BG
(
input MCLK,
input PCLK_EN,
input [8:0] PH, // CRTC
input [8:0] PV,
input [7:0] BGSCX, // SCRREG
input [7:0] BGSCY,
output reg [9:0] BGVAD, // VRAM
input [15:0] BGVDT,
output reg [12:0] BGCAD,
input [31:0] BGCDT,
output [8:0] BGOUT // OUTPUT
);
wire [8:0] POSH = PH+BGSCX+9'd2;
wire [8:0] POSV = PV+BGSCY+9'd32;
wire [9:0] CHRNO = {BGVDT[15:14],BGVDT[7:0]};
reg [31:0] CDT;
reg [3:0] PAL;
reg [3:0] OUT;
always @( posedge MCLK ) begin
if (PCLK_EN)
case(POSH[2:0])
0: begin OUT <= CDT[7:4] ; PAL <= BGVDT[11:8]; end
1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end
2: begin OUT <= CDT[15:12]; end
3: begin OUT <= CDT[11:8] ; end
4: begin OUT <= CDT[23:20]; BGCAD <= {CHRNO,POSV[2:0]}; end
5: begin OUT <= CDT[19:16]; end
6: begin OUT <= CDT[31:28]; end
7: begin OUT <= CDT[27:24]; CDT <= BGCDT; end
endcase
end
assign BGOUT = { 1'b1, PAL, OUT };
endmodule
module DSEL4_9B
(
output [8:0] OUT,
input EN1,
input [8:0] IN1,
input EN2,
input [8:0] IN2,
input EN3,
input [8:0] IN3,
input EN4,
input [8:0] IN4,
input [8:0] IND
);
assign OUT = EN1 ? IN1:
EN2 ? IN2:
EN3 ? IN3:
EN4 ? IN4:
IND;
endmodule

50
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v
View File

@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@ -39,27 +39,23 @@
module pll (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire5),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
@ -102,10 +98,6 @@ module pll (
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@ -139,7 +131,7 @@ module pll (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
@ -180,11 +172,8 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@ -205,26 +194,18 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@ -247,14 +228,11 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@ -263,10 +241,6 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@ -299,7 +273,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@ -318,13 +292,11 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE

1026
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/gfx1.hex
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File diff suppressed because it is too large Load Diff

12
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_rom.bat
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@ -1,12 +0,0 @@
copy /b ninja-1.7a + ninja-2.7b + ninja-3.7d + ninja-4.7e cpu1_rom.bin
copy /b ninja-5.7h + ninja-2.7b + ninja-3.7d + ninja-4.7e cpu2_rom.bin
copy /b ninja-10.2c + ninja-11.2d + ninja-12.4c + ninja-13.4d bg.bin
copy /b cpu1_rom.bin + cpu2_rom.bin + bg.bin NINJAKUN.ROM
copy /b ninja-6.7n + ninja-7.7p + ninja-8.7s + ninja-9.7t fg.bin
make_vhdl_prom.exe ninja-6.7n fg1_rom.vhd
make_vhdl_prom.exe ninja-7.7p fg2_rom.vhd
make_vhdl_prom.exe ninja-8.7s fg3_rom.vhd
make_vhdl_prom.exe ninja-9.7t fg4_rom.vhd
pause

BIN
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe
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BIN
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/ninjakun.zip
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Binary file not shown.

BIN
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/srec_cat.exe
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42
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv
View File

@ -59,8 +59,13 @@ module sdram (
input [15:0] port2_d,
output reg [31:0] port2_q,
input [16:2] bg_addr,
output reg [31:0] bg_q,
input [16:2] fg_addr,
output reg [31:0] fg_q,
input [16:2] sp_addr,
output reg [31:0] sp_q
output reg [31:0] sp_q,
output reg sp_rdy
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
@ -81,7 +86,7 @@ localparam RFRSH_CYCLES = 10'd842;
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
@ -153,7 +158,7 @@ assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[2];
reg [16:2] addr_last2[2];
reg [16:2] addr_last2[4];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
@ -162,14 +167,16 @@ reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_CPU2 = 2'd2;
localparam PORT_SP = 2'd1;
localparam PORT_REQ = 2'd3;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_SP = 3'd1;
localparam PORT_FG = 3'd2;
localparam PORT_BG = 3'd3;
localparam PORT_REQ = 3'd4;
reg [1:0] next_port[2];
reg [1:0] port[2];
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
@ -203,6 +210,12 @@ always @(*) begin
end else if (sp_addr != addr_last2[PORT_SP]) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
end else if (fg_addr != addr_last2[PORT_FG]) begin
next_port[1] = PORT_FG;
addr_latch_next[1] = { 1'b1, 7'd0, fg_addr, 1'b0 };
end else if (bg_addr != addr_last2[PORT_BG]) begin
next_port[1] = PORT_BG;
addr_latch_next[1] = { 1'b1, 7'd0, bg_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
@ -218,6 +231,8 @@ always @(posedge clk) begin
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
sp_rdy <= 0;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
@ -328,6 +343,8 @@ always @(posedge clk) begin
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q[15:0] <= sd_din;
PORT_FG : fg_q[15:0] <= sd_din;
PORT_BG : bg_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
@ -338,10 +355,13 @@ always @(posedge clk) begin
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_SP : begin sp_q[31:16] <= sd_din; end
PORT_FG : begin fg_q[31:16] <= sd_din; end
PORT_BG : begin bg_q[31:16] <= sd_din; end
PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy <= 1; end
default: ;
endcase;
end
end
end

8
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v
View File

@ -4,6 +4,8 @@ module Z80IP
(
input reset_in,
input clk,
input clken_p,
input clken_n,
output [15:0] adr,
input [7:0] data_in,
output [7:0] data_out,
@ -19,8 +21,10 @@ wire nmireq = 0;
wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh;
T80s cpu(
.CLK(~clk),
T80pa cpu(
.CLK(clk),
.CEN_p(clken_p),
.CEN_n(clken_n),
.RESET_n(~reset_in),
.INT_n(~intreq),
.NMI_n(~nmireq),