diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/cpu_mem.vhd index 8f4813d3..d7a2374b 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/cpu_mem.vhd +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/cpu_mem.vhd @@ -262,9 +262,12 @@ end process; -- RAM -- The original hardware multiplexes access to the RAM between the CPU and video hardware. In the FPGA it's -- easier to use dual-ported RAM -RAM: entity work.ram1k_dp +RAM: entity work.dpram +generic map( + widthad_a => 10, + width_a => 8) port map( - clock => clk6, + clock_a => clk6, -- CPU side address_a => adr(9 downto 0), wren_a => ram_we, @@ -272,6 +275,7 @@ port map( q_a=> CPUram_dout, -- Video side + clock_b => clk6, address_b => Vram_addr, wren_b => '0', data_b => x"FF", diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv index d5f08d27..25899384 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv @@ -3,7 +3,7 @@ // // MSBI is the highest bit number. NOT amount of bits! // -module dac #(parameter MSBI=13, parameter INV=1'b1) +module dac #(parameter MSBI=7, parameter INV=1'b1) ( output reg DACout, //Average Output feeding analog lowpass input [MSBI:0] DACin, //DAC input (excess 2**MSBI) diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dpram.vhd b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..9ea85a26 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dpram.vhd @@ -0,0 +1,130 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_a, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.qip b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.qip deleted file mode 100644 index a2e1e6a2..00000000 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram1k_dp.vhd"] diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd deleted file mode 100644 index 0907d677..00000000 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd +++ /dev/null @@ -1,224 +0,0 @@ --- megafunction wizard: %RAM: 2-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: ram1k_dp.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2014 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY ram1k_dp IS - PORT - ( - address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0); - clock : IN STD_LOGIC := '1'; - data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END ram1k_dp; - - -ARCHITECTURE SYN OF ram1k_dp IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); - -BEGIN - q_a <= sub_wire0(7 DOWNTO 0); - q_b <= sub_wire1(7 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK0", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK0", - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 1024, - numwords_b => 1024, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "CLOCK0", - outdata_reg_b => "CLOCK0", - power_up_uninitialized => "FALSE", - read_during_write_mode_mixed_ports => "DONT_CARE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => 10, - widthad_b => 10, - width_a => 8, - width_b => 8, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK0" - ) - PORT MAP ( - clock0 => clock, - wren_a => wren_a, - address_b => address_b, - data_b => data_b, - wren_b => wren_b, - address_a => address_a, - data_a => data_a, - q_a => sub_wire0, - q_b => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" --- Retrieval info: PRIVATE: CLRdata NUMERIC "0" --- Retrieval info: PRIVATE: CLRq NUMERIC "0" --- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRrren NUMERIC "0" --- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRwren NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "0" --- Retrieval info: PRIVATE: Clock_A NUMERIC "0" --- Retrieval info: PRIVATE: Clock_B NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" --- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "../roms/033455e1.hex" --- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" --- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" --- Retrieval info: PRIVATE: REGdata NUMERIC "1" --- Retrieval info: PRIVATE: REGq NUMERIC "1" --- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" --- Retrieval info: PRIVATE: REGrren NUMERIC "0" --- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" --- Retrieval info: PRIVATE: REGwren NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" --- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" --- Retrieval info: PRIVATE: VarWidth NUMERIC "0" --- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" --- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" --- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" --- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" --- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: enable NUMERIC "0" --- Retrieval info: PRIVATE: rden NUMERIC "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" --- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" --- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" --- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" --- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" --- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]" --- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" --- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" --- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" --- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" --- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" --- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" --- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 --- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 --- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 --- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 --- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 --- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv index eef9fcb4..2406115a 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv @@ -87,14 +87,19 @@ sprint2 sprint2 ( .Lamp2_O(led2) ); -dac dac ( +dac dac1 ( .CLK(clk_48), .RESET(1'b0), - .DACin({audio1, audio2}), + .DACin(audio1), .DACout(AUDIO_L) ); - -assign AUDIO_R = AUDIO_L; + +dac dac2 ( + .CLK(clk_48), + .RESET(1'b0), + .DACin(audio2), + .DACout(AUDIO_R) + ); wire hs, vs; wire hb, vb; diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd index f0bd0765..dffaca54 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd @@ -233,11 +233,11 @@ port map( -- Audio mixer, also mutes sound in attract mode -Audio1 <= ('0' & motor1_snd) + ("00" & screech1) + ('0' & bang_filtered);-- when attract = '0' - --else "0000000"; +Audio1 <= ('0' & motor1_snd) + ("00" & screech1) + ('0' & bang_filtered) when attract = '0' + else "0000000"; -Audio2 <= ('0' & motor2_snd) + ("00" & screech2) + ('0' & bang_filtered);-- when attract = '0' - --else "0000000"; +Audio2 <= ('0' & motor2_snd) + ("00" & screech2) + ('0' & bang_filtered) when attract = '0' + else "0000000"; diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf index 1a2d62dc..1d603b9e 100644 Binary files a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf and b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf differ diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf index 291514ff..06dfc92c 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf @@ -150,7 +150,6 @@ set_global_assignment -name VHDL_FILE rtl/collision.vhd set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd set_global_assignment -name VHDL_FILE rtl/Inputs.vhd set_global_assignment -name VHDL_FILE rtl/sprint2_sound.vhd -set_global_assignment -name QIP_FILE rtl/ram1k_dp.qip set_global_assignment -name VHDL_FILE rtl/screech.vhd set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv @@ -183,4 +182,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27 +set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file