diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qsf b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qsf
index 6be0183c..433ec086 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qsf	
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qsf	
@@ -183,7 +183,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
 
 # Assembler Assignments
 # =====================
@@ -193,7 +193,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
 # SignalTap II Assignments
 # ========================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/video.stp
 
 # Power Estimation Assignments
 # ============================
@@ -415,10 +415,11 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(Capitol_MiST)
-# ------------------------
\ No newline at end of file
+# ------------------------
+set_global_assignment -name SIGNALTAP_FILE output_files/video.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.sdc b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.sdc
index 3eba3b05..ea8cd2c9 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.sdc	
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.sdc	
@@ -23,11 +23,20 @@
 
 # Clock constraints
 
-create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
-create_clock -name {SPI_SCK}  -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
 # Automatically constrain PLL and other generated clocks
 derive_pll_clocks -create_base_clocks
 
 # Automatically calculate clock uncertainty to jitter and other effects.
 derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv
index b460b5f4..300bb245 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv	
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv	
@@ -40,13 +40,12 @@ localparam CONF_STR = {
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clk_sys, clk_mist;
+wire clk_sys;
 wire pll_locked;
 pll pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_mist),//22
-	.c1(clk_sys)//11
+	.c0(clk_sys)//11
 	);
 
 wire [31:0] status;
@@ -58,7 +57,7 @@ wire        scandoublerD;
 wire        ypbpr;
 reg	[11:0] audio;
 wire 			hb1, hb2, vb;
-wire        blankn = ~(hb1 | hb2 | vb);
+wire        blankn = ~((hb1 & hb2) | vb);
 wire 			hs, vs;
 wire  [1:0] r,g,b;
 
@@ -84,21 +83,22 @@ phoenix phoenix(
 	.audio(audio)
 	);
 	
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_mist),
+mist_video #(.COLOR_DEPTH(2)) mist_video(
+	.clk_sys(clk_sys),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(blankn ? {r,r,r} : "000"),
-	.G(blankn ? {g,g,g} : "000"),
-	.B(blankn ? {b,b,b} : "000"),
-	.HSync(hs),
-	.VSync(vs),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? b : 0),
+	.HSync(~hs),
+	.VSync(~vs),
 	.VGA_R(VGA_R),
 	.VGA_G(VGA_G),
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.ce_divider(1'b1),
 	.rotate({1'b1,status[2]}),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
@@ -108,7 +108,7 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_mist       ),
+	.clk_sys        (clk_sys        ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -130,9 +130,9 @@ user_io(
 dac #(
 	.C_bits(15))
 dac(
-	.clk_i(clk_mist),
+	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({audio, 4'b0000}),
+	.dac_i({audio, 3'b000}),
 	.dac_o(AUDIO_L)
 	);
 //											Rotated														Normal
@@ -157,7 +157,7 @@ wire [7:0] key_code;
 wire       key_strobe;
 
 
-always @(posedge clk_mist) begin
+always @(posedge clk_sys) begin
 if(key_strobe) begin
 		case(key_code)
 			'h75: btn_up          <= key_pressed; // up
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd
index f65529b1..e2f40e65 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd	
@@ -290,12 +290,25 @@ color_id  <=  (fr_bit0 or fr_bit1) &  fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
 -- address palette with pixel bits color and color set
 palette_adr <= color_set2 & color_set & color_id;
 -- output video to top level
-video_vblank <= vblank;
-video_hblank_fg <= hblank_frgrd;
-video_hblank_bg <= hblank_bkgrd;
-video_r     <= rgb_1(0) & rgb_0(0) when (hcnt>=192) else "00";
-video_g     <= rgb_1(2) & rgb_0(2) when (hcnt>=192) else "00";
-video_b     <= rgb_1(1) & rgb_0(1) when (hcnt>=192) else "00";
+-- output video to top level
+process(clk) begin
+	if rising_edge(clk) then
+		if ce_pix1='1' then
+			video_vblank <= vblank;
+			video_hblank_fg <= hblank_frgrd;
+			video_hblank_bg <= hblank_bkgrd;
+			if hcnt>=192 then
+				video_r <= rgb_1(0) & rgb_0(0);
+				video_g <= rgb_1(2) & rgb_0(2);
+				video_b <= rgb_1(1) & rgb_0(1);
+			else
+				video_r <= "00";
+				video_g <= "00";
+				video_b <= "00";
+			end if;
+		end if;
+	end if;
+end process;
 
 frgnd_bit0 : entity work.PROM_39
 port map(
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf
new file mode 100644
index 00000000..55f387da
--- /dev/null
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf	
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd
index 25a2d8f7..cf6d2d12 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd	
@@ -44,8 +44,7 @@ ENTITY pll IS
 	(
 		areset		: IN STD_LOGIC  := '0';
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -55,10 +54,9 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -69,10 +67,6 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -131,26 +125,20 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	sub_wire2    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 27,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 22,
+		clk0_multiply_by => 11,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 11,
-		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -184,7 +172,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -203,7 +191,7 @@ BEGIN
 	)
 	PORT MAP (
 		areset => areset,
-		inclk => sub_wire4,
+		inclk => sub_wire3,
 		clk => sub_wire0
 	);
 
@@ -231,11 +219,8 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "22.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "11.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -256,26 +241,18 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "22"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "22.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "11.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -298,26 +275,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "22"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -350,7 +320,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -370,13 +340,11 @@ END SYN;
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qsf b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qsf
index 46772dd4..4b061871 100644
--- a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qsf	
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qsf	
@@ -183,7 +183,7 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
 
 # Assembler Assignments
 # =====================
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.sdc b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.sdc
index 3eba3b05..ea8cd2c9 100644
--- a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.sdc	
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.sdc	
@@ -23,11 +23,20 @@
 
 # Clock constraints
 
-create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
-create_clock -name {SPI_SCK}  -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
 # Automatically constrain PLL and other generated clocks
 derive_pll_clocks -create_base_clocks
 
 # Automatically calculate clock uncertainty to jitter and other effects.
 derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv
index c270258e..03f8e933 100644
--- a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv	
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv	
@@ -40,13 +40,12 @@ localparam CONF_STR = {
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clk_sys, clk_mist;
+wire clk_sys;
 wire pll_locked;
 pll pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_mist),//22
-	.c1(clk_sys)//11
+	.c0(clk_sys)//11
 	);
 
 wire [31:0] status;
@@ -59,7 +58,7 @@ wire        ypbpr;
 wire [10:0] ps2_key;
 reg	[11:0] audio;
 wire 			hb1, hb2, vb;
-wire        blankn = ~(hb1 | hb2 | vb);
+wire        blankn = ~((hb1 & hb2) | vb);
 wire 			ce_pix;
 wire 			hs, vs;
 wire  [1:0] r,g,b;
@@ -87,21 +86,22 @@ phoenix phoenix(
 	.audio(audio)
 	);
 	
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_mist),
+mist_video #(.COLOR_DEPTH(2)) mist_video(
+	.clk_sys(clk_sys),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(blankn ? {r,r,r} : "000"),
-	.G(blankn ? {g,g,g} : "000"),
-	.B(blankn ? {b,b,b} : "000"),
-	.HSync(hs),
-	.VSync(vs),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? b : 0),
+	.HSync(~hs),
+	.VSync(~vs),
 	.VGA_R(VGA_R),
 	.VGA_G(VGA_G),
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.ce_divider(1'b1),
 	.rotate({1'b1,status[2]}),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
@@ -111,7 +111,7 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_mist       ),
+	.clk_sys        (clk_sys        ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -132,9 +132,9 @@ user_io(
 dac #(
 	.C_bits(15))
 dac(
-	.clk_i(clk_mist),
+	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({audio, 4'b0000}),
+	.dac_i({audio, 3'b000}),
 	.dac_o(AUDIO_L)
 	);
 //											Rotated														Normal
@@ -159,7 +159,7 @@ wire [7:0] key_code;
 wire       key_strobe;
 
 
-always @(posedge clk_mist) begin
+always @(posedge clk_sys) begin
 if(key_strobe) begin
 		case(key_code)
 			'h75: btn_up          <= key_pressed; // up
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix.vhd b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix.vhd
index 9fc4d8ea..de232aa0 100644
--- a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix.vhd	
@@ -287,12 +287,24 @@ color_id  <=  (fr_bit0 or fr_bit1) &  fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
 palette_adr <= '0' & color_set & color_id;
 
 -- output video to top level
-video_vblank <= vblank;
-video_hblank_fg <= hblank_frgrd;
-video_hblank_bg <= hblank_bkgrd;
-video_r     <= rgb_1(0) & rgb_0(0) when (hcnt>=192) else "00";
-video_g     <= rgb_1(2) & rgb_0(2) when (hcnt>=192) else "00";
-video_b     <= rgb_1(1) & rgb_0(1) when (hcnt>=192) else "00";
+process(clk) begin
+	if rising_edge(clk) then
+		if ce_pix1='1' then
+			video_vblank <= vblank;
+			video_hblank_fg <= hblank_frgrd;
+			video_hblank_bg <= hblank_bkgrd;
+			if hcnt>=192 then
+				video_r <= rgb_1(0) & rgb_0(0);
+				video_g <= rgb_1(2) & rgb_0(2);
+				video_b <= rgb_1(1) & rgb_0(1);
+			else
+				video_r <= "00";
+				video_g <= "00";
+				video_b <= "00";
+			end if;
+		end if;
+	end if;
+end process;
 
 G_yes_tile_rom: if C_tile_rom generate
 -- foreground graphix ROM bit0
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.ppf b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.ppf
new file mode 100644
index 00000000..55f387da
--- /dev/null
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.ppf	
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.vhd b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.vhd
index 25a2d8f7..cf6d2d12 100644
--- a/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.vhd	
@@ -44,8 +44,7 @@ ENTITY pll IS
 	(
 		areset		: IN STD_LOGIC  := '0';
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -55,10 +54,9 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -69,10 +67,6 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -131,26 +125,20 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	sub_wire2    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 27,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 22,
+		clk0_multiply_by => 11,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 11,
-		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -184,7 +172,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -203,7 +191,7 @@ BEGIN
 	)
 	PORT MAP (
 		areset => areset,
-		inclk => sub_wire4,
+		inclk => sub_wire3,
 		clk => sub_wire0
 	);
 
@@ -231,11 +219,8 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "22.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "11.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -256,26 +241,18 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "22"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "22.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "11.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -298,26 +275,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "22"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -350,7 +320,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -370,13 +340,11 @@ END SYN;
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Pleiads_mist.sdc b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Pleiads_mist.sdc
index 3eba3b05..ea8cd2c9 100644
--- a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Pleiads_mist.sdc	
+++ b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/Pleiads_mist.sdc	
@@ -23,11 +23,20 @@
 
 # Clock constraints
 
-create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
-create_clock -name {SPI_SCK}  -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
 # Automatically constrain PLL and other generated clocks
 derive_pll_clocks -create_base_clocks
 
 # Automatically calculate clock uncertainty to jitter and other effects.
 derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/Pleiads_MiST.sv b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/Pleiads_MiST.sv
index 024b06d6..0c80b8b4 100644
--- a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/Pleiads_MiST.sv	
+++ b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/Pleiads_MiST.sv	
@@ -40,13 +40,12 @@ localparam CONF_STR = {
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clk_sys, clk_mist;
+wire clk_sys;
 wire pll_locked;
 pll pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
-	.c0(clk_mist),//22
-	.c1(clk_sys)//11
+	.c0(clk_sys)//11
 	);
 
 wire [31:0] status;
@@ -58,7 +57,7 @@ wire        scandoublerD;
 wire        ypbpr;
 reg	[11:0] audio;
 wire 			hb1, hb2, vb;
-wire        blankn = ~(hb1 | hb2 | vb);
+wire        blankn = ~((hb1 & hb2) | vb);
 wire 			ce_pix;
 wire 			hs, vs;
 wire  [1:0] r,g,b;
@@ -86,21 +85,22 @@ phoenix phoenix(
 	.audio(audio)
 	);
 	
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_mist),
+mist_video #(.COLOR_DEPTH(2)) mist_video(
+	.clk_sys(clk_sys),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(blankn ? {r,r,r} : "000"),
-	.G(blankn ? {g,g,g} : "000"),
-	.B(blankn ? {b,b,b} : "000"),
-	.HSync(hs),
-	.VSync(vs),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? b : 0),
+	.HSync(~hs),
+	.VSync(~vs),
 	.VGA_R(VGA_R),
 	.VGA_G(VGA_G),
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
+	.ce_divider(1'b1),
 	.rotate({1'b1,status[2]}),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
@@ -110,7 +110,7 @@ mist_video #(.COLOR_DEPTH(3)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clk_mist       ),
+	.clk_sys        (clk_sys        ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -132,9 +132,9 @@ user_io(
 dac #(
 	.C_bits(15))
 dac(
-	.clk_i(clk_mist),
+	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({audio, 4'b0000}),
+	.dac_i({audio, 3'b000}),
 	.dac_o(AUDIO_L)
 	);
 //											Rotated														Normal
@@ -159,7 +159,7 @@ wire [7:0] key_code;
 wire       key_strobe;
 
 
-always @(posedge clk_mist) begin
+always @(posedge clk_sys) begin
 if(key_strobe) begin
 		case(key_code)
 			'h75: btn_up          <= key_pressed; // up
diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/phoenix.vhd b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/phoenix.vhd
index 01d363b3..39cad64e 100644
--- a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/phoenix.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/phoenix.vhd	
@@ -289,14 +289,27 @@ color_id  <=  (fr_bit0 or fr_bit1) &  fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
 
 -- address palette with pixel bits color and color set
 palette_adr <= color_set2 & color_set & color_id;
+
 -- output video to top level
-video_vblank <= vblank;
-video_hblank_fg <= hblank_frgrd;
-video_hblank_bg <= hblank_bkgrd;
-video_r     <= rgb_1(0) & rgb_0(0) when (hcnt>=192) else "00";
-video_g     <= rgb_1(2) & rgb_0(2) when (hcnt>=192) else "00";
-video_b     <= rgb_1(1) & rgb_0(1) when (hcnt>=192) else "00";
-	
+process(clk) begin
+	if rising_edge(clk) then
+		if ce_pix1='1' then
+			video_vblank <= vblank;
+			video_hblank_fg <= hblank_frgrd;
+			video_hblank_bg <= hblank_bkgrd;
+			if hcnt>=192 then
+				video_r <= rgb_1(0) & rgb_0(0);
+				video_g <= rgb_1(2) & rgb_0(2);
+				video_b <= rgb_1(1) & rgb_0(1);
+			else
+				video_r <= "00";
+				video_g <= "00";
+				video_b <= "00";
+			end if;
+		end if;
+	end if;
+end process;
+
 frgnd_bit0 : entity work.ic39
 port map(
 	clk  => clk,
diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.ppf b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.ppf
index 2dc9dced..55f387da 100644
--- a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.ppf	
+++ b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.ppf	
@@ -5,7 +5,6 @@
 <pin name="areset" direction="input" scope="external"  />
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
 <pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
 
 </global>
 </pinplan>
diff --git a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.vhd b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.vhd
index 25a2d8f7..cf6d2d12 100644
--- a/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.vhd	
+++ b/Arcade_MiST/Phoenix Hardware/Pleiads_MIST/rtl/pll.vhd	
@@ -44,8 +44,7 @@ ENTITY pll IS
 	(
 		areset		: IN STD_LOGIC  := '0';
 		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC 
+		c0		: OUT STD_LOGIC 
 	);
 END pll;
 
@@ -55,10 +54,9 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -69,10 +67,6 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -131,26 +125,20 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	sub_wire2    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 27,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 22,
+		clk0_multiply_by => 11,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 11,
-		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -184,7 +172,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -203,7 +191,7 @@ BEGIN
 	)
 	PORT MAP (
 		areset => areset,
-		inclk => sub_wire4,
+		inclk => sub_wire3,
 		clk => sub_wire0
 	);
 
@@ -231,11 +219,8 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "22.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "11.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -256,26 +241,18 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "22"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "22.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "11.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -298,26 +275,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "22"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -350,7 +320,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -370,13 +340,11 @@ END SYN;
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE