From 9c5464541c1ccc0d080cbaba202a8696600e88d6 Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com>
Date: Wed, 21 Dec 2022 01:18:35 +0100
Subject: [PATCH] Alpha68k HW
---
.../Alpha Densi M68000 Hardware/Alpha68k.qpf | 31 +
.../Alpha Densi M68000 Hardware/Alpha68k.qsf | 225 +++
.../Alpha Densi M68000 Hardware/Alpha68k.sdc | 138 ++
.../Alpha Densi M68000 Hardware/README.md | 118 ++
.../Alpha Densi M68000 Hardware/clean.bat | 36 +
.../meta/Gang Wars.mra | 73 +
...Gold Medalist (Set 1, Alpha68k II PCB).mra | 71 +
.../meta/Sky Adventure (World).mra | 63 +
.../meta/Sky Soldiers (US).mra | 95 ++
.../meta/Super Champion Baseball (Japan).mra | 68 +
.../meta/Time Soldiers (US Rev 3).mra | 83 ++
.../meta/WIP/Super Champion Baseball (US).mra | 68 +
.../rtl/Alpha68k.sv | 1263 +++++++++++++++++
.../rtl/Alpha68k_MiST.sv | 345 +++++
.../rtl/build_id.tcl | 35 +
.../rtl/chip_select.v | 285 ++++
.../Alpha Densi M68000 Hardware/rtl/defs.v | 9 +
.../rtl/dual_port_ram.vhd | 117 ++
.../Alpha Densi M68000 Hardware/rtl/math.vhd | 72 +
.../rtl/pll_mist.qip | 4 +
.../rtl/pll_mist.v | 309 ++++
.../Alpha Densi M68000 Hardware/rtl/sdram.sv | 449 ++++++
.../rtl/video_timing.v | 99 ++
23 files changed, 4056 insertions(+)
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/README.md
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gold Medalist (Set 1, Alpha68k II PCB).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Adventure (World).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Soldiers (US).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Super Champion Baseball (Japan).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/Time Soldiers (US Rev 3).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/meta/WIP/Super Champion Baseball (US).mra
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv
create mode 100644 Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf
new file mode 100644
index 00000000..99b0aa98
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Intel and sold by Intel or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
+# Date created = 04:04:47 October 16, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "04:04:47 October 16, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Alpha68k"
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf
new file mode 100644
index 00000000..5b516b59
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.qsf
@@ -0,0 +1,225 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 05:08:48 November 15, 2017
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# Arcade-Scramble_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY Alpha68k_MiST
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# ----------------------
+# start ENTITY(Alpha68k)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(Alpha68k)
+# --------------------
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name FORCE_SYNCH_CLEAR ON
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Alpha68k_MiST.sv
+set_global_assignment -name QIP_FILE rtl/pll_mist.qip
+set_global_assignment -name VERILOG_FILE rtl/video_timing.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Alpha68k.sv
+set_global_assignment -name VHDL_FILE rtl/math.vhd
+set_global_assignment -name VHDL_FILE rtl/dual_port_ram.vhd
+set_global_assignment -name VERILOG_FILE rtl/chip_select.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
+set_global_assignment -name QIP_FILE ../../common/Sound/JT12/hdl/jt03.qip
+set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt2413.qip
+set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip
+set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name CDF_FILE output_files/Alpha68k.cdf
+set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/cpu2.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/fg.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/mcu.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc
new file mode 100644
index 00000000..0746a9e8
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/Alpha68k.sdc
@@ -0,0 +1,138 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -from {Alpha68k:Alpha68k|T80pa:z80|T80:u0|*} -setup 2
+set_multicycle_path -from {Alpha68k:Alpha68k|T80pa:z80|T80:u0|*} -hold 1
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/README.md b/Arcade_MiST/Alpha Densi M68000 Hardware/README.md
new file mode 100644
index 00000000..44acf881
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/README.md
@@ -0,0 +1,118 @@
+
+# Alpha Denshi M68000 FPGA Implementation
+
+FPGA compatible core of Alpha Denshi M68000 (ALPHA68K96V based) arcade hardware written by [**Darren Olafson**](https://twitter.com/Darren__O).
+
+FPGA implementation has been verified against schematics for Sky Adventure. PCB measurements taken from Gang Wars (ALPHA-68K96V) and Sky Soldiers (ALPHA-96KII).
+
+Sky Adventure (bootleg) PCB purchased by [**Darren Olafson**](https://twitter.com/Darren__O) / [**atrac17**](https://github.com/atrac17). Gang Wars, Sky Soldiers, and The Next Space (authentic) PCBs purchased by [**atrac17**](https://github.com/atrac17).
+
+The intent is for this core to be a 1:1 playable implementation of Alpha Denshi M68000 arcade hardware. Currently in **beta state**, this core is in active development with assistance from [**atrac17**](https://github.com/atrac17).
+
+MiST port, new SDRAM controller, some fixes and enhancements by Gyorgy Szombathelyi.
+
+## Supported Games
+
+| Title | PCB
Number | Status | Released | ROM Set |
+|-------|---------------|---------|----------|---------|
+| [**Gang Wars**](https://en.wikipedia.org/wiki/Gang_Wars_(video_game)) | ALPHA-68K96V (GW) | Implemented | Yes | .249 merged set |
+| [**Super Champion Baseball**](https://snk.fandom.com/wiki/Super_Champion_Baseball) | ALPHA-68K96V (GW) | Implemented | Yes | .249 (**sbasebalj** only) |
+| [**Sky Adventure**](https://snk.fandom.com/wiki/Sky_Adventure) | ALPHA-68K96V (GW) | Implemented | Yes | .249 merged set |
+| [**バトル フィールド**](https://en.wikipedia.org/wiki/Time_Soldiers)
Time Soldiers | ALPHA-68K96II (SS) | Implemented | Yes | .249 merged set |
+| [**Sky Soldiers**](https://en.wikipedia.org/wiki/Sky_Soldiers) | ALPHA-68K96II (SS) | Implemented | Yes | .249 merged set |
+| [**Gold Medalist**](https://snk.fandom.com/wiki/Gold_Medalist) | ALPHA-68K96II (SS) | Implemented | No | .249 (**goldmedl** only) |
+| [**Paddle Mania**](https://snk.fandom.com/wiki/Paddle_Mania) | ALPHA-68K96I | **W.I.P** | No | N/A |
+| [**The Next Space**](https://snk.fandom.com/wiki/The_Next_Space) | A8004-1 | **Separate
Repository** | No | N/A |
+| [**Super Stingray**](https://segaretro.org/Super_Stingray) | N/A | **W.I.P** | No | N/A |
+| [**Kyros no Yakata**](http://www.hardcoregaming101.net/kyros-desolator/) | N/A | **W.I.P** | No | N/A |
+| [**Mahjong Block Jongbou**](https://snk.fandom.com/wiki/Jongbou) | ALPHA-68K96N | **W.I.P** | No | N/A |
+
+## External Modules
+
+|Name| Purpose | Author |
+|----|---------|--------|
+| [**fx68k**](https://github.com/ijor/fx68k) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Jorge Cwik |
+| [**t80**](https://opencores.org/projects/t80) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Daniel Wallner |
+| [**jt2413**](https://github.com/jotego/jtopl) | [**Yamaha OPL-L**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | Jose Tejada |
+| [**jt03**](https://github.com/jotego/jt12) | [**Yamaha OPN**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | Jose Tejada |
+
+# PCB Check List
+
+
+
+FPGA implementation has been verified against [**schematics**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) for Sky Adventure. The schematics are improperly labeled Prehistoric Isle (hand written), this was discovered during development of the [**Prehistoric Isle FPGA implementation**](https://github.com/va7deo/PrehistoricIsle). PCB measurements taken from Gang Wars (ALPHA-68K96V) and Sky Adventure (ALPHA-68K96II).
+
+### Clock Information
+
+H-Sync | V-Sync | Source | PCB
Number |
+------------|-------------|----------|----------------|
+15.625kHz | 59.185606Hz | [**DSLogic+**](FILLME) | ALPHA-68K96V (GW) |
+15.625kHz | 59.185606Hz | [**DSLogic+**](FILLME) | ALPHA-68K96II (SS) |
+
+### Crystal Oscillators
+
+- MAME documentation for the Alpha96k.cpp states that ALPHA-68K96II hardware runs the M68000 at 8.00 MHZ. The actual frequency for the M68000 is 9.00 MHZ based on board readings from Sky Soldier.
+
+Location | PCB
Number | Freq (MHz) | Use |
+------------------------|--------------------|------------|----------------------------------------------------------------------------------------------|
+X-1 (24 MHZ) | ALPHA-68K96V (GW) | 24.000 | Z80 CLK (6MHZ)
YM2203 (CLK 3 MHZ)
Sprite CLK (12 MHZ)
Pixel CLK (6 MHZ) |
+X-2 (20 MHZ) | ALPHA-68K96V (GW) | 20.000 | M68000 CLK (10 MHZ) |
+X-3 (3.579545 MHz) | ALPHA-68K96V (GW) | 3.579545 | YM2413 CLK (3.579545 MHz) |
+X-1 (3.579545 MHz) | ALPHA-68K96II (SS) | 24.000 | YM2413 CLK (3.579545 MHz) |
+X-2 (18 MHZ) | ALPHA-68K96II (SS) | 18.000 | M68000 CLK (9 MHZ) |
+X-3 (24 MHZ) | ALPHA-68K96II (SS) | 3.579545 | Z80 CLK (6MHZ)
YM2203 (CLK 3 MHZ)
Sprite CLK (12 MHZ)
Pixel CLK (6 MHZ) |
+
+**Pixel clock:** 6.00 MHz
+
+**Estimated geometry:**
+
+ 383 pixels/line
+
+ 263 pixels/line
+
+### Main Components
+
+Location | PCB
Number | Chip | Use |
+---------|---------------|------|-----|
+68000D | ALPHA-68K96V (GW) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
+Z80B | ALPHA-68K96V (GW) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
+YM2203 | ALPHA-68K96V (GW) | [**Yamaha YM2203**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | OPN |
+YM2413 | ALPHA-68K96V (GW) | [**Yamaha YM2413**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | OPL-L |
+
+Location | PCB
Number | Chip | Use |
+---------|---------------|------|-----|
+68000-10 | ALPHA-68K96II (SS) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
+Z80B | ALPHA-68K96II (SS) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
+YM2203 | ALPHA-68K96II (SS) | [**Yamaha YM2203**](https://en.wikipedia.org/wiki/Yamaha_YM2203) | OPN |
+YM2413 | ALPHA-68K96II (SS) | [**Yamaha YM2413**](https://en.wikipedia.org/wiki/Yamaha_YM2413) | OPL-L |
+
+### Custom Components
+
+Location | PCB
Number | Chip | Use |
+---------|---------------|------|-----|
+SP85
ALPHA-8511
ALPHA-8411 | ALPHA-68K96V (GW)
ALPHA-68K96II (SS)
ALPHA-68K96V (SA) | [**SP85N**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Coin Handling
Dipswitch Handling
Screen Inversion Handling |
+SNKCLK | ALPHA-68K96V (GW) | [**SNK CLK**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Counter |
+INPUT 84 | ALPHA-68K96II | [**ALPHA-INPUT 84**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Rotary Handling |
+INPUT 87 | ALPHA-68K96V (GW) | [**ALPHA-INPUT 87**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | Input Handling |
+ALPHA-8921 | ALPHA-68K96V (GW) | [**ALPHA-8921**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/ALPHA68K-96V_Schematics.pdf) | GFX Muxing |
+
+### SP85 / ALPHA-8511 / ALPHA-8411 Handling
+
+The SP85N or ALPHA-8511/8411 utilized on Alpha Denshi M68000 hardware for I/O handling appears to be closely related to the Motorola M68705p5. Early Alpha Denshi M68000 hardware utilized the M68705 before SNK / Alpha Denshi moved to a custom component. It's possible this is a rebadged custom.
+There is a known dump for the ALPHA-8511 (possibly a M68705 from a bootleg) used on Super Stingray and a dump of the M68705 used on the Kyros no Yakata bootleg. The program code from the Kyros no Yakata bootleg may match the original ALPHA-8511 program code according to mame documentation.
+The Sky Adventure bootleg purchased also uses a M68705p5 which is dumpable and will be submitted to mame along with the ROMs. Disassembly of the program code will be done for analysis based on current MCU implementation.
+[**Readings have been pulled from the Gang Wars SP85N**](https://github.com/va7deo/alpha68k/blob/main/doc/ALPHA-68K96V/Gang%20Wars/SP85N_Readings/SP85N_Gang_Wars_Readings.png) revealed that the MCU pushes 15 interrupts per second, mame's driver for Alpha68k has this coded as 100 or 120 interrupts per second.
+
+# Core Features
+
+### Rotary Joystick Support
+
+- Rotary control is supported via gamepad L and R buttons, or right stick on dual-stick gamepads.
+
+# Support
+
+Please consider showing support for this and future projects via [**Darren's Ko-fi**](https://ko-fi.com/darreno) and [**atrac17's Patreon**](https://www.patreon.com/atrac17). While it isn't necessary, it's greatly appreciated.
+
+# Licensing
+
+Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat b/Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat
new file mode 100644
index 00000000..1e6a801a
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/clean.bat
@@ -0,0 +1,36 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
+for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del *.rpt
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+pause
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra
new file mode 100644
index 00000000..fda2d171
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gang Wars.mra
@@ -0,0 +1,73 @@
+
+ Gang Wars
+ gangwars
+ alpha68k
+ 0249
+ 1989
+ Alpha Denshi Co.
+ World
+ 8-Way
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 01 3A
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FF
+
+ FF
+
+ FF
+
+ FF
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gold Medalist (Set 1, Alpha68k II PCB).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gold Medalist (Set 1, Alpha68k II PCB).mra
new file mode 100644
index 00000000..dc2c2dbf
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Gold Medalist (Set 1, Alpha68k II PCB).mra
@@ -0,0 +1,71 @@
+
+ Gold Medalist (Set 1, Alpha68k II PCB)
+ goldmedl
+ alpha68k
+ 0249
+ 1988
+ Alpha Denshi Co.
+ World
+ 8-Way
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 07 0E
+
+
+
+
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+ FF
+ FF
+ FF
+ FF
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Adventure (World).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Adventure (World).mra
new file mode 100644
index 00000000..caea158e
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Adventure (World).mra
@@ -0,0 +1,63 @@
+
+ Sky Adventure (World)
+ skyadvnt
+ alpha68k
+ 0249
+ 1989
+ Alpha Denshi Co.
+ World
+ 8-Way
+ vertical (cw)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 80 34
+
+
+
+
+
+
+ FF
+
+
+
+ FF
+
+ FF
+
+ FF
+
+ FF
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Soldiers (US).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Soldiers (US).mra
new file mode 100644
index 00000000..f793d296
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Sky Soldiers (US).mra
@@ -0,0 +1,95 @@
+
+ Sky Soldiers (US)
+ skysoldr
+ alpha68k
+ 0249
+ 1988
+ Alpha Denshi Co.
+ US
+ 8-Way
+ vertical (cw)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 85 0C
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FF
+
+ FF
+
+ FF
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Super Champion Baseball (Japan).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Super Champion Baseball (Japan).mra
new file mode 100644
index 00000000..83b09553
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Super Champion Baseball (Japan).mra
@@ -0,0 +1,68 @@
+
+ Super Champion Baseball (J)
+ sbasebalj
+ alpha68k
+ 1989
+ Alpha Denshi Co.
+ US
+ 8-Way
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 02 3A
+
+
+
+
+
+
+ FF
+
+
+
+ FF
+
+ FF
+
+ FF
+
+ FF
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Time Soldiers (US Rev 3).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Time Soldiers (US Rev 3).mra
new file mode 100644
index 00000000..9def3971
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/Time Soldiers (US Rev 3).mra
@@ -0,0 +1,83 @@
+
+ Time Soldiers (US Rev 3)
+ timesold
+ alpha68k
+ 0249
+ 1987
+ Alpha Denshi Co.
+ US
+ Rotary
+ vertical (cw)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 86 01
+
+
+
+
+
+
+
+
+
+
+ FF
+
+
+
+ FF
+
+ FF
+
+ FF
+
+
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/meta/WIP/Super Champion Baseball (US).mra b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/WIP/Super Champion Baseball (US).mra
new file mode 100644
index 00000000..20ebe36c
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/meta/WIP/Super Champion Baseball (US).mra
@@ -0,0 +1,68 @@
+
+ Super Champion Baseball (US)
+ sbasebal
+ alpha68k
+ 1989
+ Alpha Denshi Co.
+ US
+ 8-Way
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 03 3A
+
+
+
+
+
+
+ FF
+
+
+
+ FF
+
+ FF
+
+ FF
+
+ FF
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv
new file mode 100644
index 00000000..331f8484
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k.sv
@@ -0,0 +1,1263 @@
+//============================================================================
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+// more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+`default_nettype none
+
+module Alpha68k
+(
+ input pll_locked,
+ input clk_sys, // 72 MHz
+ input reset,
+ input [3:0] pcb,
+ input [7:0] brd,
+
+ input flip_in,
+ output flipped,
+
+ input [7:0] p1,
+ input [7:0] p2,
+ input [7:0] dsw_m68k,
+ input [7:0] dsw_sp85,
+ input coin_a,
+ input coin_b,
+ input [11:0] rotary1,
+ input [11:0] rotary2,
+
+ output hbl,
+ output vbl,
+ output hsync,
+ output vsync,
+ output [7:0] r,
+ output [7:0] g,
+ output [7:0] b,
+
+ output [15:0] audio_l,
+ output [15:0] audio_r,
+
+ input [3:0] hs_offset,
+ input [3:0] vs_offset,
+ input [3:0] hs_width,
+ input [3:0] vs_width,
+
+ input rom_download,
+ input [23:0] ioctl_addr,
+ input ioctl_wr,
+ input [7:0] ioctl_dout,
+
+ output [12:0] SDRAM_A,
+ output [1:0] SDRAM_BA,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nCS,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nWE
+);
+
+`include "defs.v"
+
+assign m68k_a[0] = 0;
+
+wire flip = flip_in ^ scr_flip;
+assign flipped = flip;
+
+//-- board config 6 bits
+// 00 = II
+// 01 = III
+// 11 = V
+//mcu id 00 = don't care
+// 01 = 0x8814
+// 10 = 0x8512
+// 11 = 0x8713
+//coin 0 = 0x2222 / 1 = 0x2423
+//invert 0 = input not inverted / 1 = inverted
+wire [1:0] board_rev = brd[5:4];
+wire [1:0] mcu_type = brd[3:2];
+wire coin_type = brd[1];
+wire invert_in = brd[0];
+
+localparam CLKSYS=72;
+
+reg [15:0] clk_fx68_count;
+reg [5:0] clk6_count;
+reg [7:0] clk358_count;
+reg [5:0] clk3_count;
+reg [23:0] clk_io_count;
+
+reg clk3_en;
+reg clk358_en;
+reg clk4_en_p, clk4_en_n;
+reg clk6_en_p, clk6_en_n;
+reg clk_fx68_en_p, clk_fx68_en_n;
+reg clk_io_en;
+always @(posedge clk_sys) begin
+ if (reset) begin
+ clk3_count <= 0;
+ clk358_count <= 0;
+ clk_fx68_count <= 0;
+ clk_io_count <= 0;
+ clk358_en <= 0;
+ {clk6_en_p, clk6_en_n} <= 0;
+ {clk_fx68_en_p, clk_fx68_en_n} <= 0;
+ clk_io_en <= 0;
+ end else begin
+ clk3_count <= clk3_count + 1'd1;
+ if (clk3_count == 23) begin
+ clk3_count <= 0;
+ end
+ clk3_en <= clk3_count == 0;
+
+ // M=9 / N=181
+ clk358_en <= 0;
+ if ( clk358_count > 180 ) begin
+ clk358_en <= 1;
+ clk358_count <= clk358_count - 8'd171;
+ end else begin
+ clk358_count <= clk358_count + 8'd9;
+ end
+
+ clk6_count <= clk6_count + 1'd1;
+ if (clk6_count == 11) clk6_count <= 0;
+ clk6_en_p <= clk6_count == 0;
+ clk6_en_n <= clk6_count == 5;
+
+ if ( board_rev == 3 ) begin
+ // 10 MHz
+ clk_fx68_en_p <= 0;
+ clk_fx68_count <= clk_fx68_count + 8'd10;
+ if ( (clk_fx68_count + 8'd10) >= 72 ) begin
+ clk_fx68_en_p <= 1 ;
+ clk_fx68_count <= clk_fx68_count - (8'd72 - 8'd10);
+ end
+ clk_fx68_en_n <= clk_fx68_en_p;
+ end else begin
+ // 9MHZ
+ clk_fx68_en_p <= clk_fx68_count == 0;
+ clk_fx68_en_n <= clk_fx68_count == 4;
+ clk_fx68_count <= clk_fx68_count + 1'd1;
+ if ( clk_fx68_count == 7 ) begin
+ clk_fx68_count <= 0;
+ end
+ end
+
+ clk_io_en <= clk_io_count == 0;
+ clk_io_count <= clk_io_count + 1'd1;
+ if ( clk_io_count == (pcb == GOLDMEDL ? 720000 : 4_666_234) ) begin // 100 Hz/15.4 Hz
+ clk_io_count <= 0;
+ end
+ end
+end
+
+wire [8:0] hc;
+wire [8:0] vc;
+wire [8:0] hcflip = !flip ? hc[8:0] : { hc[8], ~hc[7:0] };
+wire [8:0] vcflip = !flip ? vc : {vc[8], ~vc[7:0]};
+
+video_timing video_timing (
+ .clk(clk_sys),
+ .clk_pix(clk6_en_p),
+ .hc(hc),
+ .vc(vc),
+ .hs_offset(hs_offset),
+ .vs_offset(vs_offset),
+ .hs_width(hs_width),
+ .vs_width(vs_width),
+ .hbl_shift(board_rev == 3),
+ .hbl(hbl),
+ .vbl(vbl),
+ .hsync(hsync),
+ .vsync(vsync)
+);
+
+// foreground layer
+wire [9:0] fg_tile = { hcflip[7:3], vcflip[7:3] };
+assign fg_ram_addr = { fg_tile, hc[0] };
+reg [4:0] fg_colour, fg_colour_d;
+wire [8:0] fg_x = hcflip;
+wire [8:0] fg_y = vcflip;
+reg [15:0] fg_ram_dout0, fg_ram_dout1;
+reg [15:0] fg_pix_data;
+reg [8:0] fg;
+
+always @(posedge clk_sys) begin
+ if (clk6_en_p) begin
+ if (hc[0])
+ fg_ram_dout1 <= fg_ram_dout;
+ else
+ fg_ram_dout0 <= fg_ram_dout;
+
+ if ( board_rev == 3 ) begin
+ if (fg_x[0] == ~flip) begin
+ fg_rom_addr <= { tile_bank[2:0], fg_ram_dout0[7:0], ~fg_x[2], fg_x[1], fg_y[2:0] } ;
+ fg_colour <= fg_ram_dout0[15:12];
+ fg_pix_data <= fg_rom_addr[1] ? fg_rom_data[31:16] : fg_rom_data[15:0];
+ fg_colour <= fg_ram_dout1[4:0];
+ fg_colour_d <= fg_colour;
+ end
+ case ( fg_x[0] )
+ 0: fg <= { fg_colour, ~fg_rom_addr[0] ? fg_pix_data[11: 8] : fg_pix_data[3:0] };
+ 1: fg <= { fg_colour, ~fg_rom_addr[0] ? fg_pix_data[15:12] : fg_pix_data[7:4] };
+ endcase
+ end
+ else
+ begin
+ if (fg_x[1:0] == ({2{flip}} ^ 2'b11)) begin
+ fg_rom_addr <= { tile_bank[6:4], fg_ram_dout0[7:0], ~fg_x[2], fg_y[2:0], 1'b0 };
+ fg_pix_data <= fg_rom_addr[1] ? fg_rom_data[31:16] : fg_rom_data[15:0];
+ fg_colour <= fg_ram_dout1[4:0];
+ fg_colour_d <= fg_colour;
+ end
+ case ( fg_x[1:0] )
+ 0: fg <= { fg_colour_d, fg_pix_data[12], fg_pix_data[8], fg_pix_data[4], fg_pix_data[0] };
+ 1: fg <= { fg_colour_d, fg_pix_data[13], fg_pix_data[9], fg_pix_data[5], fg_pix_data[1] };
+ 2: fg <= { fg_colour_d, fg_pix_data[14], fg_pix_data[10], fg_pix_data[6], fg_pix_data[2] };
+ 3: fg <= { fg_colour_d, fg_pix_data[15], fg_pix_data[11], fg_pix_data[7], fg_pix_data[3] };
+ endcase
+ end
+ end
+end
+
+// sprite rendering into dual line buffers
+reg [4:0] sprite_state;
+reg [31:0] spr_pix_data;
+
+wire [8:0] sp_y = vcflip + (flip ? -1'd1 : 1'd1);
+
+reg [7:0] sprite_colour;
+reg [14:0] sprite_tile_num;
+reg sprite_flip_x;
+reg sprite_flip_y;
+reg [1:0] sprite_group;
+reg [4:0] sprite_col;
+reg [7:0] sprite_col_x;
+reg [15:0] sprite_col_y;
+reg [8:0] sprite_col_idx;
+reg [8:0] spr_x_pos;
+reg [3:0] spr_x_ofs;
+reg [1:0] sprite_layer;
+
+wire [3:0] spr_pen = { spr_pix_data[ 8 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]],
+ spr_pix_data[ 0 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]],
+ spr_pix_data[24 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]],
+ spr_pix_data[16 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]] } ;
+
+always @ (posedge clk_sys) begin
+ if ( reset == 1 ) begin
+ sprite_state <= 0;
+ end else begin
+ // sprites. -- need 3 sprite layers
+ spr_buf_w <= 0;
+ if ( sprite_state == 0 && hc == 0 ) begin
+ // init
+ sprite_state <= 22;
+ sprite_layer <= 0;
+ spr_x_pos <= 0;
+ end else if ( sprite_state == 22 ) begin
+ // start
+ case ( sprite_layer )
+ 0: begin
+ sprite_group <= 1;
+ sprite_col <= 31;
+ end
+ 1: begin
+ sprite_group <= 2;
+ sprite_col <= 0;
+ end
+ 2: begin
+ sprite_group <= 3;
+ sprite_col <= 0;
+ end
+ 3: begin
+ sprite_group <= 1;
+ sprite_col <= 0;
+ end
+ endcase
+ sprite_state <= 1;
+ end else if ( sprite_state == 1 ) begin
+ // setup x/y read
+ sprite_ram_addr <= { sprite_col, 3'b0, sprite_group };
+ sprite_state <= 2;
+ end else if ( sprite_state == 2 ) begin
+ sprite_state <= 3;
+ end else if ( sprite_state == 3 ) begin
+ sprite_col_x <= sprite_ram_dout[7:0];
+ sprite_col_y <= sprite_ram_dout[23:8];
+ if ( sprite_layer == 0 ) begin
+ if ( flip == 0 ) begin
+ sprite_col_y <= sprite_ram_dout[23:8] - 1'd1;
+ end else begin
+ sprite_col_y <= sprite_ram_dout[23:8] + 1'd1;
+ end
+ end
+ sprite_state <= 5;
+ end else if ( sprite_state == 5 ) begin
+ // tile ofset from the top of the column
+ sprite_col_idx <= sp_y + sprite_col_y[8:0] ;
+ sprite_state <= 6;
+ end else if ( sprite_state == 6 ) begin
+ // setup sprite tile index/colour read
+ sprite_ram_addr <= { sprite_group[1:0], sprite_col[4:0], sprite_col_idx[8:4] };
+ sprite_state <= 7;
+ end else if ( sprite_state == 7 ) begin
+ sprite_state <= 8;
+ end else if ( sprite_state == 8 ) begin
+ if ( board_rev == 3 ) begin
+ sprite_colour <= sprite_ram_dout[7:0] ; // 0xff
+ end else begin
+ sprite_colour <= sprite_ram_dout[6:0] ; // 0x7f
+ end
+ if ( pcb == SKYADV || pcb == SKYADVU ) begin
+ sprite_flip_x <= 1'b0;
+ sprite_flip_y <= sprite_ram_dout[23] ;
+ sprite_tile_num <= sprite_ram_dout[22:8] ;
+ end else if ( pcb == GANGWARS ) begin
+ sprite_flip_x <= sprite_ram_dout[23];
+ sprite_flip_y <= 1'b0; // 0x8000
+ sprite_tile_num <= sprite_ram_dout[22:8] ;
+ end else begin
+ sprite_flip_x <= sprite_ram_dout[22] ;
+ sprite_flip_y <= sprite_ram_dout[23] ;
+ sprite_tile_num <= sprite_ram_dout[21:8] ;
+ end
+ spr_x_ofs <= 0;
+ spr_x_pos <= { sprite_col_x[7:0], sprite_col_y[15] } ;
+ sprite_state <= 10;
+ end else if ( sprite_state == 10 ) begin
+ sprite_rom_addr <= { sprite_tile_num, ~sprite_flip_x, sprite_flip_y ? ~sprite_col_idx[3:0] : sprite_col_idx[3:0] };
+
+ sprite_rom_req <= ~sprite_rom_req;
+ sprite_state <= 11;
+ end else if ( sprite_state == 11 ) begin
+ // wait for sprite bitmap data
+ if ( sprite_rom_req == sprite_rom_ack ) begin
+ // prefetch pix 8-15 from rom
+ if (spr_x_ofs == 0) begin
+ sprite_rom_addr[4] <= ~sprite_rom_addr[4];
+ sprite_rom_req <= ~sprite_rom_req;
+ end
+ spr_pix_data <= sprite_rom_data;
+ sprite_state <= 12 ;
+ end
+ end else if ( sprite_state == 12 ) begin
+ spr_buf_addr_w <= { vc[0], spr_x_pos };
+
+ spr_buf_w <= | spr_pen ; // don't write if 0 - transparent
+
+ spr_buf_din <= { sprite_colour, spr_pen };
+
+ if ( spr_x_ofs < 15 ) begin
+ spr_x_ofs <= spr_x_ofs + 1'd1;
+ spr_x_pos <= spr_x_pos + 1'd1;
+
+ // the second 8 pixel needs another rom read
+ if ( spr_x_ofs == 7 ) begin
+ if (sprite_rom_req == sprite_rom_ack)
+ spr_pix_data <= sprite_rom_data;
+ else
+ sprite_state <= 11;
+ end
+
+ end else begin
+ if ( sprite_col < 30 || (sprite_col < 31 && sprite_layer < 3) ) begin
+ sprite_col <= sprite_col + 1'd1;
+ sprite_state <= 1;
+ end else begin
+ if ( sprite_layer < 3 ) begin
+ sprite_layer <= sprite_layer + 1'd1;
+ sprite_state <= 22;
+ end else begin
+ sprite_state <= 0;
+ end
+ end
+ end
+ end
+ end
+end
+wire [7:0] spr_offs = board_rev == 3 ? 8'd4 : 8'd8;
+wire [8:0] spr_pos = (flip ? spr_offs : -spr_offs) + hcflip;
+assign spr_buf_addr_r = { ~vc[0], spr_pos };
+reg [11:0] sp;
+always @ (posedge clk_sys) if (clk6_en_p) sp <= spr_buf_dout[11:0];
+
+// final color mix
+wire [11:0] pen = ( { fg[8], fg[3:0] } == 0 ) ? sp[11:0] : { 3'b0, fg[7:0] }; // fg[8] == 1 means tile is opaque
+
+// resistor dac 220, 470, 1k, 2.2k, 3.9k / has 8.2k pulldown for dimming (2nd block of 16)
+wire [7:0] dac_weight[0:63] = '{8'd0,8'd13,8'd22,8'd34,8'd46,8'd57,8'd65,8'd75,8'd91,8'd100,8'd107,8'd116,8'd126,8'd134,8'd140,8'd148,
+ 8'd168,8'd175,8'd180,8'd187,8'd194,8'd200,8'd205,8'd211,8'd220,8'd226,8'd230,8'd235,8'd241,8'd246,8'd250,8'd255,
+ // dim
+ 8'd0, 8'd7,8'd17,8'd28,8'd41,8'd52,8'd60,8'd71,8'd87,8'd96,8'd103,8'd112,8'd122,8'd130,8'd136,8'd144,
+ 8'd165,8'd172,8'd177,8'd184,8'd191,8'd197,8'd202,8'd208,8'd218,8'd223,8'd227,8'd233,8'd239,8'd244,8'd248,8'd253};
+always @ (posedge clk_sys) begin
+ if (clk6_en_p) begin
+ if ( pen[3:0] == 0 ) begin
+ if ( board_rev == 3 ) begin
+ tile_pal_addr <= 12'hfff ; // background pen
+ end else begin
+ tile_pal_addr <= 12'h7ff ; // background pen
+ end
+ end else begin
+ tile_pal_addr <= pen[11:0] ;
+ end
+ r <= dac_weight[r_pal];
+ g <= dac_weight[g_pal];
+ b <= dac_weight[b_pal];
+ end
+end
+
+/// 68k cpu
+
+reg scr_flip ;
+reg [2:0] tile_offset;
+
+assign m68k_dtack_n = m68k_rom_cs ? !m68k_rom_valid :
+ m68k_rom_2_cs ? !m68k_rom_valid :
+ m68k_ram_cs ? !m68k_ram_dtack :
+ 1'b0;
+
+assign m68k_din = m68k_rom_cs ? m68k_rom_data :
+ m68k_ram_cs ? m68k_ram_dout :
+ m68k_rom_2_cs ? m68k_rom_data :
+ // high byte of even addressed sprite ram not connected. pull high.
+ (m68k_spr_cs & !m68k_a[1]) ? {8'hff, m68k_sprite_dout[7:0]} :
+ (m68k_spr_cs & m68k_a[1]) ? {m68k_sprite_dout[23:8]} :
+ m68k_fg_ram_cs ? m68k_fg_ram_dout :
+ m68k_pal_cs ? m68k_pal_dout :
+ input_p1_cs ? {16{invert_in}} ^ { p2, p1 } :
+ m68k_dsw_cs ? { rotary1[7:0], invert_in ? ~dsw_m68k[7:0] : dsw_m68k[7:0] } :
+ m68k_sp85_cs ? 16'h0 :
+ m68k_rotary2_cs ? { rotary2[7:0], 8'h0 } :
+ m68k_rotary_msb_cs ? { rotary2[11:8], rotary1[11:8], 8'h0 } :
+ 16'h0000;
+
+reg [7:0] tile_bank;
+reg [1:0] vbl_sr;
+reg [1:0] hbl_sr;
+
+reg [7:0] credits;
+reg [3:0] coin_count;
+reg coin_latch;
+
+// Coin tables for games with MCU id 2222
+
+// Time Soldiers, Sky Soldiers
+reg [7:0] coin_ratio_a_II [0:7] = '{ 8'h01, 8'h02, 8'h03, 8'h04, 8'h05, 8'h06, 8'h13, 8'h22 }; // (#coins-1) / credits
+reg [7:0] coin_ratio_b_II [0:7] = '{ 8'h01, 8'h11, 8'h21, 8'h31, 8'h41, 8'h51, 8'h61, 8'h71 }; // (#coins-1) / credits
+
+// Sky Adventure
+reg [7:0] coin_ratio_a_V [0:7] = '{ 8'h01, 8'h05, 8'h03, 8'h13, 8'h02, 8'h06, 8'h04, 8'h22 }; // (#coins-1) / credits
+reg [7:0] coin_ratio_b_V [0:7] = '{ 8'h01, 8'h41, 8'h21, 8'h61, 8'h11, 8'h51, 8'h31, 8'h71 }; // (#coins-1) / credits
+
+wire [7:0] coin_ratio_a = (board_rev != 3) ? coin_ratio_a_II[~dsw_sp85[2:0]] : coin_ratio_a_V[~dsw_sp85[3:1]];
+wire [7:0] coin_ratio_b = (board_rev != 3) ? coin_ratio_b_II[~dsw_sp85[2:0]] : coin_ratio_b_V[~dsw_sp85[3:1]];
+
+reg [12:0] mcu_addr;
+reg [7:0] mcu_din;
+reg [7:0] mcu_dout;
+reg mcu_wh;
+reg mcu_wl;
+
+reg mcu_busy;
+reg mcu_2nd_write;
+reg [12:0] mcu_2nd_addr;
+reg [7:0] mcu_2nd_din;
+reg mcu_2nd_wh;
+reg mcu_2nd_wl;
+
+always @ (posedge clk_sys) begin
+
+ if ( reset == 1 ) begin
+ scr_flip <= 0;
+
+ m68k_ipl0_n <= 1 ;
+ m68k_ipl1_n <= 1 ;
+
+ m68k_latch <= 0;
+ tile_bank <= 0;
+
+ mcu_addr <= 0;
+ mcu_din <= 0 ;
+ mcu_wh <= 0;
+ mcu_wl <= 0;
+
+ z80_nmi_n <= 1 ;
+ z80_bank <= 0;
+
+ credits <= 0;
+ coin_latch <= 0;
+ mcu_2nd_write <= 0;
+ mcu_2nd_wl <= 0;
+ mcu_2nd_wh <= 0;
+ mcu_busy <= 0;
+ end else begin
+ // vblank handling
+ vbl_sr <= { vbl_sr[0], vbl };
+ if ( vbl_sr == 2'b01 ) begin // rising edge
+ // 68k vbl interrupt
+ m68k_ipl0_n <= 0;
+ end
+
+ // mcu interrupt handling
+ hbl_sr <= { hbl_sr[0], clk_io_en };
+ if ( hbl_sr == 2'b01 ) begin // rising edge
+ // 68k mcu interrupt
+ m68k_ipl1_n <= 0;
+ end
+ if ( vbl_int_clr_cs == 1 ) begin
+ m68k_ipl0_n <= 1;
+ end
+
+ if ( cpu_int_clr_cs == 1 ) begin
+ m68k_ipl1_n <= 1;
+ end
+
+ if (m68k_mcu_dtack) begin
+ mcu_wh <= 0;
+ mcu_wl <= 0;
+ end
+ if (m68k_rw) begin
+ // mcu addresses are word
+ if ( m68k_sp85_cs == 1 ) begin
+ if ( mcu_busy == 0 ) begin
+ mcu_busy <= 1;
+ if ( m68k_a[8:1] == 8'h00 ) begin
+ mcu_addr <= m68k_a[13:1];
+ mcu_din <= dsw_sp85[7:0] ;
+ mcu_wl <= 1;
+ end else if ( m68k_a[8:1] == 8'h22 ) begin
+ mcu_addr <= m68k_a[13:1];
+ mcu_din <= credits ;
+ credits <= 0;
+ mcu_wl <= 1;
+ end else if ( m68k_a[8:1] == 8'h29 ) begin
+
+ // coins
+ if ( { coin_b, coin_a } == 0 )
+ coin_latch <= 0;
+
+ if ( coin_latch == 0 && {coin_b, coin_a} != 0 ) begin
+ coin_latch <= 1;
+ // set coin id
+ if ( coin_type == 1 ) begin
+ if ( coin_a == 1 ) begin
+ mcu_din <= 8'h23 ;
+ end else begin
+ mcu_din <= 8'h24 ;
+ end
+ end else begin
+ mcu_din <= 8'h22 ;
+ // only games with coin id 22 needs a coin counter
+ if ( coin_a == 1 ) begin
+ // calc before or after invert?
+ if ( coin_ratio_a[7:4] == coin_count ) begin
+ credits <= coin_ratio_a[3:0];
+ coin_count <= 0;
+ end else begin
+ coin_count <= coin_count + 1'd1;
+ end
+ end if ( coin_b == 1 ) begin
+ if ( coin_ratio_b[7:4] == coin_count ) begin
+ credits <= coin_ratio_b[3:0];
+ coin_count <= 0;
+ end else begin
+ coin_count <= coin_count + 1'd1;
+ end
+ end
+
+ // clear for sky adv
+ mcu_2nd_write <= 1;
+ mcu_2nd_addr <= m68k_a[13:1] - 3'd7 ;
+ mcu_2nd_din <= 0 ;
+ mcu_2nd_wl <= 1;
+ end
+ mcu_addr <= m68k_a[13:1];
+ mcu_wl <= 1;
+ end else begin
+ mcu_addr <= m68k_a[13:1];
+ mcu_din <= pcb == GOLDMEDL ? 8'h21 : 8'h00;
+ mcu_wl <= 1;
+ end
+
+ // if gang wars trigger writing the dip value to ram
+ if ( pcb == GANGWARS ) begin
+ mcu_2nd_write <= 1;
+ mcu_2nd_addr <= 13'h0163 ;
+ mcu_2nd_din <= dsw_sp85[7:0] ;
+ mcu_2nd_wh <= 1;
+ end
+ end else if ( m68k_a[8:1] == 8'hfe ) begin
+ // mcu id hign - gang wars 8512
+ mcu_addr <= m68k_a[13:1];
+ mcu_wl <= 0;
+ if ( mcu_type == 2'b01 ) begin
+ mcu_din <= 8'h88 ;
+ mcu_wl <= 1;
+ end else if ( mcu_type == 2'b10 ) begin
+ mcu_din <= 8'h85 ;
+ mcu_wl <= 1;
+ end else if ( mcu_type == 2'b11 ) begin
+ mcu_din <= 8'h87 ;
+ mcu_wl <= 1;
+ end
+ end else if ( m68k_a[8:1] == 8'hff ) begin
+ // mcu id low
+ mcu_addr <= m68k_a[13:1];
+ mcu_wl <= 0;
+ if ( mcu_type == 2'b01 ) begin
+ mcu_din <= 8'h14 ;
+ mcu_wl <= 1;
+ end else if ( mcu_type == 2'b10 ) begin
+ mcu_din <= 8'h12 ;
+ mcu_wl <= 1;
+ end else if ( mcu_type == 2'b11 ) begin
+ mcu_din <= 8'h13 ;
+ mcu_wl <= 1;
+ end
+ end
+ end
+ end else begin
+ mcu_busy <= 0;
+ end
+
+ if ( !mcu_wl & !mcu_wh & mcu_2nd_write & !m68k_mcu_dtack ) begin
+ mcu_addr <= mcu_2nd_addr;
+ mcu_din <= mcu_2nd_din ;
+ mcu_wl <= mcu_2nd_wl;
+ mcu_wh <= mcu_2nd_wh;
+
+ mcu_2nd_write <= 0;
+ mcu_2nd_wl <= 0;
+ mcu_2nd_wh <= 0;
+ end
+
+ end else begin
+ // writes
+ if ( m68k_sp85_cs == 1 ) begin
+ if ( m68k_lds_n == 0 && m68k_a[8:1] == 8'h2d ) scr_flip <= m68k_dout[0];
+ end
+
+ if ( m68k_latch_cs == 1 ) begin
+ // text tile banking
+ if ( m68k_uds_n == 0 && board_rev == 3) begin // UDS 0x80000 only Rev V
+ tile_bank <= m68k_dout[11:8] ;
+ end
+ if ( m68k_lds_n == 0 ) begin // LDS 0x80001
+ m68k_latch <= m68k_dout[7:0];
+ end
+ end
+
+ if ( m68k_lds_n == 0 && m68k_dsw_cs == 1 ) begin // LDS 0xc00xx
+ if ( board_rev != 3 ) begin
+ tile_bank[m68k_a[5:3]] <= m68k_a[6] ; //
+ end
+ end
+ end
+
+ if ( z80_wr_n == 0 ) begin
+
+ // DAC
+ if ( z80_dac_cs == 1 ) begin
+ dac <= z80_dout ;
+ end
+
+ if ( z80_latch_clr_cs == 1 ) begin
+ m68k_latch <= 0 ;
+ end
+
+ if ( z80_bank_set_cs == 1 ) begin
+ z80_bank <= z80_dout[4:0];
+ end
+ end
+ // ym2203 can disable z80 nmi by writting 1 to bit 0 of portA
+ // if enabled, nmi is triggered by falling edge of bit 0 vertical line count
+ // /NMI is negative edge triggered
+ z80_nmi_n <= (~vc[0]) | ym2203_IOA[0] | ~ym2203_OE;
+ end
+end
+
+wire m68k_rom_cs;
+wire m68k_rom_2_cs;
+wire m68k_ram_cs;
+wire m68k_pal_cs;
+wire m68k_spr_cs;
+wire m68k_fg_ram_cs;
+wire m68k_spr_flip_cs;
+wire input_p1_cs;
+wire m68k_rotary2_cs;
+wire m68k_rotary_msb_cs;
+wire m68k_dsw_cs;
+wire irq_z80_cs;
+wire m68k_latch_cs;
+wire z80_latch_read_cs;
+wire vbl_int_clr_cs;
+wire cpu_int_clr_cs;
+wire watchdog_clr_cs;
+wire m68k_sp85_cs;
+wire m68k_ipl0_ack;
+wire m68k_ipl1_ack;
+
+wire z80_rom_cs;
+wire z80_ram_cs;
+wire z80_banked_cs;
+
+wire z80_latch_cs;
+wire z80_latch_clr_cs;
+wire z80_dac_cs;
+wire z80_ym2413_cs;
+wire z80_ym2203_cs;
+wire z80_bank_set_cs;
+
+chip_select cs (
+ .pcb(pcb),
+
+ // 68k bus
+ .m68k_a(m68k_a),
+ .m68k_as_n(m68k_as_n),
+ .m68k_rw(m68k_rw),
+ .m68k_uds_n(m68k_uds_n),
+ .m68k_lds_n(m68k_lds_n),
+
+ .z80_addr(z80_addr),
+ .MREQ_n(MREQ_n),
+ .IORQ_n(IORQ_n),
+ .M1_n(M1_n),
+ .RFSH_n(RFSH_n),
+ .RD_n( z80_rd_n ),
+ .WR_n( z80_wr_n ),
+
+ // 68k chip selects
+ .m68k_rom_cs,
+ .m68k_rom_2_cs,
+ .m68k_ram_cs,
+ .m68k_spr_cs,
+ .m68k_sp85_cs,
+ .m68k_fg_ram_cs,
+ .m68k_pal_cs,
+
+ .m68k_rotary2_cs,
+ .m68k_rotary_msb_cs,
+
+ .input_p1_cs,
+ .m68k_dsw_cs,
+
+ // interrupt clear & watchdog
+ .vbl_int_clr_cs,
+ .cpu_int_clr_cs,
+ .watchdog_clr_cs,
+
+ .m68k_latch_cs, // write commands to z80 from 68k
+
+ // z80
+
+ .z80_rom_cs,
+ .z80_ram_cs,
+ .z80_banked_cs,
+
+ .z80_latch_cs,
+ .z80_latch_clr_cs,
+ .z80_dac_cs,
+ .z80_ym2413_cs,
+ .z80_ym2203_cs,
+ .z80_bank_set_cs
+
+);
+
+reg [7:0] m68k_latch;
+
+// CPU outputs
+wire m68k_rw ; // Read = 1, Write = 0
+wire m68k_as_n ; // Address strobe
+wire m68k_lds_n ; // Lower byte strobe
+wire m68k_uds_n ; // Upper byte strobe
+wire m68k_E;
+wire [2:0] m68k_fc ; // Processor state
+wire m68k_reset_n_o ; // Reset output signal
+wire m68k_halted_n ; // Halt output
+
+// CPU busses
+wire [15:0] m68k_dout ;
+wire [23:0] m68k_a /* synthesis keep */ ;
+reg [15:0] m68k_din ;
+//assign m68k_a[0] = 1'b0;
+
+// CPU inputs
+reg m68k_dtack_n;
+reg m68k_ipl0_n;
+reg m68k_ipl1_n;
+
+wire m68k_vpa_n = ~int_ack;
+
+wire int_ack = !m68k_as_n && m68k_fc == 3'b111;
+
+fx68k fx68k (
+ // input
+ .clk(clk_sys),
+ .enPhi1(clk_fx68_en_p),
+ .enPhi2(clk_fx68_en_n),
+
+ .extReset(reset),
+ .pwrUp(reset),
+
+ // output
+ .eRWn(m68k_rw),
+ .ASn(m68k_as_n),
+ .LDSn(m68k_lds_n),
+ .UDSn(m68k_uds_n),
+ .E(),
+ .VMAn(),
+ .FC0(m68k_fc[0]),
+ .FC1(m68k_fc[1]),
+ .FC2(m68k_fc[2]),
+ .BGn(),
+ .oRESETn(m68k_reset_n_o),
+ .oHALTEDn(m68k_halted_n),
+
+ // input
+ .VPAn( m68k_vpa_n ),
+ .DTACKn( m68k_dtack_n ),
+ .BERRn(1'b1),
+ .BRn(1'b1),
+ .BGACKn(1'b1),
+
+ .IPL0n(m68k_ipl0_n),
+ .IPL1n(m68k_ipl1_n),
+ .IPL2n(1'b1),
+
+ // busses
+ .iEdb(m68k_din),
+ .oEdb(m68k_dout),
+ .eab(m68k_a[23:1])
+);
+
+// z80 audio
+wire [7:0] z80_rom_data;
+wire [7:0] z80_ram_data;
+wire [7:0] z80_banked_data;
+
+wire [15:0] z80_addr;
+reg [7:0] z80_din;
+wire [7:0] z80_dout;
+
+wire z80_wr_n;
+wire z80_rd_n;
+wire z80_wait_n;
+reg z80_nmi_n;
+
+wire IORQ_n;
+wire MREQ_n;
+wire M1_n;
+wire RFSH_n;
+
+T80pa z80 (
+ .RESET_n ( ~reset ),
+ .CLK ( clk_sys ),
+ .CEN_p ( clk6_en_p ),
+ .CEN_n ( clk6_en_n ),
+ .WAIT_n ( z80_wait_n ), // z80_wait_n
+ .INT_n ( 1'b1 ),
+ .NMI_n ( z80_nmi_n ),
+ .BUSRQ_n ( 1'b1 ),
+ .RD_n ( z80_rd_n ),
+ .WR_n ( z80_wr_n ),
+ .A ( z80_addr ),
+ .DI ( z80_din ),
+ .DO ( z80_dout ),
+ // unused
+ .DIRSET ( 1'b0 ),
+ .DIR ( 212'b0 ),
+ .OUT0 ( 1'b0 ),
+ .RFSH_n ( RFSH_n ),
+ .IORQ_n ( IORQ_n ),
+ .M1_n ( M1_n ), // for interrupt ack
+ .BUSAK_n (),
+ .HALT_n ( 1'b1 ),
+ .MREQ_n ( MREQ_n ),
+ .Stop (),
+ .REG ()
+);
+
+assign z80_wait_n = (z80_rom_cs | z80_banked_cs) ? z80_rom_valid : 1'b1;
+
+assign z80_din = z80_rom_cs ? z80_rom_data :
+ z80_ram_cs ? z80_ram_data :
+ z80_latch_cs ? m68k_latch :
+ z80_banked_cs ? z80_rom_data : 8'hFF;
+
+// sound ic write enable
+
+reg signed [15:0] opll_sample;
+reg signed [15:0] opn_sample;
+
+wire opll_sample_clk;
+wire opn_sample_clk;
+
+// OPLL (3.578 MHZ)
+jt2413 ym2413 (
+ .rst(reset),
+ .clk(clk_sys),
+ .cen(clk358_en),
+ .din( z80_dout ),
+ .addr( z80_addr[0] ),
+ .cs_n(~z80_ym2413_cs),
+ .wr_n(0), //~opll_wr
+
+ .snd(opll_sample),
+ .sample(opll_sample_clk)
+);
+
+wire [7:0] ym2203_IOA;
+wire ym2203_OE;
+
+// OPN (3 MHZ)
+jt03 ym2203 (
+ .rst(reset),
+ .clk(clk_sys), // clock in is signal 1H (6MHz/2)
+ .cen(clk3_en),
+ .din( z80_dout ),
+ .addr( z80_addr[0] ),
+ .cs_n( ~z80_ym2203_cs ),
+ .wr_n( z80_wr_n ),
+ .IOA_out( ym2203_IOA ),
+ .IOA_oe( ym2203_OE ),
+
+ .snd(opn_sample)
+);
+
+reg signed [7:0] dac ;
+wire signed [15:0] dac_sample = { ~dac[7], dac[6:0], 8'h0 } ;
+
+// mix audio
+assign audio_l = ( ( opn_sample + opll_sample + dac_sample ) * 5 ) >>> 4; // ( 3*5 ) / 16th
+assign audio_r = ( ( opn_sample + opll_sample + dac_sample ) * 5 ) >>> 4; // ( 3*5 ) / 16th
+
+wire [23:0] m68k_sprite_dout;
+wire [15:0] m68k_pal_dout;
+
+reg [12:0] sprite_ram_addr;
+wire [23:0] sprite_ram_dout;
+
+// sprite RAM
+// 3x8k
+dual_port_ram #(.LEN(8192)) sprite_ram_00 (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[14:2] ),
+ .wren_a ( !m68k_rw & m68k_spr_cs & !m68k_a[1] & !m68k_lds_n),
+ .data_a ( m68k_dout[7:0] ),
+ .q_a ( m68k_sprite_dout[7:0] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( sprite_ram_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( sprite_ram_dout[7:0] )
+ );
+
+dual_port_ram #(.LEN(8192)) sprite_ram_10 (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[14:2] ),
+ .wren_a ( !m68k_rw & m68k_spr_cs & m68k_a[1] & !m68k_lds_n),
+ .data_a ( m68k_dout[7:0] ),
+ .q_a ( m68k_sprite_dout[15:8] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( sprite_ram_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( sprite_ram_dout[15:8] )
+ );
+
+dual_port_ram #(.LEN(8192)) sprite_ram_11 (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[14:2] ),
+ .wren_a ( !m68k_rw & m68k_spr_cs & m68k_a[1] & !m68k_uds_n),
+ .data_a ( m68k_dout[15:8] ),
+ .q_a ( m68k_sprite_dout[23:16] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( sprite_ram_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( sprite_ram_dout[23:16] )
+ );
+
+wire [10:0] fg_ram_addr;
+wire [15:0] fg_ram_dout;
+
+wire [15:0] m68k_fg_ram_dout;
+
+// foreground high
+/*
+dual_port_ram #(.LEN(2048)) ram_fg_h (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[11:1] ),
+ .wren_a ( !m68k_rw & m68k_fg_ram_cs & !m68k_uds_n ), // can write to m68k_fg_mirror_cs but not read
+ .data_a ( m68k_dout[15:8] ),
+ .q_a ( m68k_fg_ram_dout[15:8] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( fg_ram_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( fg_ram_dout[15:8] )
+
+ );
+*/
+// foreground low
+dual_port_ram #(.LEN(2048)) ram_fg_l (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[11:1] ),
+ .wren_a ( !m68k_rw & m68k_fg_ram_cs/* & !(m68k_lds_n & m68k_uds_n)*/ ),
+ .data_a ( m68k_dout[7:0] ),
+ .q_a ( m68k_fg_ram_dout[7:0] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( fg_ram_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( fg_ram_dout[7:0] )
+ );
+
+
+wire [5:0] r_pal = { tile_pal_dout[15], tile_pal_dout[11:8] , tile_pal_dout[14] };
+wire [5:0] g_pal = { tile_pal_dout[15], tile_pal_dout[7:4] , tile_pal_dout[13] };
+wire [5:0] b_pal = { tile_pal_dout[15], tile_pal_dout[3:0] , tile_pal_dout[12] };
+
+reg [11:0] tile_pal_addr;
+wire [15:0] tile_pal_dout;
+wire [15:0] tile_pal_din;
+
+// tile palette high
+dual_port_ram #(.LEN(4096)) tile_pal_h (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[12:1] ),
+ .wren_a ( !m68k_rw & m68k_pal_cs & !m68k_uds_n ),
+ .data_a ( m68k_dout[15:8] ),
+ .q_a ( m68k_pal_dout[15:8] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( tile_pal_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( tile_pal_dout[15:8] )
+ );
+
+// tile palette low
+dual_port_ram #(.LEN(4096)) tile_pal_l (
+ .clock_a ( clk_sys ),
+ .address_a ( m68k_a[12:1] ),
+ .wren_a ( !m68k_rw & m68k_pal_cs & !m68k_lds_n ),
+ .data_a ( m68k_dout[7:0] ),
+ .q_a ( m68k_pal_dout[7:0] ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( tile_pal_addr ),
+ .wren_b ( 1'b0 ),
+ .data_b ( ),
+ .q_b( tile_pal_dout[7:0] )
+ );
+
+// z80 ram
+dual_port_ram #(.LEN(2048)) z80_ram (
+ .clock_b ( clk_sys ),
+ .address_b ( z80_addr[10:0] ),
+ .wren_b ( z80_ram_cs & ~z80_wr_n ),
+ .data_b ( z80_dout ),
+ .q_b ( z80_ram_data )
+ );
+
+wire [15:0] spr_pal_dout ;
+wire [15:0] m68k_spr_pal_dout ;
+
+wire [9:0] spr_buf_addr_r;
+reg [9:0] spr_buf_addr_w;
+reg spr_buf_w;
+reg [15:0] spr_buf_din;
+wire [15:0] spr_buf_dout;
+
+dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) spr_buffer_ram (
+ .clock_a ( clk_sys ),
+ .address_a ( spr_buf_addr_w ),
+ .wren_a ( spr_buf_w ),
+ .data_a ( spr_buf_din ),
+ .q_a ( ),
+
+ .clock_b ( clk_sys ),
+ .address_b ( spr_buf_addr_r ),
+ .data_b ( 16'd0 ),
+ .wren_b ( clk6_en_p ),
+ .q_b ( spr_buf_dout )
+ );
+
+// M68K RAM CONTROL
+reg m68k_ram_req;
+wire m68k_ram_ack;
+reg [21:1] m68k_ram_a;
+reg m68k_ram_we;
+wire [15:0] m68k_ram_dout;
+reg [15:0] m68k_ram_din;
+reg [1:0] m68k_ram_ds;
+reg m68k_ram_dtack;
+reg m68k_mcu_dtack;
+
+localparam M68K_RAM_IDLE = 0;
+localparam M68K_RAM_M68K = 1;
+localparam M68K_RAM_MCU = 2;
+
+reg [1:0] m68k_ram_state;
+
+always @ (posedge clk_sys) begin
+ if ( reset == 1 ) begin
+ m68k_ram_dtack <= 0;
+ m68k_mcu_dtack <= 0;
+ m68k_ram_state <= M68K_RAM_IDLE;
+ end else begin
+ if (!m68k_ram_cs) m68k_ram_dtack <= 0;
+ if (!mcu_wl & !mcu_wh) m68k_mcu_dtack <= 0;
+
+ case (m68k_ram_state)
+ M68K_RAM_IDLE:
+ if ((mcu_wl | mcu_wh) & !m68k_mcu_dtack) begin
+ m68k_ram_a <= mcu_addr;
+ m68k_ram_din <= {mcu_din, mcu_din};
+ m68k_ram_we <= 1;
+ m68k_ram_ds <= {mcu_wh, mcu_wl};
+ m68k_ram_req <= !m68k_ram_req;
+ m68k_ram_state <= M68K_RAM_MCU;
+ end
+ else
+ if (m68k_ram_cs & !m68k_ram_dtack) begin
+ m68k_ram_a <= m68k_a[13:1];
+ m68k_ram_din <= m68k_dout;
+ m68k_ram_we <= !m68k_rw;
+ m68k_ram_ds <= {!m68k_uds_n, !m68k_lds_n};
+ m68k_ram_req <= !m68k_ram_req;
+ m68k_ram_state <= M68K_RAM_M68K;
+ end
+
+ M68K_RAM_M68K:
+ if (m68k_ram_req == m68k_ram_ack) begin
+ m68k_ram_dtack <= 1;
+ m68k_ram_state <= M68K_RAM_IDLE;
+ end
+ M68K_RAM_MCU:
+ if (m68k_ram_req == m68k_ram_ack) begin
+ m68k_mcu_dtack <= 1;
+ m68k_ram_state <= M68K_RAM_IDLE;
+ end
+ endcase
+ end
+end
+
+reg port1_req, port2_req;
+always @(posedge clk_sys) begin
+ if (rom_download) begin
+ if (ioctl_wr) begin
+ port1_req <= ~port1_req;
+ port2_req <= ~port2_req;
+ end
+ end
+end
+
+wire [15:0] m68k_rom_data;
+wire m68k_rom_valid;
+
+wire [15:0] cpu2_do;
+reg [4:0] z80_bank;
+wire [18:0] z80_rom_addr = z80_banked_cs ? { z80_bank[4:0], z80_addr[13:0] } : z80_addr[14:0];
+assign z80_rom_data = z80_addr[0] ? cpu2_do[7:0] : cpu2_do[15:8];
+wire z80_rom_valid;
+
+reg [19:0] sprite_rom_addr;
+wire [31:0] sprite_rom_data;
+reg sprite_rom_req;
+wire sprite_rom_ack;
+
+reg [15:0] fg_rom_addr;
+wire [31:0] fg_rom_data;
+
+sdram #(CLKSYS) sdram
+(
+ .*,
+ .init_n ( pll_locked ),
+ .clk ( clk_sys ),
+
+ // Bank 0-1 ops
+ .port1_a ( ioctl_addr[23:1] ),
+ .port1_req ( port1_req ),
+ .port1_ack (),
+ .port1_we ( rom_download ),
+ .port1_ds ( {~ioctl_addr[0], ioctl_addr[0]} ),
+ .port1_d ( {ioctl_dout, ioctl_dout} ),
+ .port1_q (),
+
+ // M68K
+ .cpu1_rom_addr ( {m68k_rom_2_cs, m68k_a[17:1]} ), //ioctl_addr >= 24'h000000) & (ioctl_addr < 24'h040000
+ .cpu1_rom_cs ( m68k_rom_cs | m68k_rom_2_cs ),
+ .cpu1_rom_q ( m68k_rom_data ),
+ .cpu1_rom_valid( m68k_rom_valid),
+
+ .cpu1_ram_req ( m68k_ram_req ),
+ .cpu1_ram_ack ( m68k_ram_ack ),
+ .cpu1_ram_addr ( m68k_ram_a ),
+ .cpu1_ram_we ( m68k_ram_we ),
+ .cpu1_ram_d ( m68k_ram_din ),
+ .cpu1_ram_q ( m68k_ram_dout ),
+ .cpu1_ram_ds ( m68k_ram_ds ),
+
+ // Audio Z80
+ .cpu2_addr ( {1'b1, z80_rom_addr[18:1]} ), // (ioctl_addr >= 24'h080000) & (ioctl_addr < 24'h100000) ;
+ .cpu2_rom_cs ( z80_rom_cs | z80_banked_cs ),
+ .cpu2_q ( cpu2_do ),
+ .cpu2_valid ( z80_rom_valid ),
+
+ .cpu3_addr ( ),
+ .cpu3_rom_cs ( ),
+ .cpu3_q ( ),
+ .cpu3_valid ( ),
+
+ .cpu4_addr ( ),
+ .cpu4_rom_cs ( ),
+ .cpu4_q ( ),
+ .cpu4_valid ( ),
+
+ // Bank 2-3 ops
+ .port2_a ( ioctl_addr[23:1] ),
+ .port2_req ( port2_req ),
+ .port2_ack ( ),
+ .port2_we ( rom_download ),
+ .port2_ds ( {~ioctl_addr[0], ioctl_addr[0]} ),
+ .port2_d ( {ioctl_dout, ioctl_dout} ),
+ .port2_q ( ),
+
+ .gfx1_addr ( {5'h10, fg_rom_addr[15:2]} ), // (ioctl_addr >= 24'h100000) & (ioctl_addr < 24'h110000) ;
+ .gfx1_q ( fg_rom_data ),
+
+ .gfx2_addr ( ),
+ .gfx2_q ( ),
+
+ .gfx3_addr ( ),
+ .gfx3_q ( ),
+
+ .sp_addr ( 20'h80000 + sprite_rom_addr ), // (ioctl_addr >= 24'h200000) & (ioctl_addr < 24'h480000)
+ .sp_req ( sprite_rom_req ),
+ .sp_ack ( sprite_rom_ack ),
+ .sp_q ( sprite_rom_data )
+);
+
+endmodule
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv
new file mode 100644
index 00000000..4cfeb4e8
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/Alpha68k_MiST.sv
@@ -0,0 +1,345 @@
+//============================================================================
+// Alpha Densi M68000 HW top-level for MiST
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+// more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module Alpha68k_MiST
+(
+ output LED,
+ output [5:0] VGA_R,
+ output [5:0] VGA_G,
+ output [5:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output AUDIO_L,
+ output AUDIO_R,
+ input SPI_SCK,
+ inout SPI_DO,
+ input SPI_DI,
+ input SPI_SS2,
+ input SPI_SS3,
+ input SPI_SS4,
+ input CONF_DATA0,
+ input CLOCK_27,
+
+ output [12:0] SDRAM_A,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nWE,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nCS,
+ output [1:0] SDRAM_BA,
+ output SDRAM_CLK,
+ output SDRAM_CKE
+);
+
+`include "build_id.v"
+`include "defs.v"
+
+`define CORE_NAME "GANGWARS"
+
+localparam CONF_STR = {
+ `CORE_NAME, ";;",
+ "O2,Rotate Controls,Off,On;",
+ "O34,Scanlines,Off,25%,50%,75%;",
+ "O5,Blending,Off,On;",
+ "O6,Joystick Swap,Off,On;",
+ "DIP;",
+ "T0,Reset;",
+ "V,v1.20.",`BUILD_DATE
+};
+
+wire rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire blend = status[5];
+wire joyswap = status[6];
+
+wire [7:0] dsw1 = status[23:16];
+wire [7:0] dsw2 = status[31:24];
+reg [7:0] dsw_m68k, dsw_sp85;
+reg [7:0] p1, p2;
+wire flipped;
+wire key_service = m_fire1[4];
+wire key_test = m_fire1[3];
+reg [3:0] pcb;
+reg [7:0] brd;
+reg tate;
+
+always @(*) begin
+
+ if ( pcb == GOLDMEDL ) begin
+ // special case gold medal
+ // controls are active low
+ p1 = {m_one_player, m_three_players, m_fire2[1], m_fire1[1], m_fire2[2], m_fire2[0], m_fire1[2], m_fire1[0]} ;
+ p2 = {m_two_players, m_four_players, m_fire4[1], m_fire3[1], m_fire4[2], m_fire4[0], m_fire3[2], m_fire3[0]} ;
+
+ dsw_m68k = ~{dsw1[7:2], ~key_test, ~key_service};
+ dsw_sp85 = dsw2[7:0];
+ end else begin
+ // non inverted - active low
+ p1 = ~{ m_one_player, m_fire1[2:0], m_right1, m_left1, m_down1, m_up1};
+ p2 = ~{ m_two_players, m_fire2[2:0], m_right2, m_left2, m_down2, m_up2};
+
+ dsw_m68k = {dsw1[7:2], ~key_test, ~key_service};
+ dsw_sp85 = dsw2[7:0];
+ end
+
+end
+
+wire rot1_cw = m_fire1[7] | m_right1B | m_up1B; // R
+wire rot1_ccw = m_fire1[6] | m_left1B | m_down1B; // L
+wire rot2_cw = m_fire2[7] | m_right2B | m_up2B; // R
+wire rot2_ccw = m_fire2[6] | m_left2B | m_down2B; // L
+
+wire [11:0] rotary1;
+wire [11:0] rotary2;
+
+rotary_ctrl rot1(clk_72, reset, rot1_cw, rot1_ccw, rotary1);
+rotary_ctrl rot2(clk_72, reset, rot2_cw, rot2_ccw, rotary2);
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_72;
+assign SDRAM_CKE = 1;
+
+wire clk_72;
+wire pll_locked;
+pll_mist pll(
+ .inclk0(CLOCK_27),
+ .c0(clk_72),
+ .locked(pll_locked)
+ );
+
+// reset generation
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_72) begin
+ reg ioctl_downlD;
+ ioctl_downlD <= ioctl_downl;
+
+ if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+ reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
+ if (ioctl_wr) begin
+ if (ioctl_addr == 0) begin
+ tate <= ioctl_dout[7];
+ pcb <= ioctl_dout[3:0];
+ end
+ else if (ioctl_addr == 1) brd <= ioctl_dout;
+ end
+end
+
+// ARM connection
+wire [63:0] status;
+wire [1:0] buttons;
+wire [1:0] switches;
+wire [31:0] joystick_0;
+wire [31:0] joystick_1;
+wire scandoublerD;
+wire ypbpr;
+wire no_csync;
+wire key_strobe;
+wire key_pressed;
+wire [7:0] key_code;
+wire [6:0] core_mod;
+
+user_io #(
+ .STRLEN($size(CONF_STR)>>3),
+ .ROM_DIRECT_UPLOAD(1))
+user_io(
+ .clk_sys (clk_72 ),
+ .conf_str (CONF_STR ),
+ .SPI_CLK (SPI_SCK ),
+ .SPI_SS_IO (CONF_DATA0 ),
+ .SPI_MISO (SPI_DO ),
+ .SPI_MOSI (SPI_DI ),
+ .buttons (buttons ),
+ .switches (switches ),
+ .scandoubler_disable (scandoublerD ),
+ .ypbpr (ypbpr ),
+ .no_csync (no_csync ),
+ .core_mod (core_mod ),
+ .key_strobe (key_strobe ),
+ .key_pressed (key_pressed ),
+ .key_code (key_code ),
+ .joystick_0 (joystick_0 ),
+ .joystick_1 (joystick_1 ),
+ .status (status )
+ );
+
+wire ioctl_downl;
+wire [7:0] ioctl_index;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+
+data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
+ .clk_sys ( clk_72 ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS2 ( SPI_SS2 ),
+ .SPI_SS4 ( SPI_SS4 ),
+ .SPI_DI ( SPI_DI ),
+ .SPI_DO ( SPI_DO ),
+ .ioctl_download( ioctl_downl ),
+ .ioctl_index ( ioctl_index ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_addr ( ioctl_addr ),
+ .ioctl_dout ( ioctl_dout )
+);
+
+wire [15:0] laudio, raudio;
+wire hs, vs;
+wire blankn = ~(hb | vb);
+wire hb, vb;
+wire [7:0] r,b,g;
+
+Alpha68k Alpha68k
+(
+ .pll_locked ( pll_locked ),
+ .clk_sys ( clk_72 ),
+ .reset ( reset ),
+ .pcb ( pcb ),
+ .brd ( brd ),
+
+ .flip_in ( 1'b0 ), // usually a DIP can be used to flip screen
+ .flipped ( flipped ),
+ .p1 ( p1 ),
+ .p2 ( p2 ),
+ .dsw_m68k ( dsw_m68k ),
+ .dsw_sp85 ( dsw_sp85 ),
+ .coin_a ( m_coin1 ),
+ .coin_b ( m_coin2 ),
+ .rotary1 ( rotary1 ),
+ .rotary2 ( rotary2 ),
+
+ .hbl ( hb ),
+ .vbl ( vb ),
+ .hsync ( hs ),
+ .vsync ( vs ),
+ .r ( r ),
+ .g ( g ),
+ .b ( b ),
+
+ .audio_l ( laudio ),
+ .audio_r ( raudio ),
+
+ .rom_download ( ioctl_downl),
+ .ioctl_addr ( ioctl_addr - 2'd2 ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_dout ( ioctl_dout ),
+
+ .SDRAM_A ( SDRAM_A ),
+ .SDRAM_BA ( SDRAM_BA ),
+ .SDRAM_DQ ( SDRAM_DQ ),
+ .SDRAM_DQML ( SDRAM_DQML ),
+ .SDRAM_DQMH ( SDRAM_DQMH ),
+ .SDRAM_nCS ( SDRAM_nCS ),
+ .SDRAM_nCAS ( SDRAM_nCAS ),
+ .SDRAM_nRAS ( SDRAM_nRAS ),
+ .SDRAM_nWE ( SDRAM_nWE )
+);
+
+mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
+ .clk_sys(clk_72),
+ .SPI_SCK(SPI_SCK),
+ .SPI_SS3(SPI_SS3),
+ .SPI_DI(SPI_DI),
+ .R(blankn ? r[7:2] : 6'd0),
+ .G(blankn ? g[7:2] : 6'd0),
+ .B(blankn ? b[7:2] : 6'd0),
+ .HSync(~hs),
+ .VSync(~vs),
+ .VGA_R(VGA_R),
+ .VGA_G(VGA_G),
+ .VGA_B(VGA_B),
+ .VGA_VS(VGA_VS),
+ .VGA_HS(VGA_HS),
+ .no_csync(no_csync),
+ .rotate({~flipped,rotate}),
+ .ce_divider(3'd5), // pix clock = 72/6
+ .blend(blend),
+ .scandoubler_disable(scandoublerD),
+ .scanlines(scanlines),
+ .ypbpr(ypbpr)
+ );
+
+dac #(16) dacl(
+ .clk_i(clk_72),
+ .res_n_i(1),
+ .dac_i({~laudio[15], laudio[14:0]}),
+ .dac_o(AUDIO_L)
+ );
+
+dac #(16) dacr(
+ .clk_i(clk_72),
+ .res_n_i(1),
+ .dac_i({~raudio[15], raudio[14:0]}),
+ .dac_o(AUDIO_R)
+ );
+
+// Common inputs
+wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
+wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
+wire m_up3, m_down3, m_left3, m_right3, m_up3B, m_down3B, m_left3B, m_right3B;
+wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4;
+
+arcade_inputs inputs (
+ .clk ( clk_72 ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( {~flipped, tate} ),
+ .joyswap ( joyswap ),
+ .oneplayer ( 1'b0 ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
+ .player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ),
+ .player3 ( {m_up3B, m_down3B, m_left3B, m_right3B, m_fire3, m_up3, m_down3, m_left3, m_right3} ),
+ .player4 ( {m_up4B, m_down4B, m_left4B, m_right4B, m_fire4, m_up4, m_down4, m_left4, m_right4} )
+);
+
+endmodule
+
+module rotary_ctrl
+(
+ input clk_sys,
+ input reset,
+ input cw,
+ input ccw,
+ output reg [11:0] rotary
+);
+
+reg cw_last, ccw_last;
+always @ (posedge clk_sys) begin
+ if (reset) begin
+ rotary <= 12'h1;
+ end else begin
+ cw_last <= cw;
+ ccw_last <= ccw;
+ if (cw & ~cw_last)
+ rotary <= { rotary[0], rotary[11:1] };
+
+ if (ccw & ~ccw_last)
+ rotary <= { rotary[10:0], rotary[11] };
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+ # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+ set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+ set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+ # Create a Verilog file for output
+ set outputFileName "rtl/build_id.v"
+ set outputFile [open $outputFileName "w"]
+
+ # Output the Verilog source
+ puts $outputFile "`define BUILD_DATE \"$buildDate\""
+ puts $outputFile "`define BUILD_TIME \"$buildTime\""
+ close $outputFile
+
+ # Send confirmation message to the Messages window
+ post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+ post_message "Date: $buildDate"
+ post_message "Time: $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v
new file mode 100644
index 00000000..2cb88660
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/chip_select.v
@@ -0,0 +1,285 @@
+//
+
+module chip_select
+(
+ input [3:0] pcb,
+
+
+ input [23:0] m68k_a,
+ input m68k_as_n,
+ input m68k_rw,
+ input m68k_uds_n,
+ input m68k_lds_n,
+
+ input [15:0] z80_addr,
+ input MREQ_n,
+ input IORQ_n,
+ input RD_n,
+ input WR_n,
+ input M1_n,
+ input RFSH_n,
+
+ // M68K selects
+ output reg m68k_rom_cs,
+ output reg m68k_rom_2_cs,
+ output reg m68k_ram_cs,
+ output reg m68k_spr_cs,
+ output reg m68k_pal_cs,
+ output reg m68k_fg_ram_cs,
+ output reg m68k_sp85_cs,
+
+ output reg input_p1_cs,
+ output reg m68k_dsw_cs,
+
+ output reg m68k_rotary2_cs,
+ output reg m68k_rotary_msb_cs,
+
+ output reg vbl_int_clr_cs,
+ output reg cpu_int_clr_cs,
+ output reg watchdog_clr_cs,
+
+ output reg m68k_latch_cs,
+
+ // Z80 selects
+ output reg z80_rom_cs,
+ output reg z80_ram_cs,
+
+ output reg z80_latch_cs,
+ output reg z80_latch_clr_cs,
+ output reg z80_dac_cs,
+ output reg z80_ym2413_cs, // OPN YM2413
+ output reg z80_ym2203_cs, // OPLL YM2203
+ output reg z80_bank_set_cs,
+ output reg z80_banked_cs
+);
+
+`include "defs.v"
+
+function m68k_cs;
+ input [23:0] start_address;
+ input [23:0] end_address;
+begin
+ m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & !(m68k_uds_n & m68k_lds_n);
+end
+endfunction
+
+function z80_mem_cs;
+ input [15:0] base_address;
+ input [7:0] width;
+begin
+ z80_mem_cs = ( z80_addr >> width == base_address >> width ) & !MREQ_n & RFSH_n;
+end
+endfunction
+
+function z80_io_cs;
+ input [7:0] address_lo;
+begin
+ z80_io_cs = ( z80_addr[7:0] == address_lo ) && !IORQ_n ;
+end
+endfunction
+
+//-- board config 6 bits
+// 00 = II
+// 01 = III
+// 11 = V
+//mcu id 00 = don't care
+// 01 = 0x8814
+// 10 = 0x8512
+// 11 = 0x8713
+//coin 0 = 0x2222 / 1 = 0x2423
+//invert 0 = input not inverted / 1 = inverted
+
+always @ (*) begin
+ // Memory mapping based on PCB type
+ m68k_rom_cs = 0;
+ m68k_ram_cs = 0;
+ m68k_latch_cs = 0;
+ input_p1_cs = 0;
+ m68k_dsw_cs = 0;
+ m68k_fg_ram_cs = 0;
+ m68k_spr_cs = 0;
+ m68k_rotary2_cs = 0;
+ m68k_rotary_msb_cs = 0;
+ m68k_sp85_cs = 0;
+ m68k_pal_cs = 0;
+ m68k_rom_2_cs = 0;
+ cpu_int_clr_cs = 0;
+ vbl_int_clr_cs = 0;
+ watchdog_clr_cs = 0;
+ z80_rom_cs = 0;
+ z80_ram_cs = 0;
+ z80_banked_cs = 0;
+ z80_latch_cs = 0;
+ z80_latch_clr_cs = 0;
+ z80_dac_cs = 0;
+ z80_ym2413_cs = 0;
+ z80_ym2203_cs = 0;
+ z80_bank_set_cs = 0;
+
+ // reset microcontroller interrupt
+ cpu_int_clr_cs = m68k_cs( 24'h0d8000, 24'h0dffff ) & m68k_rw; // tst.b $d8000.l
+
+ // reset vblank interrupt
+ vbl_int_clr_cs = m68k_cs( 24'h0e0000, 24'h0e7fff ) & m68k_rw; // tst.b $e0000.l
+
+ case (pcb)
+ SKYADV, SKYADVU, GANGWARS, SBASEBALJ, SBASEBAL: begin
+ m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
+
+ m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ;
+
+ m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
+
+ input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
+
+ m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) ;
+
+ m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
+
+ m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
+
+ m68k_rotary2_cs = 0 ;
+
+ m68k_rotary_msb_cs = 0;
+
+ m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
+
+ m68k_pal_cs = m68k_cs( 24'h400000, 24'h401fff ) ;
+
+ m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
+
+ // reset watchdog interrupt ( implement? )
+ watchdog_clr_cs = m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
+
+ z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
+ z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
+ z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
+
+ // read latch. latch is active on all i/o reads
+ z80_latch_cs = (!IORQ_n) && (!RD_n) ;
+
+ z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
+
+ // only the lower 4 bits are used to decode port
+ // 0x08-0x09
+ z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
+
+ // 0x0a-0x0b
+ z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0c-0x0d
+ z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0E-0x0F
+ z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
+ end
+
+ GOLDMEDL: begin
+ m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
+
+ m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff ) ;
+
+ m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
+
+ input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
+
+
+ m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c007f ) ;
+
+ m68k_rotary2_cs = 0 ;
+
+ m68k_rotary_msb_cs = 0;
+
+ m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
+
+ m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
+
+ m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
+
+ m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
+
+ m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
+
+ // reset watchdog interrupt ( implement? )
+ watchdog_clr_cs = 0; //m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
+
+ z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
+ z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
+ z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
+
+ // read latch. latch is active on all i/o reads
+ z80_latch_cs = (!IORQ_n) && (!RD_n) ;
+
+ z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
+
+ // only the lower 4 bits are used to decode port
+ // 0x08-0x09
+ z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
+
+ // 0x0a-0x0b
+ z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0c-0x0d
+ z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0E-0x0F
+ z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
+ end
+
+ SKYSOLDR, TIMESOLD, BATFIELD: begin
+ m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
+
+ m68k_ram_cs = m68k_cs( 24'h040000, 24'h040fff ) ;
+
+ m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
+
+ input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
+
+ // dsw / CN1 rotary / Ver II text banking
+ m68k_dsw_cs = m68k_cs( 24'h0c0000, 24'h0c007f ) ;
+
+ m68k_rotary2_cs = m68k_cs( 24'h0c8000, 24'h0c8001 ) & m68k_rw;
+
+ m68k_rotary_msb_cs = m68k_cs( 24'h0d0000, 24'h0d0001 ) ;
+
+ m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) ;
+
+ m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
+
+ m68k_sp85_cs = m68k_cs( 24'h300000, 24'h303fff ) ;
+
+ m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
+
+ m68k_rom_2_cs = m68k_cs( 24'h800000, 24'h83ffff ) ;
+
+ // reset watchdog interrupt ( implement? )
+ watchdog_clr_cs = 0; //m68k_cs( 24'h0e8000, 24'h0effff ) ; // tst.b $e8000.l
+
+ z80_rom_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] < 16'h8000 );
+ z80_ram_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'h8000 && z80_addr[15:0] < 16'h8800 );
+ z80_banked_cs = ( MREQ_n == 0 && RFSH_n && z80_addr[15:0] >= 16'hc000 );
+
+ // read latch. latch is active on all i/o reads
+ z80_latch_cs = (!IORQ_n) && (!RD_n) ;
+
+ z80_latch_clr_cs = ( z80_addr[3:1] == 3'b000 ) && ( !IORQ_n ) && (!WR_n);
+
+ // only the lower 4 bits are used to decode port
+ // 0x08-0x09
+ z80_dac_cs = ( z80_addr[3:1] == 3'b100 ) && ( !IORQ_n ) && (!WR_n) ; // 8 bit DAC
+
+ // 0x0a-0x0b
+ z80_ym2413_cs = ( z80_addr[3:1] == 3'b101 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0c-0x0d
+ z80_ym2203_cs = ( z80_addr[3:1] == 3'b110 ) && ( !IORQ_n ) && (!WR_n);
+
+ // 0x0E-0x0F
+ z80_bank_set_cs = ( z80_addr[3:1] == 3'b111 ) && ( !IORQ_n ) && (!WR_n); // select latches z80 D[4:0]
+ end
+ default:;
+ endcase
+
+end
+
+endmodule
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v
new file mode 100644
index 00000000..0da9e70d
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/defs.v
@@ -0,0 +1,9 @@
+localparam SKYADV = 0;
+localparam GANGWARS = 1;
+localparam SBASEBALJ = 2;
+localparam SBASEBAL = 3;
+localparam SKYADVU = 4;
+localparam SKYSOLDR = 5;
+localparam TIMESOLD = 6;
+localparam GOLDMEDL = 7;
+localparam BATFIELD = 8;
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd
new file mode 100644
index 00000000..e47fb4b2
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/dual_port_ram.vhd
@@ -0,0 +1,117 @@
+-- __ __ __ __ __ __
+-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
+-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
+-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
+-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
+-- ______ ______ __ ______ ______ ______
+-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
+-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
+-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
+-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
+--
+-- https://joshbassett.info
+-- https://twitter.com/nullobject
+-- https://github.com/nullobject
+--
+-- Copyright (c) 2020 Josh Bassett
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in all
+-- copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+-- SOFTWARE.
+
+-- 2022-05-24 Changed to use word count instead of address width
+-- and renamed ports to match quartus IP naming
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+--use work.common.all;
+use work.math.all;
+
+library altera_mf;
+use altera_mf.altera_mf_components.all;
+
+entity dual_port_ram is
+ generic (
+ LEN : natural := 8192;
+ DATA_WIDTH : natural := 8
+ );
+ port (
+ -- port A
+ clock_a : in std_logic;
+ address_a : in unsigned(ilog2(LEN)-1 downto 0);
+ data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
+ q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ wren_a : in std_logic := '0';
+
+ -- port B
+ clock_b : in std_logic;
+ address_b : in unsigned(ilog2(LEN)-1 downto 0);
+ data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
+ q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ wren_b : in std_logic := '0'
+ );
+end dual_port_ram;
+
+architecture arch of dual_port_ram is
+
+begin
+ altsyncram_component : altsyncram
+ generic map (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ intended_device_family => "Cyclone V",
+ lpm_type => "altsyncram",
+ numwords_a => LEN,
+ numwords_b => LEN,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => "UNREGISTERED",
+ outdata_reg_b => "UNREGISTERED",
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ width_a => DATA_WIDTH,
+ width_b => DATA_WIDTH,
+ width_byteena_a => 1,
+ width_byteena_b => 1,
+ widthad_a => ilog2(LEN),
+ widthad_b => ilog2(LEN),
+ wrcontrol_wraddress_reg_b => "CLOCK1"
+ )
+ port map (
+ address_a => std_logic_vector(address_a),
+ address_b => std_logic_vector(address_b),
+ clock0 => clock_a,
+ clock1 => clock_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+
+
+end architecture arch;
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd
new file mode 100644
index 00000000..5d64d8c7
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/math.vhd
@@ -0,0 +1,72 @@
+-- __ __ __ __ __ __
+-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
+-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
+-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
+-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
+-- ______ ______ __ ______ ______ ______
+-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
+-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
+-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
+-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
+--
+-- https://joshbassett.info
+-- https://twitter.com/nullobject
+-- https://github.com/nullobject
+--
+-- Copyright (c) 2020 Josh Bassett
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in all
+-- copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+-- SOFTWARE.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+package math is
+ -- calculates the log2 of the given number
+ function ilog2(n : natural) return natural;
+
+ -- Masks the given range of bits for a vector.
+ --
+ -- Only the bits between the MSB and LSB (inclusive) will be kept, all other
+ -- bits will be masked out.
+ function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
+ function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
+end package math;
+
+package body math is
+ function ilog2(n : natural) return natural is
+ begin
+ return natural(ceil(log2(real(n))));
+ end ilog2;
+
+ function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
+ variable n : natural;
+ variable mask : std_logic_vector(data'length-1 downto 0);
+ begin
+ n := (2**(msb-lsb+1))-1;
+ mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
+ return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
+ end mask_bits;
+
+ function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
+ begin
+ return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
+ end mask_bits;
+end package body math;
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip
new file mode 100644
index 00000000..6182871f
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v
new file mode 100644
index 00000000..09a344d2
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/pll_mist.v
@@ -0,0 +1,309 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll_mist.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_mist (
+ inclk0,
+ c0,
+ locked);
+
+ input inclk0;
+ output c0;
+ output locked;
+
+ wire [4:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire locked = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 3,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 8,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 37037,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv
new file mode 100644
index 00000000..7e9eaa36
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/sdram.sv
@@ -0,0 +1,449 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+//
+// Copyright (c) 2013 Till Harbaum
+// Copyright (c) 2019-2022 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+
+module sdram (
+
+ // interface to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, // two byte masks
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+
+ // cpu/chipset interface
+ input init_n, // init signal after FPGA config to initialize RAM
+ input clk, // sdram clock
+
+ // 1st bank
+ input port1_req,
+ output reg port1_ack,
+ input port1_we,
+ input [23:1] port1_a,
+ input [1:0] port1_ds,
+ input [15:0] port1_d,
+ output reg [15:0] port1_q,
+
+ // cpu1 rom/ram
+ input [21:1] cpu1_rom_addr,
+ input cpu1_rom_cs,
+ output reg [15:0] cpu1_rom_q,
+ output reg cpu1_rom_valid,
+
+ input cpu1_ram_req,
+ output reg cpu1_ram_ack,
+ input [21:1] cpu1_ram_addr,
+ input cpu1_ram_we,
+ input [1:0] cpu1_ram_ds,
+ input [15:0] cpu1_ram_d,
+ output reg [15:0] cpu1_ram_q,
+
+ // cpu2 rom
+ input [21:1] cpu2_addr,
+ input cpu2_rom_cs,
+ output reg [15:0] cpu2_q,
+ output reg cpu2_valid,
+ // cpu3 rom
+ input [21:1] cpu3_addr,
+ input cpu3_rom_cs,
+ output reg [15:0] cpu3_q,
+ output reg cpu3_valid,
+ // cpu4 rom
+ input [21:1] cpu4_addr,
+ input cpu4_rom_cs,
+ output reg [15:0] cpu4_q,
+ output reg cpu4_valid,
+
+ // 2nd bank
+ input port2_req,
+ output reg port2_ack,
+ input port2_we,
+ input [23:1] port2_a,
+ input [1:0] port2_ds,
+ input [15:0] port2_d,
+ output reg [31:0] port2_q,
+
+ input [22:2] gfx1_addr,
+ output reg [31:0] gfx1_q,
+ input [22:2] gfx2_addr,
+ output reg [31:0] gfx2_q,
+ input [22:2] gfx3_addr,
+ output reg [31:0] gfx3_q,
+
+ input [22:2] sp_addr,
+ input sp_req,
+ output reg sp_ack,
+ output reg [31:0] sp_q
+);
+
+parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
+localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2/3 allowed
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 2 words burst, CL2
+cmd issued registered
+ 0 RAS0 cas1 - data0 read burst terminated
+ 1 ras0
+ 2 data1 returned
+ 3 CAS0 data1 returned
+ 4 RAS1 cas0
+ 5 ras1
+ 6 CAS1 data0 returned
+*/
+
+localparam STATE_RAS0 = 3'd0; // first state in cycle
+localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1 = 3'd3;
+localparam STATE_DS1b = 3'd0;
+localparam STATE_READ1b = 3'd4;
+localparam STATE_LAST = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+ t <= t + 1'd1;
+ if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+reg init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+ if(!init_n) begin
+ reset <= 5'h1f;
+ init <= 1'b1;
+ end else begin
+ if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+ init <= !(reset == 0);
+ end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [3:0] sd_cmd; // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE = sd_cmd[0];
+
+reg [24:1] addr_latch[3];
+reg [24:1] addr_latch_next[2];
+reg [21:1] addr_last[1:5];
+reg [22:2] addr_last2[5];
+reg [15:0] din_next;
+reg [15:0] din_latch[2];
+reg oe_next;
+reg [1:0] oe_latch;
+reg we_next;
+reg [1:0] we_latch;
+reg [1:0] ds_next;
+reg [1:0] ds[2];
+
+reg port1_state;
+reg port2_state;
+reg cpu1_ram_req_state;
+reg sp_state;
+
+localparam PORT_NONE = 3'd0;
+localparam PORT_CPU1_ROM = 3'd1;
+localparam PORT_CPU1_RAM = 3'd2;
+localparam PORT_CPU2 = 3'd3;
+localparam PORT_CPU3 = 3'd4;
+localparam PORT_CPU4 = 3'd5;
+localparam PORT_GFX1 = 3'd1;
+localparam PORT_GFX2 = 3'd2;
+localparam PORT_GFX3 = 3'd3;
+localparam PORT_SP = 3'd4;
+localparam PORT_REQ = 3'd6;
+
+reg [2:0] next_port[2];
+reg [2:0] port[2];
+
+reg refresh;
+reg [10:0] refresh_cnt;
+wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ ds_next = 2'b00;
+ { oe_next, we_next } = 2'b00;
+ din_next = 0;
+
+ if (refresh) begin
+ // nothing
+ end else if (port1_req ^ port1_state) begin
+ next_port[0] = PORT_REQ;
+ addr_latch_next[0] = { 1'b0, port1_a };
+ ds_next = port1_ds;
+ { oe_next, we_next } = { ~port1_we, port1_we };
+ din_next = port1_d;
+ end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin
+ next_port[0] = PORT_CPU2;
+ addr_latch_next[0] = { 3'd0, cpu2_addr };
+ ds_next = 2'b11;
+ { oe_next, we_next } = 2'b10;
+ end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin
+ next_port[0] = PORT_CPU1_ROM;
+ addr_latch_next[0] = { 3'd0, cpu1_rom_addr };
+ ds_next = 2'b11;
+ { oe_next, we_next } = 2'b10;
+ end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin
+ next_port[0] = PORT_CPU1_RAM;
+ addr_latch_next[0] = { 2'b01, 1'b1, cpu1_ram_addr };
+ ds_next = cpu1_ram_ds;
+ { oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we };
+ din_next = cpu1_ram_d;
+ end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin
+ next_port[0] = PORT_CPU3;
+ addr_latch_next[0] = { 3'd0, cpu3_addr };
+ ds_next = 2'b11;
+ { oe_next, we_next } = 2'b10;
+ end else if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) begin
+ next_port[0] = PORT_CPU4;
+ addr_latch_next[0] = { 3'd0, cpu4_addr };
+ ds_next = 2'b11;
+ { oe_next, we_next } = 2'b10;
+ end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+ if (port2_req ^ port2_state) begin
+ next_port[1] = PORT_REQ;
+ addr_latch_next[1] = { 1'b1, port2_a };
+ end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
+ next_port[1] = PORT_GFX1;
+ addr_latch_next[1] = { 2'b10, gfx1_addr, 1'b0 };
+ end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
+ next_port[1] = PORT_GFX2;
+ addr_latch_next[1] = { 2'b10, gfx2_addr, 1'b0 };
+ end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
+ next_port[1] = PORT_GFX3;
+ addr_latch_next[1] = { 2'b10, gfx3_addr, 1'b0 };
+ end else if (sp_req ^ sp_state) begin
+ next_port[1] = PORT_SP;
+ addr_latch_next[1] = { 2'b10, sp_addr, 1'b0 };
+ end else begin
+ next_port[1] = PORT_NONE;
+ addr_latch_next[1] = addr_latch[1];
+ end
+end
+
+always @(posedge clk) begin
+
+ // permanently latch ram data to reduce delays
+ sd_din <= SDRAM_DQ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+ sd_cmd <= CMD_NOP; // default: idle
+ refresh_cnt <= refresh_cnt + 1'd1;
+
+ if(init) begin
+ { cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0;
+ // initialization takes place at the end of the reset phase
+ if(t == STATE_RAS0) begin
+
+ if(reset == 15) begin
+ sd_cmd <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1'b1; // precharge all banks
+ end
+
+ if(reset == 10 || reset == 8) begin
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+
+ if(reset == 2) begin
+ sd_cmd <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ SDRAM_BA <= 2'b00;
+ end
+ end
+ end else begin
+ if (!cpu1_rom_cs) cpu1_rom_valid <= 0;
+ if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0;
+ if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0;
+ if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) cpu4_valid <= 0;
+
+ // RAS phase
+ // bank 0,1
+ if(t == STATE_RAS0) begin
+ addr_latch[0] <= addr_latch_next[0];
+ port[0] <= next_port[0];
+ { oe_latch[0], we_latch[0] } <= 2'b00;
+
+ if (next_port[0] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[0][22:10];
+ SDRAM_BA <= addr_latch_next[0][24:23];
+ end
+ addr_last[next_port[0]] <= addr_latch_next[0][21:1];
+ ds[0] <= ds_next;
+ { oe_latch[0], we_latch[0] } <= { oe_next, we_next };
+ din_latch[0] <= din_next;
+
+ if (next_port[0] == PORT_REQ) port1_state <= port1_req;
+ if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req;
+ end
+
+ // bank 2,3
+ if(t == STATE_RAS1) begin
+ refresh <= 1'b0;
+ addr_latch[1] <= addr_latch_next[1];
+ { oe_latch[1], we_latch[1] } <= 2'b00;
+ port[1] <= next_port[1];
+
+ if (next_port[1] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[1][22:10];
+ SDRAM_BA <= addr_latch_next[1][24:23];
+ addr_last2[next_port[1]] <= addr_latch_next[1][22:2];
+ if (next_port[1] == PORT_REQ) begin
+ { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+ ds[1] <= port2_ds;
+ din_latch[1] <= port2_d;
+ port2_state <= port2_req;
+ end else begin
+ { oe_latch[1], we_latch[1] } <= 2'b10;
+ ds[1] <= 2'b11;
+ end
+ end
+ if (next_port[1] == PORT_SP) sp_state <= sp_req;
+
+ if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+ refresh <= 1'b1;
+ refresh_cnt <= 0;
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+ end
+
+ // CAS phase
+ if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+ sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+ if (we_latch[0]) begin
+ SDRAM_DQ <= din_latch[0];
+ case(port[0])
+ PORT_REQ: port1_ack <= port1_req;
+ PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req;
+ default: ;
+ endcase;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[0][24:23];
+ end
+
+ if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+ sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+ if (we_latch[1]) begin
+ SDRAM_DQ <= din_latch[1];
+ port2_ack <= port2_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[1][24:23];
+ end
+
+ // Data returned
+ if(t == STATE_READ0 && oe_latch[0]) begin
+ case(port[0])
+ PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
+ PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end
+ PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end
+ PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
+ PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end
+ PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_READ1 && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ : port2_q[15:0] <= sd_din;
+ PORT_GFX1 : gfx1_q[15:0] <= sd_din;
+ PORT_GFX2 : gfx2_q[15:0] <= sd_din;
+ PORT_GFX3 : gfx3_q[15:0] <= sd_din;
+ PORT_SP : sp_q[15:0] <= sd_din;
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+ if(t == STATE_READ1b && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+ PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end
+ PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end
+ PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end
+ PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end
+ default: ;
+ endcase;
+ end
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v
new file mode 100644
index 00000000..0e846669
--- /dev/null
+++ b/Arcade_MiST/Alpha Densi M68000 Hardware/rtl/video_timing.v
@@ -0,0 +1,99 @@
+
+module video_timing
+(
+ input clk,
+ input clk_pix,
+ input reset,
+
+ input signed [3:0] hs_offset,
+ input signed [3:0] vs_offset,
+
+ input signed [3:0] hs_width,
+ input signed [3:0] vs_width,
+ input hbl_shift,
+
+ output [8:0] hc,
+ output [8:0] vc,
+
+ output reg hsync,
+ output reg vsync,
+
+ output reg hbl,
+ output reg vbl
+);
+
+wire [8:0] h_ofs = 0;
+wire [8:0] HBL_START = hbl_shift ? 9'd262 : 9'd266 ;
+wire [8:0] HBL_END = hbl_shift ? 9'd6 : 9'd10 ;
+wire [8:0] HS_START = HBL_START + 9'd41 + $signed(hs_offset);
+wire [8:0] HS_END = HBL_START + 9'd73 + $signed(hs_offset) + $signed(hs_width);
+wire [8:0] HTOTAL = 9'd383;
+
+wire [8:0] v_ofs = 0;
+wire [8:0] VBL_START = 9'd240 ;
+wire [8:0] VBL_END = 9'd16 ;
+wire [8:0] VS_START = VBL_START + 9'd13 + $signed(vs_offset);
+wire [8:0] VS_END = VBL_START + 9'd21 + $signed(vs_offset) + $signed(vs_width);
+wire [8:0] VTOTAL = 9'd263 ;
+
+
+reg [8:0] v;
+reg [8:0] h;
+
+assign vc = v - v_ofs;
+assign hc = h - h_ofs;
+
+always @ (posedge clk) begin
+ if (reset) begin
+ h <= 0;
+ v <= 0;
+
+ hbl <= 0;
+ vbl <= 0;
+
+ hsync <= 0;
+ vsync <= 0;
+ end else if ( clk_pix == 1 ) begin
+ // counter
+ if (h == HTOTAL) begin
+ h <= 0;
+ v <= v + 1'd1;
+
+ if ( v == VTOTAL ) begin
+ v <= 0;
+ end
+ end else begin
+ h <= h + 1'd1;
+ end
+
+ // h signals
+ if ( h == HBL_START ) begin
+ hbl <= 1;
+ end else if ( h == HBL_END ) begin
+ hbl <= 0;
+ end
+
+ // v signals
+ if ( v == VBL_START ) begin
+ vbl <= 1;
+ end else if ( v == VBL_END ) begin
+ vbl <= 0;
+ end
+
+ if ( v == (VS_START ) ) begin
+ vsync <= 1;
+ end else if ( v == (VS_END ) ) begin
+ vsync <= 0;
+ end
+
+ if ( h == (HS_START ) ) begin
+ hsync <= 1;
+ end else if ( h == (HS_END ) ) begin
+ hsync <= 0;
+ end
+ end
+
+end
+
+endmodule
+