From 9ee1248e0e474a7e5cbabdfcd35813f345494f6d Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 30 May 2019 22:48:46 +0200 Subject: [PATCH] Moon Patrol: add VHDL build_id script --- .../MoonPatrol_MIST/.gitignore | 1 + .../MoonPatrol_MIST/mpatrol.qsf | 1 + .../MoonPatrol_MIST/src/build_id.tcl | 19 ++++++++++--------- .../MoonPatrol_MIST/src/mpatrol.vhd | 6 ++++-- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore index 2fe317a8..964d90b5 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore @@ -1 +1,2 @@ +build_id.vhd Output/ diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf index 7e86a389..f595a1cd 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf @@ -237,4 +237,5 @@ set_global_assignment -name VERILOG_FILE src/osd.v set_global_assignment -name VERILOG_FILE src/user_io.v set_global_assignment -name VHDL_FILE src/sprite_array.vhd set_global_assignment -name VHDL_FILE src/Clock.vhd +set_global_assignment -name VHDL_FILE src/build_id.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl index c8c7096c..ff180c9b 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl @@ -1,35 +1,36 @@ # ================================================================================ # -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 +# Build ID VHDL Module Script # -# Generates a Verilog module that contains a timestamp, +# Generates a VHDL module that contains a timestamp, # from the current build. These values are available from the build_date, build_time, # physical_address, and host_name output ports of the build_id module in the build_id.v # Verilog source file. # # ================================================================================ -proc generateBuildID_Verilog {} { +proc generateBuildID_VHDL {} { # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) set buildDate [ clock format [ clock seconds ] -format %y%m%d ] set buildTime [ clock format [ clock seconds ] -format %H%M%S ] # Create a Verilog file for output - set outputFileName "src/build_id.v" + set outputFileName "src/build_id.vhd" set outputFile [open $outputFileName "w"] # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" + puts $outputFile "package build_id is" + puts $outputFile "constant BUILD_DATE : string := \"$buildDate\";" + puts $outputFile "constant BUILD_TIME : string := \"$buildTime\";" + puts $outputFile "end build_id;" close $outputFile # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Generated build identification VHDL module: [pwd]/$outputFileName" post_message "Date: $buildDate" post_message "Time: $buildTime" } # Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file +generateBuildID_VHDL \ No newline at end of file diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd index 9dc6e7c0..b5d12d04 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd @@ -7,6 +7,8 @@ library work; use work.pace_pkg.all; use work.video_controller_pkg.all; +use work.build_id.all; + entity mpatrol is port ( @@ -86,8 +88,8 @@ architecture SYN of mpatrol is "O7,Demo mode,Off,On;"& "O8,Sector selection,Off,On;"& "O9,Test mode,Off,On;"& - "T0,Reset;"; --- "V,v1.11.",`BUILD_DATE + "T0,Reset;"& + "V,v"&BUILD_DATE; -- convert string to std_logic_vector to be given to user_io function to_slv(s: string) return std_logic_vector is