diff --git a/Arcade_MiST/Zilec BluePrint/BluePrint.qsf b/Arcade_MiST/Zilec BluePrint/BluePrint.qsf
index 27fd8f65..67c3e935 100644
--- a/Arcade_MiST/Zilec BluePrint/BluePrint.qsf
+++ b/Arcade_MiST/Zilec BluePrint/BluePrint.qsf
@@ -18,7 +18,7 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 13:46:56 February 19, 2026
+# Date created = 02:58:09 February 23, 2026
#
# -------------------------------------------------------------------------- #
#
diff --git a/Arcade_MiST/Zilec BluePrint/BluePrint.sdc b/Arcade_MiST/Zilec BluePrint/BluePrint.sdc
index 53289e4c..3d1ebf62 100644
--- a/Arcade_MiST/Zilec BluePrint/BluePrint.sdc
+++ b/Arcade_MiST/Zilec BluePrint/BluePrint.sdc
@@ -41,13 +41,6 @@ set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [ge
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
-# SDRAM delays
-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
-
-set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
diff --git a/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Japan).mra b/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Japan).mra
index a60d4055..b7479aef 100644
--- a/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Japan).mra
+++ b/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Japan).mra
@@ -11,7 +11,7 @@
Zilec Electronics / Bally Midway
Maze
- blueprnt
+ blueprntj
blueprnt
0220
BluePrint
@@ -25,7 +25,7 @@
4-way
1
-
+ Run
@@ -44,9 +44,12 @@
+ FF // BluePrint Doesn't Use 6th Rom Slot
-
-
+
+ FF
+
+ FF
@@ -57,6 +60,16 @@
+
+
+
+ 01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
+ 00 00 01 00 00 40 00 00
+
+
+
+
+
20260213000000
diff --git a/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Midway).mra b/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Midway).mra
index 7fd1368f..7fccaf84 100644
--- a/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Midway).mra
+++ b/Arcade_MiST/Zilec BluePrint/meta/Blue Print (Midway).mra
@@ -25,7 +25,7 @@
4-way
1
-
+ Run
@@ -44,6 +44,7 @@
+ FF // BluePrint Doesn't Use 6th Rom Slot
@@ -57,6 +58,16 @@
+
+
+
+ 01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
+ 00 00 01 00 00 40 00 00
+
+
+
+
+
20260213000000
diff --git a/Arcade_MiST/Zilec BluePrint/meta/Grasspin (Jaleco).mra b/Arcade_MiST/Zilec BluePrint/meta/Grasspin (Jaleco).mra
new file mode 100644
index 00000000..fc4cdf1a
--- /dev/null
+++ b/Arcade_MiST/Zilec BluePrint/meta/Grasspin (Jaleco).mra
@@ -0,0 +1,67 @@
+
+ Grasspin (Zilec)
+ World
+ no
+ no
+
+
+
+
+ 1983
+ Zilec Electronics / Jaleco
+ Maze
+ grasspin
+ grasspin
+ 0220
+ BluePrint
+
+ 15kHz
+ vertical (ccw)
+ no
+ 2 (alternating)
+ 8-way
+
+ 2
+ Fire
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FF // Grasspin Doesn't Use 6th Rom Slot
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
+ 00 00 07 00 00 50 50 FD
+
+
+
+
+
+ 20260221000000
+
diff --git a/Arcade_MiST/Zilec BluePrint/meta/Saturn (Zilec).mra b/Arcade_MiST/Zilec BluePrint/meta/Saturn (Zilec).mra
new file mode 100644
index 00000000..89464fc0
--- /dev/null
+++ b/Arcade_MiST/Zilec BluePrint/meta/Saturn (Zilec).mra
@@ -0,0 +1,73 @@
+
+ Saturn (Zilec)
+ World
+ no
+ no
+
+
+
+
+ 1983
+ Zilec Electronics / Jaleco
+ Maze
+
+ saturn
+ blueprnt
+ 0220
+ BluePrint
+
+
+ 15kHz
+ vertical (ccw)
+ no
+
+ 2 (alternating)
+ 4-way
+
+ 2
+ Fire,Double Fire
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
+ 00 00 03 80 00 28 00 2D
+
+
+
+
+
+
+
+ 20260213000000
+
diff --git a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint.sv b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint.sv
index e73f7c67..5f7e3bd1 100644
--- a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint.sv
+++ b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint.sv
@@ -100,16 +100,15 @@ wire [4:0] r, g, b;
wire [ 3:0] hoffset, voffset;
assign { voffset, hoffset } = status[31:24];
+wire [7:0] p1_controls = {m_down, m_up, m_right, m_left, m_fireA, m_fireB, m_one_player, m_coin1};
+wire [7:0] p2_controls = {m_down2, m_up2, m_right2, m_left2, m_fire2A, m_fire2B, m_two_players, m_coin2};
+
// DIP SWITCHES
reg [7:0] dip_sw[8]; // Active-LOW
always @(posedge clk_sys) begin
if(ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3])
dip_sw[ioctl_addr[2:0]] <= ioctl_dout;
end
-
-wire [7:0] p1_controls = {m_down, m_up, m_right, m_left, m_fireA, 1'b0, m_one_player, m_coin1};
-wire [7:0] p2_controls = {m_down2, m_up2, m_right2, m_left2, m_fire2A, 1'b0, m_two_players, m_coin2};
-
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
diff --git a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_CPU.sv b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_CPU.sv
index 4477840a..0a2cdfe0 100644
--- a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_CPU.sv
+++ b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_CPU.sv
@@ -49,7 +49,7 @@ module BluePrint_CPU
input [3:0] h_center, v_center,
// ROM loading
- input main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i,
+ input main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i, main6_cs_i,
input tile0_cs_i, tile1_cs_i,
input spr_r_cs_i, spr_b_cs_i, spr_g_cs_i,
input [24:0] ioctl_addr,
@@ -99,30 +99,32 @@ assign ce_pix = cen_5m;
// H counter 0-319, V counter 0-263
// From MAME: set_raw(5MHz, 320, 0, 256, 264, 16, 240)
-reg [8:0] h_cnt = 9'd0;
+reg [8:0] base_h_cnt = 9'd0;
reg [8:0] v_cnt = 9'd0;
always_ff @(posedge clk_49m) begin
if (cen_5m) begin
- if (h_cnt == 9'd319) begin
- h_cnt <= 9'd0;
+ if (base_h_cnt == 9'd319) begin
+ base_h_cnt <= 9'd0;
v_cnt <= (v_cnt == 9'd263) ? 9'd0 : v_cnt + 9'd1;
end else
- h_cnt <= h_cnt + 9'd1;
+ base_h_cnt <= base_h_cnt + 9'd1;
end
end
+wire [8:0] h_cnt = (base_h_cnt <= 9'd248) ? base_h_cnt : 9'd248;
+
// Blanking
-wire hblk = (h_cnt >= 9'd256);
+wire hblk = (base_h_cnt >= 9'd256);
wire vblk = (v_cnt < 9'd16) | (v_cnt >= 9'd240);
assign video_hblank = hblk;
assign video_vblank = vblk;
// Sync generation with screen centering offsets
-wire [8:0] hs_start = 9'd280 + {5'd0, h_center};
+wire [8:0] hs_start = 9'd280 + {5'd0, h_center}; // Was 9'd280 + {5'd0, h_center};
wire [8:0] hs_end = hs_start + 9'd32;
wire [8:0] vs_start = 9'd248 + {5'd0, v_center};
wire [8:0] vs_end = vs_start + 9'd4;
-assign video_hsync = (h_cnt >= hs_start && h_cnt < hs_end);
+assign video_hsync = (base_h_cnt >= hs_start && base_h_cnt < hs_end);
assign video_vsync = (v_cnt >= vs_start && v_cnt < vs_end);
assign video_csync = ~(video_hsync ^ video_vsync);
@@ -186,12 +188,13 @@ wire cs_cram = mem_valid & (z80_A[15:12] == 4'hF); // 0xF000-0x
//------------------------------------------------------------ ROMs ------------------------------------------------------------//
// Main program ROMs (5x 4KB)
-wire [7:0] rom1_D, rom2_D, rom3_D, rom4_D, rom5_D;
+wire [7:0] rom1_D, rom2_D, rom3_D, rom4_D, rom5_D, rom6_D;
eprom_4k main_rom1(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main1_cs_i), .WR(ioctl_wr), .DATA(rom1_D));
eprom_4k main_rom2(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main2_cs_i), .WR(ioctl_wr), .DATA(rom2_D));
eprom_4k main_rom3(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main3_cs_i), .WR(ioctl_wr), .DATA(rom3_D));
eprom_4k main_rom4(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main4_cs_i), .WR(ioctl_wr), .DATA(rom4_D));
eprom_4k main_rom5(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main5_cs_i), .WR(ioctl_wr), .DATA(rom5_D));
+eprom_4k main_rom6(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main6_cs_i), .WR(ioctl_wr), .DATA(rom6_D));
// ROM data mux based on address
wire [7:0] rom_D = (z80_A[14:12] == 3'd0) ? rom1_D :
@@ -199,6 +202,7 @@ wire [7:0] rom_D = (z80_A[14:12] == 3'd0) ? rom1_D :
(z80_A[14:12] == 3'd2) ? rom3_D :
(z80_A[14:12] == 3'd3) ? rom4_D :
(z80_A[14:12] == 3'd4) ? rom5_D :
+ (z80_A[14:12] == 3'd4) ? rom6_D :
8'hFF;
// Tile ROMs (2x 4KB) — addressed by rendering pipeline
@@ -476,11 +480,11 @@ reg spr_flipy; // flipY for current sprite (from previous sprite'
reg prev_sprite_flipy; // Carry flipY forward
reg [7:0] spr_rom_r_lat, spr_rom_b_lat, spr_rom_g_lat;
reg [2:0] spr_pix_cnt;
-reg [7:0] spr_clear_addr;
+
reg [7:0] next_scanline; // v_cnt of the line being prepared
localparam SPR_IDLE = 4'd0;
-localparam SPR_CLEAR = 4'd1;
+
localparam SPR_INIT_RD = 4'd2;
localparam SPR_INIT_LAT = 4'd3;
localparam SPR_RD_B0 = 4'd4;
@@ -498,28 +502,15 @@ always_ff @(posedge clk_49m) begin
spr_state <= SPR_IDLE;
spr_idx <= 6'd0;
prev_sprite_flipy <= 1'b0;
- spr_clear_addr <= 8'd0;
end else begin
case (spr_state)
SPR_IDLE: begin
- if (cen_5m && h_cnt == 9'd256) begin
+ if (cen_5m && base_h_cnt == 9'd256) begin
next_scanline <= v_cnt[7:0] + 8'd1;
- spr_clear_addr <= 8'd0;
- spr_state <= SPR_CLEAR;
- end
- end
-
- SPR_CLEAR: begin
- if (~linebuf_sel)
- linebuf1[spr_clear_addr] <= 3'd0;
- else
- linebuf0[spr_clear_addr] <= 3'd0;
- if (spr_clear_addr == 8'd255) begin
- sprite_scan_addr <= 8'hFE; // sprite 63, byte 2
+ sprite_scan_addr <= 8'hFE;
spr_state <= SPR_INIT_RD;
- end else
- spr_clear_addr <= spr_clear_addr + 8'd1;
+ end
end
SPR_INIT_RD: begin
@@ -580,7 +571,6 @@ always_ff @(posedge clk_49m) begin
end
SPR_ROMWAIT: begin
- // ROM data valid this cycle; latch all three planes
spr_state <= SPR_ROMWAIT2;
end
@@ -588,8 +578,6 @@ always_ff @(posedge clk_49m) begin
spr_rom_r_lat <= spr_r_D;
spr_rom_b_lat <= spr_b_D;
spr_rom_g_lat <= spr_g_D;
- spr_pix_cnt <= 3'd0;
- spr_state <= SPR_PIXELS;
spr_pix_cnt <= 3'd0;
spr_state <= SPR_PIXELS;
end
@@ -602,7 +590,7 @@ always_ff @(posedge clk_49m) begin
// flipX: bit0 first (pixel 0 = LSB); normal: bit7 first (pixel 0 = MSB)
bit_pos = spr_byte2[6] ? spr_pix_cnt : (3'd7 - spr_pix_cnt);
pixel_val = {spr_rom_g_lat[bit_pos], spr_rom_b_lat[bit_pos], spr_rom_r_lat[bit_pos]};
- x_pos = spr_byte3 + {5'd0, spr_pix_cnt} + 8'd2;
+ x_pos = spr_byte3 + {5'd0, spr_pix_cnt} + 8'd0; // + 8'd2
if (pixel_val != 3'd0) begin
if (~linebuf_sel)
linebuf1[x_pos] <= pixel_val;
@@ -631,9 +619,21 @@ always_ff @(posedge clk_49m) begin
end
end
+
//--- Sprite pixel readout ---
-wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0]] : linebuf0[h_cnt[7:0]];
+//wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0]] : linebuf0[h_cnt[7:0]];
+wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0] - 8'd3] : linebuf0[h_cnt[7:0] - 8'd3];
+// Clear display buffer as we read (becomes write buffer next line)
+always_ff @(posedge clk_49m) begin
+ if (cen_5m && visible_line) begin
+ if (linebuf_sel)
+ linebuf1[h_cnt[7:0] - 8'd3] <= 3'd0;
+ else
+ linebuf0[h_cnt[7:0] - 8'd3] <= 3'd0;
+ end
+end
+
wire sprite_transparent = (sprite_pixel == 3'b000);
// Sprite pixel bits: bit0=R, bit1=B, bit2=G (full brightness only)
diff --git a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_Top.sv b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_Top.sv
index 9e5f311a..91c8775d 100644
--- a/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_Top.sv
+++ b/Arcade_MiST/Zilec BluePrint/rtl/BluePrint_Top.sv
@@ -72,7 +72,7 @@ wire [7:0] dipsw_readback_from_snd;
wire [7:0] dipsw_readback = dipsw_readback_from_snd;
// ROM loader signals for MISTer (loads ROMs from SD card)
-wire main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i;
+wire main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i, main6_cs_i;
wire tile0_cs_i, tile1_cs_i;
wire spr_r_cs_i, spr_b_cs_i, spr_g_cs_i;
@@ -93,6 +93,7 @@ selector DLSEL
.main3_cs(main3_cs_i),
.main4_cs(main4_cs_i),
.main5_cs(main5_cs_i),
+ .main6_cs(main6_cs_i),
.tile0_cs(tile0_cs_i),
.tile1_cs(tile1_cs_i),
.spr_r_cs(spr_r_cs_i),
@@ -131,6 +132,7 @@ BluePrint_CPU main_pcb
.main3_cs_i(main3_cs_i),
.main4_cs_i(main4_cs_i),
.main5_cs_i(main5_cs_i),
+ .main6_cs_i(main6_cs_i),
.tile0_cs_i(tile0_cs_i),
.tile1_cs_i(tile1_cs_i),
.spr_r_cs_i(spr_r_cs_i),
diff --git a/Arcade_MiST/Zilec BluePrint/rtl/rom_loader.sv b/Arcade_MiST/Zilec BluePrint/rtl/rom_loader.sv
index 923459ad..268cb680 100644
--- a/Arcade_MiST/Zilec BluePrint/rtl/rom_loader.sv
+++ b/Arcade_MiST/Zilec BluePrint/rtl/rom_loader.sv
@@ -29,22 +29,24 @@
// 0x2000 - 0x2FFF = main_rom3 (bp-3.1p)
// 0x3000 - 0x3FFF = main_rom4 (bp-4.1r)
// 0x4000 - 0x4FFF = main_rom5 (bp-5.1s)
-// 0x5000 - 0x5FFF = tile_rom0 (bg-1.3c)
-// 0x6000 - 0x6FFF = tile_rom1 (bg-2.3d)
-// 0x7000 - 0x7FFF = spr_rom_r (red.17d)
-// 0x8000 - 0x8FFF = spr_rom_b (blue.18d)
-// 0x9000 - 0x9FFF = spr_rom_g (green.20d)
+// 0x4000 - 0x5FFF = main_rom6 (bp-5.1s)
+
+// 0x6000 - 0x6FFF = tile_rom0 (bg-1.3c)
+// 0x7000 - 0x7FFF = tile_rom1 (bg-2.3d)
+// 0x8000 - 0x8FFF = spr_rom_r (red.17d)
+// 0x9000 - 0x9FFF = spr_rom_b (blue.18d)
+// 0xA000 - 0xAFFF = spr_rom_g (green.20d)
// Sound board ROMs loaded separately via index 1
module selector
(
input logic [24:0] ioctl_addr,
- output logic main1_cs, main2_cs, main3_cs, main4_cs, main5_cs,
+ output logic main1_cs, main2_cs, main3_cs, main4_cs, main5_cs, main6_cs,
output logic tile0_cs, tile1_cs,
output logic spr_r_cs, spr_b_cs, spr_g_cs
);
always_comb begin
- {main1_cs, main2_cs, main3_cs, main4_cs, main5_cs,
+ {main1_cs, main2_cs, main3_cs, main4_cs, main5_cs, main6_cs,
tile0_cs, tile1_cs, spr_r_cs, spr_b_cs, spr_g_cs} = 0;
if(ioctl_addr < 'h1000) main1_cs = 1;
@@ -52,11 +54,13 @@ module selector
else if(ioctl_addr < 'h3000) main3_cs = 1;
else if(ioctl_addr < 'h4000) main4_cs = 1;
else if(ioctl_addr < 'h5000) main5_cs = 1;
- else if(ioctl_addr < 'h6000) tile0_cs = 1;
- else if(ioctl_addr < 'h7000) tile1_cs = 1;
- else if(ioctl_addr < 'h8000) spr_r_cs = 1;
- else if(ioctl_addr < 'h9000) spr_b_cs = 1;
- else if(ioctl_addr < 'hA000) spr_g_cs = 1;
+ else if(ioctl_addr < 'h6000) main6_cs = 1;
+
+ else if(ioctl_addr < 'h7000) tile0_cs = 1;
+ else if(ioctl_addr < 'h8000) tile1_cs = 1;
+ else if(ioctl_addr < 'h9000) spr_r_cs = 1;
+ else if(ioctl_addr < 'hA000) spr_b_cs = 1;
+ else if(ioctl_addr < 'hB000) spr_g_cs = 1;
end
endmodule