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Gyorgy Szombathelyi
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GNU GENERAL PUBLIC LICENSE
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the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.

67
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@@ -0,0 +1,67 @@
# JT51
YM2151 clone in verilog. FPGA proven.
(c) Jose Tejada 2016. Twitter: @topapate
You can show your appreciation through
* [Patreon](https://patreon.com/jotego), by supporting releases
* [Paypal](https://paypal.me/topapate), with a donation
Originally posted in opencores. The Github repository is now the main one.
## Using JT51 in a git project
If you are using JT51 in a git project, the best way to add it to your project is:
1. Optionally fork JT51's repository to your own GitHub account
2. Add it as a submodule to your git project: `git submodule add https://github.com/jotego/jt51.git`
3. Now you can refer to the RTL files in **jt51/hdl**
The advantages of a using a git submodule are:
1. Your project contains a reference to a commit of the JT51 repository
2. As long as you do not manually update the JT51 submodule, it will keep pointing to the same commit
3. Each time you make a commit in your project, it will include a pointer to the JT51 commit used. So you will always know the JT51 that worked for you
4. If JT51 is updated and you want to get the changes, simply update the submodule using git. The new JT51 commit used will be annotated in your project's next commit. So the history of your project will reflect that change too.
5. JT51 files will be intact and you will use the files without altering them.
## Folders
* **jt51/doc** contains documentation related to JT51 and YM2151
* **jt51/hdl** contains all the Verilog source code to implement JT51 on FPGA or ASIC
* **jt51/hdl/filter** contains an interpolator to use as first stage to on-chip sigma-delta DACs
* **jt51/syn** contains some use case examples. It has synthesizable projects in various platforms
* **jt51/syn/xilinx/contra** sound board of the arcade Contra. Checkout **hdl** subfolder for the verilog files
## Usage
All files are in **jt51/hdl**. The top level file is jt51.v. You need all files in the **jt51/hdl** folder to synthesize or simulate the design.
Alternatively you can just use the file jt51_v1.1.v at the release folder. It contains all the necessary files concatenated inside. It is generated by the script in bin/jt51_singlefile.sh
Simulation modules are added if macros
- SIMULATION
- JT51_DEBUG
are defined
Use macro JT51_ONLYTIMERS in order to avoid simulating the FM signal chain but keep the timer modules working. This is useful if a CPU depends on the timer interrupts but you do not want to simulate the full FM sound (to speed up sims).
## Related Projects
Other sound chips from the same author
Chip | Repository
-----------------------|------------
YM2203, YM2612, YM2610 | [JT12](https://github.com/jotego/jt12)
YM2151 | [JT51](https://github.com/jotego/jt51)
YM3526 | [JTOPL](https://github.com/jotego/jtopl)
YM2149 | [JT49](https://github.com/jotego/jt49)
sn76489an | [JT89](https://github.com/jotego/jt89)
OKI 6295 | [JT6295](https://github.com/jotego/jt6295)
OKI MSM5205 | [JT5205](https://github.com/jotego/jt5205)
This sound core has been used at least in the following arcade cores for FPGA
* [JTCPS1](https://github.com/jotego/jtcps1): CAPCOM SYSTEM arcade clone
* [JTDD](https://github.com/jotego/jtdd): Double Dragon 1 & 2 arcade clone
* [JTGNG](https://github.com/jotego/jt_gng): arcade clones of pre-CPS CAPCOM games. Some use YM2151 through JT51
More to come soon!

45
common/Sound/jt51/jt51.qip
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@@ -1,23 +1,22 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_csr_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_csr_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_exp2lin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_kon.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_lfo_lfsr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_lin2exp.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_mod.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_noise_lfsr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_phinc_rom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_phrom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_acc.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_eg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_exp2lin.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_exprom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_kon.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_lfo.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_lin2exp.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_mmr.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_mod.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_noise_lfsr.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_noise.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_op.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_pg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_phinc_rom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_phrom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_pm.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_reg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_sh.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_timers.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_csr_ch.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51_csr_op.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt51.v ]

88
common/Sound/jt51/jt51.v
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@@ -12,19 +12,18 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51(
input rst, // reset
input clk, // main clock
input cen, // clock enable
input cen_p1, // clock enable at half the speed
(* direct_enable *) input cen, // clock enable
(* direct_enable *) input cen_p1, // clock enable at half the speed
input cs_n, // chip select
input wr_n, // write
input a0,
@@ -40,15 +39,9 @@ module jt51(
output signed [15:0] right,
// Full resolution output
output signed [15:0] xleft,
output signed [15:0] xright,
// unsigned outputs for sigma delta converters, full resolution
output [15:0] dacleft,
output [15:0] dacright
output signed [15:0] xright
);
assign dacleft = { ~xleft [15], xleft[14:0] };
assign dacright = { ~xright[15], xright[14:0] };
// Timers
wire [9:0] value_A;
wire [7:0] value_B;
@@ -56,9 +49,10 @@ wire load_A, load_B;
wire enable_irq_A, enable_irq_B;
wire clr_flag_A, clr_flag_B;
wire flag_A, flag_B, overflow_A;
wire zero;
wire zero, half;
wire [4:0] cycles;
jt51_timers u_timers(
jt51_timers u_timers(
.clk ( clk ),
.cen ( cen_p1 ),
.rst ( rst ),
@@ -77,7 +71,7 @@ jt51_timers u_timers(
.irq_n ( irq_n )
);
/*verilator tracing_off*/
/*verilator tracing_on*/
`ifndef JT51_ONLYTIMERS
`define YM_TIMER_CTRL 8'h14
@@ -102,37 +96,51 @@ wire [3:0] d1l_I;
wire [3:0] rrate_II;
wire [1:0] cur_op;
assign sample =zero;
wire keyon_II;
wire [7:0] lfo_freq;
wire [1:0] lfo_w;
wire lfo_rst;
wire [6:0] am;
wire lfo_up;
wire [7:0] am;
wire [7:0] pm;
wire [6:0] amd, pmd;
wire [7:0] test_mode;
wire noise;
wire m1_enters, m2_enters, c1_enters, c2_enters;
wire use_prevprev1,use_internal_x,use_internal_y, use_prev2,use_prev1;
assign sample = zero & cen_p1; // single strobe
jt51_lfo u_lfo(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // should it be cen_p1?
.zero ( zero ),
.lfo_rst ( lfo_rst ),
.cen ( cen_p1 ),
.cycles ( cycles ),
// Configuration
.lfo_freq ( lfo_freq ),
.lfo_w ( lfo_w ),
.lfo_amd ( amd ),
.lfo_pmd ( pmd ),
.lfo_up ( lfo_up ),
.noise ( noise ),
// Test
.test ( test_mode ),
.lfo_clk ( ),
.am ( am ),
.pm_u ( pm )
.pm ( pm )
);
wire [ 4:0] keycode_III;
wire [ 9:0] ph_X;
wire pg_rst_III;
/*verilator tracing_on*/
jt51_pg u_pg(
.rst ( rst ),
.clk ( clk ), // P1
@@ -163,7 +171,7 @@ wire [9:0] eg_XI;
jt51_eg u_eg(
`ifdef TEST_SUPPORT
.test_eg ( test_eg ),
`endif
`endif
.rst ( rst ),
.clk ( clk ),
.cen ( cen_p1 ),
@@ -187,12 +195,13 @@ jt51_eg u_eg(
.eg_XI ( eg_XI )
);
/*verilator tracing_off*/
wire signed [13:0] op_out;
jt51_op u_op(
`ifdef TEST_SUPPORT
.test_eg ( test_eg ),
.test_op0 ( test_op0 ),
.test_op0 ( test_op0 ),
`endif
.rst ( rst ),
.clk ( clk ),
@@ -210,7 +219,7 @@ jt51_op u_op(
.use_internal_x ( use_internal_x ),
.use_internal_y ( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 ),
.use_prev1 ( use_prev1 ),
.test_214 ( 1'b0 ),
`ifdef SIMULATION
.zero ( zero ),
@@ -219,18 +228,20 @@ jt51_op u_op(
.op_XVII ( op_out )
);
wire [4:0] nfrq;
wire [10:0] noise_out;
wire ne, op31_acc, op31_no;
wire [ 4:0] nfrq;
wire [11:0] noise_mix;
wire ne, op31_acc, op31_no;
jt51_noise u_noise(
.rst ( rst ),
.clk ( clk ),
.cen ( cen_p1 ),
.nfrq ( nfrq ),
.cycles ( cycles ),
.nfrq ( nfrq ),
.eg ( eg_XI ),
.out ( noise_out ),
.op31_no( op31_no )
.op31_no( op31_no ),
.out ( noise ),
.mix ( noise_mix )
);
jt51_acc u_acc(
@@ -246,7 +257,7 @@ jt51_acc u_acc(
.con_I ( con_I ),
.op_out ( op_out ),
.ne ( ne ),
.noise ( noise_out ),
.noise_mix ( noise_mix ),
.left ( left ),
.right ( right ),
.xleft ( xleft ),
@@ -275,20 +286,21 @@ jt51_mmr u_mmr(
.din ( din ),
.busy ( busy ),
.test_mode ( test_mode ),
// CT
.ct1 ( ct1 ),
.ct1 ( ct1 ), // the LFO clock can be outputted via CT1 -not implemented-
.ct2 ( ct2 ),
// LFO
.lfo_freq ( lfo_freq ),
.lfo_w ( lfo_w ),
.lfo_amd ( amd ),
.lfo_pmd ( pmd ),
.lfo_rst ( lfo_rst ),
.lfo_up ( lfo_up ),
// Noise
.ne ( ne ),
.nfrq ( nfrq ),
// Timers
.value_A ( value_A ),
.value_B ( value_B ),
@@ -297,9 +309,9 @@ jt51_mmr u_mmr(
.enable_irq_A( enable_irq_A ),
.enable_irq_B( enable_irq_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.clr_flag_B ( clr_flag_B ),
.overflow_A ( overflow_A ),
`ifdef TEST_SUPPORT
`ifdef TEST_SUPPORT
// Test
.test_eg ( test_eg ),
.test_op0 ( test_op0 ),
@@ -329,6 +341,8 @@ jt51_mmr u_mmr(
.op31_no ( op31_no ),
.op31_acc ( op31_acc ),
.zero ( zero ),
.half ( half ),
.cycles ( cycles ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),

15
common/Sound/jt51/jt51_acc.v
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@@ -12,13 +12,12 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.1 Date: 14- 4-2017
Version: 1.0 Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_acc(
input rst,
@@ -33,18 +32,18 @@ module jt51_acc(
input [2:0] con_I,
input signed [13:0] op_out,
input ne, // noise enable
input signed [10:0] noise,
input signed [11:0] noise_mix,
output signed [15:0] left,
output signed [15:0] right,
output reg signed [15:0] xleft, // exact outputs
output reg signed [15:0] xright
output reg signed [15:0] xright
);
reg signed [13:0] op_val;
always @(*) begin
if( ne && op31_acc ) // cambiar a OP 31
op_val = { {2{noise[10]}}, noise, 1'd0 };
op_val = { {2{noise_mix[11]}}, noise_mix };
else
op_val = op_out;
end
@@ -55,7 +54,7 @@ always @(*) begin
case ( con_I )
3'd0,3'd1,3'd2,3'd3: sum_en = m2_enters;
3'd4: sum_en = m1_enters | m2_enters;
3'd5,3'd6: sum_en = ~c1_enters;
3'd5,3'd6: sum_en = ~c1_enters;
3'd7: sum_en = 1'b1;
default: sum_en = 1'bx;
endcase
@@ -76,7 +75,7 @@ wire rst_sum = c2_enters;
function signed [15:0] lim16;
input signed [16:0] din;
lim16 = !din[16] && din[15] ? 16'h7fff :
lim16 = !din[16] && din[15] ? 16'h7fff :
( din[16] && !din[15] ? 16'h8000 : din[15:0] );
endfunction
@@ -104,7 +103,7 @@ always @(posedge clk) begin
end
end
end
reg signed [15:0] opsum;
wire signed [16:0] opsum10 = {{3{op_val[13]}},op_val}+{total[15],total};

65
common/Sound/jt51/jt51_eg.v
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@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_eg(
`ifdef TEST_SUPPORT
@@ -41,7 +40,7 @@ module jt51_eg(
output reg pg_rst_III,
// envelope number
input [6:0] tl_VII,
input [6:0] am,
input [7:0] am,
input [1:0] ams_VII,
input amsen_VII,
output [9:0] eg_XI
@@ -56,12 +55,12 @@ localparam ATTACK=2'd0,
DECAY2=2'd2,
RELEASE=2'd3;
reg [4:0] d1level_II;
reg [2:0] cnt_V;
reg [5:0] rate_IV;
wire [9:0] eg_VI;
reg [9:0] eg_VII, eg_VIII;
wire [9:0] eg_II;
reg [ 4:0] d1level_II;
reg [ 2:0] cnt_V;
reg [ 5:0] rate_IV;
wire [ 9:0] eg_VI;
reg [ 9:0] eg_VII, eg_VIII;
wire [ 9:0] eg_II;
reg [11:0] sum_eg_tl_VII;
reg step_V, step_VI;
@@ -71,10 +70,10 @@ reg [5:1] rate_VI;
// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };
reg [1:0] eg_cnt_base;
reg [ 1:0] eg_cnt_base;
reg [14:0] eg_cnt /*verilator public*/;
reg [8:0] am_final_VII;
reg [ 9:0] am_final_VII;
always @(posedge clk) begin : envelope_counter
if( rst ) begin
@@ -97,18 +96,12 @@ end
wire cnt_out; // = all_cnt_last[3*31-1:3*30];
reg [6:0] pre_rate_III;
reg [4:0] kshift_III;
reg [4:0] cfg_III;
always @(*) begin : pre_rate_calc
if( cfg_III == 5'd0 )
pre_rate_III = 7'd0;
else
case( ks_III )
2'd3: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 2'b0, keycode_III };
2'd2: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 3'b0, keycode_III[4:1] };
2'd1: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 4'b0, keycode_III[4:2] };
2'd0: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 5'b0, keycode_III[4:3] };
endcase
kshift_III = keycode_III >> ~ks_III;
pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 2'b0, kshift_III };
end
@@ -140,7 +133,7 @@ always @(*) begin : rate_step
endcase
end
// a rate_IV of zero keeps the level still
step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
step_V = rate_V[5:2]==4'd0 ? 1'b0 : step_idx[ cnt_V ];
end
@@ -313,23 +306,24 @@ end
// VII
always @(*) begin : sum_eg_and_tl
casez( {amsen_VII, ams_VII } )
3'b0??,3'b100: am_final_VII = 9'd0;
3'b101: am_final_VII = { 2'b00, am };
3'b110: am_final_VII = { 1'b0, am, 1'b0};
3'b111: am_final_VII = { am, 2'b0 };
3'b0_??,
3'b1_00: am_final_VII = 10'd0;
3'b1_01: am_final_VII = { 2'b0, am }; // 23.9 dB max
3'b1_10: am_final_VII = { 1'b0, am, 1'b0 }; // 47 dB
3'b1_11: am_final_VII = { am, 2'b0 }; // 95.6 dB
endcase
`ifdef TEST_SUPPORT
if( test_eg && tl_VII!=7'd0 )
sum_eg_tl_VII = 12'd0;
else
`endif
sum_eg_tl_VII = { 2'b0, tl_VII, 3'd0 }
+ {2'b0, eg_VII}
+ {2'b0, am_final_VII, 1'b0 };
sum_eg_tl_VII = { 2'b0, tl_VII, 3'd0 } // 0.75 dB steps
+ { 2'b0, eg_VII } // 0.094 dB steps
+ { 2'b0, am_final_VII };
end
always @(posedge clk) if(cen) begin
eg_VIII <= sum_eg_tl_VII[11:10] > 2'b0 ? {10{1'b1}} : sum_eg_tl_VII[9:0];
eg_VIII <= |sum_eg_tl_VII[11:10] ? {10{1'b1}} : sum_eg_tl_VII[9:0];
end
jt51_sh #( .width(10), .stages(3) ) u_egpadding (
@@ -391,7 +385,7 @@ jt51_sh #( .width(2), .stages(32-3+2), .rstval(1'b1) ) u_statesh(
.drop ( state_II )
);
`ifndef JT51_NODEBUG
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
@@ -412,10 +406,10 @@ sep32 #(.width(7),.stg(7)) sep_tl(
.cnt ( cnt )
);
sep32 #(.width(2),.stg(2)) sep_state(
sep32 #(.width(2),.stg(3)) sep_state(
.clk ( clk ),
.cen ( cen ),
.mixed ( state_II ),
.mixed ( state_in_III ),
.cnt ( cnt )
);
@@ -425,13 +419,20 @@ sep32 #(.width(5),.stg(6)) sep_rate(
.cnt ( cnt )
);
sep32 #(.width(9),.stg(7)) sep_amfinal(
sep32 #(.width(10),.stg(7)) sep_amfinal(
.clk ( clk ),
.cen ( cen ),
.mixed ( am_final_VII ),
.cnt ( cnt )
);
sep32 #(.width(5),.stg(3)) sep_kcfinal(
.clk ( clk ),
.cen ( cen ),
.mixed ( keycode_III ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif
`endif

1
common/Sound/jt51/jt51_exp2lin.v
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@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_exp2lin(
output reg signed [15:0] lin,

1
common/Sound/jt51/jt51_exprom.v
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@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT51.

1
common/Sound/jt51/jt51_kon.v
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@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT51.

417
common/Sound/jt51/jt51_lfo.v
View File

@@ -12,260 +12,223 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
/*
tab size 4
*/
module jt51_lfo(
input rst,
input clk,
input cen,
input zero,
input lfo_rst,
input [4:0] cycles,
// configuration
input [7:0] lfo_freq,
input [6:0] lfo_amd,
input [6:0] lfo_pmd,
input [6:0] lfo_pmd,
input [1:0] lfo_w,
output reg [6:0] am,
output reg [7:0] pm_u
input lfo_up,
input noise,
// test
input [7:0] test,
output reg lfo_clk,
// data
output reg [7:0] am,
output reg [7:0] pm
);
reg signed [7:0] pm;
localparam [1:0] SAWTOOTH = 2'd0,
SQUARE = 2'd1,
TRIANG = 2'd2,
NOISE = 2'd3;
always @(*) begin: signed_to_unsigned
if( pm[7] ) begin
pm_u[7] = pm[7];
pm_u[6:0] = ~pm[6:0];
end
else pm_u = pm;
end
reg [14:0] lfo_lut[0:15];
wire [6:0] noise_am;
wire [7:0] noise_pm;
// counters
reg [ 3:0] cnt1, cnt3, bitcnt;
reg [14:0] cnt2;
reg [15:0] next_cnt2;
reg [ 1:0] cnt1_ov, cnt2_ov;
parameter b0=3;
reg [15+b0:0] base;
// LFO state (value)
reg [15:0] val, // counts next integrator step
out2; // integrator for PM/AM
reg [ 6:0] out1;
wire pm_sign;
reg trig_sign, saw_sign;
always @(posedge clk) begin : base_counter
if( rst ) begin
base <= {b0+16{1'b0}};
end
else if(cen) begin
if( zero ) base <= base + 1'b1;
end
end
reg bitcnt_rst, cnt2_load, cnt3_step;
wire lfo_clk_next;
reg lfo_clk_latch;
reg sel_base;
reg [4:0] freq_sel;
wire cyc_5 = cycles[3:0]==4'h5;
wire cyc_6 = cycles[3:0]==4'h6;
wire cyc_c = cycles[3:0]==4'hc; // 12
wire cyc_d = cycles[3:0]==4'hd; // 13
wire cyc_e = cycles[3:0]==4'he; // 14
wire cyc_f = cycles[3:0]==4'hf; // 15
always @(*) begin : base_mux
freq_sel = {1'b0,lfo_freq[7:4]}
+ ( lfo_w==2'd2 ? 5'b1 : 5'b0 );
case( freq_sel )
5'h10: sel_base = base[b0-1];
5'hf: sel_base = base[b0+0];
5'he: sel_base = base[b0+1];
5'hd: sel_base = base[b0+2];
5'hc: sel_base = base[b0+3];
5'hb: sel_base = base[b0+4];
5'ha: sel_base = base[b0+5];
5'h9: sel_base = base[b0+6];
5'h8: sel_base = base[b0+7];
5'h7: sel_base = base[b0+8];
5'h6: sel_base = base[b0+9];
5'h5: sel_base = base[b0+10];
5'h4: sel_base = base[b0+11];
5'h3: sel_base = base[b0+12];
5'h2: sel_base = base[b0+13];
5'h1: sel_base = base[b0+14];
5'h0: sel_base = base[b0+15];
default: sel_base = base[b0-1];
endcase
end
reg cnt3_clk;
wire ampm_sel = bitcnt[3];
wire bit7 = &bitcnt[2:0];
reg [7:0] cnt, cnt_lim;
reg lfo_up_latch;
reg signed [10:0] am_bresenham;
reg signed [ 9:0] pm_bresenham;
assign pm_sign = lfo_w==TRIANG ? trig_sign : saw_sign;
assign lfo_clk_next = test[2] | next_cnt2[15] | cnt3_step;
always @(*) begin : counter_limit
case( lfo_freq[3:0] )
4'hf: cnt_lim = 8'd66;
4'he: cnt_lim = 8'd68;
4'hd: cnt_lim = 8'd70;
4'hc: cnt_lim = 8'd73;
4'hb: cnt_lim = 8'd76;
4'ha: cnt_lim = 8'd79;
4'h9: cnt_lim = 8'd82;
4'h8: cnt_lim = 8'd85;
4'h7: cnt_lim = 8'd89;
4'h6: cnt_lim = 8'd93;
4'h5: cnt_lim = 8'd98;
4'h4: cnt_lim = 8'd102;
4'h3: cnt_lim = 8'd108;
4'h2: cnt_lim = 8'd114;
4'h1: cnt_lim = 8'd120;
4'h0: cnt_lim = 8'd128;
endcase
end
wire signed [7:0] pmd_min = (~{1'b0, lfo_pmd[6:0]})+8'b1;
reg lfo_clk, last_base, am_up, pm_up;
always @(posedge clk, posedge rst)
if( rst ) begin
last_base <= 1'd0;
lfo_clk <= 1'b0;
cnt <= 8'd0;
am <= 7'd0;
pm <= 8'd0;
am_up <= 1'b1;
pm_up <= 1'b1;
am_bresenham <= 11'd0;
pm_bresenham <= 10'd0;
always @(*) begin
if( cnt2_load ) begin
next_cnt2 = {1'b0, lfo_lut[ lfo_freq[7:4] ] };
end else begin
if( lfo_rst ) begin // synchronous reset
last_base <= 1'd0;
lfo_clk <= 1'b0;
cnt <= 8'd0;
am <= 7'd0;
pm <= 8'd0;
am_up <= 1'b1;
pm_up <= 1'b1;
am_bresenham <= 11'd0;
pm_bresenham <= 10'd0;
end else if ( cen ) begin
last_base <= sel_base;
if( last_base != sel_base ) begin
case( lfo_w )
2'd0: begin // AM sawtooth
if( am_bresenham > 0 ) begin
if( am == lfo_amd ) begin
am <= 7'd0;
am_bresenham <= 11'd0;
end
else begin
am <= am + 1'b1;
am_bresenham <= am_bresenham
- { 2'd0, cnt_lim, 1'b0} + {4'd0,lfo_amd};
end
end
else am_bresenham <= am_bresenham + {4'd0,lfo_amd};
next_cnt2 = {1'd0,cnt2 } + {15'd0,cnt1_ov[1]|test[3]};
end
end
if( pm_bresenham > 0 ) begin
if( pm == { 1'b0, lfo_pmd } ) begin
pm <= pmd_min;
pm_bresenham <= 10'd0;
end
else begin
pm <= pm + 1'b1;
pm_bresenham <= pm_bresenham
- {2'd0,cnt_lim} + {3'd0,lfo_pmd};
end
end
else pm_bresenham <= pm_bresenham + {3'b0,lfo_pmd};
end
2'd1: // AM square waveform
if( cnt == cnt_lim ) begin
cnt <= 8'd0;
lfo_clk <= ~lfo_clk;
am <= lfo_clk ? lfo_amd : 7'd0;
pm <= lfo_clk ? {1'b0, lfo_pmd } : pmd_min;
end
else cnt <= cnt + 1'd1;
2'd2: begin // AM triangle
if( am_bresenham > 0 ) begin
if( am == lfo_amd && am_up) begin
am_up <= 1'b0;
am_bresenham <= 11'd0;
end
else if( am == 7'd0 && !am_up) begin
am_up <= 1'b1;
am_bresenham <= 11'd0;
end
else begin
am <= am_up ? am+1'b1 : am-1'b1;
am_bresenham <= am_bresenham
- { 2'b0, cnt_lim, 1'b0} + {4'd0,lfo_amd};
end
end
else am_bresenham <= am_bresenham + {4'd0,lfo_amd};
if( pm_bresenham > 0 ) begin
if( pm == {1'b0, lfo_pmd} && pm_up) begin
pm_up <= 1'b0;
pm_bresenham <= 10'd0;
end
else if( pm == pmd_min && !pm_up) begin
pm_up <= 1'b1;
pm_bresenham <= 10'd0;
end
else begin
pm <= pm_up ? pm+1'b1 : pm-1'b1;
pm_bresenham <= pm_bresenham
- {2'd0,cnt_lim} + {3'd0,lfo_pmd};
end
end
else pm_bresenham <= pm_bresenham + {3'd0,lfo_pmd};
end
2'd3: begin
casez( lfo_amd ) // same as real chip
7'b1??????: am <= noise_am[6:0];
7'b01?????: am <= { 1'b0, noise_am[5:0] };
7'b001????: am <= { 2'b0, noise_am[4:0] };
7'b0001???: am <= { 3'b0, noise_am[3:0] };
7'b00001??: am <= { 4'b0, noise_am[2:0] };
7'b000001?: am <= { 5'b0, noise_am[1:0] };
7'b0000001: am <= { 6'b0, noise_am[0] };
default: am <= 7'd0;
endcase
casez( lfo_pmd )
7'b1??????: pm <= noise_pm;
7'b01?????: pm <= { {2{noise_pm[7]}}, noise_pm[5:0] };
7'b001????: pm <= { {3{noise_pm[7]}}, noise_pm[4:0] };
7'b0001???: pm <= { {4{noise_pm[7]}}, noise_pm[3:0] };
7'b00001??: pm <= { {5{noise_pm[7]}}, noise_pm[2:0] };
7'b000001?: pm <= { {6{noise_pm[7]}}, noise_pm[1:0] };
7'b0000001: pm <= { {7{noise_pm[7]}}, noise_pm[0] };
default: pm <= 8'd0;
endcase
end
endcase
always @(posedge clk) begin
if( lfo_up )
lfo_up_latch <= 1;
else if( cen )
lfo_up_latch <= 0;
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
cnt1 <= 4'd0;
cnt2 <= 15'd0;
cnt3 <= 4'd0;
cnt1_ov <= 2'd0;
cnt3_step <= 0;
bitcnt <= 4'h8;
end else if( cen ) begin
// counter 1
if( cyc_c )
{ cnt1_ov[0], cnt1 } <= { 1'b0, cnt1 } + 1'd1;
else
cnt1_ov[0] <= 0;
cnt1_ov[1] <= cnt1_ov[0];
bitcnt_rst <= cnt1==4'd2;
if( bitcnt_rst && !cyc_c )
bitcnt <= 4'd0;
else if( cyc_e )
bitcnt <= bitcnt + 1'd1;
// counter 2
cnt2_load <= lfo_up_latch | next_cnt2[15];
cnt2 <= next_cnt2[14:0];
if( cyc_e ) begin
cnt2_ov[0] <= next_cnt2[15];
lfo_clk_latch <= lfo_clk_next;
end
if( cyc_5 ) cnt2_ov[1] <= cnt2_ov[0];
// counter 3
cnt3_step <= 0;
if( cnt2_ov[1] & cyc_d ) begin
cnt3_clk <= 1;
// frequency LSB control
if( !cnt3[0] ) cnt3_step <= lfo_freq[3];
else if( !cnt3[1] ) cnt3_step <= lfo_freq[2];
else if( !cnt3[2] ) cnt3_step <= lfo_freq[1];
else if( !cnt3[3] ) cnt3_step <= lfo_freq[0];
end else begin
cnt3_clk <= 0;
end
if( cnt3_clk )
cnt3 <= cnt3 + 1'd1;
// LFO clock
lfo_clk <= lfo_clk_next;
end
end
// LFO value
reg [1:0] val_sum;
reg val_c, wcarry, val0_next;
reg w1, w2, w3, w4, w5, w6, w7, w8;
reg [6:0] dmux;
reg integ_c, out1bit;
reg [1:0] out2sum;
wire [7:0] out2b;
reg [2:0] bitsel;
assign out2b = out2[15:8];
always @(*) begin
w1 = !lfo_clk || lfo_w==NOISE || !cyc_f;
w4 = lfo_clk_latch && lfo_w==NOISE;
w3 = !w4 && val[15] && !test[1];
w2 = !w1 && lfo_w==TRIANG;
wcarry = !w1 || ( !cyc_f && lfo_w!=NOISE && val_c);
val_sum = {1'b0, w2} + {1'b0, w3} + {1'b0, wcarry};
val0_next = val_sum[0] || (lfo_w==NOISE && lfo_clk_latch && noise);
// LFO compound output, AM/PM base value one after the other
w5 = ampm_sel ? saw_sign : (!trig_sign || lfo_w!=TRIANG);
w6 = w5 ^ w3;
w7 = cycles[3:0]<4'd7 || cycles[3:0]==4'd15;
w8 = lfo_w == SQUARE ? (ampm_sel?cyc_6 : !saw_sign) : w6;
w8 = ~(w8 & w7);
// Integrator
dmux = (ampm_sel ? lfo_pmd : lfo_amd) &~out1;
bitsel = ~(bitcnt[2:0]+3'd1);
out1bit = dmux[ bitsel ] & ~bit7;
out2sum = {1'b0, out1bit} + {1'b0, out2[0] && bitcnt[2:0]!=0} + {1'b0, integ_c & ~cyc_f };
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
val <= 16'd0;
val_c <= 0;
trig_sign <= 0;
saw_sign <= 0;
out1 <= ~7'd0;
out2 <= 16'd0;
integ_c <= 0;
end else if( cen ) begin
val <= {val[14:0], val0_next };
val_c <= val_sum[1];
if( cyc_f ) begin
trig_sign <= val[7];
saw_sign <= val[8];
end
// current step
out1 <= {out1[5:0], w8};
// integrator
integ_c <= out2sum[1];
out2 <= { out2sum[0], out2[15:1] };
// final output
if( bit7 & cyc_f ) begin
if( ampm_sel )
pm <= lfo_pmd==7'd0 ? 8'd0 : { out2b[7]^pm_sign, out2b[6:0]};
else
am <= out2b;
end
end
end
genvar aux;
generate
for( aux=0; aux<7; aux=aux+1 ) begin : amnoise
jt51_lfo_lfsr #(.init(aux*aux+aux) ) u_noise_am(
.rst( rst ),
.clk( clk ),
.cen( cen ),
.base(sel_base),
.out( noise_am[aux] )
);
end
for( aux=0; aux<8; aux=aux+1 ) begin : pmnoise
jt51_lfo_lfsr #(.init(4*aux*aux-3*aux+40) ) u_noise_pm(
.rst( rst ),
.clk( clk ),
.cen( cen ),
.base(sel_base),
.out( noise_pm[aux] )
);
end
endgenerate
initial begin
lfo_lut[0] = 15'h0000;
lfo_lut[1] = 15'h4000;
lfo_lut[2] = 15'h6000;
lfo_lut[3] = 15'h7000;
lfo_lut[4] = 15'h7800;
lfo_lut[5] = 15'h7c00;
lfo_lut[6] = 15'h7e00;
lfo_lut[7] = 15'h7f00;
lfo_lut[8] = 15'h7f80;
lfo_lut[9] = 15'h7fc0;
lfo_lut[10] = 15'h7fe0;
lfo_lut[11] = 15'h7ff0;
lfo_lut[12] = 15'h7ff8;
lfo_lut[13] = 15'h7ffc;
lfo_lut[14] = 15'h7ffe;
lfo_lut[15] = 15'h7fff;
end
endmodule

1
common/Sound/jt51/jt51_lin2exp.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_lin2exp(
input [15:0] lin,

31
common/Sound/jt51/jt51_mmr.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_mmr(
input rst,
@@ -29,6 +28,9 @@ module jt51_mmr(
input a0,
output reg busy,
// Original test bits
output reg [7:0] test_mode,
// CT
output reg ct1,
output reg ct2,
@@ -42,7 +44,7 @@ module jt51_mmr(
output reg [1:0] lfo_w,
output reg [6:0] lfo_amd,
output reg [6:0] lfo_pmd,
output reg lfo_rst,
output reg lfo_up,
// Timers
output reg [9:0] value_A,
output reg [7:0] value_B,
@@ -84,7 +86,9 @@ module jt51_mmr(
output op31_no,
output op31_acc,
output zero,
output zero, // high once per round
output half, // high twice per round
output [4:0] cycles,
output m1_enters,
output m2_enters,
output c1_enters,
@@ -105,8 +109,6 @@ reg up_rl, up_kc, up_kf, up_pms,
reg [1:0] up_op;
reg [2:0] up_ch;
wire busy_reg;
`ifdef SIMULATION
reg mmr_dump;
`endif
@@ -143,12 +145,13 @@ always @(posedge clk, posedge rst) begin : memory_mapped_registers
enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
// LFO
{ lfo_amd, lfo_pmd } <= 14'h0;
lfo_up <= 1'b0;
lfo_freq <= 8'd0;
lfo_w <= 2'd0;
lfo_rst <= 1'b0;
{ ct2, ct1 } <= 2'd0;
csm <= 1'b0;
din_copy <= 8'd0;
test_mode <= 8'd0;
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
@@ -176,7 +179,7 @@ always @(posedge clk, posedge rst) begin : memory_mapped_registers
if( selected_register < 8'h20 ) begin
case( selected_register)
// registros especiales
REG_TEST: lfo_rst <= 1'b1; // regardless of din
REG_TEST: test_mode <= din; // regardless of din
`ifdef TEST_SUPPORT
REG_TEST2: { test_op0, test_eg } <= din[1:0];
`endif
@@ -191,7 +194,10 @@ always @(posedge clk, posedge rst) begin : memory_mapped_registers
enable_irq_B, enable_irq_A,
load_B, load_A } <= din[5:0];
end
REG_LFRQ: lfo_freq <= din;
REG_LFRQ: begin
lfo_freq <= din;
lfo_up <= 1;
end
REG_PMDAMD: begin
if( !din[7] )
lfo_amd <= din[6:0];
@@ -237,8 +243,8 @@ always @(posedge clk, posedge rst) begin : memory_mapped_registers
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
csm <= 1'b0;
lfo_rst <= 1'b0;
csm <= 0;
lfo_up <= 0;
{ clr_flag_B, clr_flag_A } <= 2'd0;
end
end
@@ -287,7 +293,6 @@ jt51_reg u_reg(
.csm ( csm ),
.overflow_A ( overflow_A),
.busy ( busy_reg ),
.rl_I ( rl_I ),
.fb_II ( fb_II ),
.con_I ( con_I ),
@@ -315,6 +320,8 @@ jt51_reg u_reg(
.op31_no ( op31_no ),
.op31_acc ( op31_acc ),
.zero ( zero ),
.half ( half ),
.cycles ( cycles ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),
@@ -345,7 +352,7 @@ end
`endif
`ifndef JT51_NODEBUG
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;

1
common/Sound/jt51/jt51_mod.v
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT51.

120
common/Sound/jt51/jt51_noise.v
View File

@@ -12,84 +12,98 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
Date: 6-2-2021
*/
`timescale 1ns / 1ps
/*
tab size 4
See xapp052.pdf from Xilinx
The NFRQ formula in the App. Note does not make sense:
NFRQ formula in the App:
Output rate is 55kHz but for NFRQ=1 the formula states that
the noise is 111kHz, twice the output rate per channel.
the noise is 111kHz, twice the output rate per channel. The
reason must be the inversion of the LFSR data
That would suggest that the noise for LEFT and RIGHT are
different but the rest of the system suggest that LEFT and
RIGHT outputs are calculated at the same time, based on the
same OP output.
Also, the block diagram states a 1 bit serial input from
EG to NOISE and that seems unnecessary too.
I have not been able to measure noise in actual chip because
operator 31 does not produce any output on my two chips.
operator 31 does not produce any output on my two chips. This
module is based on NukeYKT's work
*/
module jt51_noise(
input rst,
input clk,
input cen,
input [4:0] nfrq,
input [9:0] eg,
input op31_no,
output reg [10:0] out
input rst,
input clk,
input cen, // phi 1
input [ 4:0] cycles,
// Noise Frequency
input [ 4:0] nfrq,
// Noise envelope
input [ 9:0] eg, // serial signal in the original design
input op31_no,
output out,
output reg [11:0] mix
);
reg update, nfrq_met;
reg [ 4:0] cnt;
reg [15:0] lfsr;
reg last_lfsr0;
wire all1, fb;
wire mix_sgn;
reg base;
reg [3:0] cnt;
assign out = lfsr[0];
always @(posedge clk, posedge rst)
// period counter
always @(posedge clk, posedge rst) begin
if( rst ) begin
cnt <= 4'b0;
end
else if(cen) begin
if( op31_no ) begin
if ( &cnt ) begin
cnt <= nfrq[4:1]; // we do not need to use nfrq[0]
// because I run it off P1, YM2151 probably ran off PM
// but the result is the same, as for NFREQ=31 the YM2151
// trips the noise output at each output sample, and for
// NFREQ=0 (or 1), the output trips every 16 samples
// so NFREQ[0] does not really add resolution
end
else cnt <= cnt + 4'b1;
base <= &cnt;
cnt <= 5'b0;
end else if(cen) begin
if( &cycles[3:0] ) begin
cnt <= update ? 5'd0 : (cnt+5'd1);
end
else base <= 1'b0;
update <= nfrq_met;
nfrq_met <= ~nfrq == cnt;
end
wire rnd_sign;
always @(posedge clk) if(cen) begin
if( op31_no )
out <= { rnd_sign, {10{~rnd_sign}}^eg };
end
jt51_noise_lfsr #(.init(90)) u_lfsr (
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.base ( base ),
.out ( rnd_sign )
);
// LFSR
assign fb = update ? ~((all1 & ~last_lfsr0) | (lfsr[2]^last_lfsr0))
: ~lfsr[0];
assign all1 = &lfsr;
always @(posedge clk, posedge rst) begin
if( rst ) begin
lfsr <= 16'hffff;
last_lfsr0 <= 1'b0;
end else if(cen) begin
lfsr <= { fb, lfsr[15:1] };
if(update) last_lfsr0 <= ~lfsr[0];
end
end
// Noise mix
assign mix_sgn = /*eg!=10'd0 ^*/ ~out;
always @(posedge clk, posedge rst) begin
if( rst ) begin
mix <= 12'd0;
end else if( op31_no && cen ) begin
mix <= { mix_sgn, eg[9:2] ^ {8{out}}, {3{mix_sgn}} };
end
end
endmodule

1
common/Sound/jt51/jt51_noise_lfsr.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
// See xapp052.pdf from Xilinx

3
common/Sound/jt51/jt51_op.v
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@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
// Pipeline operator
@@ -324,7 +323,7 @@ jt51_sh #( .width(1), .stages(3)) shsignbit(
);
/////////////////// Debug
`ifndef JT51_NODEBUG
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;

99
common/Sound/jt51/jt51_pg.v
View File

@@ -12,13 +12,12 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_pg(
input rst,
@@ -40,6 +39,10 @@ module jt51_pg(
input pg_rst_III,
output reg [ 4:0] keycode_III,
output [ 9:0] pg_phase_X
`ifdef JT51_PG_SIM
,output [19:0] phase_step_VII_out
,output [12:0] keycode_I_out
`endif
);
wire [19:0] ph_VII;
@@ -62,6 +65,11 @@ reg [2:0] pow2ind_IV;
reg [2:0] dt1_III, dt1_IV, dt1_V;
`ifdef JT51_PG_SIM
assign phase_step_VII_out = phase_step_VII;
assign keycode_I_out = keycode_I;
`endif
jt51_phinc_rom u_phinctable(
// .clk ( clk ),
.keycode( phinc_addr_III[9:0] ),
@@ -100,8 +108,8 @@ always @(*) begin : dt1_limit_mux
3'd5: dt1_unlimited = { pow2[4:0], 1'd0 };
default:dt1_unlimited = 6'd0;
endcase
dt1_limited_IV = dt1_unlimited > dt1_limit ?
dt1_limit[4:0] : dt1_unlimited[4:0];
dt1_limited_IV = dt1_unlimited > dt1_limit ?
dt1_limit[4:0] : dt1_unlimited[4:0];
end
reg signed [8:0] mod_I;
@@ -115,8 +123,8 @@ always @(*) begin
3'd4: mod_I = { 4'd0, pm[6:2] };
3'd5: mod_I = { 3'd0, pm[6:1] };
3'd6: mod_I = { 1'd0, pm[6:0], 1'b0 };
3'd7: mod_I = { pm[6:0], 2'b0 };
endcase
3'd7: mod_I = { pm[6:0], 2'b0 };
endcase
end
@@ -147,16 +155,18 @@ always @(posedge clk) if(cen) begin : phase_calculation
(keycode_I[7:6]==2'd3 ? 14'd64:14'd0);
2'd2: keycode_II <= { 1'b0, keycode_I } + 14'd628 +
(keycode_I[7:0]>dt2_lim2 ? 14'd64:14'd0);
2'd3: keycode_II <= { 1'b0, keycode_I } + 14'd800 +
2'd3: keycode_II <= { 1'b0, keycode_I } + 14'd800 +
(keycode_I[7:0]>dt2_lim3 ? 14'd64:14'd0);
endcase
end
// II
always @(posedge clk) if(cen) begin
always @(posedge clk) if(cen) begin
phinc_addr_III <= keycode_II[9:0];
octave_III <= keycode_II[13:10];
keycode_III <= keycode_II[12:8];
// Using bits 13:9 fixes Double Dragon issue #14
// but notes get too long in Jackal
case( dt1_II[1:0] )
2'd1: dt1_kf_III <= keycode_II[13:8] - (6'b1<<2);
2'd2: dt1_kf_III <= keycode_II[13:8] + (6'b1<<2);
@@ -166,7 +176,7 @@ always @(posedge clk) if(cen) begin
dt1_III <= dt1_II;
end
// III
// III
always @(posedge clk) if(cen) begin
case( octave_III )
4'd0: phase_base_IV <= { 8'd0, phinc_III[11:2] };
@@ -187,7 +197,7 @@ end
// IV LIMIT_BASE
always @(posedge clk) if(cen) begin
if( phase_base_IV > 18'd82976 )
if( phase_base_IV > 18'd82976 )
phase_base_V <= 18'd82976;
else
phase_base_V <= phase_base_IV;
@@ -219,11 +229,11 @@ end
always @(posedge clk, posedge rst) begin
if( rst )
ph_VIII <= 20'd0;
else if(cen) begin
else if(cen) begin
ph_VIII <= pg_rst_VII ? 20'd0 : ph_VII + phase_step_VII;
`ifdef DISPLAY_STEP
$display( "%d", phase_step_VII );
`endif
`endif
end
end
@@ -249,7 +259,7 @@ always @(posedge clk, posedge rst) begin
end
jt51_sh #( .width(20), .stages(32-3) ) u_phsh(
.rst ( rst ),
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( ph_X ),
@@ -264,33 +274,62 @@ jt51_sh #( .width(1), .stages(4) ) u_pgrstsh(
.drop ( pg_rst_VII)
);
`ifndef JT51_NODEBUG
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt));
// wire zero_VIII;
//
// jt51_sh #(.width(1),.stages(7)) u_sep_aux(
// .clk ( clk ),
// .din ( zero ),
// .drop ( zero_VIII )
// );
//
// sep32 #(.width(1),.stg(8)) sep_ref(
// .clk ( clk ),
// .cen(cen),
// .mixed ( zero_VIII ),
// .cnt ( cnt )
// );
sep32 #(.width(10),.stg(10)) sep_ph(
.clk ( clk ),
.cen(cen),
.cen ( cen ),
.mixed ( pg_phase_X ),
.cnt ( cnt )
);
);
sep32 #(.width(20),.stg(7)) sep_phstep(
.clk ( clk ),
.cen ( cen ),
.mixed ( phase_step_VII),
.cnt ( cnt )
);
sep32 #(.width(13),.stg(1)) sep_kc1(
.clk ( clk ),
.cen ( cen ),
.mixed ( keycode_I ),
.cnt ( cnt )
);
sep32 #(.width(14),.stg(2)) sep_kc2(
.clk ( clk ),
.cen ( cen ),
.mixed ( keycode_II ),
.cnt ( cnt )
);
sep32 #(.width(3),.stg(1)) sep_pms(
.clk ( clk ),
.cen ( cen ),
.mixed ( pms_I ),
.cnt ( cnt )
);
sep32 #(.width(18),.stg(4)) sep_base4(
.clk ( clk ),
.cen ( cen ),
.mixed ( phase_base_IV ),
.cnt ( cnt )
);
sep32 #(.width(18),.stg(5)) sep_base5(
.clk ( clk ),
.cen ( cen ),
.mixed ( phase_base_V ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif

1
common/Sound/jt51/jt51_phinc_rom.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_phinc_rom(
// input clk,

1
common/Sound/jt51/jt51_phrom.v
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT51.

73
common/Sound/jt51/jt51_pm.v
View File

@@ -12,84 +12,83 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_pm(
input [6:0] kc_I,
input [5:0] kf_I,
input [8:0] mod_I,
input add,
output reg [12:0] kcex
input [ 6:0] kc_I,
input [ 5:0] kf_I,
input [ 8:0] mod_I,
input add,
output reg [12:0] kcex
);
reg [9:0] lim;
reg [ 9:0] lim;
reg [13:0] kcex0, kcex1;
reg [1:0] extra;
reg [ 1:0] extra;
reg [6:0] kcin;
reg carry;
reg [ 6:0] kcin;
reg carry;
always @(*) begin: kc_input_cleaner
{ carry, kcin } = kc_I[1:0]==2'd3 ? { 1'b0, kc_I } + 8'd1 : {1'b0,kc_I};
{ carry, kcin } = kc_I[1:0]==2'd3 ? { 1'b0, kc_I } + 8'd1 : {1'b0,kc_I};
end
always @(*) begin : addition
lim = { 1'd0, mod_I } + { 4'd0, kf_I };
lim = { 1'd0, mod_I } + { 4'd0, kf_I };
case( kcin[3:0] )
default:
if( lim>=10'd448 ) extra = 2'd2;
default:
if( lim>=10'd448 ) extra = 2'd2;
else if( lim>=10'd256 ) extra = 2'd1;
else extra = 2'd0;
4'd1,4'd5,4'd9,4'd13:
if( lim>=10'd384 ) extra = 2'd2;
if( lim>=10'd384 ) extra = 2'd2;
else if( lim>=10'd192 ) extra = 2'd1;
else extra = 2'd0;
4'd2,4'd6,4'd10,4'd14:
if( lim>=10'd512 ) extra = 2'd3;
else if( lim>=10'd320 ) extra = 2'd2;
if( lim>=10'd512 ) extra = 2'd3;
else if( lim>=10'd320 ) extra = 2'd2;
else if( lim>=10'd128 ) extra = 2'd1;
else extra = 2'd0;
else extra = 2'd0;
endcase
kcex0 = {1'b0,kcin,kf_I} + { 6'd0, extra, 6'd0 } + { 5'd0, mod_I };
kcex1 = kcex0[7:6]==2'd3 ? kcex0 + 14'd64 : kcex0;
kcex1 = kcex0[7:6]==2'd3 ? kcex0 + 14'd64 : kcex0;
end
reg signed [9:0] slim;
reg [1:0] sextra;
reg [13:0] skcex0, skcex1;
reg signed [ 9:0] slim;
reg [ 1:0] sextra;
reg [13:0] skcex0, skcex1;
always @(*) begin : subtraction
slim = { 1'd0, mod_I } - { 4'd0, kf_I };
slim = { 1'd0, mod_I } - { 4'd0, kf_I };
case( kcin[3:0] )
default:
if( slim>=10'sd449 ) sextra = 2'd3;
else if( slim>=10'sd257 ) sextra = 2'd2;
default:
if( slim>=10'sd449 ) sextra = 2'd3;
else if( slim>=10'sd257 ) sextra = 2'd2;
else if( slim>=10'sd65 ) sextra = 2'd1;
else sextra = 2'd0;
4'd1,4'd5,4'd9,4'd13:
if( slim>=10'sd321 ) sextra = 2'd2;
if( slim>=10'sd321 ) sextra = 2'd2;
else if( slim>=10'sd129 ) sextra = 2'd1;
else sextra = 2'd0;
4'd2,4'd6,4'd10,4'd14:
if( slim>=10'sd385 ) sextra = 2'd2;
if( slim>=10'sd385 ) sextra = 2'd2;
else if( slim>=10'sd193 ) sextra = 2'd1;
else sextra = 2'd0;
else sextra = 2'd0;
endcase
skcex0 = {1'b0,kcin,kf_I} - { 6'd0, sextra, 6'd0 } - { 5'd0, mod_I };
skcex1 = skcex0[7:6]==2'd3 ? skcex0 - 14'd64 : skcex0;
end
always @(*) begin : mux
if ( add )
kcex = kcex1[13] | carry ? {3'd7, 4'd14, 6'd63} : kcex1[12:0];
if ( add )
kcex = kcex1[13] | carry ? {3'd7, 4'd14, 6'd63} : kcex1[12:0];
else
kcex = carry ? {3'd7, 4'd14, 6'd63} : (skcex1[13] ? 13'd0 : skcex1[12:0]);
kcex = carry ? {3'd7, 4'd14, 6'd63} : (skcex1[13] ? 13'd0 : skcex1[12:0]);
end
endmodule

23
common/Sound/jt51/jt51_reg.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_reg(
input rst,
@@ -43,7 +42,6 @@ module jt51_reg(
input csm,
input overflow_A,
output reg busy,
output [1:0] rl_I,
output [2:0] fb_II,
output [2:0] con_I,
@@ -68,6 +66,8 @@ module jt51_reg(
// Pipeline order
output reg zero,
output reg half,
output [4:0] cycles,
output reg m1_enters,
output reg m2_enters,
output reg c1_enters,
@@ -88,8 +88,8 @@ reg kon, koff;
reg [1:0] csm_state;
reg [4:0] csm_cnt;
wire csm_kon = csm_state[0];
wire csm_koff = csm_state[1];
// wire csm_kon = csm_state[0];
// wire csm_koff = csm_state[1];
always @(*) begin
m1_enters = cur_op == 2'b00;
@@ -98,8 +98,10 @@ always @(*) begin
c2_enters = cur_op == 2'b11;
end
`ifdef SIMULATION
wire up = up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
up_ks | up_amsen | up_dt2 | up_d1l | up_keyon;
`endif
reg [4:0] cur;
@@ -109,6 +111,7 @@ always @(posedge clk) if(cen) begin
end
assign cur_op = cur[4:3];
assign cycles = cur;
wire [4:0] req_I = { op, ch };
wire [4:0] req_II = req_I + 5'd1;
@@ -122,8 +125,8 @@ wire [4:0] req_VII = req_VI + 5'd1;
wire update_op_I = cur == req_I;
wire update_op_II = cur == req_II;
wire update_op_III = cur == req_III;
wire update_op_IV = cur == req_IV;
wire update_op_V = cur == req_V;
// wire update_op_IV = cur == req_IV;
// wire update_op_V = cur == req_V;
wire update_op_VI = cur == req_VI;
wire update_op_VII = cur == req_VII;
@@ -155,12 +158,12 @@ always @(posedge clk, posedge rst) begin : up_counter
if( rst ) begin
cur <= 5'h0;
zero <= 1'b0;
busy <= 1'b0;
half <= 1'b0;
end
else if(cen) begin
cur <= next;
zero <= next== 5'd0;
if( &cur ) busy <= up && !busy;
half <= next[3:0] == 4'd0;
end
end
@@ -176,7 +179,7 @@ jt51_kon u_kon (
.keyon_ch (keyon_ch ),
.cur_op (cur_op ),
.cur_ch (cur_ch ),
.up_keyon (up_keyon && busy ),
.up_keyon (up_keyon ),
.csm (csm ),
.overflow_A(overflow_A),
.keyon_II (keyon_II )
@@ -252,7 +255,7 @@ jt51_csr_ch u_csr_ch(
);
//////////////////// Debug
`ifndef JT51_NODEBUG
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;

1
common/Sound/jt51/jt51_sh.v
View File

@@ -18,7 +18,6 @@
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_sh #(parameter width=5, stages=32, rstval=1'b0 ) (
input rst,

57
common/Sound/jt51/jt51_timers.v
View File

@@ -12,13 +12,11 @@
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_timers(
input rst,
@@ -41,24 +39,24 @@ module jt51_timers(
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
jt51_timer #(.counter_width(10)) timer_A(
jt51_timer #(.CW(10)) timer_A(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.start_value( value_A ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.flag ( flag_A ),
.overflow ( overflow_A)
);
jt51_timer #(.counter_width(12)) timer_B(
jt51_timer #(.CW(8),.FREE_EN(1)) timer_B(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.clk ( clk ),
.cen ( cen ),
.zero ( zero ),
.start_value( {value_B,4'b0}),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B ),
.flag ( flag_B ),
@@ -67,21 +65,25 @@ jt51_timer #(.counter_width(12)) timer_B(
endmodule
module jt51_timer #(parameter counter_width = 10 )
(
module jt51_timer #(parameter
CW = 8, // counter bit width. This is the counter that can be loaded
FREE_EN = 0 // enables a 4-bit free enable count
) (
input rst,
input clk,
input cen,
input zero,
input [counter_width-1:0] start_value,
input clk,
input cen,
input zero,
input [CW-1:0] start_value,
input load,
input clr_flag,
output reg flag,
output reg overflow
);
reg last_load;
reg [counter_width-1:0] cnt, next;
reg last_load;
reg [CW-1:0] cnt, next;
reg [ 3:0] free_cnt, free_next;
reg free_ov;
always@(posedge clk, posedge rst)
if( rst )
@@ -93,14 +95,27 @@ always@(posedge clk, posedge rst)
end
always @(*) begin
{overflow, next } = { 1'b0, cnt } + 1'b1;
{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
/* verilator lint_off WIDTH */
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
/* verilator lint_on WIDTH */
end
always @(posedge clk) if(cen && zero) begin : counter
last_load <= load;
if( (load && !last_load) || overflow ) begin
cnt <= start_value;
end
end
else if( last_load ) cnt <= next;
end
// Free running counter
always @(posedge clk) begin
if( rst ) begin
free_cnt <= 4'd0;
end else if( cen&&zero ) begin
free_cnt <= free_next;
end
end
endmodule