diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf
index 2e0f1e35..619cb3ac 100644
Binary files a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf and b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf differ
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv
index 300bb245..e554ea09 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv
@@ -45,7 +45,7 @@ wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
- .c0(clk_sys)//11
+ .c0(clk_sys)
);
wire [31:0] status;
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_h.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_h.vhd
index 6dc9cd70..c55e597e 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_h.vhd
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_h.vhd
@@ -4,30 +4,22 @@ use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity col_h is
port (
clk : in std_logic;
- addr : in std_logic_vector(7 downto 0);
- data : out std_logic_vector(7 downto 0)
+ addr : in std_logic_vector(6 downto 0);
+ data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of col_h is
- type rom is array(0 to 255) of std_logic_vector(7 downto 0);
- signal rom_data: rom := (
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"06",X"05",X"03",X"05",X"06",X"06",X"06",
- X"01",X"03",X"03",X"06",X"02",X"03",X"03",X"03",X"07",X"05",X"05",X"03",X"07",X"05",X"05",X"05",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"03",X"03",X"03",X"01",X"04",
- X"06",X"05",X"05",X"07",X"07",X"07",X"07",X"03",X"06",X"07",X"07",X"05",X"05",X"05",X"03",X"07",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"05",X"03",X"03",X"03",X"03",X"03",
- X"01",X"03",X"03",X"06",X"06",X"06",X"06",X"06",X"05",X"05",X"05",X"03",X"05",X"05",X"05",X"05",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"04",X"04",X"04",X"03",X"04",
- X"06",X"05",X"05",X"05",X"05",X"05",X"07",X"03",X"05",X"07",X"07",X"07",X"07",X"07",X"05",X"07",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+ type rom is array(0 to 127) of std_logic_vector(3 downto 0);
+ signal rom_data: rom := (
+ "0000","0000","0000","0000","0000","0000","0000","0000","0010","0110","0101","0011","0101","0110","0110","0110",
+ "0001","0011","0011","0110","0010","0011","0011","0011","0111","0101","0101","0011","0111","0101","0101","0101",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0011","0011","0011","0001","0100",
+ "0110","0101","0101","0111","0111","0111","0111","0011","0110","0111","0111","0101","0101","0101","0011","0111",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0101","0011","0011","0011","0011","0011",
+ "0001","0011","0011","0110","0110","0110","0110","0110","0101","0101","0101","0011","0101","0101","0101","0101",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0100","0100","0100","0011","0100",
+ "0110","0101","0101","0101","0101","0101","0111","0011","0101","0111","0111","0111","0111","0111","0101","0111");
begin
process(clk)
begin
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_l.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_l.vhd
index d5a1d7dd..9c6aa0b0 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_l.vhd
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/col_l.vhd
@@ -4,30 +4,22 @@ use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity col_l is
port (
clk : in std_logic;
- addr : in std_logic_vector(7 downto 0);
- data : out std_logic_vector(7 downto 0)
+ addr : in std_logic_vector(6 downto 0);
+ data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of col_l is
- type rom is array(0 to 255) of std_logic_vector(7 downto 0);
+ type rom is array(0 to 127) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"04",X"02",X"05",X"02",X"02",X"02",
- X"00",X"01",X"02",X"00",X"02",X"01",X"01",X"01",X"00",X"01",X"01",X"01",X"06",X"04",X"04",X"04",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"03",X"03",X"03",X"01",X"00",
- X"02",X"05",X"05",X"01",X"01",X"01",X"07",X"00",X"06",X"07",X"07",X"05",X"05",X"05",X"03",X"07",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"04",X"02",X"01",X"01",X"01",X"01",
- X"00",X"01",X"02",X"00",X"02",X"02",X"02",X"02",X"00",X"01",X"01",X"01",X"04",X"04",X"04",X"04",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"04",X"04",X"04",X"03",X"04",
- X"02",X"05",X"05",X"05",X"05",X"05",X"07",X"00",X"05",X"07",X"07",X"03",X"03",X"03",X"05",X"07",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
- X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+ "0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0100","0010","0101","0010","0010","0010",
+ "0000","0001","0010","0000","0010","0001","0001","0001","0000","0001","0001","0001","0110","0100","0100","0100",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0011","0011","0011","0001","0000",
+ "0010","0101","0101","0001","0001","0001","0111","0000","0110","0111","0111","0101","0101","0101","0011","0111",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0100","0010","0001","0001","0001","0001",
+ "0000","0001","0010","0000","0010","0010","0010","0010","0000","0001","0001","0001","0100","0100","0100","0100",
+ "0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0100","0100","0100","0011","0100",
+ "0010","0101","0101","0101","0101","0101","0111","0000","0101","0111","0111","0011","0011","0011","0101","0111");
begin
process(clk)
begin
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd
index e2f40e65..af5ed868 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/phoenix.vhd
@@ -80,7 +80,7 @@ architecture struct of phoenix is
signal frgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
signal bkgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
- signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0');
+ signal palette_adr : std_logic_vector( 6 downto 0) := (others =>'0');
signal A11 : std_logic;
signal frgnd_clk : std_logic;
@@ -107,10 +107,8 @@ architecture struct of phoenix is
signal bk_lin : std_logic_vector(2 downto 0);
signal color_set : std_logic;
- signal color_set2 : std_logic;
signal color_id : std_logic_vector(5 downto 0);
- signal rgb_0 : std_logic_vector(7 downto 0);
- signal rgb_1 : std_logic_vector(7 downto 0);
+ signal rgb : std_logic_vector(7 downto 0);
signal player2 : std_logic := '0';
signal pl2_cocktail : std_logic := '0';
@@ -137,7 +135,7 @@ coin <= not btn_coin; -- insert coin
player_start <= not btn_player_start; -- select 1 or 2 players
buttons(1) <= not btn_right; -- Right
buttons(2) <= not btn_left; -- Left
-buttons(3) <= not btn_barrier; -- Protection
+buttons(3) <= '1'; -- Protection
G_not_autofire: if not C_autofire generate
buttons(0) <= not btn_fire; -- Fire
@@ -229,7 +227,6 @@ begin
when "11010" => sound_a <= cpu_do;
when "10100" => player2 <= cpu_do(0);
color_set <= cpu_do(1);
- color_set2 <= cpu_do(2);
A11 <= cpu_do(3);
when others => null;
end case;
@@ -288,7 +285,7 @@ color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
-- address palette with pixel bits color and color set
-palette_adr <= color_set2 & color_set & color_id;
+palette_adr <= color_set & color_id;
-- output video to top level
-- output video to top level
process(clk) begin
@@ -298,9 +295,9 @@ process(clk) begin
video_hblank_fg <= hblank_frgrd;
video_hblank_bg <= hblank_bkgrd;
if hcnt>=192 then
- video_r <= rgb_1(0) & rgb_0(0);
- video_g <= rgb_1(2) & rgb_0(2);
- video_b <= rgb_1(1) & rgb_0(1);
+ video_r <= rgb(4) & rgb(0);
+ video_g <= rgb(6) & rgb(2);
+ video_b <= rgb(5) & rgb(1);
else
video_r <= "00";
video_g <= "00";
@@ -338,18 +335,18 @@ port map(
data => bkgnd_bit1_graph
);
-col_l : entity work.col_l
+col_l : entity work.col_h
port map(
clk => clk,
- addr => palette_adr(7 downto 0),
- data => rgb_0
+ addr => palette_adr,
+ data => rgb(3 downto 0)
);
-col_h : entity work.col_h
+col_h : entity work.col_l
port map(
clk => clk,
- addr => palette_adr(7 downto 0),
- data => rgb_1
+ addr => palette_adr,
+ data => rgb(7 downto 4)
);
-- Program PROM
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf
index 55f387da..2dc9dced 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.ppf
@@ -5,6 +5,7 @@
+
diff --git a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd
index cf6d2d12..1c661cbc 100644
--- a/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd
+++ b/Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/pll.vhd
@@ -44,7 +44,8 @@ ENTITY pll IS
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC
);
END pll;
@@ -54,9 +55,10 @@ ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire3 : STD_LOGIC ;
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -67,6 +69,10 @@ ARCHITECTURE SYN OF pll IS
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
+ clk1_divide_by : NATURAL;
+ clk1_duty_cycle : NATURAL;
+ clk1_multiply_by : NATURAL;
+ clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
@@ -125,12 +131,14 @@ ARCHITECTURE SYN OF pll IS
END COMPONENT;
BEGIN
- sub_wire4_bv(0 DOWNTO 0) <= "0";
- sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
- sub_wire1 <= sub_wire0(0);
- c0 <= sub_wire1;
- sub_wire2 <= inclk0;
- sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+ sub_wire5_bv(0 DOWNTO 0) <= "0";
+ sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
+ sub_wire2 <= sub_wire0(0);
+ sub_wire1 <= sub_wire0(1);
+ c1 <= sub_wire1;
+ c0 <= sub_wire2;
+ sub_wire3 <= inclk0;
+ sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
@@ -139,6 +147,10 @@ BEGIN
clk0_duty_cycle => 50,
clk0_multiply_by => 11,
clk0_phase_shift => "0",
+ clk1_divide_by => 27,
+ clk1_duty_cycle => 50,
+ clk1_multiply_by => 22,
+ clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
@@ -172,7 +184,7 @@ BEGIN
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
- port_clk1 => "PORT_UNUSED",
+ port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
@@ -191,7 +203,7 @@ BEGIN
)
PORT MAP (
areset => areset,
- inclk => sub_wire3,
+ inclk => sub_wire4,
clk => sub_wire0
);
@@ -219,8 +231,11 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "22.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -241,18 +256,26 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "22"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "11"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "44"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "11.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "22.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -275,11 +298,14 @@ END SYN;
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -288,6 +314,10 @@ END SYN;
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "22"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -320,7 +350,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -340,11 +370,13 @@ END SYN;
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
diff --git a/common/mist/osd.v b/common/mist/osd.v
index 5527e729..44ecc713 100644
--- a/common/mist/osd.v
+++ b/common/mist/osd.v
@@ -96,7 +96,7 @@ wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
-always @(negedge clk_sys) begin
+always @(posedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
@@ -110,7 +110,8 @@ always @(negedge clk_sys) begin
if(hs && ~HSync) begin
cnt <= 0;
- pixsz <= (cnt >> 9) - 1;
+ if (cnt <= 512) pixsz = 0;
+ else pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end