diff --git a/.gitignore b/.gitignore index fc217d13..733c0198 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,10 @@ - +PLLJ_PLLSPE_INFO.txt +db/ +incremental_db/ +output_files/ +greybox_tmp/ +build_id.v +*.bak Robotron - Z1013_MiST/Z1013_Mist.pti_db_list.ddb Robotron - Z1013_MiST/Z1013_Mist.tis_db_list.ddb Sharp - MZ-80K_MiST/mz80k.qws diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore new file mode 100644 index 00000000..2fe317a8 --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/.gitignore @@ -0,0 +1 @@ +Output/ diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf index 77989ab8..ef0ae35c 100644 Binary files a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf and b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf differ diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf index 463ae56c..70e61ae1 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf @@ -81,45 +81,34 @@ set_location_assignment PIN_127 -to SPI_SS2 set_location_assignment PIN_91 -to SPI_SS3 set_location_assignment PIN_90 -to SPI_SS4 set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO # Classic Timing Assignments # ========================== @@ -165,7 +154,7 @@ set_global_assignment -name GENERATE_RBF_FILE ON # SignalTap II Assignments # ======================== -set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp # Advanced I/O Timing Assignments @@ -183,9 +172,9 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # Incremental Compilation Assignments # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- @@ -196,9 +185,15 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE src/bitmapctl_e.vhd +set_global_assignment -name VHDL_FILE src/tilemapctl_e.vhd +set_global_assignment -name VHDL_FILE src/target_pkg.vhd +set_global_assignment -name VHDL_FILE src/project_pkg.vhd +set_global_assignment -name VHDL_FILE src/platform_pkg.vhd set_global_assignment -name VHDL_FILE src/mpatrol.vhd +set_global_assignment -name VHDL_FILE src/video_mixer.vhd set_global_assignment -name VHDL_FILE src/platform_variant_pkg.vhd set_global_assignment -name VHDL_FILE src/spritereg.vhd set_global_assignment -name VHDL_FILE src/spritectl.vhd @@ -209,6 +204,7 @@ set_global_assignment -name VHDL_FILE src/video_controller_pkg.vhd set_global_assignment -name VHDL_FILE src/video_controller.vhd set_global_assignment -name VHDL_FILE src/moon_patrol_sound_board.vhd set_global_assignment -name VHDL_FILE src/moon_patrol_sound_prog.vhd +set_global_assignment -name SYSTEMVERILOG_FILE src/YM2149.sv set_global_assignment -name VHDL_FILE src/cpu68.vhd set_global_assignment -name VHDL_FILE src/tilemapctl.vhd set_global_assignment -name VHDL_FILE src/t80/Z80.vhd @@ -218,9 +214,7 @@ set_global_assignment -name VHDL_FILE src/t80/T80_Pack.vhd set_global_assignment -name VHDL_FILE src/t80/T80_MCode.vhd set_global_assignment -name VHDL_FILE src/t80/T80_ALU.vhd set_global_assignment -name VHDL_FILE src/t80/T80.vhd -set_global_assignment -name VHDL_FILE src/video_mixer.vhd set_global_assignment -name VHDL_FILE src/dac.vhd -set_global_assignment -name VHDL_FILE src/YM2149_linmix_sep.vhd set_global_assignment -name VHDL_FILE src/sprom.vhd set_global_assignment -name VHDL_FILE src/spram.vhd set_global_assignment -name VHDL_FILE src/platform.vhd @@ -237,9 +231,8 @@ set_global_assignment -name VHDL_FILE src/bitmap2_ctl.vhd set_global_assignment -name VHDL_FILE src/bitmap1_ctl.vhd set_global_assignment -name VHDL_FILE src/i82c55.vhd set_global_assignment -name VERILOG_FILE src/keyboard.v -set_global_assignment -name SYSTEMVERILOG_FILE src/hq2x.sv set_global_assignment -name VERILOG_FILE src/scandoubler.v -set_global_assignment -name SYSTEMVERILOG_FILE src/video_mist.sv +set_global_assignment -name SYSTEMVERILOG_FILE src/rgb2ypbpr.sv set_global_assignment -name VERILOG_FILE src/osd.v set_global_assignment -name VERILOG_FILE src/mist_io.v set_global_assignment -name VHDL_FILE src/sprite_array.vhd diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc new file mode 100644 index 00000000..3fb2db8c --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc @@ -0,0 +1,126 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd index 9f7ae625..eca8cdab 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd @@ -157,21 +157,21 @@ BEGIN altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", - clk0_divide_by => 603, + clk0_divide_by => 1350, clk0_duty_cycle => 50, - clk0_multiply_by => 80, + clk0_multiply_by => 179, clk0_phase_shift => "0", - clk1_divide_by => 18, + clk1_divide_by => 9, clk1_duty_cycle => 50, - clk1_multiply_by => 5, + clk1_multiply_by => 2, clk1_phase_shift => "0", clk2_divide_by => 9, clk2_duty_cycle => 50, - clk2_multiply_by => 10, + clk2_multiply_by => 8, clk2_phase_shift => "0", - clk3_divide_by => 27, + clk3_divide_by => 208, clk3_duty_cycle => 50, - clk3_multiply_by => 40, + clk3_multiply_by => 185, clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, @@ -251,18 +251,18 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "603" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "18" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1396" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "208" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.582090" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "30.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.580000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.014423" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -283,7 +283,7 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" @@ -291,18 +291,18 @@ END SYN; -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "80" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "40" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "185" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "37" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "185" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.58000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.50000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "30.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" @@ -316,7 +316,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" @@ -359,21 +359,21 @@ END SYN; -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "603" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1350" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "18" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "208" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "185" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD index 9c24ca4e..f057e365 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD @@ -7,77 +7,100 @@ library work; use work.pace_pkg.all; use work.video_controller_pkg.all; use work.sprite_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; entity Graphics is port ( - bitmap_ctl_i : in to_BITMAP_CTL_a(1 to 3); - bitmap_ctl_o : out from_BITMAP_CTL_a(1 to 3); - tilemap_ctl_i : in to_TILEMAP_CTL_a(1 to 1); - tilemap_ctl_o : out from_TILEMAP_CTL_a(1 to 1); - sprite_reg_i : in to_SPRITE_REG_t; - sprite_ctl_i : in to_SPRITE_CTL_t; - sprite_ctl_o : out from_SPRITE_CTL_t; - spr0_hit : out std_logic; - graphics_i : in to_GRAPHICS_t; - graphics_o : out from_GRAPHICS_t; - video_i : in from_VIDEO_t; - video_o : out to_VIDEO_t + bitmap_ctl_i : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + bitmap_ctl_o : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + tilemap_ctl_i : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + tilemap_ctl_o : out from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + + sprite_reg_i : in to_SPRITE_REG_t; + sprite_ctl_i : in to_SPRITE_CTL_t; + sprite_ctl_o : out from_SPRITE_CTL_t; + spr0_hit : out std_logic; + + graphics_i : in to_GRAPHICS_t; + graphics_o : out from_GRAPHICS_t; + + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t ); end Graphics; architecture SYN of Graphics is - alias clk : std_logic is video_i.clk; - signal from_video_ctl : from_VIDEO_CTL_t; - signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to 3); - signal tilemap_ctl_o_s : from_TILEMAP_CTL_a(1 to 1); - signal sprite_ctl_o_s : from_SPRITE_CTL_t; - signal sprite_pri : std_logic; - signal rgb_data : RGB_t; - signal video_o_s : to_VIDEO_t; + alias clk : std_logic is video_i.clk; + + signal from_video_ctl : from_VIDEO_CTL_t; + signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + signal tilemap_ctl_o_s : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + signal sprite_ctl_o_s : from_SPRITE_CTL_t; + signal sprite_pri : std_logic; + + signal osd_active : std_logic; + signal osd_colour : std_logic_vector(7 downto 0); + + signal rgb_data : RGB_t; + -- before OSD is mixed in + signal video_o_s : to_VIDEO_t; begin - video_o.clk <= video_o_s.clk; - video_o.rgb.r <= video_o_s.rgb.r; - video_o.rgb.g <= video_o_s.rgb.g; - video_o.rgb.b <= video_o_s.rgb.b; - video_o.hsync <= video_o_s.hsync; - video_o.vsync <= video_o_s.vsync; - video_o.hblank <= video_o_s.hblank; - video_o.vblank <= video_o_s.vblank; - graphics_o.y <= from_video_ctl.y; - graphics_o.hblank <= video_o_s.hblank; - graphics_o.vblank <= video_o_s.vblank; + -- dodgy OSD transparency... + video_o.clk <= video_o_s.clk; + video_o.rgb.r <= video_o_s.rgb.r; + video_o.rgb.g <= video_o_s.rgb.g; + video_o.rgb.b <= video_o_s.rgb.b; + video_o.hsync <= video_o_s.hsync; + video_o.vsync <= video_o_s.vsync; + video_o.hblank <= video_o_s.hblank; + video_o.vblank <= video_o_s.vblank; + + graphics_o.y <= from_video_ctl.y; + -- should this be the 'real' vblank or the 'active' vblank? + -- - use the real for now + graphics_o.hblank <= video_o_s.hblank; + graphics_o.vblank <= video_o_s.vblank; + --graphics_o.vblank <= from_video_ctl.vblank; pace_video_controller_inst : entity work.pace_video_controller generic map ( - CONFIG => PACE_VIDEO_VGA_800x600_60Hz, - DELAY => 7, - H_SIZE => 256, - V_SIZE => 256, - L_CROP => 0,--8 - R_CROP => 0,--8 - H_SCALE => 2,--2 - V_SCALE => 2,--2 - H_SYNC_POL => '1',--1 - V_SYNC_POL => '1',--1 - BORDER_RGB => RGB_BLACK + CONFIG => PACE_VIDEO_CONTROLLER_TYPE, + DELAY => PACE_VIDEO_PIPELINE_DELAY, + H_SIZE => PACE_VIDEO_H_SIZE, + V_SIZE => PACE_VIDEO_V_SIZE, + L_CROP => PACE_VIDEO_L_CROP, + R_CROP => PACE_VIDEO_R_CROP, + H_SCALE => PACE_VIDEO_H_SCALE, + V_SCALE => PACE_VIDEO_V_SCALE, + H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY, + V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY, + BORDER_RGB => PACE_VIDEO_BORDER_RGB ) port map ( - video_i => video_i, - reg_i.h_scale => "000", - reg_i.v_scale => "000", + -- clocking etc + video_i => video_i, + + -- register interface + reg_i.h_scale => "000", + reg_i.v_scale => "000", + -- video data signals (in) rgb_i => rgb_data, - video_ctl_o => from_video_ctl, + + -- video control signals (out) + video_ctl_o => from_video_ctl, + + -- VGA signals (out) video_o => video_o_s ); - pace_video_mixer_inst : entity work.pace_video_mixer port map ( @@ -91,93 +114,161 @@ begin graphics_i => graphics_i, rgb_o => rgb_data ); - + + GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate + --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); + end generate GEN_NO_BITMAPS; - forground_bitmapctl_inst1 : entity work.BITMAP_1 + GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1) generic map ( - DELAY => 7 + DELAY => PACE_VIDEO_PIPELINE_DELAY ) port map ( - reset => video_i.reset, - video_ctl => from_video_ctl, - ctl_i => bitmap_ctl_i(1), - ctl_o => bitmap_ctl_o_s(1), - graphics_i => graphics_i + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => bitmap_ctl_i(1), + ctl_o => bitmap_ctl_o_s(1), + + graphics_i => graphics_i ); + end generate GEN_BITMAP_1; - forground_bitmapctl_inst2 : entity work.BITMAP_2 + GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2) generic map ( - DELAY => 7 + DELAY => PACE_VIDEO_PIPELINE_DELAY ) port map ( - reset => video_i.reset, - video_ctl => from_video_ctl, - ctl_i => bitmap_ctl_i(2), - ctl_o => bitmap_ctl_o_s(2), - graphics_i => graphics_i - ); + reset => video_i.reset, + + video_ctl => from_video_ctl, + ctl_i => bitmap_ctl_i(2), + ctl_o => bitmap_ctl_o_s(2), - forground_bitmapctl_inst3 : entity work.BITMAP_3 - generic map - ( - DELAY => 7 - ) - port map - ( - reset => video_i.reset, - video_ctl => from_video_ctl, - ctl_i => bitmap_ctl_i(3), - ctl_o => bitmap_ctl_o_s(3), - graphics_i => graphics_i + graphics_i => graphics_i ); - - bitmap_ctl_o <= bitmap_ctl_o_s; + end generate GEN_BITMAP_2; - - foreground_mapctl_inst : entity work.TILEMAP_1 + GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3) generic map ( - DELAY => 7 + DELAY => PACE_VIDEO_PIPELINE_DELAY ) port map ( - reset => video_i.reset, - video_ctl => from_video_ctl, - ctl_i => tilemap_ctl_i(1), - ctl_o => tilemap_ctl_o_s(1), - graphics_i => graphics_i + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => bitmap_ctl_i(3), + ctl_o => bitmap_ctl_o_s(3), + + graphics_i => graphics_i ); + + end generate GEN_BITMAP_3; + + bitmap_ctl_o <= bitmap_ctl_o_s; + + GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate + --tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'), + -- (others => (others => '0')), '0'); + end generate GEN_NO_TILEMAPS; + + GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate + + foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => tilemap_ctl_i(1), + ctl_o => tilemap_ctl_o_s(1), + + graphics_i => graphics_i + ); + + end generate GEN_TILEMAP_1; + + GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate + + background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => tilemap_ctl_i(2), + ctl_o => tilemap_ctl_o_s(2), + + graphics_i => graphics_i + ); + + end generate GEN_TILEMAP_2; tilemap_ctl_o <= tilemap_ctl_o_s; + GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate + sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); + sprite_pri <= '0'; + spr0_hit <= '0'; + end generate GEN_NO_SPRITES; + + GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate + sprites_inst : sprite_array - generic map + generic map ( - N_SPRITES => 64, - DELAY => 7 + N_SPRITES => PACE_VIDEO_NUM_SPRITES, + DELAY => PACE_VIDEO_PIPELINE_DELAY ) port map ( - reset => video_i.reset, - reg_i => sprite_reg_i, - video_ctl => from_video_ctl, - graphics_i => graphics_i, - row_a => sprite_ctl_o_s.a, - row_d => sprite_ctl_i.d, - rgb => sprite_ctl_o_s.rgb, - set => sprite_ctl_o_s.set, - pri => sprite_pri, - spr0_set => spr0_hit + reset => video_i.reset, + + -- register interface + reg_i => sprite_reg_i, + + -- video control signals + video_ctl => from_video_ctl, + + graphics_i => graphics_i, + + row_a => sprite_ctl_o_s.a, + row_d => sprite_ctl_i.d, + + rgb => sprite_ctl_o_s.rgb, + set => sprite_ctl_o_s.set, + pri => sprite_pri, + spr0_set => spr0_hit ); + end generate GEN_SPRITES; sprite_ctl_o <= sprite_ctl_o_s; - end SYN; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149.sv b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149.sv new file mode 100644 index 00000000..eae73bb3 --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149.sv @@ -0,0 +1,329 @@ +// +// Copyright (c) MikeJ - Jan 2005 +// Copyright (c) 2016-2018 Sorgelig +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + + +// BDIR BC MODE +// 0 0 inactive +// 0 1 read value +// 1 0 write value +// 1 1 set address +// + +module YM2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input A8, + input A9_L, + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + output [5:0] ACTIVE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign ACTIVE = ~ymreg[7][5:0]; +assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; +assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; + +reg [7:0] addr; +reg [7:0] ymreg[16]; +wire cs = !A9_L & A8; + +// Write to PSG +reg env_reset; +always @(posedge CLK) begin + if(RESET) begin + ymreg <= '{default:0}; + ymreg[7] <= '1; + addr <= '0; + env_reset <= 0; + end else begin + env_reset <= 0; + if(cs & BDIR) begin + if(BC) addr <= DI; + else if(!addr[7:4]) begin + ymreg[addr[3:0]] <= DI; + env_reset <= (addr == 13); + end + end + end +end + +// Read from PSG +assign DO = dout; +reg [7:0] dout; +always_comb begin + dout = 8'hFF; + if(cs & ~BDIR & BC & !addr[7:4]) begin + case(addr[3:0]) + 0: dout = ymreg[0]; + 1: dout = ymreg[1][3:0]; + 2: dout = ymreg[2]; + 3: dout = ymreg[3][3:0]; + 4: dout = ymreg[4]; + 5: dout = ymreg[5][3:0]; + 6: dout = ymreg[6][4:0]; + 7: dout = ymreg[7]; + 8: dout = ymreg[8][4:0]; + 9: dout = ymreg[9][4:0]; + 10: dout = ymreg[10][4:0]; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = ymreg[13][3:0]; + 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; + 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; + endcase + end +end + +reg ena_div; +reg ena_div_noise; + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [2:0] noise_gen_op; + +// p_noise_gen +always @(posedge CLK) begin + reg [16:0] poly17; + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + noise_gen_op <= {3{poly17[0]}}; + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_freq[i]) begin + if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= ~tone_gen_op[i]; + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end else begin + tone_gen_op[i] <= ymreg[7][i]; + tone_gen_cnt[i] <= 0; + end + end + end + end +end + +reg env_ena; +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +reg [4:0] env_vol; + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(env_reset | RESET) begin + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end + else if(CE) begin + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end +end + +reg [5:0] A,B,C; +always @(posedge CLK) begin + A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; + B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; + C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; +end + +wire [7:0] volTable[64] = '{ + //YM2149 + 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, + + //AY8910 + 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, + 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, + 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, + 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff +}; + +assign CHANNEL_A = volTable[A]; +assign CHANNEL_B = volTable[B]; +assign CHANNEL_C = volTable[C]; + +endmodule diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd deleted file mode 100644 index 6ed2498a..00000000 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd +++ /dev/null @@ -1,574 +0,0 @@ --- changes for seperate audio outputs and enable now enables cpu access as well --- --- A simulation model of YM2149 (AY-3-8910 with bells on) - --- Copyright (c) MikeJ - Jan 2005 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 001 initial release --- --- Clues from MAME sound driver and Kazuhiro TSUJIKAWA --- --- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) --- vol 15 .. 0 --- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 --- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order --- to produced all the required values. --- (The first part of the curve is a bit steeper and the last bit is more linear than expected) --- --- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only --- accurate for designs where the outputs are buffered and not simply wired together. --- The ouput level is more complex in that case and requires a larger table. - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity YM2149 is - port ( - -- data bus - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - O_DA_OE_L : out std_logic; - -- control - I_A9_L : in std_logic; - I_A8 : in std_logic; - I_BDIR : in std_logic; - I_BC2 : in std_logic; - I_BC1 : in std_logic; - I_SEL_L : in std_logic; - - O_AUDIO : out std_logic_vector(7 downto 0); - O_CHAN : out std_logic_vector(1 downto 0); - -- port a - I_IOA : in std_logic_vector(7 downto 0); - O_IOA : out std_logic_vector(7 downto 0); - O_IOA_OE_L : out std_logic; - -- port b - I_IOB : in std_logic_vector(7 downto 0); - O_IOB : out std_logic_vector(7 downto 0); - O_IOB_OE_L : out std_logic; - - ENA : in std_logic; -- clock enable for higher speed operation - RESET_L : in std_logic; - CLK : in std_logic -- note 6 Mhz - ); -end; - -architecture RTL of YM2149 is - type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); - type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); - - signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); - signal cnt_div_t1 : std_logic_vector(3 downto 0); - signal noise_div : std_logic := '0'; - signal ena_div : std_logic; - signal ena_div_noise : std_logic; - signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); - - -- registers - signal addr : std_logic_vector(7 downto 0); - signal busctrl_addr : std_logic; - signal busctrl_we : std_logic; - signal busctrl_re : std_logic; - - signal reg : array_16x8; - signal env_reset : std_logic; - signal ioa_inreg : std_logic_vector(7 downto 0); - signal iob_inreg : std_logic_vector(7 downto 0); - - signal noise_gen_cnt : std_logic_vector(4 downto 0); - signal noise_gen_op : std_logic; - signal tone_gen_cnt : array_3x12 := (others => (others => '0')); - signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; - - signal env_gen_cnt : std_logic_vector(15 downto 0); - signal env_ena : std_logic; - signal env_hold : std_logic; - signal env_inc : std_logic; - signal env_vol : std_logic_vector(4 downto 0); - - signal tone_ena_l : std_logic; - signal tone_src : std_logic; - signal noise_ena_l : std_logic; - signal chan_vol : std_logic_vector(4 downto 0); - - signal dac_amp : std_logic_vector(7 downto 0); -begin - -- cpu i/f - p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) - variable cs : std_logic; - variable sel : std_logic_vector(2 downto 0); - begin - -- BDIR BC2 BC1 MODE - -- 0 0 0 inactive - -- 0 0 1 address - -- 0 1 0 inactive - -- 0 1 1 read - -- 1 0 0 address - -- 1 0 1 inactive - -- 1 1 0 write - -- 1 1 1 read - busctrl_addr <= '0'; - busctrl_we <= '0'; - busctrl_re <= '0'; - - cs := '0'; - if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then - cs := '1'; - end if; - - sel := (I_BDIR & I_BC2 & I_BC1); - case sel is - when "000" => null; - when "001" => busctrl_addr <= '1'; - when "010" => null; - when "011" => busctrl_re <= cs; - when "100" => busctrl_addr <= '1'; - when "101" => null; - when "110" => busctrl_we <= cs; - when "111" => busctrl_addr <= '1'; - when others => null; - end case; - end process; - - p_oe : process(busctrl_re) - begin - -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns - O_DA_OE_L <= not (busctrl_re); - end process; - - -- - -- CLOCKED - -- - p_waddr : process(RESET_L, CLK) - begin - -- looks like registers are latches in real chip, but the address is caught at the end of the address state. - if (RESET_L = '0') then - addr <= (others => '0'); - elsif rising_edge(CLK) then - if (ENA = '1') then - if (busctrl_addr = '1') then - addr <= I_DA; - end if; - end if; - end if; - end process; - - p_wdata : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - reg <= (others => (others => '0')); - env_reset <= '1'; - elsif rising_edge(CLK) then - if (ENA = '1') then - env_reset <= '0'; - if (busctrl_we = '1') then - case addr(3 downto 0) is - when x"0" => reg(0) <= I_DA; - when x"1" => reg(1) <= I_DA; - when x"2" => reg(2) <= I_DA; - when x"3" => reg(3) <= I_DA; - when x"4" => reg(4) <= I_DA; - when x"5" => reg(5) <= I_DA; - when x"6" => reg(6) <= I_DA; - when x"7" => reg(7) <= I_DA; - when x"8" => reg(8) <= I_DA; - when x"9" => reg(9) <= I_DA; - when x"A" => reg(10) <= I_DA; - when x"B" => reg(11) <= I_DA; - when x"C" => reg(12) <= I_DA; - when x"D" => reg(13) <= I_DA; env_reset <= '1'; - when x"E" => reg(14) <= I_DA; - when x"F" => reg(15) <= I_DA; - when others => null; - end case; - end if; - end if; - end if; - end process; - - p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) - begin - O_DA <= (others => '0'); -- 'X' - if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator - case addr(3 downto 0) is - when x"0" => O_DA <= reg(0) ; - when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; - when x"2" => O_DA <= reg(2) ; - when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; - when x"4" => O_DA <= reg(4) ; - when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; - when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; - when x"7" => O_DA <= reg(7) ; - when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; - when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; - when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; - when x"B" => O_DA <= reg(11); - when x"C" => O_DA <= reg(12); - when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); - when x"E" => if (reg(7)(6) = '0') then -- input - O_DA <= ioa_inreg; - else - O_DA <= reg(14); -- read output reg - end if; - when x"F" => if (Reg(7)(7) = '0') then - O_DA <= iob_inreg; - else - O_DA <= reg(15); - end if; - when others => null; - end case; - end if; - end process; - -- - p_divider : process - begin - wait until rising_edge(CLK); - -- / 8 when SEL is high and /16 when SEL is low - if (ENA = '1') then - ena_div <= '0'; - ena_div_noise <= '0'; - if (cnt_div = "0000") then - cnt_div <= (not I_SEL_L) & "111"; - ena_div <= '1'; - - noise_div <= not noise_div; - if (noise_div = '1') then - ena_div_noise <= '1'; - end if; - else - cnt_div <= cnt_div - "1"; - end if; - end if; - end process; - - p_noise_gen : process - variable noise_gen_comp : std_logic_vector(4 downto 0); - variable poly17_zero : std_logic; - begin - wait until rising_edge(CLK); - if (reg(6)(4 downto 0) = "00000") then - noise_gen_comp := "00000"; - else - noise_gen_comp := (reg(6)(4 downto 0) - "1"); - end if; - - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - - if (ENA = '1') then - if (ena_div_noise = '1') then -- divider ena - - if (noise_gen_cnt >= noise_gen_comp) then - noise_gen_cnt <= "00000"; - poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); - else - noise_gen_cnt <= (noise_gen_cnt + "1"); - end if; - end if; - end if; - end process; - noise_gen_op <= poly17(0); - - p_tone_gens : process - variable tone_gen_freq : array_3x12; - variable tone_gen_comp : array_3x12; - begin - wait until rising_edge(CLK); - -- looks like real chips count up - we need to get the Exact behaviour .. - tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); - tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); - tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); - -- period 0 = period 1 - for i in 1 to 3 loop - if (tone_gen_freq(i) = x"000") then - tone_gen_comp(i) := x"000"; - else - tone_gen_comp(i) := (tone_gen_freq(i) - "1"); - end if; - end loop; - - if (ENA = '1') then - for i in 1 to 3 loop - if (ena_div = '1') then -- divider ena - - if (tone_gen_cnt(i) >= tone_gen_comp(i)) then - tone_gen_cnt(i) <= x"000"; - tone_gen_op(i) <= not tone_gen_op(i); - else - tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); - end if; - end if; - end loop; - end if; - end process; - - p_envelope_freq : process - variable env_gen_freq : std_logic_vector(15 downto 0); - variable env_gen_comp : std_logic_vector(15 downto 0); - begin - wait until rising_edge(CLK); - env_gen_freq := reg(12) & reg(11); - -- envelope freqs 1 and 0 are the same. - if (env_gen_freq = x"0000") then - env_gen_comp := x"0000"; - else - env_gen_comp := (env_gen_freq - "1"); - end if; - - if (ENA = '1') then - env_ena <= '0'; - if (ena_div = '1') then -- divider ena - if (env_gen_cnt >= env_gen_comp) then - env_gen_cnt <= x"0000"; - env_ena <= '1'; - else - env_gen_cnt <= (env_gen_cnt + "1"); - end if; - end if; - end if; - end process; - - p_envelope_shape : process(env_reset, reg, CLK) - variable is_bot : boolean; - variable is_bot_p1 : boolean; - variable is_top_m1 : boolean; - variable is_top : boolean; - begin - -- envelope shapes - -- C AtAlH - -- 0 0 x x \___ - -- - -- 0 1 x x /___ - -- - -- 1 0 0 0 \\\\ - -- - -- 1 0 0 1 \___ - -- - -- 1 0 1 0 \/\/ - -- ___ - -- 1 0 1 1 \ - -- - -- 1 1 0 0 //// - -- ___ - -- 1 1 0 1 / - -- - -- 1 1 1 0 /\/\ - -- - -- 1 1 1 1 /___ - if (env_reset = '1') then - -- load initial state - if (reg(13)(2) = '0') then -- attack - env_vol <= "11111"; - env_inc <= '0'; -- -1 - else - env_vol <= "00000"; - env_inc <= '1'; -- +1 - end if; - env_hold <= '0'; - - elsif rising_edge(CLK) then - is_bot := (env_vol = "00000"); - is_bot_p1 := (env_vol = "00001"); - is_top_m1 := (env_vol = "11110"); - is_top := (env_vol = "11111"); - - if (ENA = '1') then - if (env_ena = '1') then - if (env_hold = '0') then - if (env_inc = '1') then - env_vol <= (env_vol + "00001"); - else - env_vol <= (env_vol + "11111"); - end if; - end if; - - -- envelope shape control. - if (reg(13)(3) = '0') then - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - else - if is_top then env_hold <= '1'; end if; - end if; - else - if (reg(13)(0) = '1') then -- hold = 1 - if (env_inc = '0') then -- down - if (reg(13)(1) = '1') then -- alt - if is_bot then env_hold <= '1'; end if; - else - if is_bot_p1 then env_hold <= '1'; end if; - end if; - else - if (reg(13)(1) = '1') then -- alt - if is_top then env_hold <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - end if; - end if; - - elsif (reg(13)(1) = '1') then -- alternate - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - if is_bot then env_hold <= '0'; env_inc <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - if is_top then env_hold <= '0'; env_inc <= '0'; end if; - end if; - end if; - - end if; - end if; - end if; - end if; - end process; - - p_chan_mixer : process(cnt_div, reg, tone_gen_op) - begin - tone_ena_l <= '1'; tone_src <= '1'; - noise_ena_l <= '1'; chan_vol <= "00000"; - case cnt_div(1 downto 0) is - when "00" => - tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); - noise_ena_l <= reg(7)(3); - when "01" => - tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); - noise_ena_l <= reg(7)(4); - when "10" => - tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); - noise_ena_l <= reg(7)(5); - when "11" => null; -- tone gen outputs become valid on this clock - when others => null; - end case; - end process; - - p_op_mixer : process - variable chan_mixed : std_logic; - variable chan_amp : std_logic_vector(4 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); - - chan_amp := (others => '0'); - if (chan_mixed = '1') then - if (chan_vol(4) = '0') then - if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet - chan_amp := "00000"; - else - chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) - end if; - else - chan_amp := env_vol(4 downto 0); - end if; - end if; - - dac_amp <= x"00"; - case chan_amp is - when "11111" => dac_amp <= x"FF"; - when "11110" => dac_amp <= x"D9"; - when "11101" => dac_amp <= x"BA"; - when "11100" => dac_amp <= x"9F"; - when "11011" => dac_amp <= x"88"; - when "11010" => dac_amp <= x"74"; - when "11001" => dac_amp <= x"63"; - when "11000" => dac_amp <= x"54"; - when "10111" => dac_amp <= x"48"; - when "10110" => dac_amp <= x"3D"; - when "10101" => dac_amp <= x"34"; - when "10100" => dac_amp <= x"2C"; - when "10011" => dac_amp <= x"25"; - when "10010" => dac_amp <= x"1F"; - when "10001" => dac_amp <= x"1A"; - when "10000" => dac_amp <= x"16"; - when "01111" => dac_amp <= x"13"; - when "01110" => dac_amp <= x"10"; - when "01101" => dac_amp <= x"0D"; - when "01100" => dac_amp <= x"0B"; - when "01011" => dac_amp <= x"09"; - when "01010" => dac_amp <= x"08"; - when "01001" => dac_amp <= x"07"; - when "01000" => dac_amp <= x"06"; - when "00111" => dac_amp <= x"05"; - when "00110" => dac_amp <= x"04"; - when "00101" => dac_amp <= x"03"; - when "00100" => dac_amp <= x"03"; - when "00011" => dac_amp <= x"02"; - when "00010" => dac_amp <= x"02"; - when "00001" => dac_amp <= x"01"; - when "00000" => dac_amp <= x"00"; - when others => null; - end case; - - cnt_div_t1 <= cnt_div; - end if; - end process; - - p_audio_output : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - O_AUDIO <= (others => '0'); - O_CHAN <= (others => '0'); - elsif rising_edge(CLK) then - - if (ENA = '1') then - O_AUDIO <= dac_amp(7 downto 0); - O_CHAN <= cnt_div_t1(1 downto 0); - end if; - end if; - end process; - - p_io_ports : process(reg) - begin - O_IOA <= reg(14); - O_IOA_OE_L <= not reg(7)(6); - O_IOB <= reg(15); - O_IOB_OE_L <= not reg(7)(7); - end process; - - p_io_ports_inreg : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then -- resync - ioa_inreg <= I_IOA; - iob_inreg <= I_IOB; - end if; - end process; -end architecture RTL; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd index d2ba927b..b7a2e3d9 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd @@ -1,34 +1,18 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -use ieee.numeric_std.all; library work; use work.pace_pkg.all; +use work.platform_pkg.all; use work.platform_variant_pkg.all; use work.video_controller_pkg.all; -entity BITMAP_1 is - generic - ( - DELAY : integer - ); - port - ( - reset : in std_logic; +-- +-- Moon Patrol Cityscape Renderer +-- - -- video control signals - video_ctl : in from_VIDEO_CTL_t; - - -- bitmap controller signals - ctl_i : in to_BITMAP_CTL_t; - ctl_o : out from_BITMAP_CTL_t; - - graphics_i : in to_GRAPHICS_t - ); -end entity BITMAP_1; - -architecture bit1 of BITMAP_1 is +architecture BITMAP_1 of bitmapCtl is alias clk : std_logic is video_ctl.clk; alias clk_en : std_logic is video_ctl.clk_ena; @@ -37,16 +21,22 @@ architecture bit1 of BITMAP_1 is alias vblank : std_logic is video_ctl.vblank; alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; - alias rgb : RGB_t is ctl_o.rgb; + + alias rgb : RGB_t is ctl_o.rgb; + alias m52_bg1xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(15 downto 8); alias m52_bg1ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(7 downto 0); +-- alias m52_bg2xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(15 downto 8); +-- alias m52_bg2ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(7 downto 0); alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); begin process (clk, reset) variable y_r : std_logic_vector(y'range); + -- ensure bgy won't wrap on the screen variable bgy : unsigned(7 downto 0); + -- must wrap at 256!!! variable bgx : unsigned(7 downto 0); variable bitmap_d_r : std_logic_vector(7 downto 0); variable pel : std_logic_vector(1 downto 0); @@ -108,4 +98,4 @@ begin -- unused ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); -end architecture bit1; +end architecture BITMAP_1; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd index baf468eb..b8b2aaff 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd @@ -1,34 +1,18 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -use ieee.numeric_std.all; library work; use work.pace_pkg.all; +use work.platform_pkg.all; use work.platform_variant_pkg.all; use work.video_controller_pkg.all; -entity BITMAP_2 is - generic - ( - DELAY : integer - ); - port - ( - reset : in std_logic; +-- +-- Moon Patrol Hills Renderer +-- - -- video control signals - video_ctl : in from_VIDEO_CTL_t; - - -- bitmap controller signals - ctl_i : in to_BITMAP_CTL_t; - ctl_o : out from_BITMAP_CTL_t; - - graphics_i : in to_GRAPHICS_t - ); -end entity BITMAP_2; - -architecture bit2 of BITMAP_2 is +architecture BITMAP_2 of bitmapCtl is alias clk : std_logic is video_ctl.clk; alias clk_en : std_logic is video_ctl.clk_ena; @@ -37,16 +21,22 @@ architecture bit2 of BITMAP_2 is alias vblank : std_logic is video_ctl.vblank; alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; - alias rgb : RGB_t is ctl_o.rgb; + + alias rgb : RGB_t is ctl_o.rgb; + alias m52_bg1xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(15 downto 8); alias m52_bg1ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(7 downto 0); +-- alias m52_bg2xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(15 downto 8); +-- alias m52_bg2ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(7 downto 0); alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); begin process (clk, reset) variable y_r : std_logic_vector(y'range); + -- ensure bgy won't wrap on the screen variable bgy : unsigned(7 downto 0); + -- must wrap at 256!!! variable bgx : unsigned(7 downto 0); variable bitmap_d_r : std_logic_vector(7 downto 0); variable pel : std_logic_vector(1 downto 0); @@ -108,4 +98,4 @@ begin -- unused ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); -end architecture bit2; +end architecture BITMAP_2; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd index e27ec7b6..a18ea5ab 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd @@ -1,34 +1,18 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -use ieee.numeric_std.all; library work; use work.pace_pkg.all; +use work.platform_pkg.all; use work.platform_variant_pkg.all; use work.video_controller_pkg.all; -entity BITMAP_3 is - generic - ( - DELAY : integer - ); - port - ( - reset : in std_logic; +-- +-- Moon Patrol Mountains Renderer +-- - -- video control signals - video_ctl : in from_VIDEO_CTL_t; - - -- bitmap controller signals - ctl_i : in to_BITMAP_CTL_t; - ctl_o : out from_BITMAP_CTL_t; - - graphics_i : in to_GRAPHICS_t - ); -end entity BITMAP_3; - -architecture bit3 of BITMAP_3 is +architecture BITMAP_3 of bitmapCtl is alias clk : std_logic is video_ctl.clk; alias clk_en : std_logic is video_ctl.clk_ena; @@ -37,7 +21,11 @@ architecture bit3 of BITMAP_3 is alias vblank : std_logic is video_ctl.vblank; alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; + alias rgb : RGB_t is ctl_o.rgb; + +-- alias m52_bg1xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(15 downto 8); +-- alias m52_bg1ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(7 downto 0); alias m52_bg2xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(15 downto 8); alias m52_bg2ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(7 downto 0); alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); @@ -46,7 +34,9 @@ begin process (clk, reset) variable y_r : std_logic_vector(y'range); + -- ensure bgy won't wrap on the screen variable bgy : unsigned(7 downto 0); + -- must wrap at 256!!! variable bgx : unsigned(7 downto 0); variable bitmap_d_r : std_logic_vector(7 downto 0); variable pel : std_logic_vector(1 downto 0); @@ -108,4 +98,4 @@ begin -- unused ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); -end architecture bit3; +end architecture BITMAP_3; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd index 1f6a995c..508109c8 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd @@ -6,7 +6,8 @@ use ieee.numeric_std.all; library work; use work.pace_pkg.all; use work.video_controller_pkg.all; - +use work.platform_pkg.all; +use work.project_pkg.all; entity bitmapCtl is generic diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v deleted file mode 100644 index ff5ab947..00000000 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "190305" -`define BUILD_TIME "212703" diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v index 4e20d2a1..2a935b22 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v @@ -96,7 +96,6 @@ module mist_io #(parameter PS2DIV=100) localparam conf_str = { "Moon Patr.;;", -// "O2,HQ2x,On,Off;",no effect "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", "T5,Reset;", "V,v1.11.",`BUILD_DATE diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd index 11f5b5d7..8d238ee5 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd @@ -37,9 +37,37 @@ port( end moon_patrol_sound_board; architecture struct of moon_patrol_sound_board is + component YM2149 + port ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + A8 : in std_logic := '1'; + A9_L : in std_logic := '0'; + BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write) + BC : in std_logic; -- Bus control + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A : out std_logic_vector(7 downto 0); + CHANNEL_B : out std_logic_vector(7 downto 0); + CHANNEL_C : out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + + ACTIVE : out std_logic_vector(5 downto 0); + + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; signal reset_n : std_logic; signal clock_div : std_logic_vector(3 downto 0); + signal cpu_clock_en : std_logic; signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); @@ -59,12 +87,18 @@ architecture struct of moon_patrol_sound_board is signal rom_cs : std_logic; signal rom_do : std_logic_vector( 7 downto 0); + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); signal ay1_do : std_logic_vector(7 downto 0); - signal ay1_audio : std_logic_vector(7 downto 0); + signal ay1_audio : std_logic_vector(9 downto 0); signal ay1_port_b_do : std_logic_vector(7 downto 0); - + + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); signal ay2_do : std_logic_vector(7 downto 0); - signal ay2_audio : std_logic_vector(7 downto 0); + signal ay2_audio : std_logic_vector(9 downto 0); signal ports_cs : std_logic; signal ports_we : std_logic; @@ -140,6 +174,7 @@ end process; -- cpu_clock is 3.58/4 cpu_clock <= clock_div(1); +cpu_clock_en <= '1' when clock_div(1 downto 0) = "00" else '0'; -- cs wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF @@ -170,8 +205,8 @@ begin if reset='1' then cpu_irq <= '0'; select_sound_7r := '0'; - else - if rising_edge(clock_div(0)) then + elsif rising_edge(clock_3p58) then + if clock_div(0) = '1' then --rising_edge(clock_div(0)) then if select_sound_7r = '0' and select_sound(7) = '1' then cpu_irq <= '1'; end if; @@ -194,8 +229,8 @@ begin port1_data <= (others=>'0'); -- port1 data set to 0 port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up) - else - if rising_edge(clock_div(0)) then + elsif rising_edge(clock_3p58) then + if clock_div(0) = '1' then --rising_edge(clock_div(0)) then if ports_cs = '1' and ports_we = '1' then if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if; if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if; @@ -222,8 +257,8 @@ process (reset, clock_div(0)) begin if reset='1' then adpcm_0_di <= (others=>'0'); - else - if rising_edge(clock_div(0)) then + elsif rising_edge(clock_3p58) then + if clock_div(0) = '1' then --rising_edge(clock_div(0)) then if adpcm_cs = '1' and adpcm_we = '1' then if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if; end if; @@ -301,7 +336,7 @@ begin end process; -- audio mux -audio <= ("00000"&ay1_audio) + ("00000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12))); +audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12))); audio_out <= audio(12 downto 1); -- microprocessor 6800/01/03 @@ -325,7 +360,7 @@ port map( -- cpu program rom cpu_prog_rom : entity work.moon_patrol_sound_prog port map( - clk => clock_div(0), -- 3p58/2 + clk => clock_3p58, -- 3p58/2 addr => cpu_addr(11 downto 0), data => rom_do ); @@ -333,7 +368,7 @@ port map( cpu_ram : entity work.spram generic map( widthad_a => 7) port map( - clock => clock_div(0), -- 3p58/2 + clock => clock_3p58, -- 3p58/2 address => cpu_addr(6 downto 0), data => cpu_do, wren => wram_we, @@ -351,69 +386,62 @@ port map( -- q => wram_do --); --- AY-3-8910 #1 -ay_3_8910_1 : entity work.YM2149 -port map( - -- data bus - I_DA => port1_data,-- in std_logic_vector(7 downto 0); - O_DA => ay1_do, -- out std_logic_vector(7 downto 0); - O_DA_OE_L => open, -- out std_logic; - -- control - I_A9_L => port2_data(4), -- in std_logic; - I_A8 => '1', -- in std_logic; - I_BDIR => port2_data(0), -- in std_logic; - I_BC2 => '1', -- in std_logic; - I_BC1 => port2_data(2), -- in std_logic; - I_SEL_L => '1', -- in std_logic; + ay83910_inst1: YM2149 + port map ( + CLK => clock_3p58, + CE => cpu_clock_en, + RESET => not reset_n, + A8 => '1', + A9_L => port2_data(4), + BDIR => port2_data(0), + BC => port2_data(2), + DI => port1_data, + DO => ay1_do, + CHANNEL_A => ay1_chan_a, + CHANNEL_B => ay1_chan_b, + CHANNEL_C => ay1_chan_c, - O_AUDIO => ay1_audio, -- out std_logic_vector(7 downto 0); --- O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); - - -- port a - I_IOA => select_sound, -- in std_logic_vector(7 downto 0); - O_IOA => open, -- out std_logic_vector(7 downto 0); - O_IOA_OE_L => open, -- out std_logic; - -- port b - I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOB => ay1_port_b_do, -- out std_logic_vector(7 downto 0); - O_IOB_OE_L => open, -- out std_logic; + SEL => '0', + MODE => '1', - ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation - RESET_L => reset_n, -- in std_logic; - CLK => cpu_clock -- in std_logic -- note 6 Mhz -); + ACTIVE => open, --- AY-3-8910 #2 -ay_3_8910_2 : entity work.YM2149 -port map( - -- data bus - I_DA => port1_data,-- in std_logic_vector(7 downto 0); - O_DA => ay2_do, -- out std_logic_vector(7 downto 0); - O_DA_OE_L => open, -- out std_logic; - -- control - I_A9_L => port2_data(3), -- in std_logic; - I_A8 => '1', -- in std_logic; - I_BDIR => port2_data(0), -- in std_logic; - I_BC2 => '1', -- in std_logic; - I_BC1 => port2_data(2), -- in std_logic; - I_SEL_L => '1', -- in std_logic; + IOA_in => select_sound, + IOA_out => open, - O_AUDIO => ay2_audio, -- out std_logic_vector(7 downto 0); --- O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); - - -- port a - I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOA => open, -- out std_logic_vector(7 downto 0); - O_IOA_OE_L => open, -- out std_logic; - -- port b - I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOB => open, -- out std_logic_vector(7 downto 0); - O_IOB_OE_L => open, -- out std_logic; + IOB_in => (others => '0'), + IOB_out => ay1_port_b_do + ); - ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation - RESET_L => reset_n, -- in std_logic; - CLK => cpu_clock -- in std_logic -- note 6 Mhz -); + ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c; + ay83910_inst2: YM2149 + port map ( + CLK => clock_3p58, + CE => cpu_clock_en, + RESET => not reset_n, + A8 => '1', + A9_L => port2_data(3), + BDIR => port2_data(0), + BC => port2_data(2), + DI => port1_data, + DO => ay2_do, + CHANNEL_A => ay2_chan_a, + CHANNEL_B => ay2_chan_b, + CHANNEL_C => ay2_chan_c, + + SEL => '0', + MODE => '1', + + ACTIVE => open, + + IOA_in => (others => '0'), + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => open + ); + + ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c; end struct; \ No newline at end of file diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd index 95c23a95..8d00c0fa 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd @@ -34,8 +34,8 @@ architecture SYN of mpatrol is signal init : std_logic := '1'; signal clk_sys : std_logic; + signal clk_aud : std_logic; signal clk_vid : std_logic; - signal clk_osd : std_logic; signal clkrst_i : from_CLKRST_t; signal buttons_i : from_BUTTONS_t; signal switches_i : from_SWITCHES_t; @@ -53,18 +53,30 @@ architecture SYN of mpatrol is signal buttons : std_logic_vector(1 downto 0); signal ps2_kbd_clk : std_logic; signal ps2_kbd_data : std_logic; - signal scan_disable : std_logic; - signal ypbpr : std_logic; - signal r : std_logic_vector(5 downto 0); - signal g : std_logic_vector(5 downto 0); - signal b : std_logic_vector(5 downto 0); - signal hs : std_logic; - signal vs : std_logic; + signal scandoubler_disable : std_logic; + signal ypbpr : std_logic; signal reset : std_logic; - signal clock_3p58 : std_logic; signal audio_out : std_logic_vector(11 downto 0); signal sound_data : std_logic_vector(7 downto 0); + signal sd_r : std_logic_vector(5 downto 0); + signal sd_g : std_logic_vector(5 downto 0); + signal sd_b : std_logic_vector(5 downto 0); + signal sd_hs : std_logic; + signal sd_vs : std_logic; + + signal osd_red_i : std_logic_vector(5 downto 0); + signal osd_green_i : std_logic_vector(5 downto 0); + signal osd_blue_i : std_logic_vector(5 downto 0); + signal osd_vs_i : std_logic; + signal osd_hs_i : std_logic; + signal osd_red_o : std_logic_vector(5 downto 0); + signal osd_green_o : std_logic_vector(5 downto 0); + signal osd_blue_o : std_logic_vector(5 downto 0); + signal vga_y_o : std_logic_vector(5 downto 0); + signal vga_pb_o : std_logic_vector(5 downto 0); + signal vga_pr_o : std_logic_vector(5 downto 0); + component keyboard port ( clk :in STD_LOGIC; @@ -84,8 +96,8 @@ component mist_io SPI_SS2 :in STD_LOGIC; switches :out STD_LOGIC_VECTOR(1 downto 0); buttons :out STD_LOGIC_VECTOR(1 downto 0); - scan_disable :out STD_LOGIC; - ypbpr :out STD_LOGIC; + scan_disable :out STD_LOGIC; + ypbpr :out STD_LOGIC; joystick_1 :out STD_LOGIC_VECTOR(7 downto 0); joystick_0 :out STD_LOGIC_VECTOR(7 downto 0); status :out STD_LOGIC_VECTOR(31 downto 0); @@ -93,48 +105,75 @@ component mist_io ps2_kbd_data :out STD_LOGIC); end component; -component video_mist - port ( - clk_sys :in STD_LOGIC; - ce_pix :in STD_LOGIC; - ce_pix_actual :in STD_LOGIC; - SPI_SCK :in STD_LOGIC; - SPI_SS3 :in STD_LOGIC; - SPI_DI :in STD_LOGIC; - R :in STD_LOGIC_VECTOR(5 downto 0); - G :in STD_LOGIC_VECTOR(5 downto 0); - B :in STD_LOGIC_VECTOR(5 downto 0); - HSync :in STD_LOGIC; - VSync :in STD_LOGIC; - VGA_R :out STD_LOGIC_VECTOR(5 downto 0); - VGA_G :out STD_LOGIC_VECTOR(5 downto 0); - VGA_B :out STD_LOGIC_VECTOR(5 downto 0); - VGA_HS :out STD_LOGIC; - VGA_VS :out STD_LOGIC; - scan_disable :in STD_LOGIC; - scanlines :in STD_LOGIC_VECTOR(1 downto 0); - hq2x :in STD_LOGIC; - ypbpr_full :in STD_LOGIC; - line_start :in STD_LOGIC; - mono :in STD_LOGIC); -end component; +component scandoubler + port ( + clk_sys : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + hs_in : in std_logic; + vs_in : in std_logic; + r_in : in std_logic_vector(5 downto 0); + g_in : in std_logic_vector(5 downto 0); + b_in : in std_logic_vector(5 downto 0); + + hs_out : out std_logic; + vs_out : out std_logic; + r_out : out std_logic_vector(5 downto 0); + g_out : out std_logic_vector(5 downto 0); + b_out : out std_logic_vector(5 downto 0) + ); +end component scandoubler; + +component osd + generic ( OSD_COLOR : integer := 1 ); -- blue + port ( + clk_sys : in std_logic; + + R_in : in std_logic_vector(5 downto 0); + G_in : in std_logic_vector(5 downto 0); + B_in : in std_logic_vector(5 downto 0); + HSync : in std_logic; + VSync : in std_logic; + + R_out : out std_logic_vector(5 downto 0); + G_out : out std_logic_vector(5 downto 0); + B_out : out std_logic_vector(5 downto 0); + + SPI_SCK : in std_logic; + SPI_SS3 : in std_logic; + SPI_DI : in std_logic + ); +end component osd; + +COMPONENT rgb2ypbpr + PORT ( + red : IN std_logic_vector(5 DOWNTO 0); + green : IN std_logic_vector(5 DOWNTO 0); + blue : IN std_logic_vector(5 DOWNTO 0); + y : OUT std_logic_vector(5 DOWNTO 0); + pb : OUT std_logic_vector(5 DOWNTO 0); + pr : OUT std_logic_vector(5 DOWNTO 0) + ); +END COMPONENT; begin + --CLOCK Clock_inst : entity work.Clock port map ( - inclk0 => CLOCK_27, - c0 => clock_3p58,--3.58 - c1 => clk_osd,--10 - c2 => clk_sys,--30 - c3 => clk_vid--40 - ); + inclk0 => CLOCK_27, + c0 => clk_aud, -- 3.58 + c1 => clk_sys, -- 6 + c2 => clk_vid -- 24 + ); + + clkrst_i.clk(0) <= clk_sys; + clkrst_i.clk(1) <= clk_sys; + + video_i.clk <= clk_sys; + video_i.clk_ena <= '1'; + video_i.reset <= clkrst_i.rst(1); - clkrst_i.clk_ref <= CLOCK_27; - clkrst_i.clk(0) <= clk_sys; - clkrst_i.clk(1) <= clk_vid; - --RESET process (clk_sys) variable count : std_logic_vector (11 downto 0) := (others => '0'); @@ -177,47 +216,15 @@ mist_io_inst : mist_io SPI_SS2 => SPI_SS2, switches => switches, buttons => buttons, - scan_disable => scan_disable, - ypbpr => ypbpr, + scan_disable => scandoubler_disable, + ypbpr => ypbpr, joystick_1 => joystick2, joystick_0 => joystick1, status => status, ps2_kbd_clk => ps2_kbd_clk, ps2_kbd_data => ps2_kbd_data ); - -video_mist_inst : video_mist - port map ( - clk_sys => clk_sys, - ce_pix => clk_osd, - ce_pix_actual => clk_osd, - SPI_SCK => SPI_SCK, - SPI_SS3 => SPI_SS3, - SPI_DI => SPI_DI, - R => video_o.rgb.r(9 downto 4), - G => video_o.rgb.g(9 downto 4), - B => video_o.rgb.b(9 downto 4), - HSync => video_o.hsync, - VSync => video_o.vsync, - VGA_R => VGA_R, - VGA_G => VGA_G, - VGA_B => VGA_B, - VGA_HS => VGA_HS, - VGA_VS => VGA_VS, - --ToDo - scan_disable => '1',--scan_disable, - scanlines => status(4 downto 3), - hq2x => status(2), - ypbpr_full => '1', - line_start => '0', - mono => '0' - ); - video_i.clk <= clk_vid; - video_i.clk_ena <= '1'; - video_i.reset <= clkrst_i.rst(1); - - u_keyboard : keyboard port map( clk => clk_sys, @@ -227,8 +234,8 @@ u_keyboard : keyboard joystick => kbd_joy ); - inputs_i.jamma_n.coin(1) <= kbd_joy(3) or status(1);--ESC - inputs_i.jamma_n.p(1).start <= kbd_joy(1) or kbd_joy(2) or status(2);--KB 1+2 + inputs_i.jamma_n.coin(1) <= joystick1(7) or joystick2(7) or kbd_joy(3);--ESC + inputs_i.jamma_n.p(1).start <= kbd_joy(1) or kbd_joy(2);--KB 1+2 inputs_i.jamma_n.p(1).up <= not (joystick1(3) or joystick2(3) or kbd_joy(4)); inputs_i.jamma_n.p(1).down <= not (joystick1(2) or joystick2(2) or kbd_joy(5)); inputs_i.jamma_n.p(1).left <= not (joystick1(1) or joystick2(1) or kbd_joy(6)); @@ -258,7 +265,7 @@ u_keyboard : keyboard moon_patrol_sound_board : entity work.moon_patrol_sound_board port map( - clock_3p58 => clock_3p58, + clock_3p58 => clk_aud, reset => clkrst_i.arst, select_sound => sound_data, audio_out => audio_out, @@ -266,21 +273,18 @@ moon_patrol_sound_board : entity work.moon_patrol_sound_board ); dac : entity work.dac - port map ( - clk_i => clk_sys, - res_n_i => '1', - dac_i => audio_out, - dac_o => audio + port map ( + clk_i => clk_aud, + res_n_i => '1', + dac_i => audio_out, + dac_o => audio ); - - AUDIO_R <= audio; - AUDIO_L <= audio; - +AUDIO_R <= audio; +AUDIO_L <= audio; - pace_inst : entity work.pace - port map - ( +pace_inst : entity work.pace + port map ( clkrst_i => clkrst_i, buttons_i => buttons_i, switches_i => switches_i, @@ -289,5 +293,66 @@ dac : entity work.dac video_i => video_i, video_o => video_o, sound_data_o => sound_data - ); + ); + +scandoubler_inst: scandoubler + port map ( + clk_sys => clk_vid, + scanlines => status(4 downto 3), + + hs_in => video_o.hsync, + vs_in => video_o.vsync, + r_in => video_o.rgb.r(9 downto 4), + g_in => video_o.rgb.g(9 downto 4), + b_in => video_o.rgb.b(9 downto 4), + + hs_out => sd_hs, + vs_out => sd_vs, + r_out => sd_r, + g_out => sd_g, + b_out => sd_b + ); + +osd_inst: osd + port map ( + clk_sys => clk_vid, + + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + + R_in => osd_red_i, + G_in => osd_green_i, + B_in => osd_blue_i, + HSync => osd_hs_i, + VSync => osd_vs_i, + + R_out => osd_red_o, + G_out => osd_green_o, + B_out => osd_blue_o + ); + +rgb2component: component rgb2ypbpr + port map ( + red => osd_red_o, + green => osd_green_o, + blue => osd_blue_o, + y => vga_y_o, + pb => vga_pb_o, + pr => vga_pr_o + ); + +osd_red_i <= video_o.rgb.r(9 downto 4) when scandoubler_disable = '1' else sd_r; +osd_green_i <= video_o.rgb.g(9 downto 4) when scandoubler_disable = '1' else sd_g; +osd_blue_i <= video_o.rgb.b(9 downto 4) when scandoubler_disable = '1' else sd_b; +osd_hs_i <= video_o.hsync when scandoubler_disable = '1' else sd_hs; +osd_vs_i <= video_o.vsync when scandoubler_disable = '1' else sd_vs; + + -- If 15kHz Video - composite sync to VGA_HS and VGA_VS high for MiST RGB cable +VGA_HS <= not (video_o.hsync xor video_o.vsync) when scandoubler_disable='1' else not (sd_hs xor sd_vs) when ypbpr='1' else sd_hs; +VGA_VS <= '1' when scandoubler_disable='1' or ypbpr='1' else sd_vs; +VGA_R <= vga_pr_o when ypbpr='1' else osd_red_o; +VGA_G <= vga_y_o when ypbpr='1' else osd_green_o; +VGA_B <= vga_pb_o when ypbpr='1' else osd_blue_o; +-- end SYN; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd index 48d2dcd0..db220a84 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd @@ -6,8 +6,9 @@ library work; use work.pace_pkg.all; use work.video_controller_pkg.all; use work.sprite_pkg.all; ---use work.platform_pkg.all; ---use work.project_pkg.all; +use work.target_pkg.all; +use work.platform_pkg.all; +use work.project_pkg.all; entity PACE is port @@ -39,8 +40,8 @@ end entity PACE; architecture SYN of PACE is - constant CLK_1US_COUNTS : integer := - integer(27 * 50 / 20); + constant CLK_1US_COUNTS : integer := + integer(PACE_CLKIN0 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY); signal mapped_inputs : from_MAPPED_INPUTS_t(0 to 6-1); diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd index ec1b95e2..c5ac6132 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd @@ -150,6 +150,13 @@ package pace_pkg is type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t; - + -- create a constant that automatically determines + -- whether this is simulation or synthesis + constant IN_SIMULATION : BOOLEAN := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + constant IN_SYNTHESIS : boolean := not IN_SIMULATION; end; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd index 571e0ce2..0a548789 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd @@ -8,6 +8,7 @@ use work.pace_pkg.all; use work.video_controller_pkg.all; use work.sprite_pkg.all; use work.platform_variant_pkg.all; +use work.platform_pkg.all; entity platform is generic @@ -267,7 +268,7 @@ begin clk_en_inst : entity work.clk_div generic map ( - DIVISOR => 16 + DIVISOR => M52_CPU_CLK_ENA_DIVIDE_BY ) port map ( diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_pkg.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_pkg.vhd new file mode 100644 index 00000000..684be8cc --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_pkg.vhd @@ -0,0 +1,47 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.target_pkg.all; +use work.project_pkg.all; + +package platform_pkg is + + + constant PACE_VIDEO_NUM_BITMAPS : natural := 3; + constant PACE_VIDEO_NUM_TILEMAPS : natural := 1; + constant PACE_VIDEO_NUM_SPRITES : natural := 64; + constant PACE_VIDEO_H_SIZE : integer := 256; + constant PACE_VIDEO_V_SIZE : integer := 256; + constant PACE_VIDEO_L_CROP : integer := 6; + constant PACE_VIDEO_R_CROP : integer := 8; + constant PACE_VIDEO_PIPELINE_DELAY : integer := 7; + + constant PACE_INPUTS_NUM_BYTES : integer := 6; + + -- + -- Platform-specific constants (optional) + -- + + constant PLATFORM : string := "m52"; + constant PLATFORM_SRC_DIR : string := ""; + + constant CLK0_FREQ_MHz : natural := + PACE_CLKIN0 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY; + constant CPU_FREQ_MHz : natural := 3; + + constant M52_CPU_CLK_ENA_DIVIDE_BY : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz; + + type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0); + type pal_a is array (natural range <>) of pal_rgb_t; + + type from_PLATFORM_IO_t is record + not_used : std_logic; + end record; + + type to_PLATFORM_IO_t is record + not_used : std_logic; + end record; + +end; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd index 7b852809..45404c4d 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd @@ -3,9 +3,9 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library work; ---use work.target_pkg.all; ---use work.project_pkg.all; ---use work.platform_pkg.all; +use work.target_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; package platform_variant_pkg is @@ -19,8 +19,6 @@ package platform_variant_pkg is constant PLATFORM_VARIANT : string := "mpatrol"; constant PLATFORM_VARIANT_SRC_DIR : string := ""; - type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0); - type pal_a is array (natural range <>) of pal_rgb_t; type rom_a is array (natural range <>) of string; constant M52_ROM : rom_a(0 to 3) := ( diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/project_pkg.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/project_pkg.vhd new file mode 100644 index 00000000..97d429d1 --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/project_pkg.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; +use work.target_pkg.all; +use work.video_controller_pkg.all; + +package project_pkg is + + -- + -- PACE constants which *MUST* be defined + -- + + -- Reference clock is 24MHz + constant PACE_HAS_PLL : boolean := true; + --constant PACE_HAS_FLASH : boolean := false; + --constant PACE_HAS_SRAM : boolean := false; + constant PACE_HAS_SDRAM : boolean := false; + constant PACE_HAS_SERIAL : boolean := false; + + constant PACE_JAMMA : PACEJamma_t := PACE_JAMMA_NONE; + + ---- * defined in platform_pkg + --constant PACE_VIDEO_H_SIZE : integer := 224; + --constant PACE_VIDEO_V_SIZE : integer := 256; -- why not 240? + + constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_320x288_50Hz; -- PACE_VIDEO_VGA_800x600_60Hz; + constant PACE_CLK0_DIVIDE_BY : natural := 27; + constant PACE_CLK0_MULTIPLY_BY : natural := 6; -- 27/27*6 = 6MHz + constant PACE_CLK1_DIVIDE_BY : natural := 27; + constant PACE_CLK1_MULTIPLY_BY : natural := 6; -- 27/27*6 = 6MHz + constant PACE_VIDEO_H_SCALE : integer := 1; + constant PACE_VIDEO_V_SCALE : integer := 1; + constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1'; + constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1'; + + + constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK; + + constant PACE_HAS_OSD : boolean := false; + constant PACE_OSD_XPOS : natural := 0; + constant PACE_OSD_YPOS : natural := 0; + + -- NAVICO-ROCKY-specific constants + + constant ROCKY_EMULATED_SRAM_WIDTH_AD : natural := 16; + constant ROCKY_EMULATED_SRAM_WIDTH : natural := 8; + + constant ROCKY_EMULATED_FLASH_INIT_FILE : string := ""; + constant ROCKY_EMULATED_FLASH_WIDTH_AD : natural := 10; + constant ROCKY_EMULATED_FLASH_WIDTH : natural := 8; + + -- Moon Patrol-specific constants + + constant M52_USE_INTERNAL_WRAM : boolean := true; + + -- derived - do not edit + + constant ROCKY_EMULATE_SRAM : boolean := false; + constant ROCKY_EMULATE_FLASH : boolean := false; + + constant PACE_HAS_FLASH : boolean := false; + constant PACE_HAS_SRAM : boolean := false; + + type from_PROJECT_IO_t is record + not_used : std_logic; + end record; + + type to_PROJECT_IO_t is record + not_used : std_logic; + end record; + +end; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/rgb2ypbpr.sv b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/rgb2ypbpr.sv new file mode 100644 index 00000000..1e1662e8 --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/rgb2ypbpr.sv @@ -0,0 +1,55 @@ +module rgb2ypbpr ( + input [5:0] red, + input [5:0] green, + input [5:0] blue, + + output [5:0] y, + output [5:0] pb, + output [5:0] pr +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign pr = yuv_full[pr_i - 8'd16]; +assign y = yuv_full[y_i - 8'd16]; +assign pb = yuv_full[pb_i - 8'd16]; + +endmodule diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v index e85cba43..9236ea7a 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v @@ -2,7 +2,6 @@ // scandoubler.v // // Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -19,164 +18,160 @@ // TODO: Delay vsync one line -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +module scandoubler ( // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, + input clk_sys, - input hq2x, + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, + input hs_in, + input vs_in, + input [5:0] r_in, + input [5:0] g_in, + input [5:0] b_in, // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out + output reg hs_out, + output reg vs_out, + output reg [5:0] r_out, + output reg [5:0] g_out, + output reg [5:0] b_out ); +// try to detect changes in input signal and lock input clock gate +// it -localparam DWIDTH = HALF_DEPTH ? 2 : 5; +reg [1:0] i_div; +wire ce_x1 = (i_div == 2'b01); +wire ce_x2 = i_div[0]; -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; always @(posedge clk_sys) begin + reg last_hs_in; + last_hs_in <= hs_in; + if(last_hs_in & !hs_in) begin + i_div <= 2'b00; + end else begin + i_div <= i_div + 2'd1; + end +end - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - reg hs, hs2, vs, ls; +// --------------------- create output signals ----------------- +// latch everything once more to make it glitch free and apply scanline effect +reg scanline; +always @(posedge clk_sys) begin + if(ce_x2) begin + hs_out <= hs_sd; + vs_out <= vs_in; + + // reset scanlines at every new screen + if(vs_out != vs_in) scanline <= 0; + + // toggle scanlines at begin of every hsync + if(hs_out && !hs_sd) scanline <= !scanline; + + // if no scanlines or not a scanline + if(!scanline || !scanlines) begin + r_out <= sd_out[17:12]; + g_out <= sd_out[11:6]; + b_out <= sd_out[5:0]; + end else begin + case(scanlines) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out <= {1'b0, sd_out[17:14], 1'b0} + {2'b00, sd_out[17:14]}; + g_out <= {1'b0, sd_out[11:8], 1'b0} + {2'b00, sd_out[11:8] }; + b_out <= {1'b0, sd_out[5:2], 1'b0} + {2'b00, sd_out[5:2] }; + end + + 2: begin // reduce 50% = 1/2 + r_out <= {1'b0, sd_out[17:14], 1'b0}; + g_out <= {1'b0, sd_out[11:8], 1'b0}; + b_out <= {1'b0, sd_out[5:2], 1'b0}; + end + + 3: begin // reduce 75% = 1/4 + r_out <= {2'b00, sd_out[17:14]}; + g_out <= {2'b00, sd_out[11:8]}; + b_out <= {2'b00, sd_out[5:2]}; + end + endcase + end + end +end + +// scan doubler output register +reg [17:0] sd_out; + +// ================================================================== +// ======================== the line buffers ======================== +// ================================================================== + +// 2 lines of 512 pixels 3*6 bit RGB +(* ramstyle = "no_rw_check" *) reg [17:0] sd_buffer[2048]; + +// use alternating sd_buffers when storing/reading data +reg line_toggle; + +// total hsync time (in 16MHz cycles), hs_total reaches 1024 +reg [9:0] hs_max; +reg [9:0] hs_rise; +reg [9:0] hcnt; + +always @(posedge clk_sys) begin + reg hsD, vsD; if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + hsD <= hs_in; // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; + if(hsD && !hs_in) begin + hs_max <= hcnt; hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; end else begin hcnt <= hcnt + 1'd1; end // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + if(!hsD && hs_in) hs_rise <= hcnt; - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; + vsD <= vs_in; + if(vsD != vs_in) line_toggle <= 0; + + // begin of incoming hsync + if(hsD && !hs_in) line_toggle <= !line_toggle; + + sd_buffer[{line_toggle, hcnt}] <= {r_in, g_in, b_in}; end +end - if(ce_x4) begin - hs2 <= hs_in; +// ================================================================== +// ==================== output timing generation ==================== +// ================================================================== + +reg [9:0] sd_hcnt; +reg hs_sd; + +// timing generation runs 32 MHz (twice the input signal analysis speed) +always @(posedge clk_sys) begin + reg hsD; + + if(ce_x2) begin + hsD <= hs_in; // output counter synchronous to input and at twice the rate sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(hsD && !hs_in) sd_hcnt <= hs_max; if(sd_hcnt == hs_max) sd_hcnt <= 0; // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; + if(sd_hcnt == hs_max) hs_sd <= 0; + if(sd_hcnt == hs_rise) hs_sd <= 1; - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + // read data from line sd_buffer + sd_out <= sd_buffer[{~line_toggle, sd_hcnt}]; end end diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd index 2addead5..880f09f2 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd @@ -8,7 +8,7 @@ library work; use work.pace_pkg.all; use work.video_controller_pkg.all; use work.sprite_pkg.all; ---use work.platform_pkg.all; +use work.platform_pkg.all; entity sprite_array is generic diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd index 900bd5fa..1dbb3159 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd @@ -5,7 +5,9 @@ use ieee.numeric_std.all; library work; use work.pace_pkg.all; use work.video_controller_pkg.all; -use work.sprite_pkg.all; +use work.sprite_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; use work.platform_variant_pkg.all; entity spritectl is @@ -56,7 +58,7 @@ begin -- the width of rowCount determines the scanline multipler -- - eg. (4 downto 0) is 1:1 -- (5 downto 0) is 2:1 (scan-doubling) - variable rowCount : unsigned(3+2 downto 0); + variable rowCount : unsigned(3+PACE_VIDEO_V_SCALE downto 0); alias row : unsigned(4 downto 0) is rowCount(rowCount'left downto rowCount'left-4); @@ -69,7 +71,7 @@ begin if rising_edge(clk) then if clk_ena = '1' then - x := unsigned(reg_i.x) + 7 - 3; + x := unsigned(reg_i.x) + PACE_VIDEO_PIPELINE_DELAY - 3; y := 254 - unsigned(reg_i.y) - 16; if video_ctl.hblank = '1' then diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/target_top.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/target_top.vhd new file mode 100644 index 00000000..530eb43c --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/target_top.vhd @@ -0,0 +1,206 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.sdram_pkg.all; +use work.video_controller_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; +use work.target_pkg.all; + +entity target_top is + port + ( + clock_30 : in std_logic; + clock_v : in std_logic; + clock_3p58 : in std_logic; + reset : in std_logic; + + dn_addr : in std_logic_vector(15 downto 0); + dn_data : in std_logic_vector(7 downto 0); + dn_wr : in std_logic; + + AUDIO : out signed(12 downto 0); + JOY : in std_logic_vector(7 downto 0); + JOY2 : in std_logic_vector(7 downto 0); + + VGA_VBLANK : out std_logic; + VGA_HBLANK : out std_logic; + + VGA_VS : out std_logic; + VGA_HS : out std_logic; + VGA_R : out std_logic_vector(3 downto 0); + VGA_G : out std_logic_vector(3 downto 0); + VGA_B : out std_logic_vector(3 downto 0) + ); +end target_top; + +architecture SYN of target_top is + + signal clkrst_i : from_CLKRST_t; + signal buttons_i : from_BUTTONS_t; + signal switches_i : from_SWITCHES_t; + signal leds_o : to_LEDS_t; + signal inputs_i : from_INPUTS_t; + signal flash_i : from_FLASH_t; + signal flash_o : to_FLASH_t; + signal sram_i : from_SRAM_t; + signal sram_o : to_SRAM_t; + signal sdram_i : from_SDRAM_t; + signal sdram_o : to_SDRAM_t; + signal video_i : from_VIDEO_t; + signal video_o : to_VIDEO_t; + signal audio_i : from_AUDIO_t; + signal audio_o : to_AUDIO_t; + signal ser_i : from_SERIAL_t; + signal ser_o : to_SERIAL_t; + signal project_i : from_PROJECT_IO_t; + signal project_o : to_PROJECT_IO_t; + signal platform_i : from_PLATFORM_IO_t; + signal platform_o : to_PLATFORM_IO_t; + signal target_i : from_TARGET_IO_t; + signal target_o : to_TARGET_IO_t; + + signal sound_data : std_logic_vector(7 downto 0); +begin + + clkrst_i.clk(0)<=clock_30; + clkrst_i.clk(1)<=clock_v; + + clkrst_i.arst <= reset; + clkrst_i.arst_n <= not clkrst_i.arst; + + GEN_RESETS : for i in 0 to 3 generate + + process (clkrst_i.clk(i), clkrst_i.arst) + variable rst_r : std_logic_vector(2 downto 0) := (others => '0'); + begin + if clkrst_i.arst = '1' then + rst_r := (others => '1'); + elsif rising_edge(clkrst_i.clk(i)) then + rst_r := rst_r(rst_r'left-1 downto 0) & '0'; + end if; + clkrst_i.rst(i) <= rst_r(rst_r'left); + end process; + + end generate GEN_RESETS; + + inputs_i.jamma_n.coin(1) <= JOY(7); + inputs_i.jamma_n.p(1).start <= JOY(6); + + inputs_i.jamma_n.coin(2) <= JOY2(7); + inputs_i.jamma_n.p(2).start <= JOY2(6); + + inputs_i.jamma_n.p(1).up <= not JOY(3); + inputs_i.jamma_n.p(1).down <= not JOY(2); + inputs_i.jamma_n.p(1).left <= not JOY(1); + inputs_i.jamma_n.p(1).right <= not JOY(0); + + inputs_i.jamma_n.p(1).button(1) <= not JOY(4); + inputs_i.jamma_n.p(1).button(2) <= not JOY(5); + inputs_i.jamma_n.p(1).button(3) <= '1'; + inputs_i.jamma_n.p(1).button(4) <= '1'; + inputs_i.jamma_n.p(1).button(5) <= '1'; + + inputs_i.jamma_n.p(2).up <= not JOY2(3); + inputs_i.jamma_n.p(2).down <= not JOY2(2); + inputs_i.jamma_n.p(2).left <= not JOY2(1); + inputs_i.jamma_n.p(2).right <= not JOY2(0); + + inputs_i.jamma_n.p(2).button(1) <= not JOY2(4); + inputs_i.jamma_n.p(2).button(2) <= not JOY2(5); + inputs_i.jamma_n.p(2).button(3) <= '1'; + inputs_i.jamma_n.p(2).button(4) <= '1'; + inputs_i.jamma_n.p(2).button(5) <= '1'; + + + -- not currently wired to any inputs + inputs_i.jamma_n.coin_cnt <= (others => '1'); + --inputs_i.jamma_n.coin(2) <= '1'; + inputs_i.jamma_n.service <= '1'; + inputs_i.jamma_n.tilt <= '1'; + inputs_i.jamma_n.test <= '1'; + + video_i.clk <= clkrst_i.clk(1); -- by convention + video_i.clk_ena <= '1'; + video_i.reset <= clkrst_i.rst(1); + + VGA_R <= video_o.rgb.r(9 downto 6); + VGA_G <= video_o.rgb.g(9 downto 6); + VGA_B <= video_o.rgb.b(9 downto 6); + VGA_HS <= video_o.hsync; + VGA_VS <= video_o.vsync; + VGA_HBLANK <= video_o.hblank; + VGA_VBLANK <= video_o.vblank; + + pace_inst : entity work.pace + port map + ( + -- clocks and resets + clkrst_i => clkrst_i, + + -- misc inputs and outputs + buttons_i => buttons_i, + switches_i => switches_i, + leds_o => open, + + -- controller inputs + inputs_i => inputs_i, + + -- external ROM/RAM + flash_i => flash_i, + flash_o => flash_o, + sram_i => sram_i, + sram_o => sram_o, + sdram_i => sdram_i, + sdram_o => sdram_o, + + -- VGA video + video_i => video_i, + video_o => video_o, + + -- sound + audio_i => audio_i, + audio_o => audio_o, + + -- SPI (flash) + spi_i.din => '0', + spi_o => open, + + -- serial + ser_i => ser_i, + ser_o => ser_o, + + sound_data_o => sound_data, + + dn_addr => dn_addr, + dn_data => dn_data, + dn_wr => dn_wr, + + -- custom i/o + project_i => project_i, + project_o => project_o, + platform_i => platform_i, + platform_o => platform_o, + target_i => target_i, + target_o => target_o + ); + + moon_patrol_sound_board : entity work.moon_patrol_sound_board + port map( + clock_3p58 => clock_3p58, + reset => reset, + + clock_30 => clock_30, + dn_addr => dn_addr, + dn_data => dn_data, + dn_wr => dn_wr, + + select_sound => sound_data, + audio_out => AUDIO + ); + +end SYN; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd index 42e2c180..89bf260a 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd @@ -4,6 +4,8 @@ use ieee.numeric_std.all; library work; use work.pace_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; use work.platform_variant_pkg.all; use work.video_controller_pkg.all; @@ -13,27 +15,7 @@ use work.video_controller_pkg.all; -- Tile data is 2 BPP. -- -entity TILEMAP_1 is - generic - ( - DELAY : integer - ); - port - ( - reset : in std_logic; - - -- video control signals - video_ctl : in from_VIDEO_CTL_t; - - -- tilemap controller signals - ctl_i : in to_TILEMAP_CTL_t; - ctl_o : out from_TILEMAP_CTL_t; - - graphics_i : in to_GRAPHICS_t - ); -end entity TILEMAP_1; - -architecture tile1 of TILEMAP_1 is +architecture TILEMAP_1 of tilemapCtl is alias clk : std_logic is video_ctl.clk; alias clk_ena : std_logic is video_ctl.clk_ena; @@ -128,4 +110,4 @@ begin end process; -end architecture tile1; +end architecture TILEMAP_1; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl_e.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl_e.vhd new file mode 100644 index 00000000..68d3fd1a --- /dev/null +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl_e.vhd @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; +use work.video_controller_pkg.all; + +entity tilemapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- tilemap controller signals + ctl_i : in to_TILEMAP_CTL_t; + ctl_o : out from_TILEMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity tilemapCtl; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd index 155afc5a..86c2b754 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd @@ -1,8 +1,7 @@ -library ieee; +library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - library work; use work.video_controller_pkg.all; @@ -259,6 +258,16 @@ begin v_back_porch_r <= 13; v_border_r <= (240-VIDEO_V_SIZE)/2; + when PACE_VIDEO_PAL_320x288_50Hz => + h_front_porch_r <= 6; + h_sync_r <= 28; + h_back_porch_r <= 30; + h_border_r <= (320-VIDEO_H_SIZE)/2; + v_front_porch_r <= 8; + v_sync_r <= 3; + v_back_porch_r <= 13; + v_border_r <= (288-VIDEO_V_SIZE)/2; + when others => null; end case; @@ -439,8 +448,8 @@ begin end if; video_o.hsync <= hsync_v after SIM_DELAY; video_o.vsync <= vsync_v after SIM_DELAY; - video_o.hblank <= hblank_v after SIM_DELAY; - video_o.vblank <= vblank_v after SIM_DELAY; + video_o.hblank <= not hactive_v; -- hblank_v after SIM_DELAY; + video_o.vblank <= not vactive_v; -- vblank_v after SIM_DELAY; -- pipelined signals hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s; vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s; diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd index 183bfe23..7e8f42c6 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd @@ -21,7 +21,8 @@ package video_controller_pkg is PACE_VIDEO_ARCADE_STD_336x240_60Hz, -- arcade std resolution (7.16MHz) PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64, -- arcade std resolution (28.64MHz) PACE_VIDEO_CVBS_720x288p_50Hz, -- generic composite - PACE_VIDEO_LCM_320x240_60Hz -- DE2 LCD + PACE_VIDEO_LCM_320x240_60Hz, -- DE2 LCD + PACE_VIDEO_PAL_320x288_50Hz ); type PACEVideoDisplay_t is diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv deleted file mode 100644 index fb9e499a..00000000 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv +++ /dev/null @@ -1,233 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mist -/*#( - parameter LINE_LENGTH = 256, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -)*/ -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scan_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [5:0] R, - input [5:0] G, - input [5:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -wire [5:0] R_sd; -wire [5:0] G_sd; -wire [5:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(800), .HALF_DEPTH(0)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [5:0] rt = (scan_disable ? R : R_sd); -wire [5:0] gt = (scan_disable ? G : G_sd); -wire [5:0] bt = (scan_disable ? B : B_sd); - - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - - -wire hs = (scan_disable ? HSync : hs_sd); -wire vs = (scan_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(10'd0, 10'd0, 3'd4) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scan_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scan_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd index ab2cccaf..fb4b4aa4 100644 --- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd +++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd @@ -7,15 +7,15 @@ library work; use work.pace_pkg.all; use work.video_controller_pkg.all; use work.sprite_pkg.all; ---use work.platform_pkg.all; +use work.platform_pkg.all; entity pace_video_mixer is port ( --bitmap_rgb : in RGB_t; --bitmap_set : in std_logic; - bitmap_ctl_o : in from_BITMAP_CTL_a(1 to 3); - tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to 1); + bitmap_ctl_o : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); sprite_rgb : in RGB_t; sprite_set : in std_logic; sprite_pri : in std_logic; @@ -30,15 +30,37 @@ architecture SYN of pace_video_mixer is signal bg_rgb : RGB_t; begin + GEN_BITMAPS : + if PACE_VIDEO_NUM_BITMAPS = 1 generate + bg_rgb <= bitmap_ctl_o(1).rgb; + elsif PACE_VIDEO_NUM_BITMAPS = 2 generate + bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else + bitmap_ctl_o(2).rgb; + elsif PACE_VIDEO_NUM_BITMAPS = 3 generate bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else bitmap_ctl_o(2).rgb when bitmap_ctl_o(2).set = '1' else bitmap_ctl_o(3).rgb when bitmap_ctl_o(3).set = '1' else (others => (others => '0')); - - + else generate + bg_rgb <= (others => (others => '0')); + end generate GEN_BITMAPS; + + GEN_TILEMAPS : + if PACE_VIDEO_NUM_TILEMAPS = 1 generate rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else sprite_rgb when sprite_set = '1' else bg_rgb; + elsif PACE_VIDEO_NUM_TILEMAPS = 2 generate + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else + tilemap_ctl_o(2).rgb when tilemap_ctl_o(2).set = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + else generate + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + end generate GEN_TILEMAPS; end architecture SYN; diff --git a/Console_MiST/GCE - Vectrex_MiST/.gitignore b/Console_MiST/GCE - Vectrex_MiST/.gitignore new file mode 100644 index 00000000..ef0b2062 --- /dev/null +++ b/Console_MiST/GCE - Vectrex_MiST/.gitignore @@ -0,0 +1,6 @@ +PLLJ_PLLSPE_INFO.txt +db/ +incremental_db/ +output_files/ +build_id.v +*.bak diff --git a/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf b/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf index 045cdea3..05a6a7bc 100644 Binary files a/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf and b/Console_MiST/GCE - Vectrex_MiST/Release/vectrex_MiST.rbf differ diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149.sv new file mode 100644 index 00000000..e4cf9525 --- /dev/null +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149.sv @@ -0,0 +1,326 @@ +// +// Copyright (c) MikeJ - Jan 2005 +// Copyright (c) 2016-2018 Sorgelig +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + + +// BDIR BC MODE +// 0 0 inactive +// 0 1 read value +// 1 0 write value +// 1 1 set address +// + +module YM2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + output [5:0] ACTIVE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign ACTIVE = ~ymreg[7][5:0]; +assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; +assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; + +reg [7:0] addr; +reg [7:0] ymreg[16]; + +// Write to PSG +reg env_reset; +always @(posedge CLK) begin + if(RESET) begin + ymreg <= '{default:0}; + ymreg[7] <= '1; + addr <= '0; + env_reset <= 0; + end else begin + env_reset <= 0; + if(BDIR) begin + if(BC) addr <= DI; + else if(!addr[7:4]) begin + ymreg[addr[3:0]] <= DI; + env_reset <= (addr == 13); + end + end + end +end + +// Read from PSG +assign DO = dout; +reg [7:0] dout; +always_comb begin + dout = 8'hFF; + if(~BDIR & BC & !addr[7:4]) begin + case(addr[3:0]) + 0: dout = ymreg[0]; + 1: dout = ymreg[1][3:0]; + 2: dout = ymreg[2]; + 3: dout = ymreg[3][3:0]; + 4: dout = ymreg[4]; + 5: dout = ymreg[5][3:0]; + 6: dout = ymreg[6][4:0]; + 7: dout = ymreg[7]; + 8: dout = ymreg[8][4:0]; + 9: dout = ymreg[9][4:0]; + 10: dout = ymreg[10][4:0]; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = ymreg[13][3:0]; + 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; + 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; + endcase + end +end + +reg ena_div; +reg ena_div_noise; + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [2:0] noise_gen_op; + +// p_noise_gen +always @(posedge CLK) begin + reg [16:0] poly17; + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + noise_gen_op <= {3{poly17[0]}}; + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_freq[i]) begin + if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= ~tone_gen_op[i]; + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end else begin + tone_gen_op[i] <= ymreg[7][i]; + tone_gen_cnt[i] <= 0; + end + end + end + end +end + +reg env_ena; +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +reg [4:0] env_vol; + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(env_reset | RESET) begin + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end + else if(CE) begin + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end +end + +reg [5:0] A,B,C; +always @(posedge CLK) begin + A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; + B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; + C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; +end + +wire [7:0] volTable[64] = '{ + //YM2149 + 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, + + //AY8910 + 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, + 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, + 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, + 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff +}; + +assign CHANNEL_A = volTable[A]; +assign CHANNEL_B = volTable[B]; +assign CHANNEL_C = volTable[C]; + +endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149_linmix_sep.vhd b/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149_linmix_sep.vhd deleted file mode 100644 index 6ed2498a..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/YM2149_linmix_sep.vhd +++ /dev/null @@ -1,574 +0,0 @@ --- changes for seperate audio outputs and enable now enables cpu access as well --- --- A simulation model of YM2149 (AY-3-8910 with bells on) - --- Copyright (c) MikeJ - Jan 2005 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 001 initial release --- --- Clues from MAME sound driver and Kazuhiro TSUJIKAWA --- --- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) --- vol 15 .. 0 --- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 --- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order --- to produced all the required values. --- (The first part of the curve is a bit steeper and the last bit is more linear than expected) --- --- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only --- accurate for designs where the outputs are buffered and not simply wired together. --- The ouput level is more complex in that case and requires a larger table. - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity YM2149 is - port ( - -- data bus - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - O_DA_OE_L : out std_logic; - -- control - I_A9_L : in std_logic; - I_A8 : in std_logic; - I_BDIR : in std_logic; - I_BC2 : in std_logic; - I_BC1 : in std_logic; - I_SEL_L : in std_logic; - - O_AUDIO : out std_logic_vector(7 downto 0); - O_CHAN : out std_logic_vector(1 downto 0); - -- port a - I_IOA : in std_logic_vector(7 downto 0); - O_IOA : out std_logic_vector(7 downto 0); - O_IOA_OE_L : out std_logic; - -- port b - I_IOB : in std_logic_vector(7 downto 0); - O_IOB : out std_logic_vector(7 downto 0); - O_IOB_OE_L : out std_logic; - - ENA : in std_logic; -- clock enable for higher speed operation - RESET_L : in std_logic; - CLK : in std_logic -- note 6 Mhz - ); -end; - -architecture RTL of YM2149 is - type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); - type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); - - signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); - signal cnt_div_t1 : std_logic_vector(3 downto 0); - signal noise_div : std_logic := '0'; - signal ena_div : std_logic; - signal ena_div_noise : std_logic; - signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); - - -- registers - signal addr : std_logic_vector(7 downto 0); - signal busctrl_addr : std_logic; - signal busctrl_we : std_logic; - signal busctrl_re : std_logic; - - signal reg : array_16x8; - signal env_reset : std_logic; - signal ioa_inreg : std_logic_vector(7 downto 0); - signal iob_inreg : std_logic_vector(7 downto 0); - - signal noise_gen_cnt : std_logic_vector(4 downto 0); - signal noise_gen_op : std_logic; - signal tone_gen_cnt : array_3x12 := (others => (others => '0')); - signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; - - signal env_gen_cnt : std_logic_vector(15 downto 0); - signal env_ena : std_logic; - signal env_hold : std_logic; - signal env_inc : std_logic; - signal env_vol : std_logic_vector(4 downto 0); - - signal tone_ena_l : std_logic; - signal tone_src : std_logic; - signal noise_ena_l : std_logic; - signal chan_vol : std_logic_vector(4 downto 0); - - signal dac_amp : std_logic_vector(7 downto 0); -begin - -- cpu i/f - p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) - variable cs : std_logic; - variable sel : std_logic_vector(2 downto 0); - begin - -- BDIR BC2 BC1 MODE - -- 0 0 0 inactive - -- 0 0 1 address - -- 0 1 0 inactive - -- 0 1 1 read - -- 1 0 0 address - -- 1 0 1 inactive - -- 1 1 0 write - -- 1 1 1 read - busctrl_addr <= '0'; - busctrl_we <= '0'; - busctrl_re <= '0'; - - cs := '0'; - if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then - cs := '1'; - end if; - - sel := (I_BDIR & I_BC2 & I_BC1); - case sel is - when "000" => null; - when "001" => busctrl_addr <= '1'; - when "010" => null; - when "011" => busctrl_re <= cs; - when "100" => busctrl_addr <= '1'; - when "101" => null; - when "110" => busctrl_we <= cs; - when "111" => busctrl_addr <= '1'; - when others => null; - end case; - end process; - - p_oe : process(busctrl_re) - begin - -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns - O_DA_OE_L <= not (busctrl_re); - end process; - - -- - -- CLOCKED - -- - p_waddr : process(RESET_L, CLK) - begin - -- looks like registers are latches in real chip, but the address is caught at the end of the address state. - if (RESET_L = '0') then - addr <= (others => '0'); - elsif rising_edge(CLK) then - if (ENA = '1') then - if (busctrl_addr = '1') then - addr <= I_DA; - end if; - end if; - end if; - end process; - - p_wdata : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - reg <= (others => (others => '0')); - env_reset <= '1'; - elsif rising_edge(CLK) then - if (ENA = '1') then - env_reset <= '0'; - if (busctrl_we = '1') then - case addr(3 downto 0) is - when x"0" => reg(0) <= I_DA; - when x"1" => reg(1) <= I_DA; - when x"2" => reg(2) <= I_DA; - when x"3" => reg(3) <= I_DA; - when x"4" => reg(4) <= I_DA; - when x"5" => reg(5) <= I_DA; - when x"6" => reg(6) <= I_DA; - when x"7" => reg(7) <= I_DA; - when x"8" => reg(8) <= I_DA; - when x"9" => reg(9) <= I_DA; - when x"A" => reg(10) <= I_DA; - when x"B" => reg(11) <= I_DA; - when x"C" => reg(12) <= I_DA; - when x"D" => reg(13) <= I_DA; env_reset <= '1'; - when x"E" => reg(14) <= I_DA; - when x"F" => reg(15) <= I_DA; - when others => null; - end case; - end if; - end if; - end if; - end process; - - p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) - begin - O_DA <= (others => '0'); -- 'X' - if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator - case addr(3 downto 0) is - when x"0" => O_DA <= reg(0) ; - when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; - when x"2" => O_DA <= reg(2) ; - when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; - when x"4" => O_DA <= reg(4) ; - when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; - when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; - when x"7" => O_DA <= reg(7) ; - when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; - when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; - when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; - when x"B" => O_DA <= reg(11); - when x"C" => O_DA <= reg(12); - when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); - when x"E" => if (reg(7)(6) = '0') then -- input - O_DA <= ioa_inreg; - else - O_DA <= reg(14); -- read output reg - end if; - when x"F" => if (Reg(7)(7) = '0') then - O_DA <= iob_inreg; - else - O_DA <= reg(15); - end if; - when others => null; - end case; - end if; - end process; - -- - p_divider : process - begin - wait until rising_edge(CLK); - -- / 8 when SEL is high and /16 when SEL is low - if (ENA = '1') then - ena_div <= '0'; - ena_div_noise <= '0'; - if (cnt_div = "0000") then - cnt_div <= (not I_SEL_L) & "111"; - ena_div <= '1'; - - noise_div <= not noise_div; - if (noise_div = '1') then - ena_div_noise <= '1'; - end if; - else - cnt_div <= cnt_div - "1"; - end if; - end if; - end process; - - p_noise_gen : process - variable noise_gen_comp : std_logic_vector(4 downto 0); - variable poly17_zero : std_logic; - begin - wait until rising_edge(CLK); - if (reg(6)(4 downto 0) = "00000") then - noise_gen_comp := "00000"; - else - noise_gen_comp := (reg(6)(4 downto 0) - "1"); - end if; - - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - - if (ENA = '1') then - if (ena_div_noise = '1') then -- divider ena - - if (noise_gen_cnt >= noise_gen_comp) then - noise_gen_cnt <= "00000"; - poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); - else - noise_gen_cnt <= (noise_gen_cnt + "1"); - end if; - end if; - end if; - end process; - noise_gen_op <= poly17(0); - - p_tone_gens : process - variable tone_gen_freq : array_3x12; - variable tone_gen_comp : array_3x12; - begin - wait until rising_edge(CLK); - -- looks like real chips count up - we need to get the Exact behaviour .. - tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); - tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); - tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); - -- period 0 = period 1 - for i in 1 to 3 loop - if (tone_gen_freq(i) = x"000") then - tone_gen_comp(i) := x"000"; - else - tone_gen_comp(i) := (tone_gen_freq(i) - "1"); - end if; - end loop; - - if (ENA = '1') then - for i in 1 to 3 loop - if (ena_div = '1') then -- divider ena - - if (tone_gen_cnt(i) >= tone_gen_comp(i)) then - tone_gen_cnt(i) <= x"000"; - tone_gen_op(i) <= not tone_gen_op(i); - else - tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); - end if; - end if; - end loop; - end if; - end process; - - p_envelope_freq : process - variable env_gen_freq : std_logic_vector(15 downto 0); - variable env_gen_comp : std_logic_vector(15 downto 0); - begin - wait until rising_edge(CLK); - env_gen_freq := reg(12) & reg(11); - -- envelope freqs 1 and 0 are the same. - if (env_gen_freq = x"0000") then - env_gen_comp := x"0000"; - else - env_gen_comp := (env_gen_freq - "1"); - end if; - - if (ENA = '1') then - env_ena <= '0'; - if (ena_div = '1') then -- divider ena - if (env_gen_cnt >= env_gen_comp) then - env_gen_cnt <= x"0000"; - env_ena <= '1'; - else - env_gen_cnt <= (env_gen_cnt + "1"); - end if; - end if; - end if; - end process; - - p_envelope_shape : process(env_reset, reg, CLK) - variable is_bot : boolean; - variable is_bot_p1 : boolean; - variable is_top_m1 : boolean; - variable is_top : boolean; - begin - -- envelope shapes - -- C AtAlH - -- 0 0 x x \___ - -- - -- 0 1 x x /___ - -- - -- 1 0 0 0 \\\\ - -- - -- 1 0 0 1 \___ - -- - -- 1 0 1 0 \/\/ - -- ___ - -- 1 0 1 1 \ - -- - -- 1 1 0 0 //// - -- ___ - -- 1 1 0 1 / - -- - -- 1 1 1 0 /\/\ - -- - -- 1 1 1 1 /___ - if (env_reset = '1') then - -- load initial state - if (reg(13)(2) = '0') then -- attack - env_vol <= "11111"; - env_inc <= '0'; -- -1 - else - env_vol <= "00000"; - env_inc <= '1'; -- +1 - end if; - env_hold <= '0'; - - elsif rising_edge(CLK) then - is_bot := (env_vol = "00000"); - is_bot_p1 := (env_vol = "00001"); - is_top_m1 := (env_vol = "11110"); - is_top := (env_vol = "11111"); - - if (ENA = '1') then - if (env_ena = '1') then - if (env_hold = '0') then - if (env_inc = '1') then - env_vol <= (env_vol + "00001"); - else - env_vol <= (env_vol + "11111"); - end if; - end if; - - -- envelope shape control. - if (reg(13)(3) = '0') then - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - else - if is_top then env_hold <= '1'; end if; - end if; - else - if (reg(13)(0) = '1') then -- hold = 1 - if (env_inc = '0') then -- down - if (reg(13)(1) = '1') then -- alt - if is_bot then env_hold <= '1'; end if; - else - if is_bot_p1 then env_hold <= '1'; end if; - end if; - else - if (reg(13)(1) = '1') then -- alt - if is_top then env_hold <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - end if; - end if; - - elsif (reg(13)(1) = '1') then -- alternate - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - if is_bot then env_hold <= '0'; env_inc <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - if is_top then env_hold <= '0'; env_inc <= '0'; end if; - end if; - end if; - - end if; - end if; - end if; - end if; - end process; - - p_chan_mixer : process(cnt_div, reg, tone_gen_op) - begin - tone_ena_l <= '1'; tone_src <= '1'; - noise_ena_l <= '1'; chan_vol <= "00000"; - case cnt_div(1 downto 0) is - when "00" => - tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); - noise_ena_l <= reg(7)(3); - when "01" => - tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); - noise_ena_l <= reg(7)(4); - when "10" => - tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); - noise_ena_l <= reg(7)(5); - when "11" => null; -- tone gen outputs become valid on this clock - when others => null; - end case; - end process; - - p_op_mixer : process - variable chan_mixed : std_logic; - variable chan_amp : std_logic_vector(4 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); - - chan_amp := (others => '0'); - if (chan_mixed = '1') then - if (chan_vol(4) = '0') then - if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet - chan_amp := "00000"; - else - chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) - end if; - else - chan_amp := env_vol(4 downto 0); - end if; - end if; - - dac_amp <= x"00"; - case chan_amp is - when "11111" => dac_amp <= x"FF"; - when "11110" => dac_amp <= x"D9"; - when "11101" => dac_amp <= x"BA"; - when "11100" => dac_amp <= x"9F"; - when "11011" => dac_amp <= x"88"; - when "11010" => dac_amp <= x"74"; - when "11001" => dac_amp <= x"63"; - when "11000" => dac_amp <= x"54"; - when "10111" => dac_amp <= x"48"; - when "10110" => dac_amp <= x"3D"; - when "10101" => dac_amp <= x"34"; - when "10100" => dac_amp <= x"2C"; - when "10011" => dac_amp <= x"25"; - when "10010" => dac_amp <= x"1F"; - when "10001" => dac_amp <= x"1A"; - when "10000" => dac_amp <= x"16"; - when "01111" => dac_amp <= x"13"; - when "01110" => dac_amp <= x"10"; - when "01101" => dac_amp <= x"0D"; - when "01100" => dac_amp <= x"0B"; - when "01011" => dac_amp <= x"09"; - when "01010" => dac_amp <= x"08"; - when "01001" => dac_amp <= x"07"; - when "01000" => dac_amp <= x"06"; - when "00111" => dac_amp <= x"05"; - when "00110" => dac_amp <= x"04"; - when "00101" => dac_amp <= x"03"; - when "00100" => dac_amp <= x"03"; - when "00011" => dac_amp <= x"02"; - when "00010" => dac_amp <= x"02"; - when "00001" => dac_amp <= x"01"; - when "00000" => dac_amp <= x"00"; - when others => null; - end case; - - cnt_div_t1 <= cnt_div; - end if; - end process; - - p_audio_output : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - O_AUDIO <= (others => '0'); - O_CHAN <= (others => '0'); - elsif rising_edge(CLK) then - - if (ENA = '1') then - O_AUDIO <= dac_amp(7 downto 0); - O_CHAN <= cnt_div_t1(1 downto 0); - end if; - end if; - end process; - - p_io_ports : process(reg) - begin - O_IOA <= reg(14); - O_IOA_OE_L <= not reg(7)(6); - O_IOB <= reg(15); - O_IOB_OE_L <= not reg(7)(7); - end process; - - p_io_ports_inreg : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then -- resync - ioa_inreg <= I_IOA; - iob_inreg <= I_IOB; - end if; - end process; -end architecture RTL; diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/build_id.v b/Console_MiST/GCE - Vectrex_MiST/rtl/build_id.v deleted file mode 100644 index 5b8a846e..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180624" -`define BUILD_TIME "125342" diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/card.qip b/Console_MiST/GCE - Vectrex_MiST/rtl/card.qip deleted file mode 100644 index 53989c71..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/card.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "card.v"] diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/card.v b/Console_MiST/GCE - Vectrex_MiST/rtl/card.v deleted file mode 100644 index 34faa9f6..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/card.v +++ /dev/null @@ -1,177 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: card.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module card ( - address, - clock, - data, - rden, - wren, - q); - - input [13:0] address; - input clock; - input [7:0] data; - input rden; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; - tri1 rden; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .rden_a (rden), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 16384, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 14, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "14" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "1" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL card.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL card.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL card.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL card.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL card_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL card_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/hq2x.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/keyboard.v b/Console_MiST/GCE - Vectrex_MiST/rtl/keyboard.v deleted file mode 100644 index afa04144..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/keyboard.v +++ /dev/null @@ -1,92 +0,0 @@ - - -module keyboard -( - input clk, - input reset, - input ps2_kbd_clk, - input ps2_kbd_data, - - output reg[15:0] joystick -); - -reg [11:0] shift_reg = 12'hFFF; -wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; -wire [7:0] kcode = kdata[9:2]; -reg release_btn = 0; - -reg [7:0] code; -reg input_strobe = 0; - -always @(negedge clk) begin - reg old_reset = 0; - - old_reset <= reset; - - if(~old_reset & reset)begin - joystick <= 0; - end - - if(input_strobe) begin - case(code) - 'h16: joystick[4] <= ~release_btn; // 1 - 'h1E: joystick[5] <= ~release_btn; // 2 - 'h26: joystick[6] <= ~release_btn; // 3 - 'h25: joystick[7] <= ~release_btn; // 4 - - 'h1D: joystick[11] <= ~release_btn; // W - 'h1B: joystick[10] <= ~release_btn; // S - 'h1C: joystick[9] <= ~release_btn; // A - 'h23: joystick[8] <= ~release_btn; // D - - 'h77: joystick[12] <= ~release_btn; // NUM - 'h4A: joystick[13] <= ~release_btn; // / - 'h7C: joystick[14] <= ~release_btn; // * - 'h7B: joystick[15] <= ~release_btn; // - - - 'h75: joystick[3] <= ~release_btn; // arrow up - 'h72: joystick[2] <= ~release_btn; // arrow down - 'h6B: joystick[1] <= ~release_btn; // arrow left - 'h74: joystick[0] <= ~release_btn; // arrow right - - - - endcase - end -end - -always @(posedge clk) begin - reg [3:0] prev_clk = 0; - reg old_reset = 0; - reg action = 0; - - old_reset <= reset; - input_strobe <= 0; - - if(~old_reset & reset)begin - prev_clk <= 0; - shift_reg <= 12'hFFF; - end else begin - prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; - if(prev_clk == 1) begin - if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin - shift_reg <= 12'hFFF; - if (kcode == 8'he0) ; - // Extended key code follows - else if (kcode == 8'hf0) - // Release code follows - action <= 1; - else begin - // Cancel extended/release flags for next time - action <= 0; - release_btn <= action; - code <= kcode; - input_strobe <= 1; - end - end else begin - shift_reg <= kdata; - end - end - end -end -endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/osd.v b/Console_MiST/GCE - Vectrex_MiST/rtl/osd.v index c62c10af..f0906039 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/osd.v +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/osd.v @@ -160,15 +160,19 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) begin + osd_hcnt <= h_cnt - h_osd_start + 2'd2; // 1+1 pixel offset for osd_byte register + osd_vcnt <= v_cnt - v_osd_start; + osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; +end wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/pll.v b/Console_MiST/GCE - Vectrex_MiST/rtl/pll.v index 86111024..7fe12a9b 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/pll.v +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 SJ Web Edition // ************************************************************ -//Copyright (C) 1991-2013 Altera Corporation +//Copyright (C) 1991-2014 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -41,14 +41,12 @@ module pll ( inclk0, c0, c1, - c2, locked); input areset; input inclk0; output c0; output c1; - output c2; output locked; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off @@ -60,20 +58,18 @@ module pll ( wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire6 = 1'h0; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( .areset (areset), - .inclk (sub_wire6), + .inclk (sub_wire5), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -119,10 +115,6 @@ module pll ( altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 4, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 9, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 2, - altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -157,7 +149,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -198,13 +190,10 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -226,33 +215,25 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -276,16 +257,13 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -298,10 +276,6 @@ endmodule // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -335,7 +309,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -355,7 +329,6 @@ endmodule // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -363,7 +336,6 @@ endmodule // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/rgb2ypbpr.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/rgb2ypbpr.sv new file mode 100644 index 00000000..1e1662e8 --- /dev/null +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/rgb2ypbpr.sv @@ -0,0 +1,55 @@ +module rgb2ypbpr ( + input [5:0] red, + input [5:0] green, + input [5:0] blue, + + output [5:0] y, + output [5:0] pb, + output [5:0] pr +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign pr = yuv_full[pr_i - 8'd16]; +assign y = yuv_full[y_i - 8'd16]; +assign pb = yuv_full[pb_i - 8'd16]; + +endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/scandoubler.v b/Console_MiST/GCE - Vectrex_MiST/rtl/scandoubler.v deleted file mode 100644 index 36e71ed2..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,194 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/sdram.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/sdram.sv new file mode 100644 index 00000000..53a14e5e --- /dev/null +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/sdram.sv @@ -0,0 +1,254 @@ +// +// sdram.v +// +// Static RAM controller implementation using SDRAM MT48LC16M16A2 +// +// Copyright (c) 2015,2016 Sorgelig +// +// Some parts of SDRAM code used from project: +// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// +// v2.1 - Add universal 8/16 bit mode. +// + +module sdram +( + input init, // reset to initialize RAM + input clk, // clock ~100MHz + // + // SDRAM_* - signals to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + output SDRAM_CKE, // clock enable + // + input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte, + // 8bit mode: 2'b00 - use addr[0] to decide which byte to write + // Ignored while reading. + // + input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations. + output [15:0] dout, // data output to cpu + input [15:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output reg ready // dout is valid. Ready to accept new read/write. +); + +assign SDRAM_nCS = command[3]; +assign SDRAM_nRAS = command[2]; +assign SDRAM_nCAS = command[1]; +assign SDRAM_nWE = command[0]; +assign SDRAM_CKE = cke; + +// no burst configured +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write +localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz +localparam cycles_per_refresh = 14'd186; // (64000*24)/8192-1 Calc'd as (64ms @ 24MHz)/8192 rose +localparam startup_refresh_max = 14'b11111111111111; + +// SDRAM commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles; +reg [3:0] command = CMD_INHIBIT; +reg cke = 0; +reg [24:0] save_addr; +reg [15:0] data; + +assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]}; +typedef enum +{ + STATE_STARTUP, + STATE_OPEN_1, + STATE_WRITE, + STATE_READ, + STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3, + STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7 +} state_t; + +state_t state = STATE_STARTUP; + +always @(posedge clk) begin + reg old_we, old_rd; + reg [CAS_LATENCY:0] data_ready_delay; + + reg [15:0] new_data; + reg [1:0] new_wtbt; + reg new_we; + reg new_rd; + reg save_we = 1; + + + command <= CMD_NOP; + refresh_count <= refresh_count+1'b1; + + data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]}; + + if(data_ready_delay[0]) data <= SDRAM_DQ; + + case(state) + STATE_STARTUP: begin + //------------------------------------------------------------------------ + //-- This is the initial startup state, where we wait for at least 100us + //-- before starting the start sequence + //-- + //-- The initialisation is sequence is + //-- * de-assert SDRAM_CKE + //-- * 100us wait, + //-- * assert SDRAM_CKE + //-- * wait at least one cycle, + //-- * PRECHARGE + //-- * wait 2 cycles + //-- * REFRESH, + //-- * tREF wait + //-- * REFRESH, + //-- * tREF wait + //-- * LOAD_MODE_REG + //-- * 2 cycles wait + //------------------------------------------------------------------------ + cke <= 1; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + SDRAM_A <= 0; + SDRAM_BA <= 0; + + // All the commands during the startup are NOPS, except these + if(refresh_count == startup_refresh_max-31) begin + // ensure all rows are closed + command <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; // all banks + SDRAM_BA <= 2'b00; + end else if (refresh_count == startup_refresh_max-23) begin + // these refreshes need to be at least tREF (66ns) apart + command <= CMD_AUTO_REFRESH; + end else if (refresh_count == startup_refresh_max-15) + command <= CMD_AUTO_REFRESH; + else if (refresh_count == startup_refresh_max-7) begin + // Now load the mode register + command <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + + //------------------------------------------------------ + //-- if startup is complete then go into idle mode, + //-- get prepared to accept a new command, and schedule + //-- the first refresh cycle + //------------------------------------------------------ + if(!refresh_count) begin + state <= STATE_IDLE; + ready <= 1; + refresh_count <= 0; + end + end + + STATE_IDLE_7: state <= STATE_IDLE_6; + STATE_IDLE_6: state <= STATE_IDLE_5; + STATE_IDLE_5: state <= STATE_IDLE_4; + STATE_IDLE_4: state <= STATE_IDLE_3; + STATE_IDLE_3: state <= STATE_IDLE_2; + STATE_IDLE_2: state <= STATE_IDLE_1; + STATE_IDLE_1: begin + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + state <= STATE_IDLE; + // mask possible refresh to reduce colliding. + if(refresh_count > cycles_per_refresh) begin + //------------------------------------------------------------------------ + //-- Start the refresh cycle. + //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 24MHz + //------------------------------------------------------------------------ + state <= STATE_IDLE_2; + command <= CMD_AUTO_REFRESH; + refresh_count <= refresh_count - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE: begin + // Priority is to issue a refresh if one is outstanding + if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1; + else if(new_rd | new_we) begin + new_we <= 0; + new_rd <= 0; + save_addr<= addr; + save_we <= new_we; + state <= STATE_OPEN_1; + command <= CMD_ACTIVE; + SDRAM_A <= addr[13:1]; + SDRAM_BA <= addr[24:23]; + end + end + + // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 24 MHz)(-75) + STATE_OPEN_1: begin + SDRAM_A <= {4'b0010, save_addr[22:14]}; + SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]); + SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]); + state <= save_we ? STATE_WRITE : STATE_READ; + end + + STATE_READ: begin + state <= STATE_IDLE_5; + command <= CMD_READ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + + // Schedule reading the data values off the bus + data_ready_delay[CAS_LATENCY] <= 1; + end + + STATE_WRITE: begin + state <= STATE_IDLE_5; + command <= CMD_WRITE; + SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]}; + ready <= 1; + end + endcase + + if(init) begin + state <= STATE_STARTUP; + refresh_count <= startup_refresh_max - sdram_startup_cycles; + end + + old_we <= we; + old_rd <= rd; + if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt}; + else + if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1}; + +end + +endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd index eeea160e..e8740fbd 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd @@ -154,7 +154,7 @@ port frame : out std_logic; audio_out : out std_logic_vector(9 downto 0); - cart_addr : out std_logic_vector(13 downto 0); + cart_addr : out std_logic_vector(14 downto 0); cart_do : in std_logic_vector( 7 downto 0); cart_rd : out std_logic; btn11 : in std_logic; @@ -180,6 +180,32 @@ end vectrex; architecture syn of vectrex is + component YM2149 + port ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write) + BC : in std_logic; -- Bus control + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A : out std_logic_vector(7 downto 0); + CHANNEL_B : out std_logic_vector(7 downto 0); + CHANNEL_C : out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + + ACTIVE : out std_logic_vector(5 downto 0); + + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + -------------------------------------------------------------- -- Configuration -------------------------------------------------------------- @@ -216,12 +242,13 @@ architecture syn of vectrex is -------------------------------------------------------------- signal clock_24n : std_logic; - signal clock_div : std_logic_vector(2 downto 0); + signal clock_div : std_logic_vector(3 downto 0); signal clock_div2: std_logic_vector(6 downto 0); signal clock_250k: std_logic; signal reset_n : std_logic; signal cpu_clock : std_logic; + signal cpu_clock_en: std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -345,7 +372,8 @@ architecture syn of vectrex is signal pot : signed(7 downto 0); signal compare : std_logic; signal players_switches : std_logic_vector(7 downto 0); - + signal ay_ioa_out : std_logic_vector(7 downto 0); + signal vectrex_bd_rate_div : std_logic_vector(7 downto 0) := X"00"; signal vectrex_serial_bit_in : std_logic; signal vectrex_serial_bit_in_d : std_logic; @@ -365,9 +393,9 @@ architecture syn of vectrex is begin -- debug -process (clock_12) +process (clock_24) begin - if rising_edge(clock_12) then + if rising_edge(clock_24) then if cpu_ifetch = '1' then dbg_cpu_addr <= cpu_addr; end if; @@ -378,23 +406,20 @@ end process; reset_n <= not reset; clock_24n <= not clock_24; -process (clock_12, reset) +process (clock_24, reset) begin if reset='1' then - clock_div <= "000"; + clock_div <= "0000"; else - if rising_edge(clock_12) then - if clock_div = "111" then - clock_div <= "000"; - else - clock_div <= clock_div + '1'; - end if; + if rising_edge(clock_24) then + clock_div <= clock_div + '1'; end if; end if; end process; -via_en_4 <= clock_div(0); -cpu_clock <= clock_div(2); +via_en_4 <= '1' when clock_div(1 downto 0) = "11" else '0'; +cpu_clock <= clock_div(3); +cpu_clock_en <= '1' when clock_div(3 downto 0) = "1111" else '0'; process (clock_24, reset) begin @@ -739,17 +764,8 @@ end process; video_hblank <= hblank; video_vblank <= vblank; scan_video_addr <= vcnt_video * std_logic_vector(to_unsigned(max_h,10)) + hcnt_video; - --- sound -process (cpu_clock) -begin - if rising_edge(cpu_clock) then - if ay_audio_chan = "00" then ay_chan_a <= ay_audio_muxed; end if; - if ay_audio_chan = "01" then ay_chan_b <= ay_audio_muxed; end if; - if ay_audio_chan = "10" then ay_chan_c <= ay_audio_muxed; end if; - end if; -end process; +-- sound audio_1 <= ("00"&ay_chan_a) + ("00"&ay_chan_b) + ("00"&ay_chan_c) + @@ -757,6 +773,59 @@ audio_1 <= ("00"&ay_chan_a) + audio_out <= "000"&audio_1(9 downto 3) + audio_speech; +-- vectrex just toggle port A forced/high Z to produce serial data +-- when in high Z vectrex sense port A to get speech chip ready for new byte +vectrex_serial_bit_in <= ay_ioa_out(4); + +-- get serial data from vectrex joystick port + +process (cpu_clock, reset) + begin + if reset='1' then + vectrex_bd_rate_div <= X"00"; + elsif rising_edge(clock_24) then + if cpu_clock_en = '1' then + + vectrex_serial_bit_in_d <= vectrex_serial_bit_in; + + if vectrex_serial_bit_in /= vectrex_serial_bit_in_d then -- reset baud counter on either edge + vectrex_bd_rate_div <= X"00"; + else + if vectrex_bd_rate_div = X"9B" then -- 1.5MHz/156 = 9615kHz + vectrex_bd_rate_div <= X"00"; + else + vectrex_bd_rate_div <= vectrex_bd_rate_div + '1'; + end if; + end if; + + if vectrex_bd_rate_div = X"4E" then + vectrex_serial_data_shift <= vectrex_serial_bit_in & vectrex_serial_data_shift(7 downto 1); -- serial is lsb first (ok speakjet/vecvoice/vecvox) + + if vectrex_serial_bit_cnt = X"0" and vectrex_serial_bit_in = '0' then + vectrex_serial_bit_cnt <= X"1"; + vectrex_serial_byte_rdy <= '0'; + end if; + + if vectrex_serial_bit_cnt > X"0" then + vectrex_serial_bit_cnt <= vectrex_serial_bit_cnt + '1'; + end if; + + if vectrex_serial_bit_cnt = X"A" then + vectrex_serial_bit_cnt <= X"0"; + end if; + + end if; + + if vectrex_bd_rate_div = X"60" then + if vectrex_serial_bit_cnt = X"9" then + vectrex_serial_byte_rdy <= '1'; + vectrex_serial_byte_out <= vectrex_serial_data_shift; + end if; + end if; + + end if; + end if; +end process; frame <= frame_line; --------------------------- @@ -766,8 +835,8 @@ frame <= frame_line; -- microprocessor 6809 main_cpu : entity work.cpu09 port map( - clk => cpu_clock,-- E clock input (falling edge) - ce => '1', + clk => clock_24,-- E clock input (falling edge) + ce => cpu_clock_en, rst => reset, -- reset input (active high) vma => open, -- valid memory address (active high) lic_out => open, -- last instruction cycle (active high) @@ -789,7 +858,7 @@ port map( cpu_prog_rom : entity work.vectrex_exec_prom port map( - clk => cpu_clock, + clk => clock_24, addr => cpu_addr(12 downto 0), data => rom_do ); @@ -822,12 +891,12 @@ port map( --); -------------------------------------------------------------------- - cart_addr <= cpu_addr(13 downto 0); +cart_addr <= cpu_addr(14 downto 0); working_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 10) port map( - clk => cpu_clock, + clk => clock_24, we => ram_we, addr => cpu_addr(9 downto 0), d => cpu_do, @@ -871,7 +940,7 @@ port map( O_PB_OE_L => open, RESET_L => reset_n, - CLK => clock_12, + CLK => clock_24, I_P2_H => cpu_clock, -- high for phase 2 clock ____----__ ENA_4 => via_en_4 -- 4x system clock (4HZ) _-_-_-_-_- ); @@ -879,36 +948,31 @@ port map( -- AY-3-8910 -ay_3_8910_2 : entity work.YM2149 -port map( - -- data bus - I_DA => via_pa_o, -- in std_logic_vector(7 downto 0); - O_DA => ay_do, -- out std_logic_vector(7 downto 0); - O_DA_OE_L => open, -- out std_logic; - -- control - I_A9_L => '0', -- in std_logic; - I_A8 => '1', -- in std_logic; - I_BDIR => via_pb_o(4), -- in std_logic; - I_BC2 => '1', -- in std_logic; - I_BC1 => via_pb_o(3), -- in std_logic; - I_SEL_L => '0', -- in std_logic; - O_AUDIO => ay_audio_muxed, -- out std_logic_vector(7 downto 0); - O_CHAN => ay_audio_chan, -- out std_logic_vector(1 downto 0); - - -- port a - I_IOA => players_switches, -- in std_logic_vector(7 downto 0); - O_IOA => open, -- out std_logic_vector(7 downto 0); - O_IOA_OE_L => ay_ioa_oe, -- out std_logic; - -- port b - I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOB => open, -- out std_logic_vector(7 downto 0); - O_IOB_OE_L => open, -- out std_logic; + ym2149_inst: YM2149 + port map ( + CLK => clock_24, + CE => cpu_clock_en, + RESET => not reset_n, + BDIR => via_pb_o(4), + BC => via_pb_o(3), + DI => via_pa_o, + DO => ay_do, + CHANNEL_A => ay_chan_a, + CHANNEL_B => ay_chan_b, + CHANNEL_C => ay_chan_c, - ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation - RESET_L => reset_n, -- in std_logic; - CLK => cpu_clock -- in std_logic -- note 6 Mhz -); + SEL => '0', + MODE => '0', + + ACTIVE => open, + + IOA_in => players_switches, + IOA_out => ay_ioa_out, + + IOB_in => (others => '0'), + IOB_out => open + ); -- select hardware speakjet or VHDL sp0256 diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv index f5f781b6..374a3556 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv @@ -1,5 +1,6 @@ module vectrex_mist ( + input CLOCK_27, output LED, output [5:0] VGA_R, output [5:0] VGA_G, @@ -14,7 +15,18 @@ module vectrex_mist input SPI_SS2, input SPI_SS3, input CONF_DATA0, - input CLOCK_27 + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE ); `include "rtl\build_id.v" @@ -22,9 +34,9 @@ module vectrex_mist localparam CONF_STR = { "Vectrex;BINVECROM;", "O2,Show Frame,Yes,No;", - "O3,Skip Logo,Yes,No;", - "O4,Second Joystick, Player 2, Player 1;", -// "O5,Speech Mode,No,Yes;", + "O3,Skip Logo,Yes,No;", + "O4,Joystick swap,Off,On;", + "O5,Second port,Joystick,Speech;", // "O23,Phosphor persistance,1,2,3,4;", // "O8,Overburn,No,Yes;", "T6,Reset;", @@ -37,6 +49,8 @@ wire [1:0] switches; wire [15:0] kbjoy; wire [7:0] joystick_0; wire [7:0] joystick_1; +wire [15:0] joy_ana_0; +wire [15:0] joy_ana_1; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; wire [7:0] pot_x_1, pot_x_2; @@ -47,7 +61,7 @@ wire [3:0] r, g, b; wire hb, vb; wire blankn = ~(hb | vb); wire cart_rd; -wire [13:0] cart_addr; +wire [14:0] cart_addr; wire [7:0] cart_do; wire ioctl_downl; wire [7:0] ioctl_index; @@ -58,45 +72,34 @@ wire [7:0] ioctl_dout; assign LED = !ioctl_downl; -wire clk_24, clk_12, clk_6; +wire clk_24, clk_12; wire pll_locked; -always @(clk_12)begin - pot_x_1 = 8'h00; - pot_y_1 = 8'h00; - pot_x_2 = 8'h00; - pot_y_2 = 8'h00; - // - if (joystick_0[1] | kbjoy[1]) pot_x_2 = 8'h80; - if (joystick_0[0] | kbjoy[0]) pot_x_2 = 8'h7F; - - if (joystick_0[3] | kbjoy[3]) pot_y_2 = 8'h7F; - if (joystick_0[2] | kbjoy[2]) pot_y_2 = 8'h80; - //Player2 - if (joystick_1[1] | kbjoy[9]) pot_x_1 = 8'h80; - if (joystick_1[0] | kbjoy[8]) pot_x_1 = 8'h7F; - - if (joystick_1[3] | kbjoy[11]) pot_y_1 = 8'h7F; - if (joystick_1[2] | kbjoy[10]) pot_y_1 = 8'h80; -end - pll pll ( .inclk0 ( CLOCK_27 ), .areset ( 0 ), - .c0 ( clk_24 ), - .c1 ( clk_12 ), - .c2 ( clk_6 ), + .c0 ( clk_24 ), + .c1 ( clk_12 ), .locked ( pll_locked ) ); -card card ( - .clock ( clk_24 ), - .address ( ioctl_downl ? ioctl_addr : cart_addr), - .data ( ioctl_dout ), - .rden ( !ioctl_downl && cart_rd), - .wren ( ioctl_downl && ioctl_wr), - .q ( cart_do ) - ); +assign SDRAM_CLK = clk_24; +wire [15:0] sdram_do; +assign cart_do = sdram_do[7:0]; + +sdram cart +( + .*, + .init(~pll_locked), + .clk(clk_24), + .wtbt(2'b00), + .dout(sdram_do), + .din ({ioctl_dout, ioctl_dout}), + .addr(ioctl_downl ? ioctl_addr : cart_addr), + .we(ioctl_downl & ioctl_wr), + .rd(!ioctl_downl & cart_rd), + .ready() +); wire reset = (status[0] | status[6] | buttons[1] | ioctl_downl | second_reset); @@ -114,6 +117,11 @@ always @(posedge clk_24) begin end end +assign pot_x_1 = status[4] ? joy_ana_1[15:8] : joy_ana_0[15:8]; +assign pot_x_2 = status[4] ? joy_ana_0[15:8] : joy_ana_1[15:8]; +assign pot_y_1 = status[4] ? ~joy_ana_1[ 7:0] : ~joy_ana_0[ 7:0]; +assign pot_y_2 = status[4] ? ~joy_ana_0[ 7:0] : ~joy_ana_1[ 7:0]; + vectrex vectrex ( .clock_24 ( clk_24 ), .clock_12 ( clk_12 ), @@ -124,7 +132,7 @@ vectrex vectrex ( .video_csync ( cs ), .video_hblank ( hb ), .video_vblank ( vb ), -// .speech_mode ( status[5] ), + .speech_mode ( status[5] ), .video_hs ( hs ), .video_vs ( vs ), .frame ( frame_line ), @@ -132,97 +140,105 @@ vectrex vectrex ( .cart_addr ( cart_addr ), .cart_do ( cart_do ), .cart_rd ( cart_rd ), - .btn11 ( joystick_0[4] | kbjoy[4] | status[4] ? joystick_1[4] : 1'b0), - .btn12 ( joystick_0[5] | kbjoy[5] | status[4] ? joystick_1[5] : 1'b0), - .btn13 ( joystick_0[6] | kbjoy[6] | status[4] ? joystick_1[6] : 1'b0), - .btn14 ( joystick_0[7] | kbjoy[7] | status[4] ? joystick_1[7] : 1'b0), - .pot_x_1 ( pot_x_1 ), - .pot_y_1 ( pot_y_1 ), - .btn21 ( kbjoy[12] | ~status[4] ? joystick_1[4] : 1'b0), - .btn22 ( kbjoy[13] | ~status[4] ? joystick_1[5] : 1'b0), - .btn23 ( kbjoy[14] | ~status[4] ? joystick_1[6] : 1'b0), - .btn24 ( kbjoy[15] | ~status[4] ? joystick_1[7] : 1'b0), - .pot_x_2 ( pot_x_2 ), - .pot_y_2 ( pot_y_2 ), + .btn11 ( status[4] ? joystick_1[4] : joystick_0[4]), + .btn12 ( status[4] ? joystick_1[5] : joystick_0[5]), + .btn13 ( status[4] ? joystick_1[6] : joystick_0[6]), + .btn14 ( status[4] ? joystick_1[7] : joystick_0[7]), + .pot_x_1 ( pot_x_1 ), + .pot_y_1 ( pot_y_1 ), + .btn21 ( status[4] ? joystick_0[4] : joystick_1[4]), + .btn22 ( status[4] ? joystick_0[5] : joystick_1[5]), + .btn23 ( status[4] ? joystick_0[6] : joystick_1[6]), + .btn24 ( status[4] ? joystick_0[7] : joystick_1[7]), + .pot_x_2 ( pot_x_2 ), + .pot_y_2 ( pot_y_2 ), .leds ( ), .dbg_cpu_addr ( ) ); - - // .pot_x_1(joya_0[7:0] ? joya_0[7:0] : {joystick_0[1], {7{joystick_0[0]}}}), - //.pot_y_1(joya_0[15:8] ? ~joya_0[15:8] : {joystick_0[2], {7{joystick_0[3]}}}), - - // .pot_x_2(joya_1[7:0] ? joya_1[7:0] : {joystick_1[1], {7{joystick_1[0]}}}), - //.pot_y_2(joya_1[15:8] ? ~joya_1[15:8] : {joystick_1[2], {7{joystick_1[3]}}}) - dac dac ( .clk_i ( clk_24 ), - .res_n_i ( 1 ), + .res_n_i ( 1 ), .dac_i ( audio ), .dac_o ( AUDIO_L ) ); assign AUDIO_R = AUDIO_L; +////////////////// VIDEO ////////////////// + wire frame_line; wire [3:0] rr,gg,bb; - assign r = status[2] & frame_line ? 4'h40 : rr; - assign g = status[2] & frame_line ? 4'h00 : gg; - assign b = status[2] & frame_line ? 4'h00 : bb; +assign r = status[2] & frame_line ? 4'h4 : blankn ? rr : 4'd0; +assign g = status[2] & frame_line ? 4'h0 : blankn ? gg : 4'd0; +assign b = status[2] & frame_line ? 4'h0 : blankn ? bb : 4'd0; -video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer ( - .clk_sys ( clk_24 ), - .ce_pix ( clk_6 ), - .ce_pix_actual ( clk_6 ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS3 ( SPI_SS3 ), - .SPI_DI ( SPI_DI ), - .R ( blankn ? r : "0000"), - .G ( blankn ? g : "0000"), - .B ( blankn ? b : "0000"), - .HSync ( hs ), - .VSync ( vs ), - .VGA_R ( VGA_R ), - .VGA_G ( VGA_G ), - .VGA_B ( VGA_B ), - .VGA_VS ( VGA_VS ), - .VGA_HS ( VGA_HS ), - .scandoubler_disable(1 ), - .ypbpr_full ( 1 ), - .line_start ( 0 ), - .mono ( 0 ) - ); +wire vsync_out; +wire hsync_out; +wire csync_out = ~(hs ^ vs); + +assign VGA_HS = ypbpr ? csync_out : hs; +assign VGA_VS = ypbpr ? 1'b1 : vs; + +wire [5:0] osd_r_o, osd_g_o, osd_b_o; + +osd osd +( + .clk_sys(clk_24), + .SPI_DI(SPI_DI), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .R_in({r, 2'b00}), + .G_in({g, 2'b00}), + .B_in({b, 2'b00}), + .HSync(hs), + .VSync(vs), + .R_out(osd_r_o), + .G_out(osd_g_o), + .B_out(osd_b_o) +); + +wire [5:0] y, pb, pr; + +rgb2ypbpr rgb2ypbpr +( + .red ( osd_r_o ), + .green ( osd_g_o ), + .blue ( osd_b_o ), + .y ( y ), + .pb ( pb ), + .pr ( pr ) +); + +assign VGA_R = ypbpr?pr:osd_r_o; +assign VGA_G = ypbpr? y:osd_g_o; +assign VGA_B = ypbpr?pb:osd_b_o; + +//////////////////////////////////////////// mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( - .clk_sys ( clk_24 ), + .clk_sys ( clk_24 ), .conf_str ( CONF_STR ), .SPI_SCK ( SPI_SCK ), .CONF_DATA0 ( CONF_DATA0 ), - .SPI_SS2 ( SPI_SS2 ), + .SPI_SS2 ( SPI_SS2 ), .SPI_DO ( SPI_DO ), .SPI_DI ( SPI_DI ), .buttons ( buttons ), - .switches ( switches ), + .switches ( switches ), .ypbpr ( ypbpr ), .ps2_kbd_clk ( ps2_kbd_clk ), - .ps2_kbd_data ( ps2_kbd_data ), - .joystick_0 ( joystick_0 ), + .ps2_kbd_data ( ps2_kbd_data ), + .joystick_0 ( joystick_0 ), .joystick_1 ( joystick_1 ), + .joystick_analog_0( joy_ana_0 ), + .joystick_analog_1( joy_ana_1 ), .status ( status ), .ioctl_download( ioctl_downl ), - .ioctl_index ( ioctl_index ), - .ioctl_wr ( ioctl_wr ), - .ioctl_addr ( ioctl_addr ), - .ioctl_dout ( ioctl_dout ) + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) ); -keyboard keyboard ( - .clk ( clk_24 ), - .reset ( 0 ), - .ps2_kbd_clk ( ps2_kbd_clk ), - .ps2_kbd_data ( ps2_kbd_data ), - .joystick ( kbjoy ) - ); - - endmodule \ No newline at end of file diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/video_mixer.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/video_mixer.sv deleted file mode 100644 index 04cfd4ba..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc index 0f315b1e..4f80488a 100644 --- a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc +++ b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.out.sdc @@ -51,16 +51,12 @@ set_time_format -unit ns -decimal_places 3 # Create Clock #************************************************************** -create_clock -name {CLOCK_27} -period 37.037 -waveform { 0.000 18.518 } [get_ports {CLOCK_27}] - +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] #************************************************************** # Create Generated Clock #************************************************************** -create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 9 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[0]}] -create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -divide_by 9 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] - #************************************************************** # Set Clock Latency @@ -72,79 +68,40 @@ create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[1]} - # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020 - - #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SS3}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[0]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[1]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[2]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[3]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[4]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[5]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[0]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[1]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[2]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[3]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[4]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[5]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_HS}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[0]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[1]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[2]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[3]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[4]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[5]}] -set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_VS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}] #************************************************************** # Set Clock Groups #************************************************************** - +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] #************************************************************** # Set False Path @@ -156,7 +113,8 @@ set_output_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [ # Set Multicycle Path #************************************************************** - +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 #************************************************************** # Set Maximum Delay diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf index 00ee2dac..86e6c1e0 100644 --- a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf +++ b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf @@ -78,6 +78,180 @@ set_location_assignment PIN_127 -to SPI_SS2 set_location_assignment PIN_91 -to SPI_SS3 set_location_assignment PIN_13 -to CONF_DATA0 set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] + +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS # Analysis & Synthesis Assignments # ================================ @@ -126,8 +300,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # start EDA_TOOL_SETTINGS(eda_simulation) # --------------------------------------- - # EDA Netlist Writer Assignments - # ============================== +# EDA Netlist Writer Assignments +# ============================== set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation @@ -143,17 +317,17 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulati # -------------------------- # start ENTITY(vectrex_mist) - # start DESIGN_PARTITION(Top) - # --------------------------- +# start DESIGN_PARTITION(Top) +# --------------------------- - # Incremental Compilation Assignments - # =================================== +# Incremental Compilation Assignments +# =================================== set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - # end DESIGN_PARTITION(Top) - # ------------------------- +# end DESIGN_PARTITION(Top) +# ------------------------- # end ENTITY(vectrex_mist) # ------------------------ @@ -161,60 +335,33 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name ENABLE_SIGNALTAP OFF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON +set_global_assignment -name USE_SIGNALTAP_FILE output_files/sdram.stp set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/vectrex.vhd set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd set_global_assignment -name VHDL_FILE rtl/m6522a.vhd -set_global_assignment -name QIP_FILE rtl/card.qip set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/keyboard.v set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VERILOG_FILE rtl/mc6809is.v set_global_assignment -name VERILOG_FILE rtl/mc6809.v set_global_assignment -name VHDL_FILE rtl/sp0256.vhd set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd -set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/rgb2ypbpr.sv +set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file