mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-20 09:44:38 +00:00
add dprom
This commit is contained in:
Gehstock
parent
bb6e62965f
commit
a3ef31be55
239
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/fg_sp_dulport_rom.v
Normal file
239
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/fg_sp_dulport_rom.v
Normal file
@ -0,0 +1,239 @@
|
||||
// megafunction wizard: %ROM: 2-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: fg_sp_dulport_rom.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module fg_sp_dulport_rom (
|
||||
address_a,
|
||||
address_b,
|
||||
clock_a,
|
||||
clock_b,
|
||||
q_a,
|
||||
q_b);
|
||||
|
||||
input [12:0] address_a;
|
||||
input [12:0] address_b;
|
||||
input clock_a;
|
||||
input clock_b;
|
||||
output [31:0] q_a;
|
||||
output [31:0] q_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock_a;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [31:0] sub_wire0;
|
||||
wire [31:0] sub_wire1;
|
||||
wire sub_wire2 = 1'h0;
|
||||
wire [31:0] sub_wire3 = 32'h0;
|
||||
wire [31:0] q_b = sub_wire0[31:0];
|
||||
wire [31:0] q_a = sub_wire1[31:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.clock0 (clock_a),
|
||||
.wren_a (sub_wire2),
|
||||
.address_b (address_b),
|
||||
.clock1 (clock_b),
|
||||
.data_b (sub_wire3),
|
||||
.wren_b (sub_wire2),
|
||||
.address_a (address_a),
|
||||
.data_a (sub_wire3),
|
||||
.q_b (sub_wire0),
|
||||
.q_a (sub_wire1)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr0 (),
|
||||
.aclr1 (),
|
||||
.addressstall_a (),
|
||||
.addressstall_b (),
|
||||
.byteena_a (),
|
||||
.byteena_b (),
|
||||
.clocken0 (),
|
||||
.clocken1 (),
|
||||
.clocken2 (),
|
||||
.clocken3 (),
|
||||
.eccstatus (),
|
||||
.rden_a (),
|
||||
.rden_b ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
altsyncram_component.address_reg_b = "CLOCK1",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.indata_reg_b = "CLOCK1",
|
||||
`ifdef NO_PLI
|
||||
altsyncram_component.init_file = "./rom/gfx1.rif"
|
||||
`else
|
||||
altsyncram_component.init_file = "./rom/gfx1.hex"
|
||||
`endif
|
||||
,
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 8192,
|
||||
altsyncram_component.numwords_b = 8192,
|
||||
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.outdata_reg_b = "CLOCK1",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.ram_block_type = "M9K",
|
||||
altsyncram_component.widthad_a = 13,
|
||||
altsyncram_component.widthad_b = 13,
|
||||
altsyncram_component.width_a = 32,
|
||||
altsyncram_component.width_b = 32,
|
||||
altsyncram_component.width_byteena_a = 1,
|
||||
altsyncram_component.width_byteena_b = 1,
|
||||
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
|
||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "./rom/gfx1.hex"
|
||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gfx1.hex"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL "address_a[12..0]"
|
||||
// Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL "address_b[12..0]"
|
||||
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
|
||||
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
|
||||
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
|
||||
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 32 0 GND 0 0 32 0
|
||||
// Retrieval info: CONNECT: @data_b 0 0 32 0 GND 0 0 32 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
|
||||
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
174
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/ninjakun_video.v
Normal file
174
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/ninjakun_video.v
Normal file
@ -0,0 +1,174 @@
|
||||
// Copyright (c) 2011,19 MiSTer-X
|
||||
|
||||
module ninjakun_video
|
||||
(
|
||||
input RESET,
|
||||
input VCLKx4,
|
||||
input VCLK,
|
||||
input [8:0] PH,
|
||||
input [8:0] PV,
|
||||
|
||||
output [8:0] PALAD, // Pixel Output (Palet Index)
|
||||
|
||||
output [9:0] FGVAD, // FG
|
||||
input [15:0] FGVDT,
|
||||
|
||||
output [9:0] BGVAD, // BG
|
||||
input [15:0] BGVDT,
|
||||
input [7:0] BGSCX,
|
||||
input [7:0] BGSCY,
|
||||
|
||||
output [10:0] SPAAD, // Sprite
|
||||
input [7:0] SPADT,
|
||||
|
||||
output VBLK,
|
||||
input DBGPD, // Palet Display (for Debug)
|
||||
// output [12:0] sp_rom_addr,
|
||||
// input [31:0] sp_rom_data,
|
||||
// output [12:0] fg_rom_addr,
|
||||
// input [31:0] fg_rom_data,
|
||||
output [12:0] bg_rom_addr,
|
||||
input [31:0] bg_rom_data
|
||||
);
|
||||
|
||||
assign VBLK = (PV>=193);
|
||||
|
||||
// ROMs
|
||||
wire SPCFT = 1'b1;
|
||||
wire [12:0] SPCAD;
|
||||
wire [31:0] SPCDT;
|
||||
|
||||
wire [12:0] FGCAD;
|
||||
wire [31:0] FGCDT;
|
||||
|
||||
wire [12:0] BGCAD;
|
||||
wire [31:0] BGCDT;
|
||||
|
||||
//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN);
|
||||
//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
|
||||
//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
|
||||
//assign sp_rom_addr = SPCAD;
|
||||
//assign SPCDT = sp_rom_data;
|
||||
//assign fg_rom_addr = FGCAD;
|
||||
//assign FGCDT = fg_rom_data;
|
||||
/*
|
||||
static GFXDECODE_START( gfx_ninjakun )
|
||||
GFXDECODE_ENTRY( "gfx1", 0, layout16x16, 0x200, 16 ) // sprites
|
||||
GFXDECODE_ENTRY( "gfx1", 0, layout8x8, 0x000, 16 ) // fg tiles
|
||||
GFXDECODE_ENTRY( "gfx2", 0, layout8x8, 0x100, 16 ) // bg tiles
|
||||
GFXDECODE_END*/
|
||||
|
||||
assign bg_rom_addr = BGCAD;
|
||||
assign BGCDT = bg_rom_data;
|
||||
|
||||
fg_sp_dulport_rom gfx1_rom(
|
||||
.address_a(SPCAD),
|
||||
.address_b(FGCAD),
|
||||
.clock_a(VCLKx4),
|
||||
.clock_b(VCLK),
|
||||
.q_a(SPCDT),
|
||||
.q_b(FGCDT)
|
||||
);
|
||||
|
||||
/*
|
||||
fg1_rom fg1_rom (
|
||||
.clk(~VCLKx4),//if sprite ? ~VCLKx4 : ~VCLK
|
||||
.addr(SPCAD),//if sprite ? SPCAD : FGCAD
|
||||
.data(SPCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
|
||||
);
|
||||
|
||||
fg2_rom fg2_rom (
|
||||
.clk(~VCLKx4),
|
||||
.addr(SPCAD),
|
||||
.data(SPCDT[15:8])
|
||||
);
|
||||
|
||||
fg3_rom fg3_rom (
|
||||
.clk(~VCLKx4),
|
||||
.addr(SPCAD),
|
||||
.data(SPCDT[23:16])
|
||||
);
|
||||
|
||||
fg4_rom fg4_rom (
|
||||
.clk(~VCLKx4),
|
||||
.addr(SPCAD),
|
||||
.data(SPCDT[31:24])
|
||||
);*//*
|
||||
|
||||
fg1_rom fg1_rom (
|
||||
.clk(~VCLK),//if sprite ? ~VCLKx4 : ~VCLK
|
||||
.addr(FGCAD),//if sprite ? SPCAD : FGCAD
|
||||
.data(FGCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
|
||||
);
|
||||
|
||||
fg2_rom fg2_rom (
|
||||
.clk(~VCLK),
|
||||
.addr(FGCAD),
|
||||
.data(FGCDT[15:8])
|
||||
);
|
||||
|
||||
fg3_rom fg3_rom (
|
||||
.clk(~VCLK),
|
||||
.addr(FGCAD),
|
||||
.data(FGCDT[23:16])
|
||||
);
|
||||
|
||||
fg4_rom fg4_rom (
|
||||
.clk(~VCLK),
|
||||
.addr(FGCAD),
|
||||
.data(FGCDT[31:24])
|
||||
);*/
|
||||
|
||||
// Fore-Ground Scanline Generator
|
||||
wire FGPRI;
|
||||
wire [8:0] FGOUT;
|
||||
ninjakun_fg fg(
|
||||
VCLK,
|
||||
PH, PV,
|
||||
FGVAD, FGVDT,
|
||||
FGCAD, FGCDT,
|
||||
{FGPRI, FGOUT}
|
||||
);
|
||||
wire FGOPQ =(FGOUT[3:0]!=0);
|
||||
wire FGPPQ = FGOPQ & (~FGPRI);
|
||||
|
||||
// Back-Ground Scanline Generator
|
||||
wire [8:0] BGOUT;
|
||||
ninjakun_bg bg(
|
||||
VCLK,
|
||||
PH, PV,
|
||||
BGSCX, BGSCY,
|
||||
BGVAD, BGVDT,
|
||||
BGCAD, BGCDT,
|
||||
BGOUT
|
||||
);
|
||||
|
||||
// Sprite Scanline Generator
|
||||
wire [8:0] SPOUT;
|
||||
ninjakun_sp sp(
|
||||
VCLKx4, VCLK,
|
||||
PH, PV,
|
||||
SPAAD, SPADT,
|
||||
SPCAD, SPCDT, SPCFT,
|
||||
SPOUT
|
||||
);
|
||||
wire SPOPQ = (SPOUT[3:0]!=0);
|
||||
|
||||
// Palet Display (for Debug)
|
||||
wire [8:0] PDOUT = (PV[7]|PV[8]) ? 0 : {PV[6:2],PH[7:4]};
|
||||
|
||||
// Color Mixer
|
||||
dataselector_4D_9B dataselector_4D_9B(
|
||||
.OUT(PALAD),
|
||||
.EN1(DBGPD),
|
||||
.IN1(PDOUT),
|
||||
.EN2(FGPPQ),
|
||||
.IN2(FGOUT),
|
||||
.EN3(SPOPQ),
|
||||
.IN3(SPOUT),
|
||||
.EN4(FGOPQ),
|
||||
.IN4(FGOUT),
|
||||
.IND(BGOUT)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1026
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/rom/gfx1.hex
Normal file
1026
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/rom/gfx1.hex
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user