From a901cf2bf490e00b8ec116b03748f91a576cb8da Mon Sep 17 00:00:00 2001 From: Marcel Date: Fri, 14 Apr 2023 15:25:46 +0200 Subject: [PATCH] Space Chaser WIP --- .../Space Chaser_MiST/README.txt | 28 + .../Space Chaser_MiST/SpaceChaser.qpf | 30 + .../Space Chaser_MiST/SpaceChaser.qsf | 176 ++++++ .../Space Chaser_MiST/SpaceChaser.sdc | 126 +++++ .../Space Chaser_MiST/clean.bat | 15 + .../Space Chaser_MiST/rtl/SpaceChaser.sv | 197 +++++++ .../Space Chaser_MiST/rtl/build_id.tcl | 35 ++ .../Space Chaser_MiST/rtl/invaders.vhd | 262 +++++++++ .../Space Chaser_MiST/rtl/invaders_audio.vhd | 496 ++++++++++++++++ .../Space Chaser_MiST/rtl/invaders_memory.sv | 57 ++ .../Space Chaser_MiST/rtl/invaders_video.vhd | 78 +++ .../Space Chaser_MiST/rtl/mw8080.vhd | 389 +++++++++++++ .../Space Chaser_MiST/rtl/pll.qip | 4 + .../Space Chaser_MiST/rtl/pll.vhd | 382 +++++++++++++ .../Space Chaser_MiST/rtl/roms/rom1.vhd | 534 ++++++++++++++++++ .../Space Chaser_MiST/rtl/roms/rom2.vhd | 150 +++++ .../Space Chaser_MiST/rtl/roms/snd.vhd | 86 +++ .../Space Chaser_MiST/rtl/spram.vhd | 55 ++ .../Space Chaser_MiST/rtl/sprom.vhd | 82 +++ 19 files changed, 3182 insertions(+) create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/README.txt create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qpf create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qsf create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.sdc create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/clean.bat create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/SpaceChaser.sv create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_audio.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_memory.sv create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_video.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/mw8080.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom1.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom2.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/snd.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/spram.vhd create mode 100644 Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/sprom.vhd diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/README.txt b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/README.txt new file mode 100644 index 00000000..260e9b9f --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/README.txt @@ -0,0 +1,28 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: SpaceChaser port to MiST by Gehstock +-- 14 April 2023 +-- +--------------------------------------------------------------------------------- +-- +-- Midway 8080 Hardware +-- Audio based on work by Paul Walsh. +-- Audio and scan converter by MikeJ. +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 : Start One Player Game +-- F2 : Start Two Player Game +-- Control Key : Accelerate + +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +ToDo: Audio + Color + diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qpf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qpf new file mode 100644 index 00000000..f59edaa3 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 21:27:39 November 20, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "21:27:39 April 14, 2023" + +# Revisions + +PROJECT_REVISION = "SpaceChaser" diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qsf b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qsf new file mode 100644 index 00000000..d2e2010d --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.qsf @@ -0,0 +1,176 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 14:19:15 April 14, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SpaceChaser_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceChaser.sv +set_global_assignment -name VHDL_FILE rtl/invaders.vhd +set_global_assignment -name VHDL_FILE rtl/mw8080.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv +set_global_assignment -name VHDL_FILE rtl/sprom.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/roms/rom1.vhd +set_global_assignment -name VHDL_FILE rtl/roms/rom2.vhd +set_global_assignment -name QIP_FILE ../../../../Mist_FPGA/common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../../Mist_FPGA/common/CPU/T80/T80.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY SpaceChaser +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# ---------------------------- +# start ENTITY(Invaders2_mist) + +# end ENTITY(Invaders2_mist) +# -------------------------- + +# ------------------------- +# start ENTITY(SpaceChaser) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(SpaceChaser) +# ----------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.sdc b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.sdc new file mode 100644 index 00000000..11d2c7a9 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/SpaceChaser.sdc @@ -0,0 +1,126 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/clean.bat b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/SpaceChaser.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/SpaceChaser.sv new file mode 100644 index 00000000..df0b34a1 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/SpaceChaser.sv @@ -0,0 +1,197 @@ +module SpaceChaser( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "SpaceChaser;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O6,Joystick Swap,Off,On;", + "OGJ,CRT H-Sync Adjust,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", + "OKN,CRT V-Sync Adjust,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;", + "T0,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +wire [1:0] scanlines = status[4:3]; +wire rotate = status[2]; +wire joyswap = status[6]; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_sys, clk_vid; +wire pll_locked; +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .c1(clk_vid) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0,joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; +wire [7:0] audio; +wire hsync,vsync; +wire hs, vs, vb, hb; +wire blankn = ~(hb | vb); +wire r,g,b; + +wire [15:0]RAB; +wire [15:0]AD; +wire [7:0]RDB; +wire [7:0]RWD; +wire [7:0]IB; +wire [5:0]SoundCtrl3; +wire [5:0]SoundCtrl5; +wire Rst_n_s; +wire RWE_n; +wire Video; +wire HSync; +wire VSync; + +invaderst invaderst( + .Rst_n(~(status[0] | buttons[1])), + .Clk(clk_sys), + .ENA(), + .GDB0({1'b0,2'b00,m_fire2A, m_right2, m_down2, m_left2, m_up2}), + .GDB1({m_coin1,m_one_player, m_two_players, m_fireA, m_right, m_down, m_left, m_up}), + .GDB2(), + .RDB(RDB), + .IB(IB), + .RWD(RWD), + .RAB(RAB), + .AD(AD), + .SoundCtrl3(SoundCtrl3), + .SoundCtrl5(SoundCtrl5), + .Rst_n_s(Rst_n_s), + .RWE_n(RWE_n), + .RED(r), + .GREEN(g), + .BLUE(b), + .HSync(hs), + .VSync(vs), + .VBlank(vb), + .HBlank(hb), + .HShift(status[19:16]), + .VShift(status[23:20]) +// .HShift(4'b1100), +// .VShift() + ); + +invaders_memory invaders_memory ( + .Clock(clk_sys), + .RW_n(RWE_n), + .Addr(AD), + .Ram_Addr(RAB), + .Ram_out(RDB), + .Ram_in(RWD), + .Rom_out(IB) + ); + +invaders_audio invaders_audio ( + .Clk(clk_sys), + .S1(SoundCtrl3), + .S2(SoundCtrl5), + .Aud(audio) + ); + +mist_video #(.COLOR_DEPTH(1)) mist_video( + .clk_sys(clk_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 0), + .G(blankn ? g : 0), + .B(blankn ? b : 0), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .rotate({1'b0,rotate}), + .scandoubler_disable(scandoublerD), + .scanlines(scanlines), + .ce_divider(1'b0), + .ypbpr(ypbpr), + .no_csync(no_csync) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + + +dac dac ( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; + +arcade_inputs inputs ( + .clk ( clk_sys ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( 2'b01 ), + .joyswap ( joyswap ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders.vhd new file mode 100644 index 00000000..a4eb3ba6 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders.vhd @@ -0,0 +1,262 @@ +-- Space Invaders core logic +-- 9.984MHz clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Cleaned up reset logic +-- +-- 0300 : MikeJ tidyup for audio release + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity invaderst is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + GDB0 : in std_logic_vector(7 downto 0); + GDB1 : in std_logic_vector(7 downto 0); + GDB2 : in std_logic_vector(7 downto 0); + RDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + RWD : out std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + AD : out std_logic_vector(15 downto 0); + SoundCtrl3 : out std_logic_vector(5 downto 0); + SoundCtrl5 : out std_logic_vector(5 downto 0); + Rst_n_s : out std_logic; + RWE_n : out std_logic; + RED : out std_logic; + GREEN : out std_logic; + BLUE : out std_logic; + HSync : out std_logic; + VSync : out std_logic; + VBlank : out std_logic; + HBlank : out std_logic; + VShift : in std_logic_vector(3 downto 0); + HShift : in std_logic_vector(3 downto 0) + ); +end invaderst; + +architecture rtl of invaderst is + + component mw8080 + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + RED : out std_logic; + GREEN : out std_logic; + BLUE : out std_logic; + HSync : out std_logic; + VSync : out std_logic; + VBlank : out std_logic; + HBlank : out std_logic; + VShift : in std_logic_vector(3 downto 0); + HShift : in std_logic_vector(3 downto 0) + ); + end component; + +-- signal GDB0 : std_logic_vector(7 downto 0); +-- signal GDB1 : std_logic_vector(7 downto 0); +-- signal GDB2 : std_logic_vector(7 downto 0); + signal S : std_logic_vector(7 downto 0); + signal GDB : std_logic_vector(7 downto 0); + signal DB : std_logic_vector(7 downto 0); + signal Sounds : std_logic_vector(7 downto 0); + signal AD_i : std_logic_vector(15 downto 0); + signal PortWr : std_logic_vector(6 downto 2); + signal EA : std_logic_vector(2 downto 0); + signal D5 : std_logic_vector(15 downto 0); + signal WD_Cnt : unsigned(7 downto 0); + signal Sample : std_logic; + signal Rst_n_s_i : std_logic; +begin + + Rst_n_s <= Rst_n_s_i; + RWD <= DB; + AD <= AD_i; + + process (Rst_n, Clk) + variable Rst_n_r : std_logic; + begin + if Rst_n = '0' then + Rst_n_r := '0'; + Rst_n_s_i <= '0'; + elsif Clk'event and Clk = '1' then + Rst_n_s_i <= Rst_n_r; + if WD_Cnt = 255 then + Rst_n_s_i <= '0'; + end if; + Rst_n_r := '1'; + end if; + end process; + + process (Rst_n_s_i, Clk) + variable Old_S0 : std_logic; + begin + if Rst_n_s_i = '0' then + WD_Cnt <= (others => '0'); + Old_S0 := '1'; + elsif Clk'event and Clk = '1' then + if Sounds(0) = '1' and Old_S0 = '0' then + WD_Cnt <= WD_Cnt + 1; + end if; + if PortWr(6) = '1' then + WD_Cnt <= (others => '0'); + end if; + Old_S0 := Sounds(0); + end if; + end process; + + u_mw8080: mw8080 + port map( + Rst_n => Rst_n_s_i, + Clk => Clk, + ENA => ENA, + RWE_n => RWE_n, + RDB => RDB, + IB => IB, + RAB => RAB, + Sounds => Sounds, + Ready => open, + GDB => GDB, + DB => DB, + AD => AD_i, + Status => open, + Systb => open, + Int => open, + Hold_n => '1', + IntE => open, + DBin_n => open, + Vait => open, + HldA => open, + Sample => Sample, + Wr => open, + RED => RED, + GREEN => GREEN, + BLUE => BLUE, + HSync => HSync, + VSync => VSync, + VBlank => VBlank, + HBlank => HBlank, + VShift => VShift, + HShift => HShift + ); + + with AD_i(9 downto 8) select + GDB <= GDB0 when "00", + GDB1 when "01", + GDB2 when "10", + S when others; + + + + PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; + PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; + PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; + PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; + PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; + + process (Rst_n_s_i, Clk) + variable OldSample : std_logic; + begin + if Rst_n_s_i = '0' then + D5 <= (others => '0'); + EA <= (others => '0'); + SoundCtrl3 <= (others => '0'); + SoundCtrl5 <= (others => '0'); + OldSample := '0'; + elsif Clk'event and Clk = '1' then + if PortWr(2) = '1' then + EA <= DB(2 downto 0); + end if; + if PortWr(3) = '1' then + SoundCtrl3 <= DB(5 downto 0); + end if; + if PortWr(4) = '1' and OldSample = '0' then + D5(15 downto 8) <= DB; + D5(7 downto 0) <= D5(15 downto 8); + end if; + if PortWr(5) = '1' then + SoundCtrl5 <= DB(5 downto 0); + end if; + OldSample := Sample; + end if; + end process; + + with EA select + S <= D5(15 downto 8) when "000", + D5(14 downto 7) when "001", + D5(13 downto 6) when "010", + D5(12 downto 5) when "011", + D5(11 downto 4) when "100", + D5(10 downto 3) when "101", + D5( 9 downto 2) when "110", + D5( 8 downto 1) when others; + +end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_audio.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_audio.vhd new file mode 100644 index 00000000..e59d342f --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_audio.vhd @@ -0,0 +1,496 @@ + +-- Version : 0300 +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- minor tidy up by MikeJ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: PaulWalsh +-- +-- Create Date: 08:45:29 11/04/05 +-- Design Name: +-- Module Name: Invaders Audio +-- Project Name: Space Invaders +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity invaders_audio is + Port ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); +end; + --* Port 3: (S1) + --* bit 0=UFO (repeats) + --* bit 1=Shot + --* bit 2=Base hit + --* bit 3=Invader hit + --* bit 4=Bonus base + --* + --* Port 5: (S2) + --* bit 0=Fleet movement 1 + --* bit 1=Fleet movement 2 + --* bit 2=Fleet movement 3 + --* bit 3=Fleet movement 4 + --* bit 4=UFO 2 + +architecture Behavioral of invaders_audio is + + signal ClkDiv : unsigned(10 downto 0) := (others => '0'); + signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); + signal Clk7680_ena : std_logic; + signal Clk480_ena : std_logic; + signal Clk240_ena : std_logic; + signal Clk60_ena : std_logic; + + signal s1_t1 : std_logic_vector(5 downto 0); + signal s2_t1 : std_logic_vector(5 downto 0); + signal tempsum : std_logic_vector(7 downto 0); + + signal vco_cnt : std_logic_vector(3 downto 0); + + signal TriDir1 : std_logic; + signal Fnum : std_logic_vector(3 downto 0); + signal comp : std_logic; + + signal SS : std_logic; + + signal TrigSH : std_logic; + signal SHCnt : std_logic_vector(8 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal SauHit : std_logic_vector(8 downto 0); + signal SHitTri : std_logic_vector(5 downto 0); + + signal TrigIH : std_logic; + signal IHDir : std_logic; + signal IHDir1 : std_logic; + signal IHCnt : std_logic_vector(8 downto 0); + signal IH : std_logic_vector(7 downto 0); + signal InHit : std_logic_vector(8 downto 0); + signal IHitTri : std_logic_vector(5 downto 0); + + signal TrigEx : std_logic; + signal Excnt : std_logic_vector(9 downto 0); + signal ExShift : std_logic_vector(15 downto 0); + signal Ex : std_logic_vector(2 downto 0); + signal Explo : std_logic; + + signal TrigMis : std_logic; + signal MisShift : std_logic_vector(15 downto 0); + signal MisCnt : std_logic_vector(8 downto 0); + signal miscnt1 : unsigned(7 downto 0); + signal Mis : std_logic_vector(2 downto 0); + signal Missile : std_logic; + + signal EnBG : std_logic; + signal BGFnum : std_logic_vector(7 downto 0); + signal BGCnum : std_logic_vector(7 downto 0); + signal bg_cnt : unsigned(7 downto 0); + signal BG : std_logic; + +begin + + -- do a crude addition of all sound samples + p_audio_mix : process + variable IHVol : std_logic_vector(6 downto 0); + variable SHVol : std_logic_vector(6 downto 0); + begin + wait until rising_edge(Clk); + + IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); + SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); + + tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); + + Aud(7) <= tempsum (7); + Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; + Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; + Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); + Aud(3 downto 0) <= tempsum (3 downto 0); + + end process; + + p_clkdiv : process + begin + wait until rising_edge(Clk); + Clk7680_ena <= '0'; + if ClkDiv = 1277 then + Clk7680_ena <= '1'; + ClkDiv <= (others => '0'); + else + ClkDiv <= ClkDiv + 1; + end if; + end process; + + p_clkdiv2 : process + begin + wait until rising_edge(Clk); + Clk480_ena <= '0'; + Clk240_ena <= '0'; + Clk60_ena <= '0'; + + if (Clk7680_ena = '1') then + ClkDiv2 <= ClkDiv2 + 1; + + if (ClkDiv2(3 downto 0) = "0000") then + Clk480_ena <= '1'; + end if; + + if (ClkDiv2(4 downto 0) = "00000") then + Clk240_ena <= '1'; + end if; + + if (ClkDiv2(7 downto 0) = "00000000") then + Clk60_ena <= '1'; + end if; + + end if; + end process; + + p_delay : process + begin + wait until rising_edge(Clk); + s1_t1 <= S1; + s2_t1 <= S2; + end process; +--*************************Saucer Sound*************************************** + +-- Implement a VCOscilator: frequency is set using counter end point(Fnum) + p_saucer_vco : process + variable term : std_logic_vector(3 downto 0); + begin + wait until rising_edge(Clk); + term := 8 + Fnum; + if (S1(0) = '1') and (Clk7680_ena = '1') then + if vco_cnt = term then + + vco_cnt <= (others => '0'); + SS <= not SS; + else + vco_cnt <= vco_cnt + 1; + end if; + end if; + end process; + +-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator + -- this is 6Hz ?? 0123454321 + p_saucer_lfo : process + begin + wait until rising_edge(Clk); + if (Clk60_ena = '1') then + if Fnum = 4 then -- 5 -1 + Comp <= '1'; + elsif Fnum = 1 then -- 0 +1 + Comp <= '0'; + end if; + + if comp = '1' then + Fnum <= Fnum - 1 ; + else + Fnum <= Fnum + 1 ; + end if; + end if; + end process; + +--**********************SAUCER HIT Sound************************** + +-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO + p_saucer_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if SHitTri = 48 then + SHitTri <= "000000"; + else + SHitTri <= SHitTri+1; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx + p_saucer_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if TriDir1 = '1' then + if (SauHit +58 - SHitTri) < 190 + 256 then + SauHit <= SauHit +58 - SHitTri; + else + SauHit <= "110111110"; + TriDir1 <= '0'; + end if; + else + if (SauHit -58 + SHitTri) > 256 then + SauHit <= SauHit -58 + SHitTri; + else + SauHit <= "100000000"; + TriDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Saucer Hit Sound + p_saucer_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigSH = '1') then + SHCnt <= "100000000"; + SH <= "11111111"; + elsif (SHCnt(8) = '1') then + SHCnt <= SHCnt + "1"; + if SHCnt(7 downto 0) = x"60" then -- 96 + SH <= "01111111"; + elsif SHCnt(7 downto 0) = x"90" then -- 144 + SH <= "00111111"; + elsif SHCnt(7 downto 0) = x"C0" then -- 192 + SH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Saucer Hit Sound + p_saucer_hit : process + begin + wait until rising_edge(Clk); + if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge + TrigSH <= '1'; + elsif (Clk480_ena = '1') then + TrigSH <= '0'; + end if; + end process; + +--***********************Invader Hit Sound***************************** +-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO + p_invader_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if IHitTri = 48-2 then + IHDir <= '0'; + elsif IHitTri =0+2 then + IHDir <= '1'; + end if; + + if IHDir ='1' then + IHitTri <= IHitTri + 2; + else + IHitTri <= IHitTri - 2; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx + p_invader_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if IHDir1 = '1' then + if (InHit +10 + IHitTri) < 110 + 256 then + InHit <= InHit +10 + IHitTri; + else + InHit <= "101101110"; + IHDir1 <= '0'; + end if; + else + if (InHit -10 - IHitTri) > 256 then + InHit <= InHit -10 - IHitTri; + else + InHit <= "100000000"; + IHDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Invader Hit Sound + p_invader_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigIH = '1') then + IHCnt <= "100000000"; + IH <= "11111111"; + elsif (IHCnt(8) = '1') then + IHCnt <= IHCnt + "1"; + if IHCnt(7 downto 0) = x"14" then -- 20 + IH <= "01111111"; + elsif IHCnt(7 downto 0) = x"1C" then -- 28 + IH <= "11111111"; + elsif IHCnt(7 downto 0) = x"30" then -- 48 + IH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Invader Hit Sound + p_invader_hit : process + begin + wait until rising_edge(Clk); + if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge + TrigIH <= '1'; + elsif (Clk480_ena = '1') then + TrigIH <= '0'; + end if; + end process; + +--***********************Explosion***************************** +-- Implement a Pseudo Random Noise Generator + p_explosion_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (ExShift = x"0000") then + ExShift <= "0000000010101001"; + else + ExShift(0) <= Exshift(14) xor ExShift(15); + ExShift(15 downto 1) <= ExShift (14 downto 0); + end if; + end if; + end process; + Explo <= ExShift(0); + + p_explosion_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigEx = '1') then + ExCnt <= "1000000000"; + Ex <= "100"; + elsif (ExCnt(9) = '1') then + ExCnt <= ExCnt + "1"; + if ExCnt(8 downto 0) = '0' & x"64" then -- 100 + Ex <= "010"; + elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 + Ex <= "001"; + elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 + Ex <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Explosion Sound + p_explosion_trig : process + begin + wait until rising_edge(Clk); + if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge + TrigEx <= '1'; + elsif (Clk480_ena = '1') then + TrigEx <= '0'; + end if; + end process; + +--***********************Missile***************************** +-- Implement a Pseudo Random Noise Generator + p_missile_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if (MisShift = x"0000") then + MisShift <= "0000000010101001"; + else + MisShift(0) <= MisShift(14) xor MisShift(15); + MisShift(15 downto 1) <= MisShift (14 downto 0); + end if; + + miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); + if miscnt1 > 60 then + miscnt1 <= "00000000"; + Missile <= not Missile; + end if; + + end if; + end process; + +-- Implement the ADSR for The Missile Sound + p_missile_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigMis = '1') then + MisCnt <= "100000000"; + Mis <= "100"; + elsif (MisCnt(8) = '1') then + MisCnt <= MisCnt + "1"; + if MisCnt(7 downto 0) = x"4b" then -- 75 + Mis <= "010"; + elsif MisCnt(7 downto 0) = x"70" then -- 112 + Mis <= "001"; + elsif MisCnt(7 downto 0) = x"96" then -- 150 + Mis <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Missile Sound + p_missile_trig : process + begin + wait until rising_edge(Clk); + if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge + TrigMis <= '1'; + elsif (Clk480_ena = '1') then + TrigMis <= '0'; + end if; + end process; + +-- ******************************** Background invader moving tones ************************** + EnBG <= S2(0) or S2(1) or S2(2) or S2(3); + + with S2(3 downto 0) select + BGFnum <= x"66" when "0001", + x"74" when "0010", + x"7C" when "0100", + x"87" when "1000", + x"87" when others; + + with S2(3 downto 0) select + BGCnum <= x"33" when "0001", + x"3A" when "0010", + x"3E" when "0100", + x"43" when "1000", + x"43" when others; + +-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) + +-- p_background : process +-- begin +-- wait until rising_edge(Clk); +-- if (Clk7680_ena = '1') then +-- if EnBG = '0' then +-- bg_cnt <= x"00"; +-- BG <= '0'; +-- else +-- bg_cnt <= bg_cnt + 1; +-- +-- if bg_cnt = unsigned(BGfnum) then +-- bg_cnt <= x"00"; +-- BG <= '0'; +-- elsif bg_cnt=unsigned(BGCnum) then +-- BG <='1'; +-- end if; +-- end if; +-- end if; +-- end process; + +end Behavioral; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_memory.sv new file mode 100644 index 00000000..4b63398b --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_memory.sv @@ -0,0 +1,57 @@ + +module invaders_memory( +input Clock, +input RW_n, +input [15:0]Addr, +input [15:0]Ram_Addr, +output [7:0]Ram_out, +input [7:0]Ram_in, +output [7:0]Rom_out +); + +wire [7:0]rom_data_0; +wire [7:0]rom_data_1; +//wire [7:0]rom_data_2; +//wire [7:0]rom_data_3; +//wire [7:0]rom_data_4; +//wire [7:0]rom_data_5; + +rom1 rom1( + .clk(Clock), + .addr(Addr[12:0]), + .data(rom_data_0) +); + +rom2 rom2( + .clk(Clock), + .addr(Addr[10:0]), + .data(rom_data_1) +); + +always @(Addr, rom_data_0, rom_data_1) begin + Rom_out = 8'b00000000; + case (Addr[15:11]) + 5'b00000 : Rom_out = rom_data_0; + 5'b00001 : Rom_out = rom_data_0;//800 2k + 5'b00010 : Rom_out = rom_data_0;//1000 4k + 5'b00011 : Rom_out = rom_data_0;//1800 6k + 5'b00100 : Rom_out = rom_data_0;//2000 8k + + 5'b01000 : Rom_out = rom_data_1;//0100 0000 0000 0000 + 5'b01001 : Rom_out = rom_data_1; + default : Rom_out = 8'b00000000; + endcase +end + +spram #( + .addr_width_g(13), + .data_width_g(8)) +u_ram0( + .address(Ram_Addr[12:0]), + .clken(1'b1), + .clock(Clock), + .data(Ram_in), + .wren(~RW_n), + .q(Ram_out) + ); +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_video.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_video.vhd new file mode 100644 index 00000000..cbeb5dff --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/invaders_video.vhd @@ -0,0 +1,78 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity invaders_video is + port( + Video : in std_logic; + Overlay : in std_logic; + CLK : in std_logic; + Rst_n_s : in std_logic; + HSync : in std_logic; + VSync : in std_logic; + O_VIDEO_R : out std_logic; + O_VIDEO_G : out std_logic; + O_VIDEO_B : out std_logic; + O_HSYNC : out std_logic; + O_VSYNC : out std_logic + ); +end invaders_video; + +architecture rtl of invaders_video is + + signal HCnt : std_logic_vector(11 downto 0); + signal VCnt : std_logic_vector(11 downto 0); + signal HSync_t1 : std_logic; + signal VideoRGB : std_logic_vector(3 downto 0); +begin + process (Rst_n_s, Clk) + variable cnt : unsigned(3 downto 0); + begin + if Rst_n_s = '0' then + cnt := "0000"; + elsif Clk'event and Clk = '1' then + if cnt = 9 then + cnt := "0000"; + else + cnt := cnt + 1; + end if; + end if; + end process; + + +-- p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) +-- begin +-- if (Video = '0') then +-- VideoRGB <= "000"; +-- else +-- if Overlay_G1 or Overlay_G2 then +-- VideoRGB <= "010"; +-- elsif Overlay_R1 then +-- VideoRGB <= "100"; +-- else +-- VideoRGB <= "111"; +-- end if; +-- end if; +-- end process; + +rom: entity work.col + port map( + clk => CLK, + addr => VCnt(7 downto 3) & HCnt(7 downto 3), + data => VideoRGB +); + + O_VIDEO_R <= Video;-- or VideoRGB(0); + O_VIDEO_G <= Video;-- or VideoRGB(1); + O_VIDEO_B <= Video;-- or VideoRGB(2); + +-- O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); +-- O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); +-- O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); + O_HSYNC <= not HSync; + O_VSYNC <= not VSync; + + +end; \ No newline at end of file diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/mw8080.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/mw8080.vhd new file mode 100644 index 00000000..7311cf27 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/mw8080.vhd @@ -0,0 +1,389 @@ +-- Midway 8080 main board +-- 9.984MHz Clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Removed the ROM +-- +-- 0300 : MikeJ tidyup for audio release +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity mw8080 is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + RED : out std_logic; + GREEN : out std_logic; + BLUE : out std_logic; + HSync : out std_logic; + VSync : out std_logic; + VBlank : out std_logic; + HBlank : out std_logic; + VShift : in std_logic_vector(3 downto 0); + HShift : in std_logic_vector(3 downto 0) + ); +end mw8080; + +architecture struct of mw8080 is + + signal Ready_i : std_logic; + signal Hold : std_logic; + signal IntTrig : std_logic; + signal IntTrigOld : std_logic; + signal Int_i : std_logic; + signal IntE_i : std_logic; + signal DBin : std_logic; + signal Sync : std_logic; + signal Wr_n, Rd_n : std_logic; + signal ClkEnCnt : unsigned(2 downto 0); + signal Status_i : std_logic_vector(7 downto 0); + signal A : std_logic_vector(15 downto 0); + signal ISel : std_logic_vector(1 downto 0); + signal DI : std_logic_vector(7 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal RR : std_logic_vector(9 downto 0); + + signal VidEn : std_logic; + signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 + signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 + signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 + signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 + signal Shift : std_logic_vector(7 downto 0); + signal HSync_Start : std_logic_vector(8 downto 0); + signal HSync_End : std_logic_vector(8 downto 0); + signal VSync_Start : std_logic_vector(8 downto 0); + signal VSync_End : std_logic_vector(8 downto 0); + + signal Video : std_logic; + signal col_ram_do : std_logic_vector(7 downto 0); + +begin + ENA <= ClkEnCnt(2); + Status <= Status_i; + Ready <= Ready_i; + DB <= DO; + Systb <= Sync; + Int <= Int_i; + Hold <= not Hold_n; + IntE <= IntE_i; + DBin_n <= not DBin; + Sample <= not Wr_n and Status_i(4); + Wr <= not Wr_n; + AD <= A; + Sounds(0) <= CntE7(3); + Sounds(1) <= CntE7(2); + Sounds(2) <= CntE7(1); + Sounds(3) <= CntE7(0); + Sounds(4) <= CntE6(3); + Sounds(5) <= CntE6(2); + Sounds(6) <= CntE6(1); + Sounds(7) <= CntE6(0); + + IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); + + ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); + ISel(1) <= Status_i(0) nor Status_i(6); + + with ISel select + DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", + GDB when "01", + IB when "10", + RR(7 downto 0) when others; + + RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); + RAB <= A(12 downto 0) when CntD5(2) = '1' else + std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); + + u_8080: entity work.T8080se + generic map ( + Mode => 2, + T2Write => 1) + port map ( + RESET_n => Rst_n, + CLK => Clk, + CLKEN => ClkEnCnt(2), + READY => Ready_i, + HOLD => Hold, + INT => Int_i, + INTE => IntE_i, + DBIN => DBin, + SYNC => Sync, + VAIT => Vait, + HLDA => HLDA, + WR_n => Wr_n, + A => A, + DI => DI, + DO => DO); + + -- Clock enables + process (Rst_n, Clk) + begin + if Rst_n = '0' then + ClkEnCnt <= "000"; + VidEn <= '0'; + elsif Clk'event and Clk = '1' then + VidEn <= not VidEn; + if ClkEnCnt = 4 then + ClkEnCnt <= "000"; + else + ClkEnCnt <= ClkEnCnt + 1; + end if; + end if; + end process; + + -- Glue + process (Rst_n, Clk) + variable OldASEL : std_logic; + begin + if Rst_n = '0' then + Status_i <= (others => '0'); + IntTrigOld <= '0'; + Int_i <= '0'; + OldASEL := '0'; + Ready_i <= '0'; + RR <= (others => '0'); + elsif Clk'event and Clk = '1' then + -- E3 + -- Interrupt + IntTrigOld <= IntTrig; + if Status_i(0) = '1' then + Int_i <= '0'; + elsif IntTrigOld = '0' and IntTrig = '1' then + Int_i <= IntE_i; + end if; + + -- D7 + -- Status register + if Sync = '1' then + Status_i <= DO; + end if; + + -- A3, C3, E3 + -- RAM register/ready logic + if Sync = '1' and A(13) = '1' then + Ready_i <= '0'; + elsif Ready_i = '1' then + Ready_i <= '1'; + else + Ready_i <= RR(9); + end if; + if Sync = '1' and A(13) = '1' then + RR <= (others => '0'); + elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge + (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge + RR(7 downto 0) <= RDB; + RR(8) <= '1'; + RR(9) <= RR(8); + end if; + OldASEL := CntD5(2); + end if; + end process; + + -- Video counters + process (Rst_n, Clk) + begin + if Rst_n = '0' then + CntD5 <= (others => '0'); + CntE5 <= (others => '0'); + CntE6 <= (others => '0'); + CntE7 <= (others => '0'); + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + CntD5 <= CntD5 + 1; + if CntD5 = 15 then + + CntE5 <= CntE5 + 1; + if CntE5(3 downto 0) = 15 then + if CntE5(4) = '0' then + CntE5 <= "11100"; + + CntE6 <= CntE6 + 1; + if CntE6 = 15 then + + CntE7 <= CntE7 + 1; + if CntE7(3 downto 0) = 15 then + if CntE7(4) = '0' then + CntE6 <= "1010"; + CntE7 <= "11101"; + else + CntE7 <= "00010"; + end if; + end if; + end if; + end if; + else + end if; + end if; + end if; + end if; + end process; + + -- Video shift register + process (Rst_n, Clk) + begin + if Rst_n = '0' then + Shift <= (others => '0'); + Video <= '0'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then + Shift(7 downto 0) <= RDB(7 downto 0); + else + Shift(6 downto 0) <= Shift(7 downto 1); + Shift(7) <= '0'; + end if; + Video <= Shift(0); + end if; + end if; + end process; + + -- Sync + + process (HShift, VShift, Rst_n) + begin + -- Defaults are centred on my CRT + HSync_Start <= std_logic_vector(469 + resize(signed(HShift),9)); + HSync_End <= std_logic_vector(485 + resize(signed(HShift),9)); + VSync_Start <= std_logic_vector(484 + resize(signed(VShift),9)); + VSync_End <= std_logic_vector(488 + resize(signed(VShift),9)); + end process; + + process (Rst_n, Clk) + variable TimeH, TimeV : std_logic_vector(8 downto 0); + begin + if Rst_n = '0' then + + HSync <= '1'; + VSync <= '1'; + HBlank <='1'; + VBlank <='1'; + + elsif Clk'event and Clk = '1' then + + if VidEn = '1' then + + -- Convert SI counters into single fields to make comparisons easier + + TimeH := std_logic_vector(CntE5(4 downto 0)) & std_logic_vector(CntD5(3 downto 0)); + TimeV := std_logic_vector(CntE7(4 downto 0)) & std_logic_vector(CntE6(3 downto 0)); + + -- Syncs + + if (TimeH = HSync_Start) then + HSync <= '0'; + elsif (TimeH = HSync_End) then + HSync <= '1'; + end if; + + if (TimeV = VSync_Start) then + VSync <= '0'; + elsif (TimeV = VSync_End) then + VSync <= '1'; + end if; + + -- Blanks + + if (TimeH = "000000101") then + HBlank <= '0'; + elsif (TimeH = "111001001") then + HBlank <= '1'; + end if; + + if (TimeV = "011111111") then + VBlank <= '1'; + elsif (TimeV = "111111111") then + VBlank <= '0'; + end if; + + end if; + + end if; +end process; + +--COLRAM: entity work.spram +-- generic map( +-- addr_width_g => 10, +-- data_width_g => 8) +-- port map( +-- address => RAM_A10 & RAM_A9 & RAM_A8 & RAM_A7 & RAM_A6 & RAM_A3 & RAM_A2 & RAM_A1 & RAM_A0 & RAM_A4, +-- clken => '1',-- CS RAM_A11 +-- clock => Clk, +-- data => "111111111", +-- wren => Wr, +-- q => col_ram_do +-- ); + + + RED <= video;-- or col_ram_do(2); + GREEN <= video;-- or col_ram_do(1); + BLUE <= video;-- or col_ram_do(0); + + + +end; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.qip b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.vhd new file mode 100644 index 00000000..39c09b03 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/pll.vhd @@ -0,0 +1,382 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1125, + clk0_duty_cycle => 50, + clk0_multiply_by => 416, + clk0_phase_shift => "0", + clk1_divide_by => 1125, + clk1_duty_cycle => 50, + clk1_multiply_by => 832, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire4, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom1.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom1.vhd new file mode 100644 index 00000000..98970070 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"C3",X"18",X"00",X"00",X"00",X"E5",X"D5",X"C5",X"F5",X"C3",X"E8",X"0C",X"00", + X"E5",X"D5",X"C5",X"F5",X"C3",X"B3",X"13",X"00",X"31",X"00",X"24",X"11",X"B0",X"03",X"CD",X"F2", + X"04",X"21",X"43",X"23",X"36",X"01",X"11",X"40",X"22",X"21",X"7C",X"46",X"06",X"19",X"CD",X"41", + X"0B",X"CD",X"D6",X"45",X"21",X"01",X"50",X"22",X"3F",X"23",X"DB",X"02",X"E6",X"04",X"C2",X"5A", + X"47",X"CD",X"E8",X"45",X"CD",X"8C",X"04",X"C3",X"00",X"40",X"CD",X"EB",X"45",X"CD",X"2A",X"04", + X"CD",X"DB",X"18",X"FE",X"03",X"CA",X"0E",X"46",X"FE",X"04",X"DA",X"E3",X"01",X"21",X"1C",X"21", + X"36",X"FF",X"F5",X"21",X"00",X"07",X"11",X"04",X"22",X"06",X"0D",X"CD",X"41",X"0B",X"F1",X"FE", + X"06",X"DA",X"7D",X"00",X"21",X"58",X"2A",X"22",X"06",X"22",X"22",X"08",X"22",X"FE",X"05",X"DA", + X"85",X"00",X"CD",X"72",X"02",X"21",X"3C",X"20",X"36",X"06",X"CD",X"79",X"04",X"D3",X"06",X"21", + X"1E",X"25",X"DA",X"98",X"00",X"21",X"1E",X"38",X"01",X"38",X"01",X"CD",X"DB",X"04",X"06",X"60", + X"CD",X"81",X"04",X"11",X"DF",X"1C",X"21",X"1E",X"38",X"CD",X"79",X"04",X"D2",X"B5",X"00",X"11", + X"CC",X"1C",X"21",X"1E",X"25",X"06",X"07",X"CD",X"22",X"08",X"06",X"60",X"CD",X"81",X"04",X"21", + X"3C",X"20",X"35",X"C2",X"8A",X"00",X"21",X"42",X"23",X"36",X"FF",X"CD",X"AA",X"0C",X"CD",X"9F", + X"0C",X"3E",X"02",X"CD",X"7E",X"06",X"3E",X"FF",X"CD",X"A0",X"06",X"3E",X"10",X"CD",X"95",X"06", + X"21",X"3D",X"20",X"7E",X"A7",X"D3",X"06",X"C2",X"8B",X"05",X"3A",X"6F",X"20",X"A7",X"21",X"03", + X"03",X"22",X"0C",X"20",X"CA",X"13",X"01",X"21",X"0A",X"21",X"7E",X"E6",X"40",X"CA",X"05",X"01", + X"21",X"0C",X"20",X"36",X"05",X"21",X"0A",X"22",X"7E",X"E6",X"40",X"CA",X"13",X"01",X"21",X"0D", + X"20",X"36",X"05",X"C3",X"5D",X"47",X"FE",X"5D",X"DA",X"3A",X"01",X"21",X"6F",X"20",X"36",X"00", + X"3E",X"10",X"CD",X"89",X"06",X"3A",X"1D",X"20",X"FE",X"6D",X"D2",X"7C",X"02",X"FE",X"66",X"D2", + X"8C",X"02",X"C3",X"6D",X"47",X"3E",X"08",X"CD",X"92",X"02",X"CD",X"37",X"02",X"21",X"1C",X"20", + X"7E",X"A7",X"CA",X"61",X"01",X"36",X"00",X"2E",X"20",X"36",X"01",X"CD",X"79",X"04",X"21",X"33", + X"23",X"DA",X"55",X"01",X"23",X"7E",X"32",X"02",X"23",X"CD",X"31",X"08",X"3E",X"01",X"CD",X"95", + X"06",X"D3",X"06",X"CD",X"DB",X"18",X"FE",X"08",X"DA",X"7E",X"01",X"FE",X"0A",X"21",X"47",X"20", + X"7E",X"D2",X"79",X"01",X"FE",X"02",X"C3",X"8E",X"01",X"FE",X"01",X"C3",X"8E",X"01",X"FE",X"06", + X"21",X"47",X"20",X"7E",X"DA",X"8C",X"01",X"FE",X"03",X"C3",X"8E",X"01",X"FE",X"08",X"DA",X"AA", + X"01",X"36",X"00",X"23",X"34",X"CD",X"53",X"05",X"06",X"02",X"AF",X"2A",X"14",X"20",X"11",X"E0", + X"FF",X"77",X"19",X"22",X"14",X"20",X"05",X"C2",X"A1",X"01",X"CD",X"79",X"04",X"21",X"03",X"23", + X"D2",X"CC",X"01",X"7E",X"FE",X"01",X"DA",X"E0",X"00",X"21",X"45",X"23",X"7E",X"A7",X"C2",X"E0", + X"00",X"36",X"FF",X"2E",X"2F",X"34",X"CD",X"2A",X"04",X"C3",X"E0",X"00",X"2E",X"06",X"7E",X"FE", + X"01",X"DA",X"E0",X"00",X"21",X"46",X"23",X"7E",X"A7",X"C2",X"E0",X"00",X"36",X"FF",X"2E",X"30", + X"C3",X"C5",X"01",X"FE",X"02",X"DA",X"85",X"00",X"F5",X"21",X"1D",X"21",X"36",X"FF",X"21",X"B0", + X"46",X"11",X"20",X"21",X"06",X"80",X"CD",X"41",X"0B",X"21",X"00",X"47",X"CD",X"22",X"04",X"21", + X"10",X"01",X"22",X"1E",X"21",X"F1",X"FE",X"03",X"DA",X"85",X"00",X"CD",X"72",X"02",X"21",X"20", + X"21",X"3E",X"04",X"77",X"2E",X"4E",X"77",X"2E",X"6C",X"77",X"2E",X"44",X"36",X"FC",X"2E",X"48", + X"36",X"FC",X"C3",X"85",X"00",X"E5",X"06",X"08",X"C5",X"1A",X"77",X"13",X"01",X"20",X"00",X"09", + X"C1",X"05",X"C2",X"28",X"02",X"E1",X"C9",X"21",X"02",X"20",X"7E",X"A7",X"CA",X"53",X"02",X"3A", + X"04",X"20",X"21",X"0F",X"1C",X"3D",X"CA",X"50",X"02",X"11",X"16",X"00",X"19",X"C3",X"45",X"02", + X"22",X"10",X"20",X"3A",X"02",X"21",X"A7",X"CA",X"63",X"02",X"3A",X"04",X"21",X"CD",X"F0",X"1A", + X"22",X"0D",X"21",X"3A",X"02",X"22",X"A7",X"C8",X"3A",X"04",X"22",X"CD",X"F0",X"1A",X"22",X"0D", + X"22",X"C9",X"21",X"6F",X"20",X"36",X"FF",X"3E",X"10",X"C3",X"7E",X"06",X"FE",X"7B",X"D2",X"9F", + X"02",X"21",X"06",X"06",X"3E",X"04",X"CD",X"92",X"02",X"C3",X"3A",X"01",X"21",X"05",X"05",X"C3", + X"84",X"02",X"22",X"0C",X"20",X"F5",X"3E",X"1C",X"CD",X"A0",X"06",X"F1",X"C3",X"95",X"06",X"3A", + X"1C",X"20",X"A7",X"C2",X"81",X"02",X"21",X"42",X"23",X"36",X"00",X"3E",X"FF",X"CD",X"A0",X"06", + X"CD",X"79",X"04",X"21",X"31",X"23",X"DA",X"BA",X"02",X"23",X"34",X"21",X"0D",X"25",X"01",X"03", + X"D0",X"CD",X"DE",X"41",X"21",X"0D",X"C5",X"01",X"33",X"03",X"3E",X"01",X"CD",X"D2",X"08",X"21", + X"0E",X"2B",X"11",X"15",X"47",X"06",X"0F",X"CD",X"22",X"08",X"CD",X"DB",X"42",X"CD",X"FD",X"05", + X"CD",X"AA",X"41",X"CD",X"4C",X"04",X"21",X"01",X"00",X"22",X"6A",X"20",X"21",X"00",X"3B",X"06", + X"0E",X"CD",X"CD",X"03",X"21",X"00",X"FF",X"22",X"6A",X"20",X"21",X"0E",X"3B",X"06",X"0B",X"CD", + X"CD",X"03",X"21",X"6C",X"20",X"36",X"FF",X"21",X"FF",X"FF",X"22",X"6A",X"20",X"CD",X"79",X"04", + X"21",X"1D",X"26",X"DA",X"19",X"03",X"21",X"1D",X"39",X"06",X"0E",X"CD",X"CD",X"03",X"CD",X"79", + X"04",X"21",X"00",X"01",X"22",X"6A",X"20",X"06",X"09",X"21",X"0F",X"26",X"DA",X"3A",X"03",X"21", + X"00",X"FF",X"22",X"6A",X"20",X"06",X"0A",X"21",X"0F",X"39",X"CD",X"CD",X"03",X"21",X"0E",X"2E", + X"11",X"24",X"47",X"CD",X"25",X"02",X"21",X"0D",X"2E",X"01",X"30",X"01",X"3E",X"38",X"CD",X"DC", + X"04",X"2A",X"12",X"20",X"22",X"01",X"23",X"CD",X"5E",X"04",X"3E",X"20",X"CD",X"9C",X"41",X"21", + X"0C",X"2F",X"CD",X"79",X"04",X"11",X"03",X"23",X"DA",X"6E",X"03",X"11",X"06",X"23",X"CD",X"80", + X"0C",X"CD",X"9A",X"41",X"CD",X"4C",X"04",X"CD",X"34",X"0C",X"CD",X"79",X"04",X"21",X"33",X"23", + X"DA",X"84",X"03",X"23",X"22",X"6E",X"20",X"7E",X"C6",X"10",X"FE",X"A0",X"DA",X"91",X"03",X"3E", + X"90",X"77",X"21",X"0F",X"2C",X"11",X"38",X"47",X"06",X"0D",X"CD",X"22",X"08",X"21",X"0F",X"31", + X"22",X"28",X"23",X"2A",X"6E",X"20",X"22",X"26",X"23",X"06",X"01",X"CD",X"52",X"08",X"CD",X"9A", + X"41",X"21",X"0B",X"CE",X"01",X"16",X"01",X"3E",X"01",X"CD",X"D2",X"08",X"21",X"0B",X"2F",X"11", + X"45",X"47",X"06",X"09",X"CD",X"22",X"08",X"CD",X"AA",X"41",X"C3",X"4A",X"00",X"C5",X"E5",X"CD", + X"F0",X"03",X"2A",X"6A",X"20",X"EB",X"E1",X"19",X"3A",X"6C",X"20",X"A7",X"C2",X"F6",X"03",X"11", + X"12",X"20",X"CD",X"08",X"04",X"06",X"20",X"CD",X"81",X"04",X"C1",X"05",X"C2",X"CD",X"03",X"C9", + X"01",X"01",X"28",X"C3",X"DE",X"41",X"CD",X"79",X"04",X"11",X"03",X"23",X"DA",X"02",X"04",X"11", + X"06",X"23",X"CD",X"11",X"04",X"C3",X"E5",X"03",X"E5",X"CD",X"1A",X"04",X"CD",X"50",X"08",X"E1", + X"C9",X"E5",X"CD",X"1A",X"04",X"CD",X"43",X"08",X"E1",X"C9",X"22",X"28",X"23",X"EB",X"22",X"26", + X"23",X"C9",X"11",X"06",X"22",X"06",X"0E",X"C3",X"41",X"0B",X"21",X"2F",X"23",X"CD",X"79",X"04", + X"DA",X"35",X"04",X"2E",X"30",X"7E",X"FE",X"02",X"D8",X"21",X"00",X"25",X"F5",X"11",X"4E",X"47", + X"CD",X"25",X"02",X"F1",X"3D",X"FE",X"02",X"D8",X"24",X"C3",X"3C",X"04",X"21",X"01",X"24",X"01", + X"1C",X"E0",X"CD",X"DE",X"41",X"21",X"01",X"C4",X"01",X"38",X"1B",X"C3",X"D0",X"08",X"21",X"02", + X"23",X"11",X"05",X"23",X"3A",X"2A",X"23",X"5F",X"CD",X"81",X"08",X"13",X"23",X"CD",X"8F",X"08", + X"21",X"00",X"23",X"11",X"03",X"00",X"C3",X"CA",X"0A",X"AF",X"3A",X"2C",X"23",X"A7",X"C0",X"37", + X"C9",X"0E",X"FF",X"0D",X"C2",X"83",X"04",X"05",X"C2",X"81",X"04",X"C9",X"21",X"C9",X"04",X"11", + X"2F",X"23",X"06",X"0C",X"CD",X"41",X"0B",X"DB",X"02",X"E6",X"03",X"06",X"03",X"80",X"21",X"2F", + X"23",X"77",X"23",X"77",X"DB",X"02",X"E6",X"08",X"C8",X"21",X"04",X"23",X"36",X"90",X"2E",X"07", + X"36",X"90",X"C3",X"BC",X"47",X"04",X"22",X"31",X"23",X"C9",X"05",X"23",X"1D",X"26",X"21",X"BA", + X"04",X"11",X"26",X"23",X"06",X"04",X"C3",X"41",X"0B",X"05",X"05",X"01",X"01",X"10",X"10",X"00", + X"40",X"00",X"40",X"D0",X"90",X"21",X"00",X"24",X"01",X"E0",X"20",X"AF",X"C5",X"E5",X"77",X"23", + X"05",X"C2",X"DE",X"04",X"E1",X"11",X"20",X"00",X"19",X"C1",X"0D",X"C2",X"DC",X"04",X"C9",X"11", + X"3F",X"02",X"21",X"00",X"20",X"C3",X"CA",X"0A",X"CD",X"EF",X"04",X"11",X"04",X"20",X"21",X"B3", + X"1B",X"06",X"14",X"CD",X"41",X"0B",X"11",X"04",X"21",X"21",X"C6",X"1B",X"06",X"17",X"CD",X"41", + X"0B",X"11",X"20",X"23",X"21",X"E7",X"1B",X"06",X"0A",X"CD",X"41",X"0B",X"21",X"72",X"20",X"22", + X"70",X"20",X"21",X"2D",X"05",X"11",X"72",X"20",X"06",X"1B",X"C3",X"41",X"0B",X"03",X"01",X"07", + X"01",X"07",X"05",X"07",X"01",X"03",X"05",X"07",X"01",X"03",X"01",X"07",X"05",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"21",X"0E",X"07",X"11",X"2A",X"23",X"06",X"03", + X"C3",X"41",X"0B",X"21",X"12",X"20",X"7E",X"A7",X"C8",X"23",X"EB",X"21",X"0E",X"1C",X"0E",X"02", + X"37",X"3E",X"99",X"CE",X"00",X"96",X"EB",X"86",X"27",X"77",X"EB",X"1B",X"2B",X"0D",X"C2",X"61", + X"05",X"21",X"00",X"3B",X"22",X"28",X"23",X"21",X"12",X"20",X"22",X"26",X"23",X"06",X"02",X"CD", + X"50",X"08",X"C3",X"BE",X"04",X"21",X"0B",X"07",X"C3",X"4B",X"05",X"CD",X"02",X"06",X"CD",X"B0", + X"40",X"CD",X"FD",X"05",X"CD",X"95",X"02",X"3A",X"3B",X"23",X"A7",X"CA",X"07",X"06",X"CD",X"79", + X"04",X"21",X"2F",X"23",X"D2",X"D0",X"05",X"7E",X"3D",X"77",X"C2",X"C7",X"05",X"CD",X"48",X"06", + X"CD",X"11",X"07",X"CD",X"9A",X"41",X"21",X"30",X"23",X"7E",X"A7",X"CA",X"19",X"06",X"CD",X"08", + X"46",X"CD",X"AC",X"06",X"C3",X"4A",X"00",X"23",X"7E",X"A7",X"CA",X"4A",X"00",X"C3",X"BE",X"05", + X"23",X"7E",X"3D",X"77",X"C2",X"F4",X"05",X"CD",X"4E",X"06",X"CD",X"11",X"07",X"CD",X"9A",X"41", + X"21",X"2F",X"23",X"7E",X"A7",X"CA",X"19",X"06",X"CD",X"9A",X"41",X"CD",X"D5",X"04",X"CD",X"C0", + X"06",X"C3",X"4A",X"00",X"2B",X"7E",X"A7",X"CA",X"4A",X"00",X"C3",X"E8",X"05",X"3E",X"12",X"CD", + X"89",X"06",X"3E",X"FF",X"C3",X"A0",X"06",X"21",X"2F",X"23",X"7E",X"3D",X"77",X"CA",X"16",X"06", + X"CD",X"9A",X"41",X"C3",X"4A",X"00",X"CD",X"11",X"07",X"3E",X"02",X"CD",X"89",X"06",X"CD",X"9A", + X"41",X"CD",X"4C",X"04",X"CD",X"8C",X"04",X"21",X"10",X"2D",X"CD",X"70",X"06",X"CD",X"9A",X"41", + X"3A",X"0E",X"23",X"A7",X"C4",X"48",X"43",X"CD",X"D6",X"45",X"21",X"43",X"23",X"36",X"FF",X"21", + X"00",X"00",X"22",X"45",X"23",X"C3",X"41",X"00",X"11",X"E3",X"06",X"C3",X"51",X"06",X"11",X"F6", + X"06",X"D5",X"21",X"06",X"CD",X"01",X"14",X"01",X"CD",X"D0",X"08",X"21",X"03",X"CD",X"01",X"14", + X"01",X"CD",X"D0",X"08",X"D1",X"21",X"06",X"2D",X"06",X"0A",X"CD",X"7B",X"41",X"21",X"03",X"2D", + X"11",X"ED",X"06",X"06",X"09",X"C3",X"7B",X"41",X"21",X"10",X"2D",X"C3",X"70",X"06",X"C5",X"21", + X"2D",X"23",X"46",X"B0",X"D3",X"05",X"77",X"C1",X"C9",X"C5",X"21",X"2D",X"23",X"46",X"2F",X"A0", + X"D3",X"05",X"77",X"C1",X"C9",X"C5",X"21",X"2E",X"23",X"46",X"B0",X"D3",X"03",X"77",X"C1",X"C9", + X"C5",X"21",X"2E",X"23",X"46",X"2F",X"A0",X"D3",X"03",X"77",X"C1",X"C9",X"21",X"0B",X"07",X"CD", + X"CE",X"45",X"F3",X"3E",X"20",X"21",X"2D",X"23",X"46",X"B0",X"D3",X"05",X"77",X"C3",X"D5",X"06", + X"CD",X"CB",X"45",X"F3",X"CD",X"DC",X"0E",X"D2",X"E1",X"06",X"3E",X"20",X"21",X"2D",X"23",X"46", + X"2F",X"A0",X"D3",X"05",X"77",X"06",X"F0",X"0E",X"FF",X"0D",X"C2",X"D9",X"06",X"05",X"C2",X"D7", + X"06",X"FB",X"C9",X"0F",X"0B",X"00",X"18",X"04",X"11",X"1B",X"1E",X"21",X"1F",X"06",X"00",X"0C", + X"04",X"1B",X"0E",X"15",X"04",X"11",X"0F",X"0B",X"00",X"18",X"04",X"11",X"1B",X"1E",X"22",X"1F", + X"05",X"05",X"B8",X"42",X"B8",X"42",X"48",X"9E",X"0A",X"9E",X"0A",X"08",X"39",X"FF",X"05",X"26", + X"00",X"21",X"03",X"23",X"3A",X"2A",X"23",X"6F",X"2B",X"2B",X"22",X"09",X"23",X"06",X"03",X"11", + X"3F",X"23",X"AF",X"1A",X"BE",X"DA",X"31",X"07",X"96",X"C0",X"23",X"13",X"05",X"C2",X"23",X"07", + X"C9",X"06",X"03",X"2A",X"09",X"23",X"11",X"3F",X"23",X"7E",X"12",X"23",X"13",X"05",X"C2",X"39", + X"07",X"CD",X"79",X"04",X"21",X"FF",X"00",X"DA",X"4D",X"07",X"21",X"FF",X"FF",X"22",X"0E",X"23", + X"21",X"1D",X"2F",X"22",X"28",X"23",X"2A",X"09",X"23",X"22",X"26",X"23",X"C3",X"43",X"08",X"0F", + X"0F",X"D2",X"93",X"07",X"CD",X"27",X"0B",X"7D",X"E6",X"1F",X"FE",X"0E",X"CA",X"7F",X"07",X"D6", + X"02",X"21",X"B4",X"12",X"CA",X"7D",X"07",X"23",X"D6",X"03",X"C2",X"77",X"07",X"7E",X"C9",X"7C", + X"FE",X"37",X"D2",X"8D",X"07",X"FE",X"2E",X"D2",X"90",X"07",X"3E",X"10",X"C9",X"3E",X"12",X"C9", + X"3E",X"11",X"C9",X"CD",X"27",X"0B",X"7C",X"D6",X"25",X"21",X"BD",X"12",X"C3",X"74",X"07",X"21", + X"8B",X"09",X"3E",X"18",X"CD",X"F2",X"07",X"21",X"B4",X"09",X"3E",X"FF",X"CD",X"F2",X"07",X"01", + X"11",X"0A",X"21",X"F5",X"09",X"CD",X"DC",X"07",X"01",X"19",X"0A",X"21",X"FC",X"09",X"CD",X"DC", + X"07",X"01",X"21",X"0A",X"21",X"03",X"0A",X"CD",X"DC",X"07",X"01",X"29",X"0A",X"21",X"0A",X"0A", + X"CD",X"DC",X"07",X"01",X"6A",X"0A",X"21",X"31",X"0A",X"C3",X"DC",X"07",X"E5",X"7E",X"FE",X"FF", + X"C2",X"E5",X"07",X"E1",X"C9",X"5F",X"23",X"56",X"EB",X"CD",X"10",X"08",X"E1",X"23",X"23",X"C3", + X"DC",X"07",X"E5",X"47",X"7E",X"FE",X"FF",X"C2",X"FC",X"07",X"E1",X"C9",X"78",X"46",X"23",X"4E", + X"23",X"5E",X"23",X"56",X"EB",X"CD",X"DC",X"04",X"E1",X"23",X"23",X"23",X"23",X"C3",X"F2",X"07", + X"C5",X"16",X"08",X"D5",X"0A",X"77",X"11",X"20",X"00",X"19",X"03",X"D1",X"15",X"C2",X"13",X"08", + X"C1",X"C9",X"D5",X"1A",X"CD",X"94",X"08",X"CD",X"AB",X"08",X"D1",X"13",X"05",X"C2",X"22",X"08", + X"C9",X"CD",X"5E",X"04",X"21",X"2A",X"23",X"7E",X"3D",X"3D",X"2E",X"26",X"77",X"2E",X"2B",X"7E", + X"2E",X"29",X"77",X"2A",X"26",X"23",X"7E",X"23",X"22",X"26",X"23",X"E6",X"0F",X"CD",X"71",X"08", + X"06",X"02",X"C5",X"2A",X"26",X"23",X"7E",X"F5",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"CD",X"71", + X"08",X"F1",X"E6",X"0F",X"CD",X"71",X"08",X"21",X"26",X"23",X"34",X"C1",X"05",X"C2",X"52",X"08", + X"C9",X"C6",X"20",X"CD",X"94",X"08",X"2A",X"28",X"23",X"CD",X"AB",X"08",X"21",X"29",X"23",X"34", + X"C9",X"06",X"03",X"AF",X"1A",X"8E",X"27",X"77",X"2B",X"1B",X"05",X"C2",X"84",X"08",X"C9",X"06", + X"03",X"C3",X"41",X"0B",X"11",X"5C",X"1D",X"A7",X"C8",X"E5",X"21",X"00",X"00",X"C5",X"01",X"05", + X"00",X"09",X"3D",X"C2",X"9E",X"08",X"19",X"EB",X"C1",X"E1",X"C9",X"C5",X"06",X"05",X"D3",X"06", + X"C5",X"1A",X"07",X"77",X"13",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"AE",X"08",X"AF",X"77", + X"01",X"20",X"00",X"09",X"77",X"09",X"77",X"09",X"C1",X"C9",X"21",X"00",X"C4",X"01",X"38",X"20", + X"3E",X"FF",X"C5",X"E5",X"77",X"23",X"05",X"C2",X"D4",X"08",X"E1",X"11",X"80",X"00",X"19",X"C1", + X"0D",X"C2",X"D2",X"08",X"C9",X"E5",X"7E",X"FE",X"FF",X"C2",X"EE",X"08",X"E1",X"C9",X"5F",X"23", + X"56",X"23",X"46",X"EB",X"3A",X"39",X"20",X"A7",X"C2",X"05",X"09",X"CD",X"0B",X"09",X"E1",X"23", + X"23",X"23",X"C3",X"E5",X"08",X"CD",X"1B",X"09",X"C3",X"FE",X"08",X"C5",X"E5",X"11",X"7B",X"09", + X"CD",X"25",X"02",X"E1",X"23",X"C1",X"05",X"C2",X"0B",X"09",X"C9",X"C5",X"E5",X"11",X"83",X"09", + X"CD",X"25",X"02",X"E1",X"24",X"C1",X"05",X"C2",X"1B",X"09",X"C9",X"05",X"26",X"08",X"11",X"26", + X"08",X"08",X"29",X"05",X"11",X"29",X"05",X"0B",X"2C",X"02",X"11",X"2C",X"02",X"0B",X"2F",X"02", + X"11",X"2F",X"02",X"0B",X"32",X"02",X"11",X"32",X"02",X"0B",X"35",X"02",X"11",X"35",X"02",X"0B", + X"38",X"02",X"11",X"38",X"02",X"08",X"3B",X"05",X"11",X"3B",X"05",X"05",X"3E",X"08",X"11",X"3E", + X"08",X"FF",X"03",X"28",X"08",X"03",X"35",X"07",X"06",X"2B",X"05",X"06",X"34",X"05",X"18",X"2B", + X"05",X"18",X"34",X"05",X"1B",X"28",X"08",X"1B",X"34",X"08",X"FF",X"18",X"18",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"00",X"00",X"00",X"01",X"D0",X"01",X"25",X"01", + X"40",X"04",X"28",X"01",X"40",X"04",X"34",X"01",X"28",X"07",X"2B",X"01",X"28",X"07",X"34",X"01", + X"28",X"16",X"2B",X"01",X"28",X"16",X"34",X"01",X"40",X"19",X"28",X"01",X"40",X"19",X"34",X"01", + X"D0",X"1C",X"25",X"FF",X"1A",X"02",X"62",X"24",X"08",X"02",X"65",X"27",X"08",X"02",X"71",X"27", + X"05",X"02",X"68",X"2A",X"05",X"02",X"71",X"2A",X"08",X"02",X"6B",X"2D",X"02",X"02",X"6B",X"30", + X"02",X"02",X"71",X"30",X"02",X"02",X"6B",X"33",X"02",X"02",X"71",X"33",X"08",X"02",X"6B",X"36", + X"05",X"02",X"68",X"39",X"05",X"02",X"71",X"39",X"08",X"02",X"65",X"3C",X"08",X"02",X"71",X"3C", + X"1A",X"02",X"62",X"3F",X"FF",X"01",X"24",X"04",X"27",X"07",X"2A",X"FF",X"01",X"3F",X"04",X"3C", + X"07",X"39",X"FF",X"1C",X"24",X"19",X"27",X"16",X"2A",X"FF",X"1C",X"3F",X"19",X"3C",X"16",X"39", + X"FF",X"00",X"00",X"00",X"F8",X"F8",X"18",X"18",X"18",X"18",X"18",X"18",X"F8",X"F8",X"00",X"00", + X"00",X"00",X"00",X"00",X"1F",X"1F",X"18",X"18",X"18",X"18",X"18",X"18",X"1F",X"1F",X"00",X"00", + X"00",X"0D",X"27",X"10",X"27",X"0D",X"2A",X"10",X"2A",X"0A",X"2D",X"13",X"2D",X"04",X"30",X"07", + X"30",X"0A",X"30",X"0D",X"30",X"10",X"30",X"13",X"30",X"16",X"30",X"19",X"30",X"04",X"33",X"07", + X"33",X"0A",X"33",X"0D",X"33",X"10",X"33",X"13",X"33",X"16",X"33",X"19",X"33",X"0A",X"36",X"13", + X"36",X"0D",X"39",X"10",X"39",X"0D",X"3C",X"10",X"3C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"08",X"00",X"18",X"02",X"30",X"04",X"F8",X"3F",X"30",X"04",X"18",X"02",X"08",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"20",X"00",X"20",X"00",X"70",X"00", + X"A0",X"00",X"20",X"00",X"20",X"00",X"20",X"00",X"70",X"00",X"F8",X"00",X"AC",X"01",X"00",X"00", + X"00",X"00",X"00",X"10",X"40",X"18",X"20",X"0C",X"FC",X"1F",X"20",X"0C",X"40",X"18",X"00",X"10", + X"00",X"00",X"00",X"00",X"80",X"35",X"00",X"1F",X"00",X"0E",X"00",X"04",X"00",X"04",X"00",X"04", + X"00",X"11",X"00",X"0E",X"00",X"04",X"00",X"04",X"00",X"04",X"AF",X"77",X"23",X"1B",X"BA",X"C2", + X"CB",X"0A",X"BB",X"C2",X"CB",X"0A",X"C9",X"7D",X"E6",X"07",X"D3",X"02",X"CD",X"27",X"0B",X"01", + X"0B",X"02",X"C9",X"CD",X"D7",X"0A",X"97",X"32",X"29",X"20",X"C5",X"E5",X"1A",X"D3",X"04",X"DB", + X"03",X"F5",X"A6",X"CA",X"FE",X"0A",X"3E",X"01",X"32",X"29",X"20",X"22",X"2A",X"20",X"F1",X"B6", + X"77",X"23",X"13",X"05",X"C2",X"EC",X"0A",X"97",X"D3",X"04",X"DB",X"03",X"F5",X"A6",X"CA",X"19", + X"0B",X"3E",X"01",X"32",X"29",X"20",X"22",X"2A",X"20",X"F1",X"B6",X"77",X"E1",X"01",X"20",X"00", + X"09",X"C1",X"0D",X"C2",X"EA",X"0A",X"C9",X"C5",X"06",X"03",X"7C",X"1F",X"67",X"7D",X"1F",X"6F", + X"05",X"C2",X"2A",X"0B",X"7C",X"E6",X"3F",X"F6",X"20",X"67",X"C1",X"C9",X"06",X"06",X"11",X"23", + X"20",X"7E",X"12",X"23",X"13",X"05",X"C2",X"41",X"0B",X"C9",X"CD",X"D7",X"0A",X"C5",X"E5",X"1A", + X"D3",X"04",X"DB",X"03",X"AE",X"A6",X"77",X"23",X"13",X"05",X"C2",X"4F",X"0B",X"97",X"D3",X"04", + X"DB",X"03",X"AE",X"A6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"4D",X"0B",X"C9", + X"CD",X"D7",X"0A",X"97",X"32",X"17",X"21",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"F5",X"A6", + X"CA",X"8B",X"0B",X"3E",X"01",X"32",X"17",X"21",X"22",X"18",X"21",X"F1",X"AE",X"77",X"23",X"13", + X"05",X"C2",X"79",X"0B",X"97",X"D3",X"04",X"DB",X"03",X"F5",X"A6",X"CA",X"A6",X"0B",X"3E",X"01", + X"32",X"17",X"21",X"22",X"18",X"21",X"F1",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D", + X"C2",X"77",X"0B",X"C9",X"CD",X"9F",X"07",X"21",X"2B",X"09",X"CD",X"E5",X"08",X"21",X"39",X"20", + X"36",X"FF",X"21",X"62",X"09",X"CD",X"E5",X"08",X"21",X"3B",X"20",X"36",X"FF",X"E5",X"21",X"F2", + X"1C",X"CD",X"EA",X"0B",X"E1",X"36",X"00",X"21",X"1B",X"1D",X"C3",X"EA",X"0B",X"AF",X"06",X"08", + X"77",X"11",X"20",X"00",X"19",X"05",X"C2",X"E0",X"0B",X"C9",X"E5",X"7E",X"FE",X"FF",X"C2",X"F3", + X"0B",X"E1",X"C9",X"5F",X"23",X"56",X"23",X"46",X"23",X"4E",X"EB",X"3A",X"3B",X"20",X"A7",X"CA", + X"08",X"0C",X"CD",X"13",X"0C",X"C3",X"0B",X"0C",X"CD",X"1D",X"0C",X"E1",X"23",X"23",X"23",X"23", + X"C3",X"EA",X"0B",X"71",X"11",X"80",X"00",X"19",X"05",X"C2",X"13",X"0C",X"C9",X"E5",X"71",X"11", + X"80",X"00",X"19",X"71",X"E1",X"23",X"05",X"C2",X"1D",X"0C",X"C9",X"21",X"42",X"23",X"7E",X"A7", + X"37",X"C8",X"3F",X"C9",X"CD",X"6A",X"42",X"21",X"1E",X"25",X"11",X"CC",X"1C",X"06",X"1A",X"CD", + X"22",X"08",X"21",X"1D",X"26",X"11",X"03",X"23",X"CD",X"80",X"0C",X"21",X"1D",X"2F",X"11",X"3F", + X"23",X"CD",X"80",X"0C",X"3A",X"3B",X"23",X"A7",X"CA",X"64",X"0C",X"21",X"1D",X"39",X"11",X"06", + X"23",X"CD",X"80",X"0C",X"CD",X"A8",X"45",X"CD",X"9B",X"45",X"21",X"00",X"2A",X"11",X"E6",X"1C", + X"06",X"04",X"CD",X"22",X"08",X"21",X"00",X"2E",X"01",X"01",X"30",X"3E",X"F8",X"C3",X"DF",X"41", + X"CD",X"1A",X"04",X"C3",X"43",X"08",X"21",X"00",X"37",X"11",X"EA",X"1C",X"06",X"06",X"C3",X"22", + X"08",X"3A",X"3D",X"23",X"C6",X"20",X"CD",X"94",X"08",X"21",X"00",X"3E",X"C3",X"AB",X"08",X"21", + X"00",X"35",X"11",X"DD",X"1B",X"06",X"0A",X"C3",X"22",X"08",X"C3",X"DD",X"1F",X"11",X"B4",X"0A", + X"CD",X"70",X"0B",X"CD",X"DB",X"18",X"FE",X"02",X"D8",X"FE",X"06",X"21",X"58",X"2A",X"D2",X"CF", + X"0C",X"FE",X"04",X"21",X"28",X"D2",X"11",X"72",X"0A",X"DA",X"70",X"0B",X"21",X"B8",X"42",X"11", + X"9E",X"0A",X"C3",X"70",X"0B",X"3A",X"44",X"23",X"A7",X"CA",X"CC",X"0E",X"C3",X"06",X"0D",X"CD", + X"79",X"04",X"DB",X"01",X"D8",X"DB",X"00",X"C9",X"CD",X"39",X"17",X"21",X"91",X"22",X"35",X"CD", + X"02",X"0E",X"DB",X"02",X"E6",X"10",X"C4",X"DE",X"0D",X"3A",X"51",X"22",X"A7",X"C2",X"B0",X"0D", + X"CD",X"2B",X"0C",X"DA",X"D5",X"0C",X"21",X"00",X"20",X"34",X"7E",X"FE",X"03",X"D2",X"44",X"16", + X"FE",X"02",X"D2",X"45",X"17",X"21",X"01",X"20",X"7E",X"A7",X"C2",X"C7",X"0E",X"23",X"7E",X"A7", + X"C2",X"82",X"0E",X"2A",X"06",X"20",X"3A",X"04",X"20",X"CD",X"5F",X"07",X"32",X"0A",X"20",X"AF", + X"47",X"3A",X"42",X"23",X"A7",X"CA",X"A3",X"0D",X"CD",X"D2",X"0E",X"E6",X"0F",X"A7",X"CA",X"76", + X"12",X"21",X"03",X"20",X"36",X"FF",X"0F",X"DA",X"4F",X"0D",X"04",X"04",X"C3",X"46",X"0D",X"3E", + X"01",X"80",X"23",X"23",X"77",X"2B",X"7E",X"47",X"23",X"BE",X"CA",X"50",X"12",X"C6",X"04",X"BE", + X"CA",X"5E",X"12",X"D6",X"08",X"BE",X"CA",X"5E",X"12",X"2A",X"06",X"20",X"11",X"08",X"05",X"19", + X"3A",X"05",X"20",X"FE",X"05",X"D2",X"64",X"12",X"FE",X"03",X"CA",X"70",X"12",X"11",X"0B",X"00", + X"19",X"CD",X"27",X"0B",X"7E",X"A7",X"C2",X"76",X"12",X"2A",X"06",X"20",X"E5",X"21",X"28",X"13", + X"3A",X"0A",X"20",X"E6",X"1F",X"3D",X"C2",X"9E",X"0D",X"5E",X"23",X"56",X"EB",X"E9",X"23",X"23", + X"C3",X"95",X"0D",X"2A",X"70",X"20",X"7E",X"32",X"05",X"20",X"21",X"04",X"20",X"C3",X"56",X"0D", + X"DB",X"01",X"E6",X"60",X"C4",X"D8",X"0D",X"CD",X"F2",X"0D",X"E6",X"10",X"06",X"01",X"21",X"40", + X"22",X"C2",X"CD",X"0D",X"7E",X"A7",X"23",X"C2",X"CD",X"0D",X"2B",X"06",X"00",X"70",X"2A",X"4E", + X"22",X"23",X"22",X"4E",X"22",X"C3",X"CC",X"0E",X"3E",X"01",X"32",X"56",X"22",X"C9",X"CD",X"E7", + X"0D",X"CD",X"A8",X"45",X"C3",X"9B",X"45",X"06",X"19",X"21",X"7C",X"46",X"11",X"40",X"22",X"C3", + X"41",X"0B",X"CD",X"03",X"46",X"DB",X"01",X"C8",X"3A",X"0F",X"23",X"A7",X"DB",X"00",X"C0",X"DB", + X"01",X"C9",X"DB",X"02",X"E6",X"20",X"C8",X"21",X"90",X"20",X"7E",X"A7",X"C0",X"31",X"00",X"24", + X"CD",X"4C",X"04",X"CD",X"BA",X"41",X"CD",X"02",X"06",X"21",X"51",X"22",X"77",X"21",X"0E",X"23", + X"77",X"23",X"77",X"21",X"1C",X"21",X"36",X"00",X"3E",X"10",X"CD",X"89",X"06",X"21",X"00",X"FF", + X"22",X"42",X"23",X"21",X"00",X"00",X"22",X"44",X"23",X"22",X"46",X"23",X"CD",X"8C",X"04",X"FB", + X"CD",X"03",X"46",X"C2",X"4C",X"0E",X"CD",X"AC",X"06",X"C3",X"4F",X"0E",X"CD",X"C0",X"06",X"21", + X"15",X"30",X"11",X"D9",X"1F",X"06",X"04",X"CD",X"22",X"08",X"CD",X"AA",X"41",X"D3",X"06",X"21", + X"16",X"20",X"36",X"00",X"21",X"90",X"20",X"36",X"00",X"C3",X"19",X"06",X"11",X"C6",X"12",X"C3", + X"90",X"12",X"3A",X"00",X"20",X"FE",X"03",X"CA",X"A3",X"1A",X"FE",X"02",X"CA",X"68",X"19",X"22", + X"08",X"20",X"21",X"05",X"20",X"46",X"2B",X"7E",X"57",X"B8",X"C2",X"94",X"0E",X"2B",X"2B",X"36", + X"00",X"C3",X"C7",X"0E",X"48",X"DA",X"BA",X"0F",X"07",X"07",X"07",X"07",X"B1",X"FE",X"71",X"36", + X"08",X"CA",X"AD",X"0E",X"FE",X"81",X"36",X"01",X"CA",X"AD",X"0E",X"15",X"72",X"2B",X"2B",X"36", + X"FF",X"CD",X"DC",X"0E",X"3A",X"09",X"20",X"DA",X"E6",X"0E",X"FE",X"80",X"D2",X"C7",X"0E",X"CD", + X"89",X"13",X"21",X"01",X"20",X"36",X"01",X"21",X"2C",X"20",X"36",X"FF",X"F1",X"C1",X"D1",X"E1", + X"FB",X"C9",X"DB",X"02",X"E6",X"40",X"C2",X"DF",X"0C",X"DB",X"01",X"C9",X"DB",X"02",X"E6",X"40", + X"C2",X"79",X"04",X"37",X"3F",X"C9",X"FE",X"80",X"DA",X"C7",X"0E",X"C3",X"BF",X"0E",X"3A",X"70", + X"22",X"A7",X"C4",X"0B",X"0F",X"3A",X"78",X"22",X"A7",X"C4",X"29",X"0F",X"3A",X"80",X"22",X"A7", + X"C4",X"47",X"0F",X"3A",X"88",X"22",X"A7",X"C2",X"65",X"0F",X"C9",X"2A",X"73",X"22",X"7C",X"FE", + X"30",X"DA",X"83",X"0F",X"7D",X"FE",X"E0",X"D2",X"83",X"0F",X"CD",X"AF",X"41",X"21",X"73",X"22", + X"CD",X"CF",X"41",X"21",X"71",X"22",X"C3",X"5A",X"41",X"2A",X"7B",X"22",X"7C",X"FE",X"E0",X"D2", + X"A5",X"0F",X"7D",X"FE",X"D0",X"D2",X"A5",X"0F",X"CD",X"AF",X"41",X"21",X"7B",X"22",X"CD",X"CF", + X"41",X"21",X"79",X"22",X"C3",X"5A",X"41",X"2A",X"83",X"22",X"7C",X"FE",X"E0",X"D2",X"AC",X"0F", + X"7D",X"FE",X"10",X"DA",X"AC",X"0F",X"CD",X"AF",X"41",X"21",X"83",X"22",X"CD",X"CF",X"41",X"21", + X"81",X"22",X"C3",X"5A",X"41",X"2A",X"8B",X"22",X"7C",X"FE",X"30",X"DA",X"B3",X"0F",X"7D",X"FE", + X"10",X"DA",X"B3",X"0F",X"CD",X"AF",X"41",X"21",X"8B",X"22",X"CD",X"CF",X"41",X"21",X"89",X"22", + X"C3",X"5A",X"41",X"AF",X"32",X"70",X"22",X"3A",X"70",X"22",X"A7",X"C0",X"3A",X"78",X"22",X"A7", + X"C0",X"3A",X"80",X"22",X"A7",X"C0",X"3A",X"88",X"22",X"A7",X"C0",X"32",X"90",X"22",X"32",X"92", + X"22",X"32",X"3D",X"20",X"C9",X"AF",X"32",X"78",X"22",X"C3",X"87",X"0F",X"AF",X"32",X"80",X"22", + X"C3",X"87",X"0F",X"AF",X"32",X"88",X"22",X"C3",X"87",X"0F",X"07",X"07",X"07",X"07",X"B1",X"FE", + X"17",X"36",X"08",X"CA",X"AD",X"0E",X"FE",X"18",X"36",X"01",X"CA",X"AD",X"0E",X"14",X"C3",X"AC", + X"0E",X"11",X"DE",X"12",X"C3",X"21",X"12",X"11",X"D8",X"12",X"C3",X"90",X"12",X"11",X"0E",X"13", + X"C3",X"21",X"12",X"11",X"CC",X"12",X"C3",X"90",X"12",X"11",X"E4",X"12",X"C3",X"21",X"12",X"11", + X"D2",X"12",X"C3",X"90",X"12",X"11",X"08",X"13",X"C3",X"21",X"12",X"11",X"EA",X"12",X"C3",X"21", + X"12",X"11",X"F0",X"12",X"C3",X"21",X"12",X"11",X"FC",X"12",X"C3",X"21",X"12",X"11",X"02",X"13", + X"C3",X"21",X"12",X"11",X"14",X"13",X"21",X"2F",X"20",X"06",X"0A",X"CD",X"47",X"12",X"E1",X"7C", + X"FE",X"80",X"D2",X"33",X"10",X"FE",X"68",X"2A",X"31",X"20",X"D2",X"72",X"0E",X"2A",X"2F",X"20", + X"C3",X"72",X"0E",X"FE",X"9C",X"D2",X"3E",X"10",X"2A",X"33",X"20",X"C3",X"72",X"0E",X"FE",X"B4", + X"2A",X"37",X"20",X"D2",X"72",X"0E",X"2A",X"35",X"20",X"C3",X"72",X"0E",X"11",X"1E",X"13",X"C3", + X"16",X"10",X"E1",X"7C",X"FE",X"38",X"D2",X"5F",X"10",X"21",X"70",X"2A",X"C3",X"72",X"0E",X"FE", + X"50",X"21",X"70",X"5A",X"D2",X"72",X"0E",X"21",X"70",X"42",X"C3",X"72",X"0E",X"E1",X"7C",X"FE", + X"80",X"D2",X"7A",X"10",X"21",X"70",X"72",X"C3",X"72",X"0E",X"FE",X"98",X"21",X"70",X"A2",X"D2", + X"72",X"0E",X"21",X"70",X"8A",X"C3",X"72",X"0E",X"E1",X"7C",X"FE",X"C8",X"D2",X"95",X"10",X"21", + X"70",X"BA",X"C3",X"72",X"0E",X"FE",X"E0",X"21",X"70",X"EA",X"D2",X"72",X"0E",X"21",X"70",X"D2", + X"C3",X"72",X"0E",X"E1",X"7D",X"FE",X"B2",X"D2",X"B6",X"10",X"FE",X"39",X"DA",X"C4",X"10",X"E5", + X"11",X"F6",X"12",X"C3",X"21",X"12",X"FE",X"C6",X"21",X"D0",X"8A",X"D2",X"72",X"0E",X"21",X"B8", + X"8A",X"C3",X"72",X"0E",X"FE",X"22",X"21",X"28",X"8A",X"D2",X"72",X"0E",X"21",X"10",X"8A",X"C3", + X"72",X"0E",X"21",X"2A",X"EA",X"22",X"17",X"20",X"E1",X"78",X"FE",X"03",X"CA",X"B1",X"11",X"7C", + X"CD",X"0D",X"12",X"21",X"18",X"20",X"46",X"B8",X"D2",X"C7",X"0E",X"21",X"09",X"20",X"77",X"CD", + X"DC",X"0E",X"3A",X"09",X"20",X"DA",X"82",X"11",X"FE",X"80",X"D2",X"C7",X"0E",X"CD",X"89",X"13", + X"21",X"02",X"20",X"7E",X"A7",X"CA",X"0B",X"11",X"2B",X"36",X"01",X"3A",X"29",X"20",X"A7",X"C2", + X"1D",X"11",X"21",X"2C",X"20",X"7E",X"A7",X"CA",X"C7",X"0E",X"C3",X"C0",X"14",X"2A",X"2A",X"20", + X"22",X"1E",X"20",X"2A",X"06",X"21",X"CD",X"5C",X"11",X"D2",X"BF",X"1C",X"2A",X"06",X"22",X"CD", + X"5C",X"11",X"D2",X"BF",X"1C",X"21",X"1C",X"20",X"36",X"FF",X"23",X"34",X"2A",X"2A",X"20",X"3E", + X"1F",X"A5",X"6F",X"3A",X"05",X"20",X"0F",X"0F",X"DA",X"55",X"11",X"AF",X"77",X"11",X"20",X"00", + X"19",X"77",X"C3",X"12",X"11",X"11",X"60",X"00",X"19",X"C3",X"4B",X"11",X"CD",X"27",X"0B",X"7D", + X"E6",X"1F",X"47",X"3A",X"1E",X"20",X"E6",X"1F",X"B8",X"CA",X"73",X"11",X"3D",X"B8",X"CA",X"73", + X"11",X"37",X"C9",X"3A",X"1F",X"20",X"BC",X"CA",X"7F",X"11",X"3D",X"BC",X"C2",X"71",X"11",X"37", + X"3F",X"C9",X"FE",X"80",X"DA",X"C7",X"0E",X"C3",X"FD",X"10",X"21",X"42",X"D2",X"C3",X"D5",X"10", + X"21",X"5A",X"BA",X"C3",X"D5",X"10",X"21",X"2A",X"5A",X"C3",X"D5",X"10",X"21",X"72",X"A2",X"C3", + X"D5",X"10",X"21",X"BA",X"EA",X"C3",X"D5",X"10",X"C3",X"90",X"11",X"C3",X"8A",X"11",X"C3",X"D2", + X"10",X"7C",X"CD",X"17",X"12",X"21",X"17",X"20",X"46",X"B8",X"DA",X"C7",X"0E",X"C3",X"EB",X"10", + X"21",X"D2",X"12",X"22",X"19",X"20",X"E1",X"78",X"FE",X"01",X"CA",X"E0",X"11",X"7D",X"CD",X"17", + X"12",X"21",X"1A",X"20",X"46",X"B8",X"DA",X"C7",X"0E",X"21",X"08",X"20",X"77",X"C3",X"EF",X"10", + X"7D",X"CD",X"0D",X"12",X"21",X"19",X"20",X"46",X"B8",X"D2",X"C7",X"0E",X"C3",X"D9",X"11",X"21", + X"BA",X"2A",X"C3",X"C3",X"11",X"21",X"A2",X"42",X"C3",X"C3",X"11",X"C3",X"F5",X"11",X"C3",X"C0", + X"11",X"C3",X"F5",X"11",X"C3",X"F5",X"11",X"C3",X"EF",X"11",X"C3",X"C0",X"11",X"21",X"0B",X"20", + X"46",X"3C",X"05",X"C2",X"11",X"12",X"C9",X"21",X"0B",X"20",X"46",X"3D",X"05",X"C2",X"1B",X"12", + X"C9",X"21",X"2F",X"20",X"CD",X"45",X"12",X"E1",X"7D",X"FE",X"88",X"DA",X"34",X"12",X"2A",X"2F", + X"20",X"C3",X"72",X"0E",X"FE",X"60",X"DA",X"3F",X"12",X"2A",X"31",X"20",X"C3",X"72",X"0E",X"2A", + X"33",X"20",X"C3",X"72",X"0E",X"06",X"06",X"1A",X"77",X"23",X"13",X"05",X"C2",X"47",X"12",X"C9", + X"2A",X"06",X"20",X"E5",X"21",X"04",X"20",X"46",X"21",X"4C",X"13",X"C3",X"90",X"0D",X"2A",X"06", + X"20",X"C3",X"72",X"0E",X"11",X"00",X"0C",X"C2",X"80",X"0D",X"11",X"F5",X"FF",X"C3",X"80",X"0D", + X"11",X"00",X"F5",X"C3",X"80",X"0D",X"21",X"03",X"20",X"36",X"00",X"21",X"04",X"20",X"46",X"23", + X"70",X"C3",X"50",X"12",X"21",X"D0",X"EA",X"C3",X"7F",X"0E",X"21",X"D0",X"8A",X"C3",X"7F",X"0E", + X"21",X"2F",X"20",X"CD",X"45",X"12",X"E1",X"7C",X"FE",X"80",X"D2",X"A3",X"12",X"2A",X"2F",X"20", + X"C3",X"72",X"0E",X"FE",X"C0",X"D2",X"AE",X"12",X"2A",X"31",X"20",X"C3",X"72",X"0E",X"2A",X"33", + X"20",X"C3",X"72",X"0E",X"23",X"47",X"8B",X"11",X"10",X"12",X"89",X"45",X"21",X"24",X"48",X"8C", + X"0D",X"0E",X"0F",X"8A",X"46",X"22",X"D0",X"2A",X"D0",X"8A",X"D0",X"EA",X"B8",X"42",X"B8",X"8A", + X"B8",X"D2",X"28",X"42",X"28",X"8A",X"28",X"D2",X"10",X"2A",X"10",X"8A",X"10",X"EA",X"D0",X"EA", + X"70",X"EA",X"10",X"EA",X"B8",X"D2",X"70",X"D2",X"28",X"D2",X"A0",X"BA",X"70",X"BA",X"40",X"BA", + X"A0",X"A2",X"70",X"A2",X"40",X"A2",X"A0",X"8A",X"70",X"8A",X"40",X"8A",X"A0",X"72",X"70",X"72", + X"40",X"72",X"A0",X"5A",X"70",X"5A",X"40",X"5A",X"B8",X"42",X"70",X"42",X"28",X"42",X"D0",X"2A", + X"70",X"2A",X"10",X"2A",X"A0",X"5A",X"A0",X"72",X"A0",X"8A",X"A0",X"A2",X"A0",X"BA",X"40",X"5A", + X"40",X"72",X"40",X"8A",X"40",X"A2",X"40",X"BA",X"6C",X"0E",X"D1",X"0F",X"D7",X"0F",X"DD",X"0F", + X"E3",X"0F",X"E9",X"0F",X"EF",X"0F",X"F5",X"0F",X"13",X"10",X"FB",X"0F",X"4C",X"10",X"0D",X"10", + X"07",X"10",X"A3",X"10",X"01",X"10",X"52",X"10",X"6D",X"10",X"88",X"10",X"D2",X"10",X"C0",X"11", + X"AE",X"11",X"0A",X"12",X"8A",X"11",X"EF",X"11",X"AB",X"11",X"07",X"12",X"90",X"11",X"F5",X"11", + X"A8",X"11",X"04",X"12",X"01",X"12",X"FE",X"11",X"FB",X"11",X"96",X"11",X"9C",X"11",X"A2",X"11", + X"2A",X"06",X"20",X"CD",X"A0",X"42",X"01",X"04",X"02",X"7B",X"C3",X"D2",X"08",X"2A",X"06",X"21", + X"C3",X"73",X"13",X"2A",X"06",X"22",X"C3",X"73",X"13",X"2A",X"0E",X"20",X"EB",X"2A",X"06",X"20", + X"CD",X"4A",X"0B",X"1E",X"FF",X"CD",X"70",X"13",X"2A",X"10",X"20",X"EB",X"2A",X"08",X"20",X"CD", + X"E3",X"0A",X"2A",X"10",X"20",X"22",X"0E",X"20",X"2A",X"08",X"20",X"22",X"06",X"20",X"1E",X"05", + X"C3",X"70",X"13",X"3A",X"92",X"22",X"A7",X"C4",X"EE",X"0E",X"DB",X"01",X"07",X"DA",X"04",X"14", + X"21",X"3E",X"23",X"7E",X"A7",X"CA",X"E4",X"13",X"2B",X"7E",X"FE",X"09",X"D2",X"FC",X"13",X"3C", + X"77",X"FE",X"09",X"D2",X"FC",X"13",X"3A",X"42",X"23",X"A7",X"C2",X"E0",X"13",X"CD",X"91",X"0C", + X"AF",X"32",X"3E",X"23",X"3A",X"43",X"23",X"A7",X"CA",X"98",X"14",X"3A",X"42",X"23",X"A7",X"C2", + X"98",X"14",X"3A",X"3D",X"23",X"A7",X"C2",X"09",X"14",X"C3",X"9B",X"40",X"3E",X"04",X"CD",X"7E", + X"06",X"C3",X"DD",X"13",X"3E",X"01",X"C3",X"E1",X"13",X"3A",X"16",X"20",X"A7",X"C2",X"CC",X"0E", + X"3E",X"01",X"32",X"16",X"20",X"31",X"00",X"24",X"FB",X"CD",X"BA",X"41",X"21",X"44",X"23",X"36", + X"00",X"CD",X"D5",X"04",X"CD",X"F7",X"45",X"21",X"13",X"30",X"11",X"56",X"47",X"06",X"04",X"CD", + X"22",X"08",X"3A",X"3D",X"23",X"3D",X"21",X"11",X"27",X"06",X"16",X"C2",X"75",X"14",X"11",X"F2", + X"1B",X"CD",X"22",X"08",X"DB",X"01",X"E6",X"40",X"CA",X"32",X"14",X"CD",X"48",X"05",X"06",X"99", + X"AF",X"32",X"3B",X"23",X"3A",X"3D",X"23",X"80",X"27",X"32",X"3D",X"23",X"3E",X"04",X"CD",X"89", + X"06",X"CD",X"91",X"0C",X"21",X"43",X"23",X"36",X"00",X"C3",X"E1",X"47",X"11",X"06",X"00",X"CD", + X"CA",X"0A",X"C3",X"4A",X"00",X"11",X"9D",X"1B",X"CD",X"22",X"08",X"DB",X"01",X"07",X"07",X"DA", + X"4B",X"14",X"07",X"DA",X"89",X"14",X"C3",X"32",X"14",X"CD",X"48",X"05",X"21",X"3B",X"23",X"36", + X"FF",X"06",X"98",X"3E",X"FF",X"C3",X"51",X"14",X"21",X"20",X"20",X"7E",X"A7",X"CA",X"A4",X"14", + X"35",X"C3",X"A9",X"14",X"3E",X"01",X"CD",X"A0",X"06",X"21",X"2C",X"20",X"7E",X"A7",X"C2",X"C8", + X"14",X"23",X"7E",X"A7",X"C2",X"FD",X"1A",X"23",X"7E",X"A7",X"C2",X"98",X"15",X"C3",X"CC",X"0E", + X"21",X"2C",X"20",X"36",X"00",X"C3",X"CC",X"0E",X"21",X"01",X"20",X"7E",X"A7",X"CA",X"D4",X"14", + X"35",X"C3",X"C0",X"14",X"CD",X"DC",X"0E",X"3A",X"09",X"20",X"DA",X"E8",X"14",X"FE",X"80",X"DA", + X"C0",X"14",X"CD",X"89",X"13",X"C3",X"00",X"11",X"FE",X"80",X"D2",X"C0",X"14",X"C3",X"E2",X"14", + X"21",X"3A",X"20",X"7E",X"A7",X"C2",X"DC",X"17",X"36",X"FF",X"3A",X"04",X"21",X"0F",X"0F",X"DA", + X"1B",X"15",X"21",X"06",X"21",X"7E",X"26",X"20",X"46",X"B8",X"D2",X"16",X"15",X"3E",X"01",X"21", + X"05",X"21",X"77",X"C3",X"6E",X"19",X"3E",X"05",X"C3",X"0F",X"15",X"21",X"07",X"21",X"7E",X"26", + X"20",X"46",X"B8",X"3E",X"07",X"DA",X"0F",X"15",X"3E",X"03",X"C3",X"0F",X"15",X"C2",X"33",X"15", + X"C3",X"BD",X"17",X"2A",X"06",X"21",X"CD",X"D4",X"1A",X"32",X"05",X"21",X"CD",X"E1",X"1A",X"C3", + X"D3",X"17",X"21",X"0C",X"20",X"C3",X"10",X"12",X"21",X"0C",X"20",X"C3",X"1A",X"12",X"21",X"0D", + X"20",X"C3",X"10",X"12",X"21",X"0D",X"20",X"C3",X"1A",X"12",X"21",X"14",X"21",X"36",X"07",X"C3", + X"ED",X"18",X"21",X"14",X"21",X"36",X"03",X"21",X"BA",X"2A",X"C3",X"F0",X"18",X"21",X"14",X"21", + X"36",X"07",X"C3",X"67",X"15",X"21",X"14",X"21",X"36",X"03",X"21",X"A2",X"42",X"C3",X"F0",X"18", + X"21",X"14",X"21",X"36",X"07",X"C3",X"7A",X"15",X"C3",X"80",X"15",X"C3",X"E8",X"18",X"C3",X"80", + X"15",X"2A",X"06",X"21",X"E5",X"C3",X"CF",X"18",X"21",X"46",X"20",X"7E",X"A7",X"C2",X"B6",X"15", + X"2B",X"2B",X"34",X"7E",X"FE",X"F0",X"DA",X"B6",X"15",X"36",X"00",X"23",X"34",X"7E",X"FE",X"0A", + X"DA",X"B6",X"15",X"23",X"36",X"FF",X"0E",X"03",X"3A",X"42",X"23",X"A7",X"CA",X"DC",X"15",X"CD", + X"D2",X"0E",X"E6",X"10",X"A7",X"CA",X"13",X"16",X"21",X"48",X"20",X"7E",X"FE",X"18",X"D2",X"DC", + X"15",X"3E",X"02",X"CD",X"95",X"06",X"21",X"47",X"20",X"34",X"0E",X"04",X"3A",X"46",X"20",X"A7", + X"CA",X"E5",X"15",X"0E",X"02",X"21",X"0B",X"20",X"71",X"21",X"1C",X"21",X"7E",X"A7",X"C2",X"F7", + X"15",X"23",X"7E",X"A7",X"CA",X"2A",X"16",X"CD",X"DC",X"0E",X"3A",X"09",X"22",X"DA",X"0B",X"16", + X"FE",X"80",X"DA",X"2A",X"16",X"CD",X"00",X"17",X"C3",X"2A",X"16",X"FE",X"80",X"D2",X"2A",X"16", + X"C3",X"05",X"16",X"3E",X"02",X"CD",X"A0",X"06",X"0E",X"03",X"C3",X"DC",X"15",X"21",X"2E",X"20", + X"36",X"FF",X"21",X"00",X"20",X"36",X"00",X"C3",X"CC",X"0E",X"21",X"2E",X"20",X"36",X"00",X"C3", + X"CC",X"0E",X"3A",X"17",X"21",X"A7",X"37",X"C8",X"2A",X"18",X"21",X"22",X"1E",X"20",X"2A",X"06", + X"20",X"C3",X"5C",X"11",X"21",X"1C",X"21",X"7E",X"A7",X"C2",X"A8",X"19",X"23",X"7E",X"A7",X"CA", + X"1D",X"16",X"CD",X"32",X"16",X"D2",X"BF",X"1C",X"2A",X"06",X"22",X"EB",X"2A",X"0F",X"22",X"19", + X"EB",X"21",X"10",X"22",X"7E",X"07",X"D2",X"9D",X"16",X"2B",X"7E",X"07",X"23",X"23",X"7A",X"D2", + X"73",X"16",X"7B",X"46",X"B8",X"DA",X"7B",X"16",X"C3",X"A9",X"16",X"CD",X"D6",X"16",X"CD",X"B0", + X"16",X"CD",X"DC",X"0E",X"3A",X"09",X"22",X"DA",X"95",X"16",X"FE",X"80",X"D2",X"1D",X"16",X"CD", + X"00",X"17",X"C3",X"1D",X"16",X"FE",X"80",X"DA",X"1D",X"16",X"C3",X"8F",X"16",X"A7",X"23",X"7A", + X"C2",X"A4",X"16",X"7B",X"46",X"B8",X"D2",X"7B",X"16",X"EB",X"22",X"08",X"22",X"C3",X"81",X"16", + X"21",X"10",X"22",X"7E",X"07",X"D2",X"C8",X"16",X"2B",X"7E",X"07",X"21",X"88",X"0A",X"D2",X"C4", + X"16",X"21",X"9E",X"0A",X"22",X"0D",X"22",X"C9",X"0F",X"A7",X"21",X"B4",X"0A",X"C2",X"C4",X"16", + X"21",X"72",X"0A",X"C3",X"C4",X"16",X"21",X"1F",X"21",X"34",X"7E",X"2B",X"BE",X"DA",X"E3",X"16", + X"23",X"36",X"00",X"21",X"20",X"21",X"01",X"05",X"00",X"3D",X"CA",X"F1",X"16",X"09",X"C3",X"E9", + X"16",X"11",X"0F",X"22",X"06",X"05",X"CD",X"41",X"0B",X"2A",X"12",X"22",X"22",X"08",X"22",X"C9", + X"2A",X"0B",X"22",X"EB",X"2A",X"06",X"22",X"CD",X"70",X"0B",X"2A",X"0D",X"22",X"EB",X"2A",X"08", + X"22",X"CD",X"70",X"0B",X"CD",X"DB",X"18",X"FE",X"04",X"DA",X"21",X"17",X"1E",X"FF",X"CD",X"83", + X"13",X"2A",X"0D",X"22",X"22",X"0B",X"22",X"2A",X"08",X"22",X"22",X"06",X"22",X"CD",X"DB",X"18", + X"FE",X"04",X"D8",X"1E",X"03",X"CD",X"83",X"13",X"C9",X"21",X"2C",X"20",X"36",X"00",X"23",X"36", + X"00",X"23",X"36",X"00",X"C9",X"CD",X"39",X"17",X"CD",X"32",X"16",X"D2",X"BF",X"1C",X"21",X"02", + X"21",X"7E",X"A7",X"C2",X"6B",X"19",X"2A",X"06",X"21",X"3A",X"04",X"21",X"CD",X"5F",X"07",X"FE", + X"A0",X"C2",X"6C",X"17",X"3E",X"07",X"32",X"04",X"21",X"C3",X"6F",X"17",X"32",X"0A",X"21",X"21", + X"15",X"21",X"7E",X"A7",X"CA",X"7B",X"17",X"35",X"C3",X"DC",X"17",X"21",X"14",X"21",X"36",X"00", + X"21",X"0A",X"20",X"7E",X"26",X"21",X"BE",X"CA",X"F0",X"14",X"47",X"AF",X"32",X"3A",X"20",X"78", + X"E6",X"1F",X"FE",X"0D",X"D2",X"A2",X"17",X"78",X"E6",X"E0",X"47",X"7E",X"E6",X"E0",X"B8",X"CA", + X"E9",X"17",X"2E",X"1B",X"36",X"00",X"2E",X"0A",X"7E",X"E6",X"1F",X"FE",X"10",X"D2",X"54",X"1B", + X"FE",X"0E",X"CA",X"22",X"18",X"3A",X"04",X"21",X"0F",X"0F",X"DA",X"33",X"15",X"2A",X"06",X"21", + X"44",X"EB",X"3A",X"07",X"20",X"B8",X"3E",X"07",X"D2",X"CD",X"17",X"3E",X"03",X"32",X"05",X"21", + X"CD",X"C5",X"1A",X"19",X"CD",X"27",X"0B",X"7E",X"A7",X"CA",X"5B",X"19",X"2A",X"06",X"21",X"E5", + X"3A",X"0A",X"21",X"21",X"79",X"1B",X"C3",X"93",X"0D",X"7E",X"26",X"20",X"46",X"90",X"FE",X"02", + X"CA",X"F8",X"17",X"FE",X"FE",X"C2",X"DC",X"17",X"21",X"0F",X"21",X"7E",X"A7",X"C2",X"DC",X"17", + X"36",X"FF",X"3A",X"05",X"20",X"32",X"05",X"21",X"C3",X"6B",X"19",X"3A",X"04",X"21",X"FE",X"03", + X"26",X"20",X"7E",X"C2",X"1D",X"18",X"E6",X"20",X"C0",X"2A",X"06",X"21",X"C9",X"E6",X"80",X"C3", + X"18",X"18",X"26",X"20",X"7E",X"E6",X"20",X"CA",X"31",X"18",X"2A",X"06",X"21",X"E5",X"C3",X"ED", + X"18",X"7E",X"FE",X"11",X"C2",X"B5",X"17",X"3A",X"06",X"21",X"FE",X"30",X"DA",X"B5",X"17",X"FE", + X"C0",X"D2",X"B5",X"17",X"C3",X"2A",X"18",X"21",X"14",X"21",X"36",X"05",X"21",X"2A",X"EA",X"22", + X"12",X"21",X"E1",X"3A",X"00",X"20",X"FE",X"03",X"D2",X"13",X"1A",X"3A",X"04",X"21",X"FE",X"03", + X"CA",X"76",X"18",X"7C",X"CD",X"42",X"15",X"21",X"13",X"21",X"46",X"B8",X"D2",X"82",X"18",X"21", + X"09",X"21",X"77",X"C3",X"87",X"19",X"7C",X"CD",X"48",X"15",X"21",X"12",X"21",X"46",X"B8",X"D2", + X"6F",X"18",X"3A",X"14",X"21",X"A7",X"C2",X"53",X"19",X"21",X"06",X"21",X"7E",X"26",X"20",X"46", + X"B8",X"3E",X"01",X"DA",X"53",X"19",X"3E",X"05",X"C3",X"53",X"19",X"21",X"14",X"21",X"36",X"01", + X"C3",X"4C",X"18",X"21",X"14",X"21",X"36",X"05",X"21",X"42",X"D2",X"C3",X"4F",X"18",X"21",X"14", + X"21",X"36",X"01",X"C3",X"A8",X"18",X"21",X"14",X"21",X"36",X"05",X"21",X"5A",X"BA",X"C3",X"4F", + X"18",X"21",X"14",X"21",X"36",X"01",X"C3",X"BB",X"18",X"21",X"2A",X"5A",X"C3",X"4F",X"18",X"21", + X"72",X"A2",X"C3",X"4F",X"18",X"21",X"BA",X"EA",X"C3",X"4F",X"18",X"CD",X"79",X"04",X"21",X"31", + X"23",X"DA",X"E6",X"18",X"2E",X"32",X"7E",X"C9",X"21",X"14",X"21",X"36",X"03",X"21",X"D2",X"12", + X"22",X"10",X"21",X"E1",X"3A",X"00",X"20",X"FE",X"03",X"D2",X"53",X"1A",X"3A",X"04",X"21",X"FE", + X"01",X"CA",X"30",X"19",X"7D",X"CD",X"48",X"15",X"21",X"11",X"21",X"46",X"B8",X"DA",X"3C",X"19", + X"21",X"08",X"21",X"77",X"CD",X"DC",X"0E",X"3A",X"09",X"21",X"DA",X"28",X"19",X"FE",X"80",X"D2", + X"98",X"19",X"CD",X"2A",X"1B",X"C3",X"98",X"19",X"FE",X"80",X"DA",X"98",X"19",X"C3",X"22",X"19", + X"7D",X"CD",X"42",X"15",X"21",X"10",X"21",X"46",X"B8",X"DA",X"10",X"19",X"21",X"07",X"21",X"3A", + X"14",X"21",X"A7",X"C2",X"53",X"19",X"7C",X"21",X"07",X"20",X"46",X"B8",X"3E",X"07",X"DA",X"53", + X"19",X"3E",X"03",X"32",X"05",X"21",X"21",X"14",X"21",X"36",X"00",X"2A",X"06",X"21",X"E5",X"3A", + X"0A",X"21",X"21",X"28",X"13",X"C3",X"93",X"0D",X"22",X"08",X"21",X"21",X"05",X"21",X"46",X"2B", + X"7E",X"57",X"B8",X"C2",X"82",X"19",X"2B",X"2B",X"36",X"00",X"21",X"15",X"21",X"36",X"06",X"C3", + X"98",X"19",X"70",X"2B",X"2B",X"36",X"FF",X"CD",X"DC",X"0E",X"3A",X"09",X"21",X"DA",X"A0",X"19", + X"FE",X"80",X"D2",X"98",X"19",X"CD",X"2A",X"1B",X"21",X"2D",X"20",X"36",X"FF",X"C3",X"CC",X"0E", + X"FE",X"80",X"DA",X"98",X"19",X"C3",X"95",X"19",X"CD",X"32",X"16",X"D2",X"BF",X"1C",X"3A",X"02", + X"22",X"A7",X"C2",X"A6",X"1A",X"2A",X"08",X"22",X"3A",X"04",X"22",X"CD",X"5F",X"07",X"32",X"0A", + X"22",X"21",X"01",X"22",X"7E",X"A7",X"CA",X"CD",X"19",X"35",X"C3",X"FA",X"19",X"21",X"14",X"21", + X"36",X"00",X"21",X"04",X"22",X"7E",X"0F",X"0F",X"DA",X"04",X"1A",X"2A",X"06",X"22",X"44",X"EB", + X"3A",X"07",X"20",X"B8",X"3E",X"07",X"D2",X"EB",X"19",X"3E",X"03",X"32",X"05",X"22",X"CD",X"C5", + X"1A",X"19",X"CD",X"27",X"0B",X"7E",X"A7",X"CA",X"99",X"1A",X"2A",X"06",X"22",X"E5",X"3A",X"0A", + X"22",X"C3",X"E3",X"17",X"2A",X"06",X"22",X"CD",X"D4",X"1A",X"32",X"05",X"22",X"CD",X"E1",X"1A", + X"C3",X"F1",X"19",X"3A",X"04",X"22",X"FE",X"03",X"CA",X"2E",X"1A",X"7C",X"CD",X"4E",X"15",X"21", + X"13",X"21",X"46",X"B8",X"D2",X"3A",X"1A",X"21",X"09",X"22",X"77",X"C3",X"81",X"16",X"7C",X"CD", + X"54",X"15",X"21",X"12",X"21",X"46",X"B8",X"D2",X"27",X"1A",X"3A",X"14",X"21",X"A7",X"C2",X"91", + X"1A",X"21",X"06",X"22",X"7E",X"26",X"20",X"46",X"B8",X"3E",X"01",X"DA",X"91",X"1A",X"3E",X"05", + X"C3",X"91",X"1A",X"3A",X"04",X"22",X"FE",X"01",X"CA",X"6E",X"1A",X"7D",X"CD",X"54",X"15",X"21", + X"11",X"21",X"46",X"B8",X"DA",X"7A",X"1A",X"21",X"08",X"22",X"77",X"C3",X"81",X"16",X"7D",X"CD", + X"4E",X"15",X"21",X"10",X"21",X"46",X"B8",X"DA",X"67",X"1A",X"21",X"07",X"22",X"3A",X"14",X"21", + X"A7",X"C2",X"91",X"1A",X"7C",X"21",X"07",X"20",X"46",X"B8",X"3E",X"07",X"DA",X"91",X"1A",X"3E", + X"03",X"32",X"05",X"22",X"21",X"14",X"21",X"36",X"00",X"2A",X"06",X"22",X"E5",X"3A",X"0A",X"22", + X"C3",X"62",X"19",X"22",X"08",X"22",X"21",X"05",X"22",X"46",X"2B",X"7E",X"57",X"B8",X"C2",X"BD", + X"1A",X"2B",X"2B",X"36",X"00",X"21",X"01",X"22",X"36",X"0A",X"C3",X"1D",X"16",X"70",X"2B",X"2B", + X"36",X"FF",X"C3",X"81",X"16",X"EB",X"11",X"08",X"05",X"19",X"FE",X"03",X"11",X"00",X"0C",X"C0", + X"11",X"00",X"F4",X"C9",X"45",X"EB",X"2A",X"06",X"20",X"7D",X"B8",X"3E",X"01",X"D0",X"3E",X"05", + X"C9",X"EB",X"11",X"08",X"05",X"19",X"FE",X"01",X"11",X"F4",X"FF",X"C0",X"11",X"0C",X"00",X"C9", + X"21",X"72",X"0A",X"3D",X"C8",X"11",X"16",X"00",X"19",X"3D",X"C3",X"F3",X"1A",X"21",X"01",X"21", + X"7E",X"A7",X"CA",X"0E",X"1B",X"35",X"21",X"2D",X"20",X"36",X"00",X"C3",X"CC",X"0E",X"CD",X"DC", + X"0E",X"3A",X"09",X"21",X"DA",X"22",X"1B",X"FE",X"80",X"DA",X"06",X"1B",X"CD",X"2A",X"1B",X"C3", + X"06",X"1B",X"FE",X"80",X"D2",X"06",X"1B",X"C3",X"1C",X"1B",X"2A",X"0B",X"21",X"EB",X"2A",X"06", + X"21",X"CD",X"70",X"0B",X"2A",X"0D",X"21",X"EB",X"2A",X"08",X"21",X"CD",X"70",X"0B",X"1E",X"FF", + X"CD",X"7D",X"13",X"2A",X"0D",X"21",X"22",X"0B",X"21",X"2A",X"08",X"21",X"22",X"06",X"21",X"1E", + X"03",X"C3",X"7D",X"13",X"0F",X"DA",X"91",X"15",X"0F",X"DA",X"B5",X"17",X"3A",X"04",X"21",X"FE", + X"03",X"21",X"0A",X"20",X"7E",X"C2",X"B5",X"17",X"E6",X"20",X"CA",X"B5",X"17",X"21",X"14",X"21", + X"36",X"05",X"2A",X"06",X"21",X"E5",X"C3",X"CF",X"18",X"47",X"18",X"E8",X"18",X"9B",X"18",X"5A", + X"15",X"A3",X"18",X"62",X"15",X"AE",X"18",X"6D",X"15",X"B6",X"18",X"75",X"15",X"C1",X"18",X"80", + X"15",X"88",X"15",X"8B",X"15",X"8E",X"15",X"C9",X"18",X"CF",X"18",X"D5",X"18",X"1B",X"21",X"1B", + X"0E",X"11",X"1B",X"22",X"1B",X"0F",X"0B",X"00",X"18",X"04",X"11",X"12",X"1B",X"01",X"14",X"13", + X"13",X"0E",X"0D",X"07",X"07",X"10",X"90",X"10",X"90",X"23",X"03",X"03",X"03",X"93",X"1C",X"93", + X"1C",X"40",X"00",X"E0",X"33",X"00",X"07",X"07",X"D0",X"90",X"D0",X"90",X"21",X"B4",X"0A",X"B4", + X"0A",X"03",X"00",X"80",X"BA",X"70",X"42",X"72",X"0A",X"70",X"42",X"72",X"0A",X"01",X"0E",X"0D", + X"14",X"12",X"1B",X"24",X"20",X"20",X"20",X"1D",X"26",X"1D",X"29",X"1D",X"2F",X"05",X"23",X"1D", + X"26",X"FF",X"1B",X"0E",X"0D",X"0B",X"18",X"1B",X"21",X"1B",X"0F",X"0B",X"00",X"18",X"04",X"11", + X"12",X"1B",X"01",X"14",X"13",X"13",X"0E",X"0D",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"78", + X"00",X"10",X"00",X"30",X"00",X"F8",X"00",X"F0",X"07",X"E0",X"3F",X"F0",X"07",X"F8",X"00",X"30", + X"00",X"10",X"00",X"78",X"00",X"00",X"10",X"10",X"08",X"08",X"05",X"CC",X"03",X"F8",X"07",X"F0", + X"03",X"A8",X"03",X"C0",X"01",X"80",X"09",X"40",X"07",X"00",X"02",X"00",X"01",X"00",X"01",X"00", + X"01",X"80",X"03",X"80",X"03",X"80",X"03",X"C0",X"07",X"C8",X"27",X"E8",X"2F",X"F8",X"3E",X"48", + X"24",X"04",X"00",X"08",X"04",X"50",X"08",X"E0",X"19",X"F0",X"0F",X"E0",X"07",X"E0",X"0A",X"C0", + X"01",X"C8",X"00",X"70",X"01",X"20",X"00",X"00",X"1E",X"00",X"08",X"00",X"0C",X"00",X"1F",X"E0", + X"0F",X"FC",X"07",X"E0",X"0F",X"00",X"1F",X"00",X"0C",X"00",X"08",X"00",X"1E",X"40",X"00",X"E0", + X"02",X"90",X"01",X"80",X"03",X"C0",X"15",X"C0",X"0F",X"E0",X"1F",X"C0",X"33",X"A0",X"10",X"10", + X"08",X"08",X"08",X"24",X"12",X"7C",X"1F",X"F4",X"17",X"E4",X"13",X"E0",X"03",X"C0",X"01",X"C0", + X"01",X"C0",X"01",X"80",X"00",X"80",X"00",X"80",X"00",X"00",X"04",X"80",X"E0",X"00",X"13",X"80", + X"03",X"50",X"07",X"E0",X"07",X"F0",X"0F",X"98",X"07",X"10",X"0A",X"20",X"10",X"00",X"20",X"21", + X"42",X"23",X"36",X"00",X"21",X"3D",X"20",X"36",X"FF",X"C3",X"CC",X"0E",X"12",X"02",X"0E",X"11", + X"04",X"1C",X"21",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B",X"12", + X"02",X"0E",X"11",X"04",X"1C",X"22",X"05",X"14",X"04",X"0B",X"02",X"11",X"04",X"03",X"08",X"13", + X"1B",X"30",X"01",X"C4",X"38",X"06",X"04",X"C7",X"14",X"06",X"04",X"D3",X"14",X"06",X"07",X"CA", + X"0E",X"06",X"07",X"D3",X"0E",X"06",X"16",X"CA",X"0E",X"06",X"16",X"D3",X"0E",X"06",X"19",X"C7", + X"14",X"06",X"19",X"D3",X"14",X"06",X"1C",X"C4",X"38",X"06",X"FF",X"02",X"C4",X"1A",X"06",X"05", + X"C7",X"09",X"06",X"10",X"C7",X"09",X"06",X"07",X"CA",X"07",X"06",X"10",X"CA",X"06",X"06",X"0A", + X"CD",X"0A",X"06",X"0A",X"D0",X"04",X"06",X"10",X"D0",X"04",X"06",X"0A",X"D3",X"04",X"06",X"10", + X"D3",X"04",X"06",X"0A",X"D6",X"0A",X"06",X"08",X"D9",X"06",X"06",X"10",X"D9",X"06",X"06",X"05", + X"DC",X"09",X"06",X"10",X"DC",X"09",X"06",X"02",X"DF",X"1A",X"06",X"FF",X"1F",X"24",X"44",X"24", + X"1F",X"7F",X"49",X"49",X"49",X"36",X"3E",X"41",X"41",X"41",X"22",X"7F",X"41",X"41",X"41",X"3E", + X"7F",X"49",X"49",X"49",X"41",X"7F",X"48",X"48",X"48",X"40",X"3E",X"41",X"41",X"45",X"47",X"7F", + X"08",X"08",X"08",X"7F",X"00",X"41",X"7F",X"41",X"00",X"02",X"01",X"01",X"01",X"7E",X"7F",X"08", + X"14",X"22",X"41",X"7F",X"01",X"01",X"01",X"01",X"7F",X"20",X"18",X"20",X"7F",X"7F",X"10",X"08", + X"04",X"7F",X"3E",X"41",X"41",X"41",X"3E",X"7F",X"48",X"48",X"48",X"30",X"3E",X"41",X"45",X"42", + X"3D",X"7F",X"48",X"4C",X"4A",X"31",X"32",X"49",X"49",X"49",X"26",X"40",X"40",X"7F",X"40",X"40", + X"7E",X"01",X"01",X"01",X"7E",X"7C",X"02",X"01",X"02",X"7C",X"7F",X"02",X"0C",X"02",X"7F",X"63", + X"14",X"08",X"14",X"63",X"60",X"10",X"0F",X"10",X"60",X"43",X"45",X"49",X"51",X"61",X"00",X"00", + X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"22",X"14",X"7F", + X"14",X"22",X"08",X"14",X"22",X"41",X"00",X"00",X"41",X"22",X"14",X"08",X"3E",X"45",X"49",X"51", + X"3E",X"00",X"21",X"7F",X"01",X"00",X"23",X"45",X"49",X"49",X"31",X"42",X"41",X"49",X"59",X"66", + X"0C",X"14",X"24",X"7F",X"04",X"72",X"51",X"51",X"51",X"4E",X"1E",X"29",X"49",X"49",X"46",X"40", + X"47",X"48",X"50",X"60",X"36",X"49",X"49",X"49",X"36",X"31",X"49",X"49",X"4A",X"3C",X"14",X"14", + X"14",X"14",X"14",X"01",X"02",X"04",X"08",X"10",X"00",X"00",X"00",X"00",X"00",X"18",X"18",X"18", + X"18",X"18",X"00",X"00",X"18",X"18",X"00",X"00",X"1F",X"14",X"16",X"09",X"00",X"1E",X"01",X"01", + X"1E",X"00",X"1F",X"15",X"15",X"0A",X"00",X"00",X"1F",X"15",X"15",X"11",X"00",X"1F",X"08",X"04", + X"1F",X"00",X"1F",X"11",X"11",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"40",X"0E",X"60", + X"0C",X"10",X"10",X"00",X"03",X"80",X"07",X"00",X"0F",X"00",X"04",X"00",X"00",X"00",X"20",X"00", + X"10",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"60",X"00", + X"0A",X"00",X"1C",X"00",X"08",X"80",X"01",X"00",X"03",X"40",X"0B",X"80",X"5F",X"00",X"20",X"00", + X"52",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"00",X"1F",X"00",X"16",X"00",X"A0",X"00",X"85", + X"01",X"12",X"01",X"31",X"00",X"70",X"00",X"42",X"04",X"A4",X"08",X"0E",X"0C",X"0F",X"10",X"18", + X"00",X"00",X"08",X"00",X"38",X"00",X"44",X"00",X"01",X"02",X"49",X"01",X"D0",X"01",X"54",X"02", + X"08",X"00",X"84",X"00",X"60",X"00",X"31",X"00",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"18",X"80",X"00",X"40",X"C1",X"21",X"F2",X"03",X"18",X"0A",X"C8",X"18",X"02",X"3B",X"F4",X"46", + X"24",X"10",X"4C",X"1B",X"40",X"49",X"10",X"00",X"B8",X"46",X"80",X"13",X"01",X"10",X"42",X"20", + X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"90",X"60",X"40",X"08",X"41",X"10", + X"00",X"10",X"01",X"00",X"00",X"62",X"0D",X"00",X"08",X"F4",X"F8",X"11",X"00",X"38",X"B2",X"02", + X"60",X"AB",X"C7",X"07",X"40",X"DB",X"DB",X"37",X"00",X"FD",X"3F",X"03",X"80",X"3D",X"FE",X"02", + X"C1",X"8B",X"7F",X"07",X"E0",X"E7",X"F7",X"0F",X"E0",X"E9",X"FD",X"0F",X"E0",X"EC",X"AE",X"09", + X"C0",X"DC",X"76",X"0D",X"80",X"8C",X"B9",X"05",X"80",X"2C",X"DF",X"03",X"C0",X"78",X"D3",X"03", + X"20",X"59",X"EE",X"03",X"90",X"F9",X"FF",X"01",X"80",X"F1",X"C7",X"04",X"84",X"7B",X"17",X"10", + X"80",X"F7",X"FB",X"02",X"00",X"2F",X"39",X"04",X"00",X"1E",X"1C",X"00",X"00",X"8C",X"01",X"10", + X"00",X"80",X"00",X"00",X"00",X"80",X"00",X"41",X"10",X"00",X"04",X"C2",X"08",X"80",X"0C",X"00", + X"1D",X"13",X"00",X"08",X"13",X"0E",X"1B",X"02",X"0E",X"11",X"0F",X"0E",X"11",X"00",X"13",X"08", + X"0E",X"0D",X"1D",X"08",X"0D",X"12",X"04",X"11",X"13",X"1B",X"02",X"0E",X"08",X"0D",X"00",X"01", + X"FF",X"00",X"00",X"67",X"1E",X"10",X"00",X"01",X"02",X"00",X"00",X"83",X"1E",X"10",X"00",X"FF", + X"01",X"00",X"00",X"A1",X"1E",X"10",X"00",X"FF",X"FE",X"00",X"00",X"C0",X"1E",X"10",X"33",X"01", + X"31",X"01",X"2D",X"01",X"2B",X"01",X"28",X"01",X"26",X"01",X"24",X"01",X"22",X"01",X"20",X"01", + X"1E",X"01",X"1D",X"01",X"1B",X"01",X"19",X"01",X"00",X"13",X"08",X"0B",X"13",X"CD",X"DB",X"18", + X"FE",X"03",X"21",X"D0",X"90",X"C2",X"AD",X"0C",X"2A",X"39",X"23",X"C3",X"AD",X"0C",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"3A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom2.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom2.vhd new file mode 100644 index 00000000..5447e323 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/rom2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CD",X"9A",X"41",X"CD",X"AA",X"0C",X"21",X"44",X"23",X"36",X"FF",X"D3",X"06",X"21",X"44",X"20", + X"7E",X"FE",X"1C",X"DA",X"2C",X"40",X"36",X"00",X"2A",X"70",X"20",X"7E",X"32",X"05",X"20",X"23", + X"7D",X"FE",X"81",X"DA",X"29",X"40",X"21",X"72",X"20",X"22",X"70",X"20",X"CD",X"37",X"02",X"3A", + X"3D",X"20",X"A7",X"C2",X"A5",X"40",X"21",X"44",X"23",X"7E",X"A7",X"C2",X"0B",X"40",X"CD",X"BA", + X"41",X"CD",X"08",X"46",X"CD",X"61",X"42",X"CD",X"F2",X"41",X"CD",X"34",X"0C",X"21",X"14",X"2C", + X"11",X"2C",X"47",X"06",X"0C",X"CD",X"22",X"08",X"21",X"0A",X"2F",X"11",X"06",X"42",X"01",X"02", + X"2C",X"CD",X"66",X"41",X"CD",X"9A",X"41",X"21",X"07",X"28",X"11",X"80",X"1F",X"06",X"13",X"CD", + X"22",X"08",X"CD",X"AA",X"41",X"26",X"2F",X"06",X"A6",X"2E",X"EB",X"04",X"7E",X"B8",X"C2",X"3C", + X"17",X"CD",X"08",X"46",X"CD",X"61",X"42",X"CD",X"34",X"0C",X"21",X"11",X"2C",X"11",X"93",X"1F", + X"06",X"0B",X"CD",X"22",X"08",X"CD",X"9A",X"41",X"C3",X"41",X"00",X"3A",X"44",X"23",X"A7",X"CA", + X"CC",X"0E",X"C3",X"98",X"14",X"21",X"44",X"23",X"36",X"00",X"CD",X"B0",X"40",X"C3",X"1F",X"40", + X"F3",X"11",X"70",X"22",X"21",X"9E",X"1F",X"06",X"23",X"CD",X"41",X"0B",X"3E",X"01",X"32",X"70", + X"22",X"32",X"78",X"22",X"32",X"80",X"22",X"32",X"88",X"22",X"32",X"90",X"22",X"2A",X"06",X"20", + X"E5",X"22",X"8B",X"22",X"01",X"00",X"10",X"09",X"22",X"83",X"22",X"E1",X"11",X"20",X"00",X"19", + X"22",X"73",X"22",X"09",X"22",X"7B",X"22",X"FB",X"21",X"00",X"C4",X"01",X"38",X"20",X"3E",X"01", + X"CD",X"D2",X"08",X"2A",X"06",X"20",X"CD",X"A0",X"42",X"01",X"08",X"04",X"3E",X"07",X"CD",X"D0", + X"08",X"21",X"92",X"22",X"36",X"01",X"2A",X"06",X"20",X"E5",X"7C",X"C6",X"08",X"67",X"7D",X"C6", + X"08",X"6F",X"CD",X"27",X"0B",X"11",X"E0",X"1E",X"01",X"02",X"10",X"CD",X"66",X"41",X"CD",X"AF", + X"42",X"E1",X"7C",X"FE",X"D8",X"D2",X"2B",X"41",X"C3",X"2D",X"41",X"26",X"E4",X"CD",X"27",X"0B", + X"11",X"00",X"1F",X"01",X"04",X"20",X"CD",X"66",X"41",X"3A",X"90",X"22",X"A7",X"D3",X"06",X"C2", + X"06",X"41",X"AF",X"D3",X"03",X"21",X"2E",X"23",X"36",X"00",X"C3",X"AA",X"41",X"5E",X"23",X"56", + X"23",X"7E",X"23",X"4E",X"23",X"46",X"61",X"6F",X"EB",X"C9",X"4E",X"23",X"46",X"23",X"79",X"86", + X"77",X"23",X"78",X"86",X"77",X"C9",X"C5",X"E5",X"1A",X"77",X"23",X"13",X"0D",X"C2",X"68",X"41", + X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"66",X"41",X"C9",X"C5",X"D5",X"1A",X"CD",X"94", + X"08",X"CD",X"AB",X"08",X"D1",X"C1",X"13",X"3E",X"07",X"32",X"91",X"22",X"3A",X"91",X"22",X"D3", + X"06",X"3D",X"C2",X"8C",X"41",X"05",X"C2",X"7B",X"41",X"C9",X"3E",X"50",X"FB",X"32",X"91",X"22", + X"3A",X"91",X"22",X"A7",X"D3",X"06",X"C2",X"A0",X"41",X"C9",X"3E",X"80",X"C3",X"9C",X"41",X"CD", + X"A0",X"42",X"01",X"04",X"02",X"3E",X"05",X"C3",X"D2",X"08",X"11",X"70",X"22",X"21",X"9E",X"1F", + X"06",X"23",X"C3",X"41",X"0B",X"11",X"80",X"00",X"71",X"19",X"05",X"C2",X"C8",X"41",X"C9",X"CD", + X"4D",X"41",X"48",X"06",X"02",X"C3",X"B4",X"42",X"CD",X"27",X"0B",X"01",X"03",X"18",X"AF",X"C5", + X"E5",X"77",X"23",X"0D",X"C2",X"E1",X"41",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"DF", + X"41",X"C9",X"21",X"07",X"C4",X"01",X"06",X"38",X"CD",X"C5",X"41",X"21",X"0A",X"CF",X"01",X"0C", + X"02",X"3E",X"04",X"C3",X"D2",X"08",X"00",X"E0",X"00",X"D8",X"00",X"C6",X"80",X"C1",X"60",X"C0", + X"10",X"A4",X"10",X"A4",X"D0",X"A7",X"10",X"A4",X"08",X"94",X"08",X"90",X"08",X"90",X"08",X"90", + X"F4",X"88",X"44",X"89",X"44",X"89",X"F4",X"88",X"02",X"84",X"02",X"84",X"02",X"84",X"02",X"84", + X"01",X"82",X"7D",X"82",X"01",X"82",X"02",X"84",X"02",X"84",X"02",X"84",X"02",X"85",X"04",X"89", + X"F4",X"89",X"04",X"89",X"04",X"89",X"08",X"90",X"08",X"90",X"08",X"90",X"88",X"93",X"50",X"A4", + X"50",X"A4",X"90",X"A3",X"10",X"A0",X"60",X"C0",X"80",X"C1",X"00",X"C6",X"00",X"D8",X"00",X"E0", + X"00",X"21",X"11",X"CC",X"01",X"06",X"18",X"CD",X"C5",X"41",X"21",X"00",X"C5",X"01",X"05",X"0A", + X"CD",X"C5",X"41",X"21",X"00",X"CA",X"01",X"04",X"08",X"CD",X"C5",X"41",X"21",X"1E",X"C4",X"01", + X"04",X"12",X"CD",X"C5",X"41",X"21",X"1E",X"CD",X"01",X"05",X"14",X"CD",X"C5",X"41",X"21",X"1E", + X"D7",X"01",X"03",X"12",X"CD",X"C5",X"41",X"21",X"00",X"CE",X"01",X"01",X"0C",X"C3",X"C5",X"41", + X"7D",X"E6",X"07",X"D3",X"02",X"CD",X"27",X"0B",X"C5",X"01",X"00",X"A0",X"09",X"C1",X"C9",X"3E", + X"20",X"C3",X"95",X"06",X"7D",X"E6",X"07",X"D3",X"02",X"CD",X"27",X"0B",X"C5",X"E5",X"1A",X"D3", + X"04",X"DB",X"03",X"77",X"23",X"13",X"05",X"C2",X"BE",X"42",X"AF",X"D3",X"04",X"DB",X"03",X"77", + X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"BC",X"42",X"C9",X"06",X"06",X"C5",X"21",X"BE", + X"1F",X"CD",X"EE",X"42",X"C1",X"05",X"C2",X"DD",X"42",X"3E",X"01",X"C3",X"89",X"06",X"7E",X"A7", + X"C8",X"23",X"4E",X"47",X"07",X"DA",X"2F",X"43",X"E5",X"CD",X"05",X"43",X"E1",X"0D",X"C2",X"F8", + X"42",X"23",X"C3",X"EE",X"42",X"21",X"F0",X"07",X"50",X"E5",X"D5",X"3E",X"01",X"CD",X"7E",X"06", + X"D1",X"E1",X"2B",X"7C",X"A7",X"C8",X"15",X"C2",X"12",X"43",X"50",X"E5",X"D5",X"3E",X"01",X"CD", + X"89",X"06",X"D1",X"E1",X"2B",X"7C",X"A7",X"C8",X"15",X"C2",X"24",X"43",X"C3",X"08",X"43",X"E5", + X"21",X"FF",X"30",X"2B",X"7C",X"A7",X"C2",X"33",X"43",X"0D",X"C2",X"30",X"43",X"E1",X"23",X"C3", + X"EE",X"42",X"CD",X"AC",X"06",X"C3",X"58",X"43",X"CD",X"03",X"46",X"CA",X"42",X"43",X"3A",X"0F", + X"23",X"A7",X"C2",X"42",X"43",X"CD",X"C0",X"06",X"CD",X"08",X"46",X"CD",X"34",X"0C",X"CD",X"92", + X"45",X"21",X"96",X"46",X"11",X"40",X"22",X"06",X"19",X"CD",X"41",X"0B",X"21",X"17",X"25",X"11", + X"51",X"46",X"06",X"1B",X"CD",X"22",X"08",X"21",X"12",X"27",X"11",X"5C",X"1D",X"CD",X"F1",X"43", + X"21",X"10",X"27",X"CD",X"F1",X"43",X"21",X"0E",X"27",X"0E",X"05",X"CD",X"F3",X"43",X"21",X"0E", + X"33",X"11",X"47",X"1E",X"01",X"01",X"10",X"CD",X"66",X"41",X"21",X"0E",X"36",X"11",X"57",X"1E", + X"01",X"01",X"10",X"CD",X"66",X"41",X"11",X"6C",X"46",X"21",X"06",X"2A",X"06",X"10",X"CD",X"22", + X"08",X"06",X"0A",X"CD",X"81",X"04",X"3A",X"51",X"22",X"A7",X"CA",X"7F",X"45",X"3A",X"4F",X"22", + X"FE",X"20",X"D2",X"7F",X"45",X"CD",X"04",X"44",X"CD",X"F2",X"0D",X"E6",X"0A",X"FE",X"08",X"CC", + X"30",X"44",X"FE",X"02",X"CC",X"86",X"44",X"3A",X"56",X"22",X"A7",X"C2",X"7F",X"45",X"3A",X"41", + X"22",X"A7",X"C2",X"D0",X"44",X"01",X"50",X"02",X"CD",X"81",X"04",X"CD",X"0F",X"44",X"C3",X"B1", + X"43",X"0E",X"0B",X"C5",X"01",X"01",X"05",X"CD",X"66",X"41",X"01",X"60",X"01",X"09",X"C1",X"0D", + X"C2",X"F3",X"43",X"C9",X"2A",X"52",X"22",X"3E",X"2D",X"CD",X"94",X"08",X"C3",X"AB",X"08",X"2A", + X"52",X"22",X"3E",X"1B",X"CD",X"94",X"08",X"C3",X"AB",X"08",X"01",X"50",X"06",X"CD",X"F2",X"0D", + X"E6",X"0A",X"CA",X"2E",X"44",X"0D",X"C2",X"1D",X"44",X"05",X"C2",X"1D",X"44",X"C9",X"E1",X"C9", + X"CD",X"1A",X"44",X"CD",X"0F",X"44",X"2A",X"52",X"22",X"7D",X"FE",X"11",X"CA",X"61",X"44",X"FE", + X"0F",X"CA",X"6A",X"44",X"7C",X"FE",X"33",X"CA",X"75",X"44",X"24",X"24",X"7C",X"FE",X"35",X"D2", + X"55",X"44",X"C3",X"5B",X"44",X"CD",X"0F",X"44",X"21",X"0D",X"36",X"22",X"52",X"22",X"C3",X"04", + X"44",X"7C",X"FE",X"3B",X"D2",X"7A",X"44",X"C3",X"70",X"44",X"7C",X"FE",X"3B",X"D2",X"80",X"44", + X"24",X"24",X"C3",X"5B",X"44",X"26",X"34",X"C3",X"4A",X"44",X"21",X"0F",X"27",X"C3",X"5B",X"44", + X"21",X"0D",X"27",X"C3",X"5B",X"44",X"CD",X"1A",X"44",X"CD",X"0F",X"44",X"2A",X"52",X"22",X"7D", + X"FE",X"11",X"CA",X"AA",X"44",X"FE",X"0F",X"CA",X"BB",X"44",X"7C",X"FE",X"28",X"DA",X"C4",X"44", + X"FE",X"34",X"C2",X"B0",X"44",X"26",X"33",X"C3",X"B0",X"44",X"7C",X"FE",X"28",X"DA",X"B5",X"44", + X"25",X"25",X"C3",X"5B",X"44",X"21",X"11",X"27",X"C3",X"5B",X"44",X"7C",X"FE",X"28",X"DA",X"CA", + X"44",X"C3",X"B0",X"44",X"21",X"0F",X"3B",X"C3",X"5B",X"44",X"21",X"11",X"3B",X"C3",X"5B",X"44", + X"01",X"FF",X"20",X"CD",X"81",X"04",X"3A",X"50",X"22",X"FE",X"0A",X"D2",X"64",X"45",X"3A",X"52", + X"22",X"FE",X"11",X"CA",X"FE",X"44",X"FE",X"0F",X"CA",X"04",X"45",X"3A",X"53",X"22",X"FE",X"32", + X"D2",X"0C",X"45",X"CD",X"3F",X"45",X"C6",X"16",X"CD",X"46",X"45",X"C3",X"B1",X"43",X"CD",X"3F", + X"45",X"C3",X"46",X"45",X"CD",X"3F",X"45",X"C6",X"0B",X"C3",X"46",X"45",X"FE",X"35",X"D2",X"7F", + X"45",X"3A",X"50",X"22",X"A7",X"CA",X"35",X"45",X"2A",X"54",X"22",X"25",X"22",X"54",X"22",X"3E", + X"1B",X"CD",X"94",X"08",X"CD",X"AB",X"08",X"21",X"50",X"22",X"35",X"21",X"44",X"22",X"3A",X"50", + X"22",X"85",X"6F",X"36",X"1B",X"AF",X"32",X"40",X"22",X"32",X"41",X"22",X"C3",X"B1",X"43",X"3A", + X"53",X"22",X"D6",X"27",X"0F",X"C9",X"21",X"44",X"22",X"F5",X"3A",X"50",X"22",X"85",X"6F",X"F1", + X"77",X"2A",X"54",X"22",X"CD",X"94",X"08",X"CD",X"AB",X"08",X"22",X"54",X"22",X"21",X"50",X"22", + X"34",X"C3",X"35",X"45",X"3A",X"52",X"22",X"FE",X"0D",X"C2",X"7F",X"45",X"3A",X"53",X"22",X"FE", + X"32",X"D2",X"77",X"45",X"C3",X"7F",X"45",X"FE",X"36",X"D2",X"7F",X"45",X"C3",X"11",X"45",X"AF", + X"32",X"51",X"22",X"32",X"0F",X"23",X"32",X"0E",X"23",X"CD",X"A8",X"45",X"CD",X"9B",X"45",X"C3", + X"4C",X"04",X"01",X"01",X"50",X"21",X"1E",X"2D",X"C3",X"DE",X"41",X"2A",X"42",X"22",X"11",X"44", + X"22",X"3A",X"50",X"22",X"47",X"C3",X"22",X"08",X"3A",X"50",X"22",X"A7",X"CA",X"BF",X"45",X"47", + X"3E",X"0A",X"90",X"37",X"3F",X"1F",X"C6",X"2D",X"67",X"2E",X"1E",X"22",X"42",X"22",X"C9",X"21", + X"1E",X"2D",X"22",X"42",X"22",X"3E",X"0A",X"32",X"50",X"22",X"C9",X"21",X"0E",X"07",X"11",X"2A", + X"23",X"06",X"03",X"C3",X"41",X"0B",X"AF",X"D3",X"03",X"D3",X"05",X"D3",X"06",X"21",X"2D",X"23", + X"77",X"CD",X"03",X"46",X"C0",X"C3",X"B2",X"06",X"CD",X"BA",X"41",X"CD",X"08",X"46",X"CD",X"F8", + X"04",X"CD",X"B4",X"0B",X"C3",X"FA",X"45",X"CD",X"CA",X"08",X"CD",X"34",X"0C",X"CD",X"86",X"0C", + X"C3",X"91",X"0C",X"DB",X"02",X"E6",X"40",X"C9",X"CD",X"CA",X"08",X"C3",X"D5",X"04",X"21",X"47", + X"23",X"34",X"7E",X"FE",X"04",X"D2",X"3F",X"46",X"FE",X"02",X"21",X"47",X"46",X"DA",X"2B",X"46", + X"FE",X"03",X"21",X"C8",X"1B",X"D2",X"2B",X"46",X"21",X"4C",X"46",X"11",X"06",X"21",X"06",X"05", + X"CD",X"41",X"0B",X"2A",X"06",X"21",X"22",X"39",X"23",X"CD",X"DB",X"18",X"C3",X"58",X"00",X"36", + X"00",X"21",X"47",X"46",X"C3",X"2B",X"46",X"40",X"58",X"40",X"58",X"8B",X"B8",X"98",X"B8",X"98", + X"45",X"07",X"08",X"1C",X"12",X"02",X"0E",X"11",X"04",X"11",X"1B",X"0D",X"00",X"0C",X"04",X"1B", + X"11",X"04",X"06",X"08",X"12",X"13",X"11",X"00",X"13",X"08",X"0E",X"0D",X"0D",X"00",X"0C",X"04", + X"1B",X"1B",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"00",X"00",X"00",X"00", + X"1B",X"1B",X"13",X"00",X"08",X"13",X"0E",X"1B",X"1B",X"1B",X"00",X"00",X"00",X"00",X"11",X"27", + X"07",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"1B",X"1B",X"1B",X"1B",X"1B", + X"1B",X"1B",X"1B",X"1B",X"00",X"00",X"00",X"FF",X"11",X"27",X"07",X"30",X"00",X"00",X"00",X"00", + X"03",X"00",X"72",X"28",X"D2",X"00",X"FD",X"BA",X"70",X"D2",X"FD",X"FF",X"42",X"70",X"BA",X"00", + X"FD",X"5A",X"40",X"BA",X"03",X"00",X"A2",X"40",X"5A",X"00",X"03",X"8A",X"A0",X"5A",X"03",X"00", + X"BA",X"A0",X"8A",X"00",X"FD",X"42",X"B8",X"8A",X"FD",X"FF",X"32",X"B8",X"42",X"00",X"03",X"8A", + X"28",X"42",X"03",X"00",X"A2",X"28",X"8A",X"00",X"03",X"BA",X"A0",X"8A",X"FD",X"FF",X"4A",X"A0", + X"BA",X"00",X"FD",X"8A",X"40",X"BA",X"FD",X"FF",X"2A",X"40",X"8A",X"00",X"03",X"D2",X"28",X"8A", + X"28",X"D2",X"28",X"D2",X"46",X"72",X"0A",X"72",X"0A",X"03",X"00",X"72",X"28",X"D2",X"00",X"72", + X"0A",X"28",X"D2",X"72",X"0A",X"02",X"0E",X"0D",X"06",X"11",X"00",X"13",X"14",X"0B",X"00",X"13", + X"08",X"0E",X"0D",X"12",X"00",X"08",X"08",X"08",X"7F",X"08",X"08",X"08",X"12",X"0F",X"00",X"02", + X"04",X"1B",X"02",X"07",X"00",X"12",X"04",X"11",X"2E",X"03",X"0E",X"13",X"2A",X"1B",X"1B",X"1B", + X"0F",X"0E",X"08",X"0D",X"13",X"06",X"0E",X"0E",X"03",X"1B",X"0B",X"14",X"02",X"0A",X"0F",X"03", + X"1E",X"FE",X"1E",X"03",X"0F",X"00",X"0F",X"14",X"12",X"07",X"C3",X"41",X"00",X"CD",X"DB",X"18", + X"FE",X"07",X"3A",X"1D",X"20",X"DA",X"16",X"01",X"FE",X"4C",X"C3",X"18",X"01",X"CD",X"DB",X"18", + X"FE",X"07",X"21",X"04",X"04",X"DA",X"35",X"01",X"21",X"05",X"05",X"C3",X"35",X"01",X"7E",X"A7", + X"C2",X"FA",X"19",X"36",X"FF",X"3A",X"04",X"20",X"21",X"05",X"22",X"77",X"C3",X"A6",X"1A",X"CD", + X"9C",X"47",X"0F",X"21",X"0D",X"2B",X"CD",X"9C",X"47",X"C3",X"60",X"47",X"D2",X"AC",X"47",X"F5", + X"E5",X"3E",X"1D",X"CD",X"94",X"08",X"E1",X"CD",X"AB",X"08",X"F1",X"C9",X"01",X"08",X"00",X"C5", + X"70",X"11",X"20",X"00",X"19",X"C1",X"0D",X"C2",X"AF",X"47",X"C9",X"00",X"DB",X"00",X"07",X"07", + X"DA",X"D4",X"47",X"07",X"21",X"03",X"03",X"D2",X"CD",X"47",X"21",X"05",X"05",X"22",X"31",X"23", + X"C9",X"00",X"00",X"00",X"07",X"21",X"04",X"04",X"D2",X"CD",X"47",X"21",X"06",X"06",X"C3",X"CD", + X"47",X"DB",X"02",X"E6",X"08",X"CA",X"F4",X"47",X"21",X"04",X"23",X"36",X"90",X"2E",X"07",X"36", + X"90",X"C3",X"4A",X"00",X"21",X"03",X"23",X"C3",X"6C",X"14",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/snd.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/snd.vhd new file mode 100644 index 00000000..93cea934 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/roms/snd.vhd @@ -0,0 +1,86 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity snd is +port ( + clk : in std_logic; + addr : in std_logic_vector(9 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of snd is + type rom is array(0 to 1023) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C", + X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C", + X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C", + X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C", + X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2", + X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"2",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3", + X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3",X"3"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/spram.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/spram.vhd new file mode 100644 index 00000000..d8043481 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/sprom.vhd b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/sprom.vhd new file mode 100644 index 00000000..a81ac959 --- /dev/null +++ b/Arcade_MiST/Midway-Taito 8080 Hardware/Space Chaser_MiST/rtl/sprom.vhd @@ -0,0 +1,82 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END sprom; + + +ARCHITECTURE SYN OF sprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN;