diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/README.txt b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/README.txt new file mode 100644 index 00000000..d0fbc83b --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/README.txt @@ -0,0 +1,126 @@ +--------------------------------------------------------------------------------- +-- DE10_lite Top level for Sky Skipper by Dar (darfpga@aol.fr) (26/12/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (26/12/2019) +-- +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Use popeye_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +-- +-- Main features : +-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) +-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection) +-- +-- Video : VGA 31kHz/60Hz progressive and TV 15kHz interlaced +-- Cocktail mode : NO +-- Sound : OK +-- +-- For hardware schematic see my other project : NES +-- +-- Uses 1 pll 40MHz from 50MHz to make 20MHz and 8Mhz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F1 : Add coin +-- F2 : Start 1 player +-- F3 : Start 2 players + +-- F7 : Service mode +-- F8 : 15kHz interlaced / 31 kHz progressive + +-- SPACE : punch + +-- RIGHT arrow : move right +-- LEFT arrow : move left +-- UP arrow : up stairs +-- DOWN arrow : down stairs +-- +-- Other details : see popeye.vhd +-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite +--------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +-- Popeye by Dar (darfpga@aol.fr) (26/12/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (26/12/2019) +-- +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : VGA 31kHz/60Hz progressive and TV 15kHz interlaced +-- Coctail mode : NO +-- Sound : OK + +-- Use with MAME roms from popeye.zip & popeyeu.zip +-- +-- Use make_popeye_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Popeye Hardware caracteristics : TODO +-- +--------------------------------------------------------------------------------- +-- Schematics remarks : +-- +-- Display is 512x448 pixels (video 640 pixels x 256 interlaced lines @ 10.08MHz ) + +-- 640/10.08e6 = 63.49us per line (15.750KHz) +-- 63.49*256 = 16.254ms per frame (61.52Hz) +-- +--------------------------------------------------------------------------------- ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Mon Dec 30 10:06:20 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; +; Revision Name ; popeye_de10_lite ; +; Top-level Entity Name ; popeye_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 3,354 / 49,760 ( 7 % ) ; +; Total combinational functions ; 3,247 / 49,760 ( 7 % ) ; +; Dedicated logic registers ; 865 / 49,760 ( 2 % ) ; +; Total registers ; 865 ; +; Total pins ; 121 / 360 ( 34 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 613,888 / 1,677,312 ( 37 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM new file mode 100644 index 00000000..cdb95838 Binary files /dev/null and b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/Release/SKYSKIP.ROM differ diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qpf b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qpf new file mode 100644 index 00000000..bfbd5ab3 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 00:21:03 December 03, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "00:21:03 December 03, 2019" + +# Revisions + +PROJECT_REVISION = "SkySkipper" + diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf new file mode 100644 index 00000000..f4ebf1e0 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf @@ -0,0 +1,243 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:56:33 December 30, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SkySkipper_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SkySkipper_MiST.sv +set_global_assignment -name VHDL_FILE rtl/SkySkipper.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_sp_bits_4.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_sp_bits_3.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_sp_bits_2.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_sp_bits_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_palette_rg.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_palette_gb.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_ch_palette_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_ch_bits.vhd +set_global_assignment -name VHDL_FILE rtl/rom/skyskip_bg_palette_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VERILOG_FILE rtl/pll_mist.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY SkySkipper_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------- +# start ENTITY(Popeye_MiST) + + # Pin & Location Assignments + # ========================== + + # Fitter Assignments + # ================== + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Popeye_MiST) +# ----------------------- +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_global_assignment -name VERILOG_FILE rtl/jtpopeye_security.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.sdc b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.sdc new file mode 100644 index 00000000..33ffd42f --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.sdc @@ -0,0 +1,134 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/clean.bat b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd new file mode 100644 index 00000000..07d8315b --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd @@ -0,0 +1,992 @@ +--------------------------------------------------------------------------------- +-- Sky Skipper by Dar (darfpga@aol.fr) (26/12/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (26/12/2019) +-- +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : VGA 31kHz/60Hz progressive and TV 15kHz interlaced +-- Coctail mode : NO +-- Sound : OK + +-- Use with MAME roms from popeye.zip & popeyeu.zip +-- +-- Use make_popeye_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Popeye Hardware caracteristics : TODO +-- +--------------------------------------------------------------------------------- +-- Schematics remarks : +-- +-- Display is 512x448 pixels (video 640 pixels x 256 interlaced lines @ 10.08MHz ) + +-- 640/10.08e6 = 63.49us per line (15.750KHz) +-- 63.49*256 = 16.254ms per frame (61.52Hz) +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity SkySkipper is +port( + clock_40 : in std_logic; + reset : in std_logic; + tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_clk : out std_logic; + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : buffer std_logic; + + audio_out : out std_logic_vector(15 downto 0); + + coin1 : in std_logic; + coin2 : in std_logic; + start1 : in std_logic; + start2 : in std_logic; + + right1 : in std_logic; + left1 : in std_logic; + up1 : in std_logic; + down1 : in std_logic; + fire11 : in std_logic; + fire12 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + up2 : in std_logic; + down2 : in std_logic; + fire21 : in std_logic; + fire22 : in std_logic; + sw1 : in std_logic_vector(3 downto 0); + sw2 : in std_logic_vector(7 downto 0); + + service : in std_logic; + cpu_rom_addr : out std_logic_vector(14 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end SkySkipper; + +architecture struct of SkySkipper is + + signal reset_n : std_logic; + signal clock_vid : std_logic; + signal clock_vidn: std_logic; + signal clock_cnt1: std_logic_vector(3 downto 0) := "0000"; + signal clock_cnt2: std_logic_vector(3 downto 0) := "0000"; + + signal hcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter + signal hflip : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter flip + signal vcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter + signal vflip : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter flip + + signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ; + signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic; + signal top_frame : std_logic := '0'; + signal init_eo : std_logic; + + signal pix_ena : std_logic; + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_rd_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_ioreq_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_m1_n : std_logic; + +-- signal cpu_rom_addr : std_logic_vector(14 downto 0); +-- signal cpu_rom_do : std_logic_vector( 7 downto 0); + signal cpu_rom_do_swp : std_logic_vector( 7 downto 0); + + signal wram_addr : std_logic_vector(10 downto 0); + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + signal wram_do_r : std_logic_vector( 7 downto 0); + +-- signal dbg_wram_do : std_logic_vector( 7 downto 0); + + signal ch_ram_addr : std_logic_vector(9 downto 0); + signal ch_ram_txt_we : std_logic; + signal ch_ram_txt_do : std_logic_vector(7 downto 0); + signal ch_ram_color_we : std_logic; + signal ch_ram_color_do : std_logic_vector(3 downto 0); + + signal ch_code : std_logic_vector( 7 downto 0); + signal ch_code_line : std_logic_vector(11 downto 0); + signal ch_graphx_do : std_logic_vector( 7 downto 0); + signal ch_vid : std_logic; + signal ch_color : std_logic_vector( 4 downto 0); + + signal hoffset : std_logic_vector( 7 downto 0); + signal hshift : std_logic_vector( 9 downto 0); + signal voffset : std_logic_vector( 7 downto 0); + signal vshift : std_logic_vector( 9 downto 0); + + signal bg_ram_addr : std_logic_vector(11 downto 0); + signal bg_ram_lnib_we : std_logic; + signal bg_ram_lnib_do : std_logic_vector(3 downto 0); + signal bg_ram_hnib_we : std_logic; + signal bg_ram_hnib_do : std_logic_vector(3 downto 0); + + signal bg_graphx : std_logic_vector(3 downto 0); + signal bg_color : std_logic_vector(3 downto 0); + + signal move_buf : std_logic; + signal read_buf : std_logic; + signal sp_ram_addr : std_logic_vector(9 downto 0); + signal sp_ram1_we : std_logic; + signal sp_ram1_do : std_logic_vector(7 downto 0); + signal sp_ram2_we : std_logic; + signal sp_ram2_do : std_logic_vector(7 downto 0); + signal sp_ram3_we : std_logic; + signal sp_ram3_do : std_logic_vector(7 downto 0); + signal sp_ram4_we : std_logic; + signal sp_ram4_do : std_logic_vector(7 downto 0); + + signal sp_vcnt : std_logic_vector(9 downto 0); + signal sp_on_line : std_logic; + + signal sp_buffer_ram1_addr : std_logic_vector( 5 downto 0); + signal sp_buffer_ram1_we : std_logic; + signal sp_buffer_ram1_di : std_logic_vector(17 downto 0); + signal sp_buffer_ram1_do : std_logic_vector(17 downto 0); + + signal sp_buffer_ram2_addr : std_logic_vector( 5 downto 0); + signal sp_buffer_ram2_we : std_logic; + signal sp_buffer_ram2_di : std_logic_vector(17 downto 0); + signal sp_buffer_ram2_do : std_logic_vector(17 downto 0); + + signal sp_buffer_sel : std_logic; + + signal sp_graphx1_do : std_logic_vector( 7 downto 0); + signal sp_graphx2_do : std_logic_vector( 7 downto 0); + signal sp_graphx3_do : std_logic_vector( 7 downto 0); + signal sp_graphx4_do : std_logic_vector( 7 downto 0); + + signal sp_graphx0 : std_logic_vector( 15 downto 0); + signal sp_graphx_sr0 : std_logic_vector( 15 downto 0); + signal sp_graphx1 : std_logic_vector( 15 downto 0); + signal sp_graphx_sr1 : std_logic_vector( 15 downto 0); + + signal sp_code_line : std_logic_vector(12 downto 0); + signal sp_code_line0 : std_logic_vector(12 downto 0); + + signal sp_hflip : std_logic; + signal sp_hflip_r : std_logic; + signal sp_hflip_rr : std_logic; + signal sp_hoffset : std_logic_vector(1 downto 0); + signal sp_color : std_logic_vector(2 downto 0); + signal sp_color_r : std_logic_vector(2 downto 0); + signal sp_color_rr : std_logic_vector(2 downto 0); + signal sp_vid : std_logic_vector(1 downto 0); + signal sp_hcnt : std_logic_vector(3 downto 0); + + signal ch_palette_addr : std_logic_vector(4 downto 0); + signal ch_palette_do : std_logic_vector(7 downto 0); + signal bg_palette_addr : std_logic_vector(4 downto 0); + signal bg_palette_do : std_logic_vector(7 downto 0); + signal sp_palette_addr : std_logic_vector(7 downto 0); + signal sp_palette_rg_do : std_logic_vector(7 downto 0); -- only 4 bits used + signal sp_palette_gb_do : std_logic_vector(7 downto 0); -- only 4 bits used + + signal input_0 : std_logic_vector(7 downto 0); + signal input_1 : std_logic_vector(7 downto 0); + signal input_2 : std_logic_vector(7 downto 0); + + + signal ay_do : std_logic_vector(7 downto 0); + signal ay_bdir : std_logic; + signal ay_bc1 : std_logic; + signal ay_audio : std_logic_vector(7 downto 0); + signal ay_ena : std_logic; + + signal ay_iob_do : std_logic_vector(7 downto 0); + signal ay_ioa_di : std_logic_vector(7 downto 0); + signal sec_cs : std_logic; + signal sec_we : std_logic; + signal sec_data : std_logic_vector(7 downto 0); + + COMPONENT jtpopeye_security + PORT + ( + clk : IN STD_LOGIC; + cen : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + cs : IN STD_LOGIC; + A0 : IN STD_LOGIC; + rd_n : IN STD_LOGIC; + wr_n : IN STD_LOGIC + ); +END COMPONENT; + +begin + +clock_vid <= clock_40; +clock_vidn <= not clock_40; +reset_n <= not reset; + +-- debug +process (reset, clock_vid) +begin + if rising_edge(clock_vid) then -- and cpu_ena ='1' and cpu_mreq_n ='0' then + dbg_cpu_addr<= cpu_addr; + end if; +end process; + +-- make enables clock from clock_vid +process (clock_vid, reset) +begin + if reset='1' then + clock_cnt1 <= (others=>'0'); + clock_cnt2 <= (others=>'0'); + else + if rising_edge(clock_vid) then + + if clock_cnt1 = "1111" then -- divide by 16 + clock_cnt1 <= (others=>'0'); + else + clock_cnt1 <= clock_cnt1 + 1; + end if; + + if clock_cnt2 = "10011" then -- divide by 20 + clock_cnt2 <= (others=>'0'); + else + clock_cnt2 <= clock_cnt2 + 1; + end if; + + end if; + end if; +end process; +-- +cpu_ena <= '1' when clock_cnt2 = "00000" or clock_cnt2 = "01010" else '0'; -- (4MHz for cpu) + +ay_ena <= '1' when clock_cnt2 = "00000" else '0'; -- (2MHz for ay-3-8910) + +pix_ena <= '1' when (clock_cnt1(1 downto 0) = "11" and tv15Khz_mode = '1') or -- (10MHz for video interleaved) + (clock_cnt1(0) = '1' and tv15Khz_mode = '0') else '0'; -- (20MHz for video progressive) + +----------------------------------- +-- Video scanner 640x512 @20Mhz -- +-- 640x256 @10Mhz -- +-- display 512x448 -- +----------------------------------- +process (reset, clock_vid) +begin + if reset='1' then + hcnt <= (others=>'0'); + vcnt <= (others=>'0'); + top_frame <= '0'; + else + if rising_edge(clock_vid) then + if pix_ena = '1' then + + hcnt <= hcnt + 1; + if hcnt = 639 then + hcnt <= (others=>'0'); + vcnt <= vcnt + 1; +-- if (vcnt = 511 and tv15Khz_mode = '0') or (vcnt = 255 and tv15Khz_mode = '1') then + if (vcnt = 525 and tv15Khz_mode = '0') or (vcnt = 262 and tv15Khz_mode = '1') then -- extension to classic video standard + vcnt <= (others=>'0'); + top_frame <= not top_frame; + end if; + end if; + + if tv15Khz_mode = '0' then + -- progessive mode + + -- tune 31kHz vertical screen position here + if vcnt = 490+8 then video_vs <= '0'; end if; -- front porch 10 + if vcnt = 492+8 then video_vs <= '1'; end if; -- sync pulse 2 + -- back porch 33 + -- tune 31kHz horizontal screen position here + if hcnt = 512+13+12 then video_hs <= '0'; end if; -- front porch 16/25*20 = 13 + if hcnt = 512+90+12 then video_hs <= '1'; end if; -- sync pulse 96/25*20 = 77 + -- back porch 48/25*20 = 38 + video_blankn <= '0'; + if hcnt >= 2+16 and hcnt < 514+16-1 and + vcnt >= 32 and vcnt < 480 then video_blankn <= '1';end if; + + else -- interlaced mode + + if hcnt = 530+18 then -- tune 15KHz horizontal screen position here + hs_cnt <= (others => '0'); + if (vcnt = 248) then -- tune 15KHz vertical screen position here + vs_cnt <= (others => '0'); + else + vs_cnt <= vs_cnt +1; + end if; + + if vcnt = 260 then video_vs <= '0'; end if; + if vcnt = 262 then video_vs <= '1'; end if; + + else + hs_cnt <= hs_cnt + 1; + end if; + + video_blankn <= '0'; + if hcnt >= 2+16 and hcnt < 514+16-1 and + vcnt >= 16 and vcnt < 240 then video_blankn <= '1';end if; + + if hs_cnt = 0 then hsync0 <= '0'; + elsif hs_cnt = 47 then hsync0 <= '1'; + end if; + + if hs_cnt = 0 then hsync1 <= '0'; + elsif hs_cnt = 23 then hsync1 <= '1'; + elsif hs_cnt = 320+ 0 then hsync1 <= '0'; + elsif hs_cnt = 320+23 then hsync1 <= '1'; + end if; + + if hs_cnt = 0 then hsync2 <= '0'; + elsif hs_cnt = 320-47 then hsync2 <= '1'; + elsif hs_cnt = 320 then hsync2 <= '0'; + elsif hs_cnt = 640-47 then hsync2 <= '1'; + end if; + + + if hs_cnt = 0 then hsync3 <= '0'; + elsif hs_cnt = 23 then hsync3 <= '1'; + elsif hs_cnt = 320 then hsync3 <= '0'; + elsif hs_cnt = 640-47 then hsync3 <= '1'; + end if; + + if hs_cnt = 0 then hsync4 <= '0'; + elsif hs_cnt = 320-47 then hsync4 <= '1'; + elsif hs_cnt = 320 then hsync4 <= '0'; + elsif hs_cnt = 320+23 then hsync4 <= '1'; + end if; + + + if vs_cnt = 1 then video_csync <= hsync1; + elsif vs_cnt = 2 then video_csync <= hsync1; + elsif vs_cnt = 3 then video_csync <= hsync1; + elsif vs_cnt = 4 and top_frame = '1' then video_csync <= hsync3; + elsif vs_cnt = 4 and top_frame = '0' then video_csync <= hsync1; + elsif vs_cnt = 5 then video_csync <= hsync2; + elsif vs_cnt = 6 then video_csync <= hsync2; + elsif vs_cnt = 7 and top_frame = '1' then video_csync <= hsync4; + elsif vs_cnt = 7 and top_frame = '0' then video_csync <= hsync2; + elsif vs_cnt = 8 then video_csync <= hsync1; + elsif vs_cnt = 9 then video_csync <= hsync1; + elsif vs_cnt = 10 then video_csync <= hsync1; + elsif vs_cnt = 11 then video_csync <= hsync0; + else video_csync <= hsync0; + end if; + + end if; + + end if; + end if; + end if; +end process; + +-------------------- +-- players inputs -- +-------------------- +input_0 <= fire12 & "11" & fire11 & down1 & up1 & left1 & right1; +input_1 <= fire22 & "11" & fire21 & down2 & up2 & left2 & right2; +input_2 <= coin1 & service & coin2 & '1' & start2 & start1 & "11"; + +------------------------------------------ +-- cpu data input with address decoding -- +------------------------------------------ +cpu_rom_addr <= (cpu_addr(14 downto 10) & cpu_addr(8 downto 7) & cpu_addr(0) & cpu_addr(1) & cpu_addr(2) & cpu_addr(4) & cpu_addr(5) & cpu_addr(9) & cpu_addr(3) & cpu_addr(6)) xor ("000" & x"0FC"); + + cpu_rom_do_swp <= + cpu_rom_do(3) & cpu_rom_do(4) & cpu_rom_do(2) & cpu_rom_do(5) & + cpu_rom_do(1) & cpu_rom_do(6) & cpu_rom_do(0) & cpu_rom_do(7); + +cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko + wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800 +-- sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else + sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 0) = "1110000000000001" else + input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else + input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else + input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else + ay_do when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "11") else + X"FF"; +-- +------------------------------------------ +-- write enable / ram access from CPU -- +------------------------------------------ +wram_addr <= cpu_addr(10 downto 0) when hcnt(0) = '0' else '1' & sp_ram_addr(9 downto 0); + +wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"8000" and hcnt(0) = '0' else '0'; +ch_ram_txt_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"EC00") = x"A000" and hcnt(0) = '0' else '0'; +ch_ram_color_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"EC00") = x"A400" and hcnt(0) = '0' else '0'; +bg_ram_lnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"C000" and hcnt(0) = '0' else '0'; +bg_ram_hnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"D000" and hcnt(0) = '0' else '0';--not needed +--sec_cs <= '1' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else '0'; +sec_cs <= '1' when cpu_addr(15 downto 0) = "1110000000000001" else '0'; +----------------------------------------------------- +-- Transfer sprite data from wram to sprite ram +-- once per frame. Read sprite ram on every scanline. +----------------------------------------------------- +sp_ram1_we <= hcnt(0) when move_buf = '1' and sp_ram_addr(1 downto 0) = "00" else '0'; +sp_ram2_we <= hcnt(0) when move_buf = '1' and sp_ram_addr(1 downto 0) = "01" else '0'; +sp_ram3_we <= hcnt(0) when move_buf = '1' and sp_ram_addr(1 downto 0) = "10" else '0'; +sp_ram4_we <= hcnt(0) when move_buf = '1' and sp_ram_addr(1 downto 0) = "11" else '0'; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if hcnt(0) = '0' then wram_do_r <= wram_do; end if; + + if move_buf = '0' and read_buf ='0' then + sp_ram_addr <= (others => '0'); + + if hcnt = 1 and pix_ena = '1' then + if (vcnt = 500 and tv15Khz_mode = '0') or (vcnt = 250 and tv15Khz_mode = '1') then + move_buf <= '1'; + else + read_buf <= '1'; + end if; + end if; + end if; + + if move_buf = '1' and pix_ena = '1' and hcnt(0) = '1' then + if sp_ram_addr >= 640 then + move_buf <= '0'; + else + sp_ram_addr <= sp_ram_addr + 1; + end if; + end if; + + if read_buf = '1' and pix_ena = '1' and hcnt(0) = '1' then + if sp_ram_addr >= 640 then + read_buf <= '0'; + else + sp_ram_addr <= sp_ram_addr + 4; + end if; + end if; + + end if; +end process; + +------------------------------------------------------------------------ +-- Misc registers : write enable / interrupt / ay-3-8910 IF +------------------------------------------------------------------------ + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if cpu_mreq_n = '0' and cpu_wr_n = '0' then + if (cpu_addr = x"8C00") then hoffset <= cpu_do; end if; + if (cpu_addr = x"8C01") then voffset <= cpu_do; end if; + + if (cpu_addr = x"8C03") then + sp_palette_addr(7 downto 5) <= cpu_do(2 downto 0); + bg_palette_addr(4) <= cpu_do(3); + end if; + end if; + + end if; +end process; + +cpu_nmi_n <= video_vs; + +audio_out <= ay_audio & X"00"; +-- +-- bdir bc1 (bc2 = 1) +-- 0 0 : Inactive +-- 0 1 : Read +-- 1 0 : Write +-- 1 1 : Address + +ay_bdir <= '1' when cpu_ioreq_n = '0' and cpu_wr_n = '0' else '0'; +ay_bc1 <= '1' when cpu_ioreq_n = '0' and (cpu_rd_n = '0' or (cpu_wr_n = '0' and cpu_addr(0) = '0')) else '0'; + +ay_ioa_di <= not sw2(to_integer(unsigned(ay_iob_do(3 downto 1)))) & "000" & not sw1; + +------------------------------------ +---------- sprite machine ---------- +------------------------------------ +hflip <= hcnt; -- do not apply mirror horizontal flip +vflip <= vcnt(8 downto 0) & not top_frame when tv15Khz_mode = '1' else vcnt; -- do not apply mirror flip + +sp_buffer_sel <= vflip(1) when tv15Khz_mode = '1' else vflip(0); + +sp_vcnt <= vflip + (sp_ram2_do & '0') - 14 when tv15Khz_mode = '1' else -- tune v sprite position for 15KHz (interlaced) + vflip + (sp_ram2_do & '0') - 15; -- tune v sprite position for 31KHz (progressive) + +sp_on_line <= '1' when (sp_vcnt(8 downto 4) = (x"F"&'1')) and (read_buf = '1') else '0'; + +-- feed and read line buffers + +sp_buffer_ram1_di <= sp_ram4_do(4 downto 0) & sp_ram1_do(1 downto 0) & sp_ram3_do & sp_vcnt(3 downto 1) when sp_buffer_sel = '1' else "00"&x"0000"; +sp_buffer_ram1_addr <= sp_ram1_do(7 downto 2) when sp_buffer_sel = '1' else hflip(8 downto 3); +sp_buffer_ram1_we <= pix_ena and hcnt(0) and sp_on_line when sp_buffer_sel = '1' else pix_ena and hcnt(2) and hcnt(1) and hcnt(0); + +sp_buffer_ram2_di <= sp_ram4_do(4 downto 0) & sp_ram1_do(1 downto 0) & sp_ram3_do & sp_vcnt(3 downto 1) when sp_buffer_sel = '0' else "00"&x"0000"; +sp_buffer_ram2_addr <= sp_ram1_do(7 downto 2) when sp_buffer_sel = '0' else hflip(8 downto 3); +sp_buffer_ram2_we <= pix_ena and hcnt(0) and sp_on_line when sp_buffer_sel = '0' else pix_ena and hcnt(2) and hcnt(1) and hcnt(0); + +sp_code_line0 <= + (sp_buffer_ram1_do(15) & sp_buffer_ram1_do(17) & sp_buffer_ram1_do(9 downto 0) & sp_vcnt(0)) xor ('0' & x"00F") when sp_buffer_sel = '0' and sp_buffer_ram1_do(16) = '1' else + (sp_buffer_ram1_do(15) & sp_buffer_ram1_do(17) & sp_buffer_ram1_do(9 downto 0) & sp_vcnt(0)) xor ('0' & x"000") when sp_buffer_sel = '0' and sp_buffer_ram1_do(16) = '0' else + (sp_buffer_ram2_do(15) & sp_buffer_ram2_do(17) & sp_buffer_ram2_do(9 downto 0) & sp_vcnt(0)) xor ('0' & x"00F") when sp_buffer_sel = '1' and sp_buffer_ram2_do(16) = '1' else + (sp_buffer_ram2_do(15) & sp_buffer_ram2_do(17) & sp_buffer_ram2_do(9 downto 0) & sp_vcnt(0)) xor ('0' & x"000"); + +sp_code_line <= sp_code_line0 xor ('1'&x"FFF") when tv15Khz_mode = '1' else -- ok for 15 KHz + sp_code_line0 xor ('1'&x"FFE"); -- ok for 31 KHz + +sp_hflip <= sp_buffer_ram1_do(10) when sp_buffer_sel = '0' else sp_buffer_ram2_do(10); +sp_hoffset <= sp_buffer_ram1_do(12 downto 11) when sp_buffer_sel = '0' else sp_buffer_ram2_do(12 downto 11); +sp_color <= sp_buffer_ram1_do(15 downto 13) when sp_buffer_sel = '0' else sp_buffer_ram2_do(15 downto 13); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(2 downto 0) = "111" then + + sp_graphx0 <= sp_graphx1_do & sp_graphx2_do; + sp_graphx1 <= sp_graphx3_do & sp_graphx4_do; + sp_color_r <= sp_color; + sp_hflip_r <= sp_hflip; + + if sp_color = "000" then + sp_hcnt <= "01" & not sp_hoffset; + else + sp_hcnt <= "11" & not sp_hoffset; + end if; + + else + if hcnt(0)='1' then sp_hcnt <= sp_hcnt + 1; end if; + end if; + + if hcnt(0) = '0' and sp_hcnt = x"F" then + sp_graphx_sr0 <= sp_graphx0; + sp_graphx_sr1 <= sp_graphx1; + sp_color_rr <= sp_color_r; + sp_hflip_rr <= sp_hflip_r; + else + if sp_hflip_rr = '0' then + sp_graphx_sr0 <= '0' & sp_graphx_sr0(15 downto 1); + sp_graphx_sr1 <= '0' & sp_graphx_sr1(15 downto 1); + else + sp_graphx_sr0 <= sp_graphx_sr0(14 downto 0) & '0'; + sp_graphx_sr1 <= sp_graphx_sr1(14 downto 0) & '0'; + end if; + end if; + + end if; + end if; +end process; + +sp_palette_addr(1 downto 0) <= sp_graphx_sr0(0) & sp_graphx_sr1(0) when sp_hflip_rr = '0' else sp_graphx_sr0(15) & sp_graphx_sr1(15); +sp_palette_addr(4 downto 2) <= sp_color_rr; + +---------------------------- +------- char machine ------- +---------------------------- +ch_ram_addr <= cpu_addr(9 downto 0) when hcnt(0) = '0' else vflip(8 downto 4) & hflip(8 downto 4); + +ch_code_line <= '1' & ch_code & vflip(3 downto 1); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(0) = '1' then + if hcnt(3 downto 1) = "111" then + ch_code <= ch_ram_txt_do; + ch_color <= ch_ram_color_do(3) & ch_ram_color_do; + end if; + end if; + + ch_palette_addr <= ch_color; + ch_vid <= ch_graphx_do(to_integer(unsigned(hflip(3 downto 1)))); + + end if; + + end if; +end process; + + +---------------------------- +---- background machine ---- +---------------------------- +bg_ram_addr <= cpu_addr(11 downto 0) when hcnt(0) = '0' else vshift(7 downto 2) & hshift(8 downto 3); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt = 540 then -- tune background h pos w.r.t char (use odd value to keep hshift(0) = hcnt(0)) + hshift <= '0' & hoffset & '0'; + else + hshift <= hshift + 1 ; + end if; + + if hcnt = 540 then + if tv15Khz_mode = '0' then + vshift <= ('0' & voffset & '0') + vflip + ("01" & x"01"); -- tune background v pos w.r.t char + else + vshift <= ('0' & voffset & '0') + vflip + ("01" & x"02"); -- tune background v pos w.r.t char + end if; + end if; + + if hcnt(0) = '1' then + if hcnt(1) = '1' then + if vshift(8) = '1' then + bg_color <= bg_ram_lnib_do; + else + bg_color <= bg_ram_hnib_do; + end if; + end if; + end if; + + bg_palette_addr(3 downto 0) <= bg_color; + + end if; + + end if; +end process; + +--------------------------- +-- mux char/sprite video -- +--------------------------- +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if hoffset = x"00" then + video_r <= "000"; + video_g <= "000"; + video_b <= "00"; + else + video_r <= not bg_palette_do(2 downto 0); + video_g <= not bg_palette_do(5 downto 3); + video_b <= not bg_palette_do(7 downto 6); + end if; + + if sp_palette_addr(1 downto 0) /= "00" then + video_r <= not (sp_palette_rg_do(2 downto 0)); + video_g <= not (sp_palette_gb_do(1 downto 0) & sp_palette_rg_do(3)); + video_b <= not (sp_palette_gb_do(3 downto 2)); + end if; + + if ch_vid = '1' then + video_r <= not ch_palette_do(2 downto 0); + video_g <= not ch_palette_do(5 downto 3); + video_b <= not ch_palette_do(7 downto 6); + end if; + + end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_vid, + CLKEN => cpu_ena, + WAIT_n => '1', + INT_n => '1', -- cpu_irq_n, + NMI_n => cpu_nmi_n, + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_ioreq_n, + RD_n => cpu_rd_n, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu program ROM 0x0000-0xDFFF +--rom_cpu : entity work.popeye_cpu +--port map( +-- clk => clock_vidn, +-- addr => cpu_rom_addr, +-- data => cpu_rom_do +--); + +-- working RAM 8000-87FF/8800-8FFF 2Ko +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_vidn, + we => wram_we, + addr => wram_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- char RAM (text) A000-A3FF 1Ko + mirroring 1000 +char_ram_txt : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_vidn, + we => ch_ram_txt_we, + addr => ch_ram_addr, + d => cpu_do, + q => ch_ram_txt_do +); + +-- char RAM (color) A400-A7FF 1Ko + mirroring 1000 +char_ram_color : entity work.gen_ram +generic map( dWidth => 4, aWidth => 10) +port map( + clk => clock_vidn, + we => ch_ram_color_we, + addr => ch_ram_addr, + d => cpu_do(3 downto 0), + q => ch_ram_color_do +); + +-- video RAM C000-CFFF 4K x 4bits +video_ram_lnib : entity work.gen_ram +generic map( dWidth => 4, aWidth => 12) +port map( + clk => clock_vidn, + we => bg_ram_lnib_we, + addr => bg_ram_addr, + d => cpu_do(3 downto 0), + q => bg_ram_lnib_do +); + +-- video RAM D000-DFFF 4K x 4bits +video_ram_hnib : entity work.gen_ram +generic map( dWidth => 4, aWidth => 12) +port map( + clk => clock_vidn, + we => bg_ram_hnib_we, + addr => bg_ram_addr, + d => cpu_do(3 downto 0), + q => bg_ram_hnib_do +); + + +-- sprite RAMs (no cpu access) +sprite_ram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram1_we, + addr => sp_ram_addr(9 downto 2), + d => wram_do, +-- d => dbg_wram_do, + q => sp_ram1_do +); + +sprite_ram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram2_we, + addr => sp_ram_addr(9 downto 2), + d => wram_do, +-- d => dbg_wram_do, + q => sp_ram2_do +); + +sprite_ram3 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram3_we, + addr => sp_ram_addr(9 downto 2), + d => wram_do, +-- d => dbg_wram_do, + q => sp_ram3_do +); + +sprite_ram4 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram4_we, + addr => sp_ram_addr(9 downto 2), + d => wram_do, +-- d => dbg_wram_do, + q => sp_ram4_do +); + +-- sprite line buffer 1 +sprlinebuf1a : entity work.gen_ram +generic map( dWidth => 18, aWidth => 6) +port map( + clk => clock_vidn, + we => sp_buffer_ram1_we, + addr => sp_buffer_ram1_addr, + d => sp_buffer_ram1_di, + q => sp_buffer_ram1_do +); + +-- sprite line buffer 2 +sprlinebuf2 : entity work.gen_ram +generic map( dWidth => 18, aWidth => 6) +port map( + clk => clock_vidn, + we => sp_buffer_ram2_we, + addr => sp_buffer_ram2_addr, + d => sp_buffer_ram2_di, + q => sp_buffer_ram2_do +); + +-- char graphics ROM 5N +ch_graphics : entity work.skyskip_ch_bits +port map( + clk => clock_vidn, + addr => ch_code_line(10 downto 0), + data => ch_graphx_do +); + +-- sprite graphics ROM 1E +sprite_graphics1 : entity work.skyskip_sp_bits_1 +port map( + clk => clock_vidn, + addr => sp_code_line(11 downto 0), + data => sp_graphx1_do +); + +-- sprite graphics ROM 1F +sprite_graphics2 : entity work.skyskip_sp_bits_2 +port map( + clk => clock_vidn, + addr => sp_code_line(11 downto 0), + data => sp_graphx2_do +); + +-- sprite graphics ROM 1J +sprite_graphics3 : entity work.skyskip_sp_bits_3 +port map( + clk => clock_vidn, + addr => sp_code_line(11 downto 0), + data => sp_graphx3_do +); + +-- sprite graphics ROM 1k +sprite_graphics4 : entity work.skyskip_sp_bits_4 +port map( + clk => clock_vidn, + addr => sp_code_line(11 downto 0), + data => sp_graphx4_do +); + +-- char palette +ch_palette : entity work.skyskip_ch_palette_rgb +port map( + clk => clock_vidn, + addr => ch_palette_addr, + data => ch_palette_do +); + +-- background palette +bg_palette : entity work.skyskip_bg_palette_rgb +port map( + clk => clock_vidn, + addr => bg_palette_addr, + data => bg_palette_do +); + +-- sprites palettes +sp_palette_rg : entity work.skyskip_palette_rg +port map( + clk => clock_vidn, + addr => sp_palette_addr, + data => sp_palette_rg_do +); + +sp_palette_gb : entity work.skyskip_palette_gb +port map( + clk => clock_vidn, + addr => sp_palette_addr, + data => sp_palette_gb_do +); + +ym2149 : entity work.ym2149 +port map ( +-- data bus + I_DA => cpu_do, --: in std_logic_vector(7 downto 0); + O_DA => ay_do, --: out std_logic_vector(7 downto 0); + O_DA_OE_L => open, --: out std_logic; +-- control + I_A9_L => '0', --: in std_logic; + I_A8 => '1', --: in std_logic; + I_BDIR => ay_bdir, --: in std_logic; + I_BC2 => '1', --: in std_logic; + I_BC1 => ay_bc1, --: in std_logic; + I_SEL_L => '1', --: in std_logic; +-- audio + O_AUDIO => ay_audio, --: out std_logic_vector(7 downto 0); +-- port a + I_IOA => ay_ioa_di, --: in std_logic_vector(7 downto 0); + O_IOA => open, --: out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, --: out std_logic; +-- port b + I_IOB => "11111111", --: in std_logic_vector(7 downto 0); + O_IOB => ay_iob_do, --: out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, --: out std_logic; + + ENA => ay_ena, --: in std_logic; -- clock enable for higher speed operation + RESET_L => '1', --: in std_logic; + CLK => clock_vid --: in std_logic -- note 6 Mhz! +); + +sec : jtpopeye_security +port map ( + clk => clock_vid, + cen => cpu_ena, + din => cpu_do, + dout => sec_data, + rd_n => cpu_rd_n, + wr_n => cpu_wr_n, + cs => sec_cs, + A0 => cpu_addr(0) +); + +end; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper_MiST.sv b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper_MiST.sv new file mode 100644 index 00000000..5b1afa1a --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper_MiST.sv @@ -0,0 +1,273 @@ + +module SkySkipper_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "rtl/build_id.v" + +localparam CONF_STR = { + "SKYSKIP;;", +// "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blend,Off,On;", + "O7,Service,Off,On;",//Beep on REV4 ROM, not needed + "T0,Reset;", + "V,v1.0.",`BUILD_DATE +}; + + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = sdram_clk; +assign SDRAM_CKE = 1; +assign AUDIO_R = AUDIO_L; + +wire sys_clk, sdram_clk; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(sdram_clk),//48 + .c1(sys_clk),//40 + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [15:0] audio; +wire hs, vs, cs; +wire blankn; +wire [2:0] g, r; +wire [1:0] b; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io data_io( + .clk_sys ( sys_clk ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +reg port1_req, port2_req; +sdram sdram( + .*, + .init_n ( pll_locked ), + .clk ( sdram_clk ), + + // port1 used for main CPU + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]}), + .cpu1_q ( rom_do ), + + // port2 for gfx + .port2_req ( ), + .port2_ack ( ), + .port2_a ( ), + .port2_ds ( ), + .port2_we ( ), + .port2_d ( ), + .port2_q ( ), + + .gfx_addr ( ), + .gfx_q ( ) +); + +always @(posedge sdram_clk) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge sys_clk) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded; +end + +SkySkipper SkySkipper( + .clock_40(sys_clk), + .reset(reset), + .tv15Khz_mode(scandoublerD), + .video_r(r), + .video_g(g), + .video_b(b), + .video_csync(cs), + .video_blankn(blankn), + .video_hs(hs), + .video_vs(vs), + .audio_out(audio), + .coin1(btn_coin), + .coin2(1'b0), + .start1(btn_one_player), + .start2(btn_two_players), + .right1(m_right), + .left1(m_left), + .up1(m_up), + .down1(m_down), + .fire11(m_fire1), + .fire12(m_fire2), + .right2(m_right), + .left2(m_left), + .up2(m_up), + .down2(m_down), + .fire21(m_fire1), + .fire22(m_fire2), + .sw1("0000"), + .sw2("01000101"), + .service(status[7]), + .cpu_rom_addr(rom_addr), + .cpu_rom_do(rom_addr[0] ? rom_do[15:8] : rom_do[7:0]) + ); + +wire vs_out; +wire hs_out; +assign VGA_VS = scandoublerD | vs_out; +assign VGA_HS = scandoublerD ? cs : hs_out; + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( sys_clk ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,b[1]} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( vs_out ), + .VGA_HS ( hs_out ), + .ce_divider ( 1'b1 ), + .blend ( status[5] ), + .rotate ( {1'b1, status[2]} ), + .scandoubler_disable(1),//scandoublerD ), + .scanlines ( "00"),//status[3:4] ), + .no_csync ( 1'b1 ), + .ypbpr ( ypbpr ) + ); + + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (sys_clk ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .C_bits(16)) +dac_l( + .clk_i(sys_clk), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up = btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5]; +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge sys_clk) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + 'h29: btn_fire1 <= key_pressed; // Space + 'h11: btn_fire2 <= key_pressed; // l. Alt + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/build_id.tcl b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v new file mode 100644 index 00000000..736475d2 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v @@ -0,0 +1,96 @@ +/* This file is part of JTPOPEYE. + JTPOPEYE program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JTPOPEYE program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR AD PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JTPOPEYE. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 12-3-2019 */ + +`timescale 1ns/1ps + +// 7J: '139 decoder +// /MemWR and /MemRD serve as enable signals. If H all outputs will be H +// +// /OE is the same as addr1 +// Mode is the same addr0. Mode pin is not used in this model. +// +// CPU || /MemWR || /MemRD +// /sec_cs addr0 || A[1:0] || /OE || Mode +// =========================================== +// 0 0 || 10 || 1 || 0 +// 0 1 || 01 || 0 || 1 +// 1 x || 11 || 1 || 1 + +// based on code provided by www.JAMMARCADE.net + +module jtpopeye_security( + input clk, + input cen, + input [7:0] din, + output reg [7:0] dout, + input cs, + input A0, + input rd_n, + input wr_n +); + +reg [7:0] fifo [1:0]; +reg [2:0] shift; + +reg last_addr0, last_addr1; +reg addr0, addr1, oen; +wire csn = ~cs; +reg [7:0] result; + +always @(*) begin + addr0 = 1'b1; + addr1 = 1'b1; + oen = 1'b1; + // mode = 1'b1; + if( csn ) begin + if(!wr_n) begin + addr0 = A0; + addr1 = ~A0; + end + if(!rd_n) begin + oen = A0; + //mode = ~A0; + end + end + // dout = result; + // dout = A0 ? 8'd0 : result; +end + + +always @(posedge clk) if(cen) begin + // if( !addr0 ) + // shift <= din[2:0]; + // if( !addr1 ) begin + // fifo[0] <= fifo[1]; + // fifo[1] <= din; + // end + if( cs && !wr_n ) begin + if( A0 ) begin + fifo[0] <= fifo[1]; + fifo[1] <= din; + end else begin + shift <= din[2:0]; + end + end + result <= (fifo[1] << shift) | (fifo[0] >> (4'd8-{1'b0,shift})); + // dout <= { result[7:3], A0 ? 3'd0 : result[2:0] }; + if( cs && !rd_n) dout <= A0 ? 8'd0 : result; +end + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/pll_mist.v b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/pll_mist.v new file mode 100644 index 00000000..d9bf0d39 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/pll_mist.v @@ -0,0 +1,337 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_mist.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_mist ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 80, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 27, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 40, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "80" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_bg_palette_rgb.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_bg_palette_rgb.vhd new file mode 100644 index 00000000..c71efdf3 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_bg_palette_rgb.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_bg_palette_rgb is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_bg_palette_rgb is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"BF",X"BF",X"FD",X"FE",X"F4",X"EC",X"F5",X"E7",X"F7",X"D1",X"F2",X"AD",X"B8",X"64",X"27",X"BF", + X"FF",X"FF",X"6F",X"FA",X"09",X"AD",X"D6",X"7F",X"F3",X"C9",X"F5",X"FD",X"EC",X"F4",X"1D",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_bits.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_bits.vhd new file mode 100644 index 00000000..7c3f3efc --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_bits.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_ch_bits is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_ch_bits is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"1C",X"32",X"63",X"63",X"63",X"26",X"1C",X"00",X"18",X"1C",X"18",X"18",X"18",X"18",X"7E", + X"00",X"3E",X"63",X"70",X"3C",X"1E",X"07",X"7F",X"00",X"7E",X"30",X"18",X"3C",X"60",X"63",X"3E", + X"00",X"38",X"3C",X"36",X"33",X"7F",X"30",X"30",X"00",X"3F",X"03",X"3F",X"60",X"60",X"63",X"3E", + X"00",X"3C",X"06",X"03",X"3F",X"63",X"63",X"3E",X"00",X"7F",X"63",X"30",X"18",X"0C",X"0C",X"0C", + X"00",X"1E",X"23",X"27",X"1C",X"7B",X"61",X"3E",X"00",X"3E",X"63",X"63",X"7E",X"60",X"30",X"1E", + X"00",X"1C",X"36",X"63",X"63",X"7F",X"63",X"63",X"00",X"3F",X"63",X"63",X"3F",X"63",X"63",X"3F", + X"00",X"3C",X"66",X"03",X"03",X"03",X"66",X"3C",X"00",X"1F",X"33",X"63",X"63",X"63",X"33",X"1F", + X"00",X"7E",X"06",X"06",X"3E",X"06",X"06",X"7E",X"00",X"7F",X"03",X"03",X"3F",X"03",X"03",X"03", + X"00",X"7C",X"06",X"03",X"73",X"63",X"66",X"7C",X"00",X"63",X"63",X"63",X"7F",X"63",X"63",X"63", + X"00",X"7E",X"18",X"18",X"18",X"18",X"18",X"7E",X"00",X"60",X"60",X"60",X"60",X"60",X"63",X"3E", + X"00",X"63",X"33",X"1B",X"0F",X"1F",X"3B",X"73",X"00",X"06",X"06",X"06",X"06",X"06",X"06",X"7E", + X"00",X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63",X"67",X"6F",X"7F",X"7B",X"73",X"63", + X"00",X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"3F",X"63",X"63",X"63",X"3F",X"03",X"03", + X"00",X"3E",X"63",X"63",X"63",X"7B",X"33",X"5E",X"00",X"3F",X"63",X"63",X"73",X"1F",X"3B",X"73", + X"00",X"1E",X"33",X"03",X"3E",X"60",X"63",X"3E",X"00",X"7E",X"18",X"18",X"18",X"18",X"18",X"18", + X"00",X"63",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"63",X"63",X"63",X"77",X"3E",X"1C",X"08", + X"00",X"63",X"63",X"6B",X"7F",X"7F",X"36",X"22",X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63", + X"00",X"66",X"66",X"24",X"3C",X"18",X"18",X"18",X"00",X"7F",X"70",X"38",X"1C",X"0E",X"07",X"7F", + X"00",X"40",X"20",X"10",X"08",X"04",X"02",X"01",X"00",X"00",X"00",X"18",X"18",X"10",X"10",X"08", + X"00",X"00",X"00",X"00",X"00",X"18",X"18",X"00",X"00",X"63",X"55",X"49",X"22",X"22",X"14",X"08", + X"00",X"08",X"49",X"2A",X"1C",X"2A",X"49",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"24",X"12",X"36",X"36",X"00",X"00",X"00",X"00",X"6C",X"6C",X"48",X"24",X"00",X"00",X"00", + X"00",X"00",X"00",X"DE",X"96",X"9E",X"86",X"86",X"00",X"00",X"00",X"3B",X"09",X"39",X"21",X"B9", + X"00",X"00",X"00",X"3E",X"36",X"3E",X"06",X"3E",X"00",X"3C",X"2C",X"2C",X"0C",X"3E",X"0C",X"0C", + X"00",X"00",X"00",X"00",X"3E",X"36",X"36",X"3E",X"30",X"36",X"3E",X"00",X"00",X"00",X"00",X"00", + X"00",X"06",X"06",X"06",X"3E",X"36",X"36",X"36",X"00",X"00",X"18",X"00",X"18",X"18",X"18",X"18", + X"00",X"00",X"30",X"00",X"30",X"30",X"30",X"30",X"36",X"36",X"3E",X"00",X"00",X"00",X"00",X"00", + X"00",X"06",X"06",X"06",X"36",X"1E",X"36",X"36",X"00",X"08",X"18",X"18",X"18",X"18",X"18",X"18", + X"00",X"00",X"06",X"7E",X"56",X"56",X"56",X"56",X"00",X"00",X"06",X"3E",X"36",X"36",X"36",X"36", + X"00",X"00",X"00",X"3E",X"36",X"36",X"36",X"3E",X"00",X"00",X"00",X"00",X"3E",X"36",X"36",X"3E", + X"06",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"36",X"36",X"3E", + X"30",X"30",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"36",X"3E",X"06",X"06",X"06", + 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X"70",X"30",X"38",X"18",X"1C",X"1C",X"1E",X"1E",X"80",X"C0",X"C0",X"C0",X"E0",X"60",X"60",X"70", + X"3F",X"1F",X"03",X"E0",X"FF",X"9F",X"80",X"80",X"1F",X"38",X"38",X"78",X"70",X"70",X"70",X"78", + X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"0F",X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0E",X"06",X"06",X"07",X"03",X"03",X"03",X"38",X"98",X"D8",X"DC",X"CE",X"0F",X"0D",X"0C", + X"C1",X"E0",X"60",X"60",X"70",X"70",X"70",X"30",X"01",X"03",X"01",X"00",X"00",X"01",X"01",X"01", + X"80",X"80",X"C0",X"C0",X"E0",X"E0",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"3C",X"36",X"33",X"39",X"38",X"18",X"F8",X"F8",X"E0",X"E0",X"E0",X"F0",X"70",X"70",X"78",X"38", + X"80",X"C0",X"80",X"00",X"00",X"C0",X"C0",X"E0",X"3C",X"0F",X"03",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"F0",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"03",X"83",X"C3",X"61",X"31",X"19",X"0D",X"07",X"00",X"1C",X"1C",X"0E",X"07",X"07",X"07",X"03", + X"31",X"31",X"1F",X"1F",X"1F",X"07",X"00",X"00",X"C0",X"E0",X"F0",X"D8",X"CC",X"66",X"63",X"71", + X"86",X"C7",X"C3",X"E3",X"A6",X"BE",X"9C",X"C0",X"00",X"70",X"78",X"38",X"1C",X"1C",X"0C",X"8E", + X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"19",X"00",X"00",X"80",X"C0",X"63",X"3F",X"1F",X"7E",X"F7",X"E1",X"E0",X"E0",X"73",X"37",X"1D", + X"0F",X"03",X"01",X"01",X"00",X"00",X"38",X"7C",X"00",X"00",X"00",X"00",X"0F",X"1F",X"1F",X"1F", + X"99",X"D9",X"DD",X"CD",X"CC",X"CC",X"8E",X"86",X"60",X"70",X"F0",X"F0",X"30",X"30",X"39",X"99", + X"87",X"87",X"C3",X"C0",X"C0",X"C0",X"E0",X"E0",X"00",X"01",X"07",X"0F",X"0F",X"0E",X"0E",X"87", + X"C0",X"C0",X"E0",X"E0",X"F8",X"7F",X"3F",X"1F",X"07",X"0F",X"1F",X"3F",X"7E",X"FC",X"F1",X"E1", + X"E4",X"FC",X"FC",X"F8",X"00",X"00",X"00",X"01",X"00",X"F0",X"FE",X"FF",X"0F",X"01",X"00",X"00", + X"FE",X"1E",X"0E",X"1E",X"3C",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",X"00",X"70",X"FC",X"FC", + X"70",X"70",X"70",X"70",X"70",X"70",X"F0",X"E0",X"00",X"00",X"00",X"80",X"C0",X"C0",X"E0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FE",X"03",X"C1",X"61",X"31",X"31",X"01",X"01",X"81",X"81",X"81",X"01",X"81",X"81",X"03",X"FE", + X"7F",X"C0",X"83",X"86",X"8C",X"8C",X"86",X"87",X"81",X"81",X"81",X"80",X"81",X"81",X"C0",X"7F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_palette_rgb.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_palette_rgb.vhd new file mode 100644 index 00000000..6f2a9cb3 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_ch_palette_rgb.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_ch_palette_rgb is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_ch_palette_rgb is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C0",X"F8",X"39",X"5C",X"67",X"39",X"0F",X"09",X"B9",X"C2",X"97",X"C0",X"08",X"2F",X"CF",X"EC", + X"C0",X"F8",X"39",X"5C",X"67",X"39",X"0F",X"09",X"B9",X"C2",X"97",X"C0",X"08",X"2F",X"CF",X"F5"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_gb.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_gb.vhd new file mode 100644 index 00000000..c6c51eb1 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_gb.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_palette_gb is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_palette_gb is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"02",X"0D",X"0F",X"00",X"02",X"0D",X"0F",X"00",X"0D",X"0E", + X"0F",X"0E",X"0F",X"00",X"0F",X"00",X"07",X"0C",X"0F",X"00",X"0F",X"0E",X"0F",X"0B",X"02",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"02",X"0D",X"0F",X"00",X"02",X"0D",X"0F",X"00",X"0D",X"0E", + X"0F",X"0E",X"0F",X"00",X"0F",X"00",X"07",X"0C",X"0F",X"00",X"0F",X"0E",X"0F",X"01",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_rg.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_rg.vhd new file mode 100644 index 00000000..c23d6a8e --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_palette_rg.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_palette_rg is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_palette_rg is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0F",X"0F",X"0F",X"0F",X"08",X"07",X"00",X"0F",X"08",X"07",X"00",X"0F",X"09",X"00",X"08", + X"0F",X"00",X"0A",X"08",X"0F",X"0A",X"0F",X"07",X"0F",X"08",X"0A",X"08",X"0F",X"09",X"04",X"0A", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"08",X"07",X"00",X"0F",X"08",X"07",X"00",X"0F",X"09",X"00",X"08", + X"0F",X"00",X"0A",X"08",X"0F",X"0A",X"0F",X"07",X"0F",X"08",X"0A",X"08",X"0F",X"0D",X"08",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_1.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_1.vhd new file mode 100644 index 00000000..c65e8fe9 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_sp_bits_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_sp_bits_1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"11",X"01",X"11",X"01",X"11",X"10",X"10",X"18",X"18",X"10",X"30",X"30",X"03",X"00",X"00",X"00", + X"01",X"09",X"11",X"21",X"11",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_2.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_2.vhd new file mode 100644 index 00000000..f5957114 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_2.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_sp_bits_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_sp_bits_2 is + type rom is array(0 to 4095) of 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Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_3.vhd new file mode 100644 index 00000000..8367a005 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_3.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_sp_bits_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_sp_bits_3 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"06",X"06",X"06",X"06",X"06",X"02",X"10",X"08",X"08",X"00",X"20",X"20",X"00",X"03",X"01",X"00", + X"06",X"0E",X"06",X"26",X"06",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_4.vhd b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_4.vhd new file mode 100644 index 00000000..715d6ab7 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/rom/skyskip_sp_bits_4.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity skyskip_sp_bits_4 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of skyskip_sp_bits_4 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"C7",X"8F",X"FF",X"FD",X"F9",X"69",X"09",X"09",X"09",X"08",X"08",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"FC",X"F8",X"78",X"2C",X"2F",X"27",X"FF",X"FF",X"FF",X"E0",X"C0",X"E0",X"FF",X"FF", + X"00",X"00",X"FC",X"F8",X"78",X"2C",X"2F",X"27",X"FF",X"FF",X"FF",X"E0",X"C0",X"E0",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"E0",X"F0",X"FC",X"81", + X"C3",X"FE",X"F0",X"F0",X"F0",X"F6",X"F6",X"70",X"70",X"30",X"3E",X"1C",X"00",X"00",X"00",X"00", + X"FF",X"97",X"F3",X"FF",X"FF",X"FF",X"22",X"22",X"22",X"24",X"44",X"44",X"00",X"FF",X"FE",X"00", + X"FF",X"97",X"F3",X"FF",X"FF",X"FF",X"22",X"22",X"22",X"24",X"44",X"44",X"00",X"FF",X"FE",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/sdram.sv b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/sdram.sv new file mode 100644 index 00000000..2f65ee17 --- /dev/null +++ b/Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/sdram.sv @@ -0,0 +1,323 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output [15:0] port1_q, + + input [15:1] cpu1_addr, + output reg [15:0] cpu1_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output [15:0] port2_q, + + input [15:1] gfx_addr, + output reg [15:0] gfx_q +); + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz +localparam RFRSH_CYCLES = 10'd842; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 cas1 + 1 ras0 + 2 CAS0 data1 returned + 3 RAS1 cas0 + 4 ras1 + 5 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5 +localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_LAST = 3'd5; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [15:1] addr_last[2]; +reg [15:1] addr_last2[2]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_REQ = 2'd2; + +localparam PORT_GFX = 2'd1; + +reg [2:0] next_port[2]; +reg [2:0] port[2]; + +reg refresh; +reg [10:0] refresh_cnt; +wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end else if (port1_req ^ port1_ack) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1]) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 9'd0, cpu1_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT2: bank 2,3 +always @(*) begin + if (port2_req ^ port2_ack) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (gfx_addr != addr_last2[PORT_GFX]) begin + next_port[1] = PORT_GFX; + addr_latch_next[1] = { 1'b1, 8'd0, gfx_addr }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 1'b0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][15:1]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end + + if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin + refresh <= 1'b1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + default: ; + endcase; + end + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end + PORT_GFX: begin gfx_q <= sd_din; end + default: ; + endcase; + end + end +end + +endmodule