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Add Mr Do Project Files

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Marcel
2021-03-28 19:11:04 +02:00
parent f4ef413666
commit abbd67ef94
29 changed files with 6701 additions and 2 deletions
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4
common/CPU/T80/T80.vhd
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@@ -118,6 +118,7 @@ entity T80 is
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
RETI_n : out std_logic;
Stop : out std_logic;
R800_mode : in std_logic := '0';
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
@@ -424,8 +425,11 @@ begin
PreserveC_r <= '0';
XY_Ind <= '0';
I_RXDD <= '0';
RETI_n <= '1';
elsif rising_edge(CLK_n) then
RETI_n <= not I_RETN;
if DIRSet = '1' then
ACC <= DIR( 7 downto 0);

1
common/CPU/T80/T80_Pack.vhd
View File

@@ -104,6 +104,7 @@ package T80_Pack is
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
RETI_n : out std_logic;
Stop : out std_logic;
R800_mode : in std_logic := '0';
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255

8
common/CPU/T80/T80se.vhd
View File

@@ -96,7 +96,9 @@ entity T80se is
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
DO : out std_logic_vector(7 downto 0);
IntE : out std_logic;
RETI_n : out std_logic
);
end T80se;
@@ -137,7 +139,9 @@ begin
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
IntCycle_n => IntCycle_n,
IntE => IntE,
RETI_n => RETI_n);
process (RESET_n, CLK_n)
begin