diff --git a/Console_MiST/GCE - Vectrex_MiST/Snapshot/vectrex_MiST.rbf b/Console_MiST/GCE - Vectrex_MiST/Snapshot/vectrex_MiST.rbf deleted file mode 100644 index 8509c3b3..00000000 Binary files a/Console_MiST/GCE - Vectrex_MiST/Snapshot/vectrex_MiST.rbf and /dev/null differ diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd b/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd deleted file mode 100644 index 83d1861e..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 9 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv index c2f81503..abdd2e61 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv @@ -189,7 +189,8 @@ mist_video #(.COLOR_DEPTH(4)) mist_video .SPI_DI(SPI_DI), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), - .scandoubler_disable(1), + .scandoubler_disable(1'b1), + .ce_divider(1'b1), .rotate(2'b00), .ypbpr(ypbpr), .HSync(hs), @@ -198,7 +199,7 @@ mist_video #(.COLOR_DEPTH(4)) mist_video .G(g), .B(b), .VGA_HS(VGA_HS), - .VGA_VS(VGS_VS), + .VGA_VS(VGA_VS), .VGA_R(VGA_R), .VGA_G(VGA_G), .VGA_B(VGA_B) diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf index 25908bfe..900dffd9 100644 --- a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf +++ b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" @@ -353,7 +353,6 @@ set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd set_global_assignment -name VHDL_FILE rtl/m6522a.vhd set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd -set_global_assignment -name VHDL_FILE rtl/dac.vhd set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VERILOG_FILE rtl/mc6809is.v set_global_assignment -name VERILOG_FILE rtl/mc6809.v diff --git a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.srf b/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.srf deleted file mode 100644 index 1c9355aa..00000000 --- a/Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.srf +++ /dev/null @@ -1,13 +0,0 @@ -{ "" "" "" "Verilog HDL or VHDL warning at vectrex.vhd(417): conditional expression evaluates to a constant" { } { } 0 10037 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "VHDL Signal Declaration warning at vectrex.vhd(126): used implicit default value for signal \"video_csync\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { } 0 10541 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10873 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10541 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13004 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/common/mist/cofi.sv b/common/mist/cofi.sv index 34f12ba8..828a9f0d 100644 --- a/common/mist/cofi.sv +++ b/common/mist/cofi.sv @@ -36,7 +36,8 @@ reg [5:0] red_last; reg [5:0] green_last; reg [5:0] blue_last; -always @(posedge clk) if (pix_ce) begin +wire ce = enable ? pix_ce : 1'b1; +always @(posedge clk) if (ce) begin hblank_out <= hblank; vblank_out <= vblank;