diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.qsf b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.qsf index b02fdbd1..cb514c34 100644 --- a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.qsf +++ b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.qsf @@ -67,7 +67,7 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 # ================== set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_NCE_PIN OFF @@ -178,4 +178,14 @@ set_global_assignment -name VERILOG_FILE rtl/osd.v set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VERILOG_FILE rtl/mist_io.v set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.sdc b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.sdc new file mode 100644 index 00000000..2b0e4f93 --- /dev/null +++ b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.sdc @@ -0,0 +1,47 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# Clock groups +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important. +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}] + +set_multicycle_path -to {VGA_*[*]} -setup 4 +set_multicycle_path -to {VGA_*[*]} -hold 3 + +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -to [get_ports {LED}] diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/ComputerSpace_MiST.sv b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/ComputerSpace_MiST.sv index 27c17a85..6d973136 100644 --- a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/ComputerSpace_MiST.sv +++ b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/ComputerSpace_MiST.sv @@ -41,19 +41,15 @@ wire clk_sys, clk_25, clk_6p25, clk_5; pll pll( .inclk0(CLOCK_27), - .c0(clk_sys),//50 - .c1(clk_25), - .c2(clk_6p25), - .c3(clk_5) + .c0(clk_sys),//50 for game/sound generator? + .c1(clk_25), //4x pixel clock + .c3(clk_5) //5,842 MHz pixel/game clock ); -video_mixer #( - .LINE_LENGTH(254), - .HALF_DEPTH(0)) -video_mixer( +video_mixer video_mixer( .clk_sys(clk_25), - .ce_pix(clk_6p25), - .ce_pix_actual(clk_6p25), + .ce_pix(clk_5), + .ce_pix_actual(clk_5), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), @@ -79,7 +75,7 @@ video_mixer( mist_io #( .STRLEN(($size(CONF_STR)>>3))) mist_io( - .clk_sys (clk_25 ), + .clk_sys (clk_sys ), .conf_str (CONF_STR ), .SPI_SCK (SPI_SCK ), .CONF_DATA0 (CONF_DATA0 ), @@ -157,9 +153,9 @@ assign rm = rs + ro + rc; assign gm = gs + go + gc; assign bm = bs + bo + bc; -assign r = (rm[5:4] ? 4'b1111 : rm[3:0]) ^ {4{inv}}; -assign g = (gm[5:4] ? 4'b1111 : gm[3:0]) ^ {4{inv}}; -assign b = (bm[5:4] ? 4'b1111 : bm[3:0]) ^ {4{inv}}; +assign r = blank ? 0 : (rm[5:4] ? 4'b1111 : rm[3:0]) ^ {4{inv}}; +assign g = blank ? 0 : (gm[5:4] ? 4'b1111 : gm[3:0]) ^ {4{inv}}; +assign b = blank ? 0 : (bm[5:4] ? 4'b1111 : bm[3:0]) ^ {4{inv}}; reg inv; always @(posedge clk_5) begin diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/pll.v b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/pll.v index 97a976a4..a8e15cb7 100644 --- a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/pll.v @@ -40,30 +40,26 @@ module pll ( inclk0, c0, c1, - c2, c3); input inclk0; output c0; output c1; - output c2; output c3; wire [4:0] sub_wire0; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire6 = 1'h0; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [3:3] sub_wire2 = sub_wire0[3:3]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire c3 = sub_wire2; wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( - .inclk (sub_wire6), + .inclk (sub_wire5), .clk (sub_wire0), .activeclock (), .areset (1'b0), @@ -106,17 +102,13 @@ module pll ( altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 50, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, + altpll_component.clk1_divide_by = 188, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 20, + altpll_component.clk1_multiply_by = 163, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 108, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 25, - altpll_component.clk2_phase_shift = "0", - altpll_component.clk3_divide_by = 27, + altpll_component.clk3_divide_by = 752, altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 5, + altpll_component.clk3_multiply_by = 163, altpll_component.clk3_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, @@ -152,7 +144,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_USED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -191,17 +183,14 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108" -// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "752" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "752" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.250000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "5.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "23.409575" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "5.852394" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -223,40 +212,32 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" -// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "5" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "652" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "163" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.25000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "5.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "5.84200000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" @@ -281,18 +262,15 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" @@ -302,17 +280,13 @@ endmodule // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "188" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "163" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "752" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "163" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" @@ -347,7 +321,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -365,14 +339,12 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/scan_counter.vhd b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/scan_counter.vhd index f7d666ed..7dd81039 100644 --- a/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/scan_counter.vhd +++ b/Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/scan_counter.vhd @@ -165,6 +165,7 @@ if rising_edge (game_clk) then hblank <= '1'; if vcount = 239 then vblank <= '1'; end if; + if vcount = 252 then vsync <= '1'; end if; if vcount < 254 then -- Increase vertical count vcount <= vcount + 1; @@ -178,6 +179,7 @@ if rising_edge (game_clk) then else vcount <= 1; vblank <= '0'; + vsync <= '0'; ver_scan_q <= "00000001"; f1_15 <= '0'; star_enable <= '0'; @@ -204,10 +206,6 @@ f1_12 <= ver_scan_q(6); ----------------------------------------------------------------------------- b2_6 <= not f1_15; ------------------------------------------------------------------------------ --- CREATING THE SYNC SIGNAL -- ------------------------------------------------------------------------------ -vsync <= vblank; ----------------------------------------------------------------------------- -- COUNT ENABLE & BLANK --