diff --git a/Arcade_MiST/Konami ScooterShooter/README.md b/Arcade_MiST/Konami ScooterShooter/README.md new file mode 100644 index 00000000..37744952 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/README.md @@ -0,0 +1,11 @@ +# MiST port of Konami Scooter Shooter by ACE + +https://github.com/MiSTer-devel/Arcade-ScooterShooter_MiSTer + +## Usage + +- Create ROM and ARC files from the MRA files using the MRA utility. + Example: mra -A -z /path/to/mame/roms "Scooter Shooter.mra" +- Copy the ROM files to the root of the SD Card +- Copy the RBF and ARC files to the same folder on the SD Card +- MRA utility: https://github.com/sebdel/mra-tools-c/ \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/Scotrsht.qpf b/Arcade_MiST/Konami ScooterShooter/Scotrsht.qpf new file mode 100644 index 00000000..6eb1f1a5 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/Scotrsht.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 00:21:03 December 03, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "00:21:03 December 03, 2019" + +# Revisions + +PROJECT_REVISION = "Scotrsht" + diff --git a/Arcade_MiST/Konami ScooterShooter/Scotrsht.qsf b/Arcade_MiST/Konami ScooterShooter/Scotrsht.qsf new file mode 100644 index 00000000..47ece6e6 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/Scotrsht.qsf @@ -0,0 +1,258 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 19:54:12 November 22, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Scotrsht_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY ScooterShooter_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/sdram.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------------ +# start ENTITY(Finalizer_MiST) + + # Pin & Location Assignments + # ========================== + + # Fitter Assignments + # ================== + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Finalizer_MiST) +# ---------------------------- +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VERILOG_MACRO "EXT_ROM=" +set_global_assignment -name FORCE_SYNCH_CLEAR ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ScooterShooter_MiST.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ScooterShooter.sv +set_global_assignment -name VERILOG_FILE rtl/audio_iir_filter.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sshooter_fm_lpf.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sshooter_ssg_lpf.sv +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom_loader.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/k005849.sv +set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v +set_global_assignment -name VERILOG_FILE rtl/jt49_dcrm2.v +set_global_assignment -name VHDL_FILE rtl/dpram_dc.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT12/hdl/jt03.qip +set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip +set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/Scotrsht.sdc b/Arcade_MiST/Konami ScooterShooter/Scotrsht.sdc new file mode 100644 index 00000000..8ca54672 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/Scotrsht.sdc @@ -0,0 +1,137 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +set_multicycle_path -from {ScooterShooter:ScooterShooter_inst|mc6809is:u12A|*} -setup 2 +set_multicycle_path -from {ScooterShooter:ScooterShooter_inst|mc6809is:u12A|*} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Konami ScooterShooter/meta/Scooter Shooter.mra b/Arcade_MiST/Konami ScooterShooter/meta/Scooter Shooter.mra new file mode 100644 index 00000000..7d7b0fa8 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/meta/Scooter Shooter.mra @@ -0,0 +1,69 @@ + + Scooter Shooter + World + no + no + + + + + 1986 + Konami + Shooter - Horizontal + + scotrsht + scotrsht + 0224 + ScotrSht + + 15kHz + no + no + + 2 (simultaneous) + 8-way + + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0E 00 00 00 00 FF 00 02 + 00 02 00 01 00 FF 10 00 + 00 00 1C A0 00 46 01 1D + 00 00 19 9C 00 03 01 40 + + + + + + + + + 20210910141626 + diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter.sv b/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter.sv new file mode 100644 index 00000000..994abf19 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter.sv @@ -0,0 +1,623 @@ +//============================================================================ +// +// Scooter Shooter PCB model +// Copyright (C) 2021 Ace +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +//============================================================================ + +module ScooterShooter +( + input reset, + input clk_49m, //Actual frequency: 49.152MHz + input [1:0] coin, + input btn_service, + input [1:0] btn_start, //1 = Player 2, 0 = Player 1 + input [3:0] p1_joystick, p2_joystick, //3 = up, 2 = down, 1 = right, 0 = left + input p1_fire, + input p2_fire, + + input [19:0] dipsw, + + //This input serves to select a fractional divider to acheive 3.072MHz for the YM2203 depending on whether Scooter Shooter + //runs with original or underclocked timings to normalize sync frequencies + input underclock, + + //Screen centering (alters HSync and VSync timing of the Konami 005849 to reposition the video output) + input [3:0] h_center, v_center, + + output signed [15:0] sound, + output video_csync, + output video_hsync, video_vsync, + output video_vblank, video_hblank, + output ce_pix, + output [3:0] video_r, video_g, video_b, //12-bit RGB, 4 bits per color + + input [24:0] ioctl_addr, + input [7:0] ioctl_data, + input ioctl_wr, + + input pause, + + input [11:0] hs_address, + input [7:0] hs_data_in, + output [7:0] hs_data_out, + input hs_write_enable, + input hs_access_write, + //SDRAM signals + output reg [15:0] main_cpu_rom_addr, + input [7:0] main_cpu_rom_do, + output reg [14:0] sub_cpu_rom_addr, + input [7:0] sub_cpu_rom_do, + output reg [14:1] char1_rom_addr, + input [15:0] char1_rom_do, + output sp1_req, + input sp1_ack, + output [15:0] sp1_rom_addr, + input [15:0] sp1_rom_do +); + +//------------------------------------------------------- Signal outputs -------------------------------------------------------// + +//Output pixel clock enable +assign ce_pix = cen_6m; + +//------------------------------------------------- MiSTer data write selector -------------------------------------------------// + +//Instantiate MiSTer data write selector to generate write enables for loading ROMs into the FPGA's BRAM +wire ep1_cs_i, ep2_cs_i, ep3_cs_i, ep4_cs_i, ep5_cs_i, ep6_cs_i; +wire cp1_cs_i, cp2_cs_i, cp3_cs_i, tl_cs_i, sl_cs_i; +selector DLSEL +( + .ioctl_addr(ioctl_addr), + .ep1_cs(ep1_cs_i), + .ep2_cs(ep2_cs_i), + .ep3_cs(ep3_cs_i), + .ep4_cs(ep4_cs_i), + .ep5_cs(ep5_cs_i), + .ep6_cs(ep6_cs_i), + .tl_cs(tl_cs_i), + .sl_cs(sl_cs_i), + .cp1_cs(cp1_cs_i), + .cp2_cs(cp2_cs_i), + .cp3_cs(cp3_cs_i) +); + +//------------------------------------------------------- Clock division -------------------------------------------------------// + +//Generate 6.144MHz and (inverted) 3.072MHz clock enables (clock division is normally handled inside the Konami 005849) +//Also generate an extra clock enable for DC offset removal in the sound section +reg [6:0] div = 7'd0; +always_ff @(posedge clk_49m) begin + div <= div + 7'd1; +end +wire cen_6m = !div[2:0]; +wire cen_3m = !div[3:0]; +wire dcrm_cen = !div; + +//Generate E and Q clock enables for MC6809E (code adapted from Sorgelig's phase generator used in the MiSTer Vectrex core) +reg E, Q; +always_ff @(posedge clk_49m) begin + reg [1:0] clk_phase = 0; + E <= 0; + Q <= 0; + if(cen_6m) begin + clk_phase <= clk_phase + 1'd1; + case(clk_phase) + 2'b01: E <= 1; + 2'b10: Q <= 1; + endcase + end +end + +//Generate 3.072MHz clock enable for YM2203 to maintain consistent sound pitch when underclocked to normalize video timings +//(uses Jotego's fractional clock divider from JTFRAME) +wire cen_3m_adjust; +jtframe_frac_cen sound_cen +( + .clk(clk_49m), + .n(10'd50), + .m(10'd786), + .cen({1'bZ, cen_3m_adjust}) +); + +//------------------------------------------------------------ CPU -------------------------------------------------------------// + +//Main CPU (Motorola MC6809E - uses synchronous version of Greg Miller's cycle-accurate MC6809E made by Sorgelig) +wire [15:0] mc6809e_A; +wire [7:0] mc6809e_Dout; +wire mc6809e_rw, mc6809e_avma; + +`ifdef CPU09 +wire vma; +cpu09 u12G +( + .clk(~clk_49m), + .ce(E), + .rst(~reset), + .rw(mc6809e_rw), + .addr(mc6809e_A), + .vma(vma), + .data_in(mc6809e_Din), + .data_out(mc6809e_Dout), + .halt(0), + .irq(~irq), + .firq(~firq), + .nmi(~nmi) +); +`else +mc6809is u12A +( + .CLK(clk_49m), + .fallE_en(E), + .fallQ_en(Q), + .D(mc6809e_Din), + .DOut(mc6809e_Dout), + .ADDR(mc6809e_A), + .RnW(mc6809e_rw), + .AVMA(mc6809e_avma), + .nIRQ(irq), + .nFIRQ(firq), + .nNMI(nmi), + .nHALT(~pause), + .nRESET(reset), + .nDMABREQ(1) +); +reg vma; +always @(posedge clk_49m) if (E) vma <= mc6809e_avma; +`endif + +//Address decoding for MC6809E +wire cs_dip2 = ~n_iocs & (mc6809e_A[10:8] == 3'b001) & mc6809e_rw; +wire cs_dip3 = ~n_iocs & (mc6809e_A[10:8] == 3'b010) & mc6809e_rw; +wire cs_palettelatch = ~n_iocs & (mc6809e_A[10:8] == 3'b000) & ~mc6809e_rw; +wire cs_soundlatch = ~n_iocs & (mc6809e_A[10:8] == 3'b001) & ~mc6809e_rw; +wire cs_controls_dip1 = ~n_iocs & (mc6809e_A[10:8] == 3'b011) & mc6809e_rw; +wire cs_k005849 = (mc6809e_A[15:14] == 2'b00); +wire cs_rom1 = (mc6809e_A[15:14] == 2'b01 || mc6809e_A[15:14] == 2'b10) & mc6809e_rw; +wire cs_rom2 = (mc6809e_A[15:14] == 2'b11) & mc6809e_rw; +//Multiplex data inputs to MC6809E +wire [7:0] mc6809e_Din = cs_dip2 ? dipsw[15:8]: + cs_dip3 ? {4'hF, dipsw[19:16]}: + cs_controls_dip1 ? controls_dip1: + (cs_k005849 & n_iocs & mc6809e_rw) ? k005849_D: + cs_rom1 ? eprom1_D: + cs_rom2 ? eprom2_D: + 8'hFF; + +//Game ROMs +`ifdef EXT_ROM +always_ff @(negedge clk_49m) + if (|mc6809e_A[15:14] & mc6809e_rw & vma) + main_cpu_rom_addr <= {&mc6809e_A[15:14], ~mc6809e_A[15] & mc6809e_A[14], mc6809e_A[13:0]}; + +wire [7:0] eprom1_D = main_cpu_rom_do; +wire [7:0] eprom2_D = main_cpu_rom_do; +`else +wire [7:0] eprom1_D; +eprom_1 u12C +( + .ADDR(mc6809e_A[14:0]), + .CLK(clk_49m), + .DATA(eprom1_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep1_cs_i), + .WR(ioctl_wr) +); +wire [7:0] eprom2_D; +eprom_2 u10C +( + .ADDR(mc6809e_A[13:0]), + .CLK(clk_49m), + .DATA(eprom2_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep2_cs_i), + .WR(ioctl_wr) +); +`endif + +//Palette latch +reg [7:0] pal_latch = 8'd0; +always_ff @(posedge clk_49m) begin + if(!reset) + pal_latch <= 8'd0; + else if(cen_3m) begin + if(cs_palettelatch) + pal_latch <= mc6809e_Dout; + end +end +wire [2:0] palette_bank = pal_latch[6:4]; + +//Sound latch +reg [7:0] sound_data = 8'd0; +always_ff @(posedge clk_49m) begin + if(cen_3m && cs_soundlatch) + sound_data <= mc6809e_Dout; +end + +//Sound IRQ trigger +reg sound_irq = 1; +always_ff @(posedge clk_49m) begin + if(cen_3m) begin + if(cs_soundlatch) + sound_irq <= 1; + else + sound_irq <= 0; + end +end + +//Sound CPU - Zilog Z80 (uses T80s variant of the T80 soft core) +wire z80_n_m1, z80_n_mreq, z80_n_iorq, z80_n_rfsh, z80_n_rd, z80_n_wr; +wire [15:0] z80_A; +wire [7:0] z80_Din, z80_Dout; +T80s u7A +( + .RESET_n(reset), + .CLK(clk_49m), + .CEN(cen_sound), + .INT_n(z80_n_int), + .MREQ_n(z80_n_mreq), + .IORQ_n(z80_n_iorq), + .RD_n(z80_n_rd), + .WR_n(z80_n_wr), + .M1_n(z80_n_m1), + .RFSH_n(z80_n_rfsh), + .A(z80_A), + .DI(z80_Din), + .DO(z80_Dout) +); +//Address decoding for data inputs to Z80 +wire z80_decode_en = (z80_n_rfsh & ~z80_n_mreq); +wire soundrom_cs = z80_decode_en & (z80_A[15:14] == 2'b00); +wire soundram_cs = z80_decode_en & (z80_A[15:14] == 2'b01); +wire sounddata_cs = z80_decode_en & (z80_A[15:14] == 2'b10); +//Multiplex data inputs to Z80 +assign z80_Din = soundrom_cs ? eprom3_D: + (soundram_cs & ~z80_n_rd) ? soundram_D: + sounddata_cs ? sound_data: + (~z80_n_iorq & ~z80_n_rd) ? ym2203_D: + 8'hFF; + +//Sound ROM +`ifdef EXT_ROM +wire [7:0] eprom3_D = sub_cpu_rom_do; +always_ff @(posedge clk_49m) + if (soundrom_cs) sub_cpu_rom_addr <= z80_A[13:0]; +`else +wire [7:0] eprom3_D; +eprom_3 u8C +( + .ADDR(z80_A[13:0]), + .CLK(clk_49m), + .DATA(eprom3_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep3_cs_i), + .WR(ioctl_wr) +); +`endif + +//Sound RAM +wire [7:0] soundram_D; +spram #(8, 11) u9C +( + .clk(clk_49m), + .we(soundram_cs & ~z80_n_wr), + .addr(z80_A[10:0]), + .data(z80_Dout), + .q(soundram_D) +); + +//Generate sound IRQ +wire sirq_clr = (~reset | ~(z80_n_m1 | z80_n_iorq)); +reg z80_n_int = 1; +always_ff @(posedge clk_49m or posedge sirq_clr) begin + if(sirq_clr) + z80_n_int <= 1; + else if(cen_sound && sound_irq) + z80_n_int <= 0; +end + + +//--------------------------------------------------- Controls & DIP switches --------------------------------------------------// + +//Multiplex player inputs and DIP switch bank 1 +wire [7:0] controls_dip1 = (mc6809e_A[1:0] == 2'b00) ? {3'b111, btn_start, btn_service, coin}: + (mc6809e_A[1:0] == 2'b01) ? {3'b111, p1_fire, p1_joystick}: + (mc6809e_A[1:0] == 2'b10) ? {3'b111, p2_fire, p2_joystick}: + (mc6809e_A[1:0] == 2'b11) ? dipsw[7:0]: + 8'hFF; + +//--------------------------------------------------- Video timing & graphics --------------------------------------------------// + +//Konami 005849 custom chip - this is a large ceramic pin-grid array IC responsible for the majority of Scooter Shooter's critical +//functions: IRQ generation, clock dividers and all video logic for generating tilemaps and sprites +wire [15:0] spriterom_A; +wire [15:0] tilerom_A; +wire [7:0] k005849_D, tilemap_lut_A, sprite_lut_A; +wire [4:0] color_A; +wire [1:0] h_cnt; +wire n_iocs, irq, firq, nmi; +k005849 u8E +( + .CK49(clk_49m), + .RES(reset), + .READ(~mc6809e_rw), + .A(mc6809e_A[13:0]), + .DBi(mc6809e_Dout), + .DBo(k005849_D), + .VCF(tilemap_lut_A[7:4]), + .VCB(tilemap_lut_A[3:0]), + .VCD(tilemap_lut_D), + .OCF(sprite_lut_A[7:4]), + .OCB(sprite_lut_A[3:0]), + .OCD(sprite_lut_D), + .COL(color_A), + .XCS(~cs_k005849), + .BUSE(0), + .SYNC(video_csync), + .HSYC(video_hsync), + .VSYC(video_vsync), + .HBLK(video_hblank), + .VBLK(video_vblank), + .FIRQ(firq), + .IRQ(irq), + .NMI(nmi), + .IOCS(n_iocs), + .R(tilerom_A), + .S(spriterom_A), + .S_req(sp1_req), + .S_ack(sp1_ack), + .RD(eprom4_D), + .SD(spriterom_D), + .HCTR(h_center), + .VCTR(v_center), + .SPFL(1), + + .hs_address(hs_address), + .hs_data_out(hs_data_out), + .hs_data_in(hs_data_in), + .hs_write_enable(hs_write_enable), + .hs_access_write(hs_access_write) +); + +//Graphics ROMs +`ifdef EXT_ROM +assign sp1_rom_addr = spriterom_A[15:0]; +wire [7:0] spriterom_D = spriterom_A[0] ? sp1_rom_do[15:8] : sp1_rom_do[7:0]; +assign char1_rom_addr = {tilerom_A[15], tilerom_A[13:1]}; +wire [7:0] eprom4_D = tilerom_A[0] ? char1_rom_do[15:8] : char1_rom_do[7:0]; +`else +wire [7:0] eprom4_D; +eprom_4 u5F +( + .ADDR({tilerom_A[15], tilerom_A[13:0]}), + .CLK(clk_49m), + .DATA(eprom4_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep4_cs_i), + .WR(ioctl_wr) +); +wire [7:0] eprom5_D, eprom6_D; + +eprom_5 u6F +( + .ADDR(spriterom_A[14:0]), + .CLK(~clk_49m), + .DATA(eprom5_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep5_cs_i), + .WR(ioctl_wr) +); + +eprom_6 u4F +( + .ADDR(spriterom_A[14:0]), + .CLK(~clk_49m), + .DATA(eprom6_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(ep6_cs_i), + .WR(ioctl_wr) +); + +//Multiplex sprite ROMs +wire [7:0] spriterom_D = spriterom_A[15] ? eprom6_D : eprom5_D; +`endif + +//Tilemap LUT PROM +wire [3:0] tilemap_lut_D; +tile_lut_prom u7F +( + .ADDR(tilemap_lut_A), + .CLK(clk_49m), + .DATA(tilemap_lut_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(tl_cs_i), + .WR(ioctl_wr) +); + +//Sprite LUT PROM +wire [3:0] sprite_lut_D; +sprite_lut_prom u8F +( + .ADDR(sprite_lut_A), + .CLK(clk_49m), + .DATA(sprite_lut_D), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(sl_cs_i), + .WR(ioctl_wr) +); + +//--------------------------------------------------------- Sound chips --------------------------------------------------------// + +//Select whether to use a fractional or integer clock divider for the YM2203 to maintain consistent sound pitch at both original +//and underclocked timings +wire cen_sound = underclock ? cen_3m_adjust : cen_3m; + +//Sound chip (Yamaha YM2203 - uses JT03 implementation by Jotego) +wire [2:0] filter_en; +wire [7:0] ym2203_D; +wire [7:0] ym2203_ssgA_raw, ym2203_ssgB_raw, ym2203_ssgC_raw; +wire signed [15:0] ym2203_fm_raw; + +jt03 u4D +( + .rst(~reset), + .clk(clk_49m), + .cen(cen_sound), + .din(z80_Dout), + .dout(ym2203_D), + .IOA_out({5'bZZZZZ, filter_en}), + .addr(z80_A[0]), + .cs_n(z80_n_iorq), + .wr_n(z80_n_wr), + .psg_A(ym2203_ssgA_raw), + .psg_B(ym2203_ssgB_raw), + .psg_C(ym2203_ssgC_raw), + .fm_snd(ym2203_fm_raw) +); + +//----------------------------------------------------- Final video output -----------------------------------------------------// + +//Scooter Shooter's final video output consists of three PROMs, one per color, addressed by the 005849 custom tilemap generator +//and palette latch +color_prom_1 u1F +( + .ADDR({color_A[4], palette_bank, color_A[3:0]}), + .CLK(clk_49m), + .DATA(video_r), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(cp1_cs_i), + .WR(ioctl_wr) +); +color_prom_2 u2F +( + .ADDR({color_A[4], palette_bank, color_A[3:0]}), + .CLK(clk_49m), + .DATA(video_g), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(cp2_cs_i), + .WR(ioctl_wr) +); +color_prom_3 u3F +( + .ADDR({color_A[4], palette_bank, color_A[3:0]}), + .CLK(clk_49m), + .DATA(video_b), + .ADDR_DL(ioctl_addr), + .CLK_DL(clk_49m), + .DATA_IN(ioctl_data), + .CS_DL(cp3_cs_i), + .WR(ioctl_wr) +); + +//----------------------------------------------------- Final audio output -----------------------------------------------------// + +//Scooter Shooter uses a 4.823KHz low-pass filter for the FM side of its YM2203 - filter the audio accordingly here. +wire signed [15:0] ym2203_fm_lpf; +sshooter_fm_lpf lpf_fm +( + .clk(clk_49m), + .reset(~reset), + .in(ym2203_fm_raw), + .out(ym2203_fm_lpf) +); + +//Scooter Shooter also uses 3 switchable low-pass filters on the SSG side of its YM2203 with a cutoff frequency of +//723.432Hz (actually closer to 492.130Hz due to internal resistance inside the 74HC4066 handling the filter switching). +//Model the switchable filters here. +wire signed [15:0] ym2203_ssgA_lpf, ym2203_ssgB_lpf, ym2203_ssgC_lpf; +sshooter_ssg_lpf lpf_ssgA +( + .clk(clk_49m), + .reset(~reset), + .in(ym2203_ssgA_dcrm), + .out(ym2203_ssgA_lpf) +); +sshooter_ssg_lpf lpf_ssgB +( + .clk(clk_49m), + .reset(~reset), + .in(ym2203_ssgB_dcrm), + .out(ym2203_ssgB_lpf) +); +sshooter_ssg_lpf lpf_ssgC +( + .clk(clk_49m), + .reset(~reset), + .in(ym2203_ssgC_dcrm), + .out(ym2203_ssgC_lpf) +); + +//Remove DC offset from SSG outputs and apply gain to prevent losing quiet sounds after low-pass filtering +wire signed [15:0] ym2203_ssgA_dcrm, ym2203_ssgB_dcrm, ym2203_ssgC_dcrm; +jt49_dcrm2 #(16) dcrm_ssgA +( + .clk(clk_49m), + .cen(dcrm_cen), + .rst(~reset), + .din({3'd0, ym2203_ssgA_raw, 5'd0}), + .dout(ym2203_ssgA_dcrm) +); +jt49_dcrm2 #(16) dcrm_ssgB +( + .clk(clk_49m), + .cen(dcrm_cen), + .rst(~reset), + .din({3'd0, ym2203_ssgB_raw, 5'd0}), + .dout(ym2203_ssgB_dcrm) +); +jt49_dcrm2 #(16) dcrm_ssgC +( + .clk(clk_49m), + .cen(dcrm_cen), + .rst(~reset), + .din({3'd0, ym2203_ssgC_raw, 5'd0}), + .dout(ym2203_ssgC_dcrm) +); + +//Apply the switchable low-pass filters and attenuate SSG outputs back to raw levels +wire signed [15:0] ym2203_ssgA = filter_en[2] ? ym2203_ssgA_lpf >>> 15'd5 : ym2203_ssgA_dcrm >>> 15'd5; +wire signed [15:0] ym2203_ssgB = filter_en[1] ? ym2203_ssgB_lpf >>> 15'd5 : ym2203_ssgB_dcrm >>> 15'd5; +wire signed [15:0] ym2203_ssgC = filter_en[0] ? ym2203_ssgC_lpf >>> 15'd5 : ym2203_ssgC_dcrm >>> 15'd5; + +//Mix all audio sources for the final output +assign sound = (ym2203_fm_lpf + (ym2203_ssgA * 15'd21) + (ym2203_ssgB * 15'd21) + (ym2203_ssgC * 15'd21)) <<< 15'd1; + +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter_MiST.sv b/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter_MiST.sv new file mode 100644 index 00000000..cbeb58f9 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/ScooterShooter_MiST.sv @@ -0,0 +1,316 @@ +module ScooterShooter_MiST ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE + +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "SCOTRSHT;;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blend,Off,On;", + "O6,Joystick Swap,Off,On;", + "O7,Service,Off,On;", + "O1,Pause,Off,On;", + "DIP;", + "T0,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire joyswap = status[6]; +wire service = status[7]; +wire pause = status[1]; + +wire [1:0] orientation = 2'b11; +wire [23:0] dip_sw = ~status[31:8]; + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clock_98; +assign SDRAM_CKE = 1; + +wire clock_98, clock_49, pll_locked; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_98), + .c1(clock_49),//49.152MHz + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire [6:0] core_mod; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_49 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .core_mod (core_mod ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +wire [15:0] main_rom_addr; +wire [15:0] main_rom_do; +wire [14:0] sub_rom_addr; +wire [15:0] sub_rom_do; +wire [15:1] ch1_addr; +wire [15:0] ch1_do; +wire sp1_req, sp1_ack; +wire [15:0] sp1_addr; +wire [15:0] sp1_do; + +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io data_io( + .clk_sys ( clock_49 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); +wire [24:0] bg_ioctl_addr = ioctl_addr - 17'h10000; + +reg port1_req, port2_req; +sdram #(98) sdram( + .*, + .init_n ( pll_locked ), + .clk ( clock_98 ), + + // port1 for CPUs + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_addr ( ioctl_downl ? 16'h0000 : main_rom_addr[15:1] ), + .cpu1_q ( main_rom_do ), + .cpu2_addr ( ioctl_downl ? 16'h0000 : sub_rom_addr[14:1] + 16'h6000 ), + .cpu2_q ( sub_rom_do ), + + // port2 for graphics + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_a ( bg_ioctl_addr[23:1] ), + .port2_ds ( {bg_ioctl_addr[0], ~bg_ioctl_addr[0]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .ch1_addr ( ioctl_downl ? 16'hffff : ch1_addr ), + .ch1_q ( ch1_do ), + .sp1_req ( sp1_req ), + .sp1_ack ( sp1_ack ), + .sp1_addr ( ioctl_downl ? 16'hffff : 16'h4000 + sp1_addr[15:1] ), + .sp1_q ( sp1_do ) +); + +// ROM download controller +always @(posedge clock_49) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clock_49) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded; +end + +wire [15:0] audio; +wire hs, vs, cs; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +wire [3:0] r, g, b; + +//Instantiate Scooter Shooter top-level module +ScooterShooter ScooterShooter_inst +( + .reset(~reset), // input reset + + .clk_49m(clock_49), // input clk_49m + + .coin({~m_coin2, ~m_coin1}), // input coin + .btn_service(~service), // input btn_service + + .btn_start({~m_two_players, ~m_one_player}), // input [1:0] btn_start + + // The game crashes when two opposite direction controls are held down. + // It's not possible with a physical controller, but it is via keyboard, + // so protect against this here. + .p1_joystick({~m_down | m_up, ~m_up, ~m_right | m_left, ~m_left}), + .p2_joystick({~m_down2 | m_up2, ~m_up2, ~m_right2 | m_left2, ~m_left2}), + .p1_fire(~m_fireA), + .p2_fire(~m_fire2A), + + .dipsw(dip_sw), // input [19:0] dipsw + + //Flag to signal that Scooter Shooter has been underclocked to normalize video timings in order to maintain consistent sound timings and pitch + .underclock(1'b0), + + .sound(audio), // output [15:0] sound + + .h_center(), // Screen centering + .v_center(), + + .video_hsync(hs), // output video_hsync + .video_vsync(vs), // output video_vsync + .video_vblank(vblank), // output video_vblank + .video_hblank(hblank), // output video_hblank + .ce_pix(ce_pix), // output ce_pix + + .video_r(r), // output [2:0] video_r + .video_g(g), // output [2:0] video_g + .video_b(b), // output [1:0] video_b + + .ioctl_addr(ioctl_addr), + .ioctl_wr(ioctl_wr && ioctl_index == 0), + .ioctl_data(ioctl_dout), + + .pause(pause), + + .hs_address(hs_address), + .hs_data_out(hs_data_out), + .hs_data_in(hs_data_in), + .hs_write_enable(hs_write_enable), + .hs_access_write(hs_access_write), + + .main_cpu_rom_addr(main_rom_addr), + .main_cpu_rom_do(main_rom_addr[0] ? main_rom_do[15:8] : main_rom_do[7:0]), + .sub_cpu_rom_addr(sub_rom_addr), + .sub_cpu_rom_do(sub_rom_addr[0] ? sub_rom_do[15:8] : sub_rom_do[7:0]), + .char1_rom_addr(ch1_addr), + .char1_rom_do(ch1_do), + .sp1_req(sp1_req), + .sp1_ack(sp1_ack), + .sp1_rom_addr(sp1_addr), + .sp1_rom_do(sp1_do) +); + +mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_49 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? b : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .ce_divider ( 0 ), + .rotate ( { orientation[1], rotate } ), + .blend ( blend ), + .scandoubler_disable( scandoublerD ), + .scanlines ( scanlines ), + .ypbpr ( ypbpr ), + .no_csync ( no_csync ) + ); + +wire audio_out; +assign AUDIO_L = audio_out; +assign AUDIO_R = audio_out; + +dac #(.C_bits(16))dac( + .clk_i(clock_49), + .res_n_i(1'b1), + .dac_i({~audio[15], audio[14:0]}), + .dac_o(audio_out) + ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; + +arcade_inputs inputs ( + .clk ( clock_49 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( orientation ), + .joyswap ( joyswap ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/audio_iir_filter.v b/Arcade_MiST/Konami ScooterShooter/rtl/audio_iir_filter.v new file mode 100644 index 00000000..ad324f04 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/audio_iir_filter.v @@ -0,0 +1,173 @@ +/*MIT License + +Copyright (c) 2019 Gregory Hogan (Soltan_G42) + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +module iir_1st_order +#( + parameter COEFF_WIDTH = 18, + parameter COEFF_SCALE = 15, + parameter DATA_WIDTH = 16, + parameter COUNT_BITS = 10 +) +( + input clk, + input reset, + input [COUNT_BITS - 1 : 0] div, + input signed [COEFF_WIDTH - 1 : 0] A2, B1, B2, + input signed [DATA_WIDTH - 1 :0] in, + output [DATA_WIDTH - 1:0] out +); + + reg signed [DATA_WIDTH-1:0] x0,x1,y0; + reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32; + reg [COUNT_BITS - 1:0] count; + + // Usage: + // Design your 1st order iir low/high-pass with a tool that will give you the + // filter coefficients for the difference equation. Filter coefficients can + // be generated in Octave/matlab/scipy using a command similar to + // [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass + // assuming 106528Hz sample rate. + // + // The Matlab output is: + // B = [0.093863 0.093863] + // A = [1.00000 -0.81227] + // + // Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer + // + // B = [3076 3076] + // A = [32768 -26616] + // + // Discard A(1) because it is assumed 1.0 before scaling + // + // This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076 + // B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768 + // + // Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz + // + // COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to + // handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0 + + assign out = y0; + + always @ (*) begin + out32 <= (B1*x0 + B2*x1) - A2*y0; //Previous output is y0 not y1 + end + + always @ (posedge clk) begin + if(reset) begin + count <= 0; + x0 <= 0; + x1 <= 0; + y0 <= 0; + end + else begin + count <= count + 1'd1; + if (count == div - 1) begin + count <= 0; + y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[COEFF_SCALE + DATA_WIDTH - 2 : COEFF_SCALE]}; + x1 <= x0; + x0 <= in; + end + end + end + +endmodule //iir_1st_order + +module iir_2nd_order +#( + parameter COEFF_WIDTH = 18, + parameter COEFF_SCALE = 14, + parameter DATA_WIDTH = 16, + parameter COUNT_BITS = 10 +) +( + input clk, + input reset, + input [COUNT_BITS - 1 : 0] div, + input signed [COEFF_WIDTH - 1 : 0] A2, A3, B1, B2, B3, + input signed [DATA_WIDTH - 1 : 0] in, + output [DATA_WIDTH - 1 : 0] out +); + + reg signed [DATA_WIDTH-1 : 0] x0,x1,x2; + reg signed [DATA_WIDTH-1 : 0] y0,y1; + reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32; + reg [COUNT_BITS : 0] count; + + + // Usage: + // Design your 1st order iir low/high-pass with a tool that will give you the + // filter coefficients for the difference equation. Filter coefficients can + // be generated in Octave/matlab/scipy using a command similar to + // [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass + // assuming 48000Hz sample rate. + // + // Output is: + // B = [ 0.072231 0.144462 0.072231] + // A = [1.00000 -1.10923 0.39815] + // + // Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer + // Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits. + // + // B = [1183 2367 1183] + // A = [16384 -18174 6523] + // + // Discard A(1) because it is assumed 1.0 before scaling + // + // This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183 + // B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384 + // + // Sample frequency is "clk rate/div" + // + // COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to + // handle temporary overflow during this computation: + // out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); + + assign out = y0; + + always @ (*) begin + out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); //Previous output is y0 not y1 + end + + always @ (posedge clk) begin + if(reset) begin + count <= 0; + x0 <= 0; + x1 <= 0; + x2 <= 0; + y0 <= 0; + y1 <= 0; + end + else begin + count <= count + 1'd1; + if (count == div - 1) begin + count <= 0; + y1 <= y0; + y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[(DATA_WIDTH + COEFF_SCALE - 2) : COEFF_SCALE]}; + x2 <= x1; + x1 <= x0; + x0 <= in; + end + end + end + +endmodule //iir_2nd_order \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/build_id.tcl b/Arcade_MiST/Konami ScooterShooter/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/dpram_dc.vhd b/Arcade_MiST/Konami ScooterShooter/rtl/dpram_dc.vhd new file mode 100644 index 00000000..69d4c5fb --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/dpram_dc.vhd @@ -0,0 +1,136 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram_dc IS + GENERIC + ( + init_file : string := " "; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0) := (others => '0'); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0'); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0'); + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1'); + byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1'); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram_dc; + + +ARCHITECTURE SYN OF dpram_dc IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ; + byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_a, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => width_a/8, + width_byteena_b => width_a/8, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1, + byteena_a => byteena_a, + byteena_b => byteena_b + ); + + + +END SYN; diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/jt49_dcrm2.v b/Arcade_MiST/Konami ScooterShooter/rtl/jt49_dcrm2.v new file mode 100644 index 00000000..4b434aec --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/jt49_dcrm2.v @@ -0,0 +1,62 @@ +/* This file is part of JT49. + + JT49 is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + JT49 is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with JT49. If not, see . + + Author: Jose Tejada Gomez. Twitter: @topapate + Version: 1.0 + Date: 15-Jan-2019 + + */ + +// DC removal filter +// input is unsigned +// output is signed + +module jt49_dcrm2 #(parameter sw=8) ( + input clk, + input cen, + input rst, + input [sw-1:0] din, + output signed [sw-1:0] dout +); + +localparam dw=10; // widht of the decimal portion + +reg signed [sw+dw:0] integ, exact, error; +//reg signed [2*(9+dw)-1:0] mult; +// wire signed [sw+dw:0] plus1 = { {sw+dw{1'b0}},1'b1}; +reg signed [sw:0] pre_dout; +// reg signed [sw+dw:0] dout_ext; +reg signed [sw:0] q; + +always @(*) begin + exact = integ+error; + q = exact[sw+dw:dw]; + pre_dout = { 1'b0, din } - q; + //dout_ext = { pre_dout, {dw{1'b0}} }; + //mult = dout_ext; +end + +assign dout = pre_dout[sw-1:0]; + +always @(posedge clk) + if( rst ) begin + integ <= {sw+dw+1{1'b0}}; + error <= {sw+dw+1{1'b0}}; + end else if( cen ) begin + integ <= integ + pre_dout; //mult[sw+dw*2:dw]; + error <= exact-{q, {dw{1'b0}}}; + end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/jtframe_frac_cen.v b/Arcade_MiST/Konami ScooterShooter/rtl/jtframe_frac_cen.v new file mode 100644 index 00000000..8707e766 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/jtframe_frac_cen.v @@ -0,0 +1,58 @@ +/////////////////////////////////////////////////////////////////////////// +// Fractional clock enable signal +// W refers to the number of divided down cen signals available +// each one is divided by 2 + +module jtframe_frac_cen #(parameter W=2)( + input clk, + input [9:0] n, // numerator + input [9:0] m, // denominator + output reg [W-1:0] cen, + output reg [W-1:0] cenb // 180 shifted +); + +wire [10:0] step={1'b0,n}; +wire [10:0] lim ={1'b0,m}; +wire [10:0] absmax = lim+step; + +reg [10:0] cencnt=11'd0; +reg [10:0] next; +reg [10:0] next2; + +always @(*) begin + next = cencnt+step; + next2 = next-lim; +end + +reg half = 1'b0; +wire over = next>=lim; +wire halfway = next >= (lim>>1) && !half; + +reg [W-1:0] edgecnt = {W{1'b0}}; +wire [W-1:0] next_edgecnt = edgecnt + 1'b1; +wire [W-1:0] toggle = next_edgecnt & ~edgecnt; + +always @(posedge clk) begin + cen <= {W{1'b0}}; + cenb <= {W{1'b0}}; + + if( cencnt >= absmax ) begin + // something went wrong: restart + cencnt <= 11'd0; + end else + if( halfway ) begin + half <= 1'b1; + cenb[0] <= 1'b1; + end + if( over ) begin + cencnt <= next2; + half <= 1'b0; + edgecnt <= next_edgecnt; + cen <= { toggle[W-2:0], 1'b1 }; + end else begin + cencnt <= next; + end +end + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/k005849.sv b/Arcade_MiST/Konami ScooterShooter/rtl/k005849.sv new file mode 100644 index 00000000..70458ede --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/k005849.sv @@ -0,0 +1,670 @@ +//============================================================================ +// +// SystemVerilog implementation of the Konami 005849 custom tilemap +// generator +// Adapted from Green Beret core Copyright (C) 2013, 2019 MiSTer-X +// Copyright (C) 2021 Ace +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +//============================================================================ + +//Note: This model of the 005849 cannot be used to replace an original 005849. + +module k005849 +( + input CK49, //49.152MHz clock input + output NCK2, //6.144MHz clock output + output X1S, //3.072MHz clock output + output H2, //1.576MHz clock output + output ER, //E clock for MC6809E + output QR, //Q clock for MC6809E + output EQ, //AND of E and Q clocks for MC6809E + input RES, //Reset input (actually an output on the original chip - active low) + input READ, //Read enable (active low) + input [13:0] A, //Address bus from CPU + input [7:0] DBi, //Data bus input from CPU + output [7:0] DBo, //Data output to CPU + output [3:0] VCF, //Color address to tilemap LUT PROM + output [3:0] VCB, //Tile index to tilemap LUT PROM + input [3:0] VCD, //Data input from tilemap LUT PROM + output [3:0] OCF, //Color address to sprite LUT PROM + output [3:0] OCB, //Sprite index to sprite LUT PROM + input [3:0] OCD, //Data input from sprite LUT PROM + output [4:0] COL, //Color data output from color mixer + input XCS, //Chip select (active low) + input BUSE, //Data bus enable (active low) + output SYNC, //Composite sync (active low) + output HSYC, //HSync (active low) - Not exposed on the original chip + output VSYC, //VSync (active low) + output HBLK, //HBlank (active high) - Not exposed on the original chip + output VBLK, //VBlank (active high) - Not exposed on the original chip + output FIRQ, //Fast IRQ output + output IRQ, //VBlank IRQ + output NMI, //Non-maskable IRQ + output IOCS, //I/O decoder enable (active low) + output CS80, //Chip select output for Konami 501 custom chip (active low) + + //Split sprite/tile busses + output reg [15:0] R, //Address output to graphics ROMs (tiles) + output [15:0] S, //Address output to graphics ROMs (sprites) + output reg S_req = 0, + input S_ack, + input [7:0] RD, //Tilemap ROM data + input [7:0] SD, //Sprite ROM data + + //Extra input for flipping the sprite bank bit (active low) + input SPFL, + + //Extra inputs for screen centering (alters HSync and VSync timing to reposition the video output) + input [3:0] HCTR, VCTR, + + //MiSTer high score system I/O + input [11:0] hs_address, + input [7:0] hs_data_in, + output [7:0] hs_data_out, + input hs_write_enable, + input hs_access_write +); + + + +//------------------------------------------------------- Signal outputs -------------------------------------------------------// + +//Generate IOCS output (active low) +assign IOCS = ~(~XCS & (A[13:12] == 2'b11)); + +//Generate chip enable for Konami 501 (active low) +assign CS80 = XCS; + +//Data output to CPU +assign DBo = BUSE ? 8'hFF: + cs_regs ? regs: + zram0_cs ? zram0_Dout: + zram1_cs ? zram1_Dout: + tileram_attrib_cs ? tileram_attrib_Dout: + tileram_code_cs ? tileram_code_Dout: + spriteram_cs ? spriteram_Dout: + 8'hFF; + +//------------------------------------------------------- Clock division -------------------------------------------------------// + +//Divide the incoming 49.152MHz clock to 6.144MHz and 3.072MHz +reg [4:0] div = 4'd0; +always_ff @(posedge CK49) begin + div <= div + 4'd1; +end +wire cen_6m = !div[2:0]; +assign NCK2 = div[2]; +assign X1S = h_cnt[0]; +assign H2 = h_cnt[1]; + +//The MC6809E requires two identical clocks with a 90-degree offset - assign these here +reg mc6809e_E = 0; +reg mc6809e_Q = 0; +always_ff @(posedge CK49) begin + reg [1:0] clk_phase = 0; + if(cen_6m) begin + clk_phase <= clk_phase + 1'd1; + case(clk_phase) + 2'b00: mc6809e_E <= 0; + 2'b01: mc6809e_Q <= 1; + 2'b10: mc6809e_E <= 1; + 2'b11: mc6809e_Q <= 0; + endcase + end +end +assign QR = mc6809e_Q; +assign ER = mc6809e_E; + +//Output EQ combines ER and QR together via an AND gate - assign this here +assign EQ = ER & QR; + +//-------------------------------------------------------- Video timings -------------------------------------------------------// + +//The horizontal and vertical counters are 9 bits wide - delcare them here +reg [8:0] h_cnt = 9'd0; +reg [8:0] v_cnt = 9'd0; + +//Increment horizontal counter on every falling edge of the pixel clock and increment vertical counter when horizontal counter +//rolls over +reg hblank = 0; +reg vblank = 0; + +reg frame_odd_even = 0; +reg hmask = 0; +always_ff @(posedge CK49) begin + if(cen_6m) begin + case(h_cnt) + 5: begin + hblank <= 0; + h_cnt <= h_cnt + 9'd1; + end + 13: begin + hmask <= 0; + h_cnt <= h_cnt + 9'd1; + end + //Blank the left-most and right-most 8 lines when the 005849's horizontal mask register bit + //(register 3 bit 7) is active + 253: begin + if(hmask_en) + hmask <= 1; + h_cnt <= h_cnt + 9'd1; + end + 261: begin + hblank <= 1; + h_cnt <= h_cnt + 9'd1; + end + 383: begin + h_cnt <= 0; + case(v_cnt) + 15: begin + vblank <= 0; + v_cnt <= v_cnt + 9'd1; + end + 239: begin + vblank <= 1; + frame_odd_even <= ~frame_odd_even; + v_cnt <= v_cnt + 9'd1; + end + 263: begin + v_cnt <= 9'd0; + end + default: v_cnt <= v_cnt + 9'd1; + endcase + end + default: h_cnt <= h_cnt + 9'd1; + endcase + end +end + +//Output HBlank and VBlank (both active high) +assign HBLK = hblank; +assign VBLK = vblank; + +//Generate horizontal sync and vertical sync (both active low) +assign HSYC = HCTR[3] ? ~(h_cnt >= 285 - ~HCTR[2:0] && h_cnt <= 316 - ~HCTR[2:0]) : ~(h_cnt >= 293 + HCTR[2:0] && h_cnt <= 324 + HCTR[2:0]); +assign VSYC = ~(v_cnt >= 254 - VCTR && v_cnt <= 261 - VCTR); +assign SYNC = HSYC ^ VSYC; + +//------------------------------------------------------------- IRQs -----------------------------------------------------------// +//Edge detection for VBlank and vertical counter bit 5 for IRQ generation +reg old_vblank, old_vcnt5; +always_ff @(posedge CK49) begin + old_vcnt5 <= v_cnt[5]; + old_vblank <= vblank; +end + +//IRQ (triggers every VBlank) +reg vblank_irq = 1; +always_ff @(posedge CK49) begin + if(!RES || !irq_mask) + vblank_irq <= 1; + else if(!old_vblank && vblank) + vblank_irq <= 0; +end + +assign IRQ = vblank_irq; + +//NMI (triggers every 32 scanlines) +reg nmi = 1; +always_ff @(posedge CK49) begin + if(!RES || !nmi_mask) + nmi <= 1; + else begin + if(old_vcnt5 && !v_cnt[5]) + nmi <= 0; + end +end +assign NMI = nmi; + +//FIRQ (triggers every second VBlank) +reg firq = 1; +always_ff @(posedge CK49) begin + if(!RES || !firq_mask) + firq <= 1; + else begin + if(frame_odd_even && !old_vblank && vblank) + firq <= 0; + end +end +assign FIRQ = firq; + +//----------------------------------------------------- Internal registers -----------------------------------------------------// + +//The 005849 has five 8-bit registers - handle these here +wire cs_regs = ~XCS & (A[13:12] == 2'b10) & (A[7:3] == 5'b01000); +reg [7:0] reg0, reg1, reg2, reg3, reg4; +//Write to the appropriate register +always_ff @(posedge CK49) begin + if(cs_regs && READ) begin + case(A[2:0]) + 3'b000: reg0 <= DBi; + 3'b001: reg1 <= DBi; + 3'b010: reg2 <= DBi; + 3'b011: reg3 <= DBi; + 3'b100: reg4 <= DBi; + default:; + endcase + end +end + +//Assign ZRAM scroll direction as bit 2 of register 2 +wire zram_scroll_dir = reg2[2]; + +//Assign tilemap bank as bit 0 of register 3 +wire tilemap_bank = reg3[0]; + +//Assign tile priority override as bit 6 of register 3 (this is used by Jailbreak to give full priority to sprites and override +//the layer priority set by bit 7 of the tilemap attribute) +wire tile_priority_override = reg3[6]; + +//Assign horizontal mask enable as bit 7 of register 3 (this bit, when enabled, masks the left-most and right-most 8 columns to +//reduce the active area from 256x224 to 240x224 +wire hmask_en = reg3[7]; + +//Assign IRQ masks and flipscreen from the lower 4 bits of register 4 +wire nmi_mask = reg4[0]; +wire irq_mask = reg4[1]; +wire firq_mask = reg4[2]; +wire flipscreen = reg4[3]; + +wire [7:0] regs = (A == 14'h2040) ? reg0: + (A == 14'h2041) ? reg1: + (A == 14'h2042) ? reg2: + (A == 14'h2043) ? reg3: + 8'hFF; + +//-------------------------------------------------------- Internal ZRAM -------------------------------------------------------// + +wire zram0_cs = ~XCS & (A[13:12] == 2'b10) & (A[7:0] >= 8'h00 && A[7:0] <= 8'h1F); +wire zram1_cs = ~XCS & (A[13:12] == 2'b10) & (A[7:0] >= 8'h20 && A[7:0] <= 8'h3F); + +//Address ZRAM with bits [7:3] of the tilemap horizontal or vertical position depending on whether line scroll or column scroll +//is in use +wire [4:0] zram_A = zram_scroll_dir ? tilemap_hpos[7:3] : tilemap_vpos[7:3]; +wire [7:0] zram0_D, zram1_D, zram0_Dout, zram1_Dout; +dpram_dc #(.widthad_a(5)) ZRAM0 +( + .clock_a(CK49), + .address_a(A[4:0]), + .data_a(DBi), + .q_a(zram0_Dout), + .wren_a(zram0_cs & READ), + + .clock_b(CK49), + .address_b(zram_A), + .q_b(zram0_D) +); +dpram_dc #(.widthad_a(5)) ZRAM1 +( + .clock_a(CK49), + .address_a(A[4:0]), + .data_a(DBi), + .q_a(zram1_Dout), + .wren_a(zram1_cs & READ), + + .clock_b(CK49), + .address_b(zram_A), + .q_b(zram1_D) +); + +//------------------------------------------------------------ VRAM ------------------------------------------------------------// + +//VRAM is external to the 005849 and combines multiple banks into a single 8KB RAM chip for tile attributes and data, and two sprite +//banks. For simplicity, this RAM has been made internal to the 005849 implementation and split into its constituent components. +wire tileram_attrib_cs = ~XCS & (A[13:11] == 3'b000); +wire tileram_code_cs = ~XCS & (A[13:11] == 3'b001); +wire spriteram_cs = ~XCS & (A[13:12] == 2'b01); + +wire [7:0] tileram_attrib_Dout, tileram_code_Dout, spriteram_Dout, tileram_attrib_D, tileram_code_D, spriteram_D; +//Tilemap +dpram_dc #(.widthad_a(11)) VRAM_TILEATTRIB +( + .clock_a(CK49), + .address_a(A[10:0]), + .data_a(DBi), + .q_a(tileram_attrib_Dout), + .wren_a(tileram_attrib_cs & READ), + + .clock_b(CK49), + .address_b(vram_A), + .q_b(tileram_attrib_D) +); +dpram_dc #(.widthad_a(11)) VRAM_TILECODE +( + .clock_a(CK49), + .address_a(A[10:0]), + .data_a(DBi), + .q_a(tileram_code_Dout), + .wren_a(tileram_code_cs & READ), + + .clock_b(CK49), + .address_b(vram_A), + .q_b(tileram_code_D) +); + +`ifndef MISTER_HISCORE +//Sprites +dpram_dc #(.widthad_a(12)) VRAM_SPR +( + .clock_a(CK49), + .address_a(A[11:0]), + .data_a(DBi), + .q_a(spriteram_Dout), + .wren_a(spriteram_cs & READ), + + .clock_b(~CK49), + .address_b(spriteram_A), + .q_b(spriteram_D) +); +`else +// Hiscore mux (this is only to be used with Jailbreak as its high scores are stored in sprite RAM) +// - Mirrored sprite RAM used to protect against corruption while retrieving highscore data +wire [11:0] VRAM_SPR_AD = hs_access_write ? hs_address : A[11:0]; +wire [7:0] VRAM_SPR_DIN = hs_access_write ? hs_data_in : DBi; +wire VRAM_SPR_WE = hs_access_write ? hs_write_enable : (spriteram_cs & READ); +//Sprites +dpram_dc #(.widthad_a(12)) VRAM_SPR +( + .clock_a(CK49), + .address_a(VRAM_SPR_AD), + .data_a(VRAM_SPR_DIN), + .q_a(spriteram_Dout), + .wren_a(VRAM_SPR_WE), + + .clock_b(~CK49), + .address_b(spriteram_A), + .q_b(spriteram_D) +); +//Sprite RAM shadow for highscore read access +dpram_dc #(.widthad_a(12)) VRAM_SPR_SHADOW +( + .clock_a(CK49), + .address_a(VRAM_SPR_AD), + .data_a(VRAM_SPR_DIN), + .wren_a(VRAM_SPR_WE), + + .clock_b(CK49), + .address_b(hs_address), + .q_b(hs_data_out) +); +`endif + + +//-------------------------------------------------------- Tilemap layer -------------------------------------------------------// + +//**The following code is the original tilemap renderer from MiSTerX's Green Beret core with some minor tweaks**// +//XOR horizontal and vertical counter bits with flipscreen bit +wire [8:0] hcnt_x = h_cnt ^ {9{flipscreen}}; +wire [8:0] vcnt_x = v_cnt ^ {9{flipscreen}}; + +//Generate tilemap position - horizontal position is the sum of the horizontal counter, vertical position is the vertical counter +// +wire [8:0] tilemap_hpos = {h_cnt[8], hcnt_x[7:0]} + (~zram_scroll_dir ? {zram1_D[0], zram0_D} : 9'd0); +wire [8:0] tilemap_vpos = vcnt_x + (zram_scroll_dir ? {zram1_D[0], zram0_D} : 9'd0); + +//Address output to tile section of VRAM +wire [10:0] vram_A = {tilemap_vpos[7:3], tilemap_hpos[8:3]}; + +//Tile index is a combination of the tilemap bank bit from the 005849's internal registers, attribute bits [7:6] and the actual +//tile code +wire [10:0] tile_index = {tilemap_bank, tileram_attrib_D[7:6], tileram_code_D}; + +//Tile color is held in the lower 4 bits of tileram attributes +wire [3:0] tile_color = tileram_attrib_D[3:0]; +reg [3:0] tile_color_r, tile_color_rr; +reg tile_attrib7_r, tile_attrib7_rr; +reg tile_hflip_r; +reg [7:0] RD_r; + +//Tile flip attributes are stored in bits 4 (horizontal) and 5 (vertical) +wire tile_hflip = tileram_attrib_D[4]; +wire tile_vflip = tileram_attrib_D[5]; + +always_ff @(posedge CK49) begin + if (cen_6m) begin + if (h_cnt[0]) begin + //Assign address outputs to tile ROM + R <= {tile_index, (tilemap_vpos[2:0] ^ {3{tile_vflip}}), (tilemap_hpos[2:1] ^ {2{tile_hflip}})}; + // Apply appropriate delay to flags + tile_hflip_r <= tile_hflip; + tile_color_r <= tile_color; + tile_color_rr <= tile_color_r; + tile_attrib7_r <= tileram_attrib_D[7]; + tile_attrib7_rr <= tile_attrib7_r; + RD_r <= RD; + end + end +end + +//Multiplex tilemap ROM data down from 8 bits to 4 using bit 0 of the horizontal position +wire [3:0] tile_pixel = (tilemap_hpos[0] ^ tile_hflip_r) ? RD_r[3:0] : RD_r[7:4]; + +//Retrieve tilemap select bit from the NOR of bit 7 of the tile attributes with the priority override bit +reg tilemap_en = 0; +always_ff @(posedge CK49) begin + if(cen_6m) begin + tilemap_en <= ~(tile_attrib7_rr | tile_priority_override); + end +end + +//Address output to tilemap LUT PROM +assign VCF = tile_color_rr; +assign VCB = tile_pixel; + +//Delay tilemap data by one horizontal line +reg [3:0] tilemap_D = 4'd0; +always_ff @(posedge CK49) begin + if(cen_6m) + tilemap_D <= VCD; +end + +//-------------------------------------------------------- Sprite layer --------------------------------------------------------// + +//The following code is the original sprite renderer from MiSTerX's Green Beret core with additional screen flipping support and +//some extra tweaks + +//Generate sprite position - horizontal position is the horizontal counter, vertical position is the vertical counter (offset by +//18, 17 when flipped, to properly position the sprite layer) +wire [8:0] sprite_hpos = h_cnt; +wire [8:0] sprite_vpos = flipscreen ? v_cnt + 9'd17 : v_cnt + 9'd18; + +//Sprite state machine +reg [5:0] sprite_index; +reg [1:0] sprite_offset; +reg [7:0] sprite_attrib0, sprite_attrib1, sprite_attrib2, sprite_attrib3; +reg [2:0] sprite_fsm_state; +always_ff @(posedge CK49) begin + if(sprite_hpos == 9'd0) begin + xcnt <= 0; + sprite_index <= 0; + sprite_offset <= 3; + sprite_fsm_state <= 1; + end + else + case(sprite_fsm_state) + 0: /* empty */ ; + 1: begin + if(sprite_index > 8'd47) //Render up to 48 sprites at once (index 0 - 47) + sprite_fsm_state <= 0; + //When the sprite Y attribute is set to 0, skip the current sprite, otherwise obtain the sprite Y attribute + //and scan out the other sprite attributes + else begin + if(hy) begin + sprite_attrib3 <= spriteram_D; + sprite_offset <= 2; + sprite_fsm_state <= sprite_fsm_state + 3'd1; + end + else sprite_index <= sprite_index + 6'd1; + end + end + 2: begin + sprite_attrib2 <= spriteram_D; + sprite_offset <= 1; + sprite_fsm_state <= sprite_fsm_state + 3'd1; + end + 3: begin + sprite_attrib1 <= spriteram_D; + sprite_offset <= 0; + sprite_fsm_state <= sprite_fsm_state + 3'd1; + end + 4: begin + sprite_attrib0 <= spriteram_D; + sprite_offset <= 3; + sprite_index <= sprite_index + 6'd1; + xcnt <= 5'b10000; + sprite_fsm_state <= sprite_fsm_state + 3'd1; + S_req <= !S_req; + end + 5: if (S_req == S_ack) begin + xcnt <= xcnt + 5'd1; + sprite_fsm_state <= wre ? sprite_fsm_state : 3'd1; + S_req <= (wre & xcnt[0]) ? !S_req : S_req; + end + default:; + endcase +end + +//Subtract sprite attribute byte 2 with bit 7 of sprite attribute byte 1 to obtain sprite X position and XOR with the +//flipscreen bit +wire [8:0] sprite_x = ({1'b0, sprite_attrib2} - {sprite_attrib1[7], 8'h00}) ^ {9{flipscreen}}; + +//If the sprite state machine is in state 1, obtain sprite Y position directly from sprite RAM, otherwise obtain it from +//sprite attribute byte 3 and XOR with the flipscreen bit +wire [7:0] sprite_y = (sprite_fsm_state == 3'd1) ? spriteram_D ^ {8{flipscreen}} : sprite_attrib3 ^ {8{flipscreen}}; + +//Sprite flip attributes are stored in bits 4 (horizontal) and 5 (vertical) of sprite attribute byte 1 +wire sprite_hflip = sprite_attrib1[4] ^ flipscreen; +wire sprite_vflip = sprite_attrib1[5] ^ flipscreen; + +//Sprite code is bit 6 of sprite attribute byte 1 appended to sprite attribute byte 0 +wire [8:0] sprite_code = {sprite_attrib1[6], sprite_attrib0}; + +//Sprite color is the lower 4 bits of sprite attribute byte 1 +wire [3:0] sprite_color = sprite_attrib1[3:0]; + +wire [8:0] ht = {1'b0, sprite_y} - sprite_vpos; +wire hy = (sprite_y != 0) & (ht[8:5] == 4'b1111) & (ht[4] ^ ~flipscreen); + +reg [4:0] xcnt; +wire [3:0] lx = xcnt[3:0] ^ {4{sprite_hflip}}; +wire [3:0] ly = ht[3:0] ^ {4{~sprite_vflip}}; + +//Assign address outputs to sprite ROMs +assign S = {sprite_code, ly[3], lx[3], ly[2:0], lx[2:1]}; + +//Multiplex sprite ROM data down from 8 bits to 4 using bit 0 of the horizontal position +wire [3:0] sprite_pixel = lx[0] ? SD[3:0] : SD[7:4]; + +//Latch the sprite bank from bit 3 of register 3 on the rising edge of VSync and XNOR with the added SPFL signal to flip this bit +//for Green Beret +//TODO: Find the actual internal register bit (if any) on the 005849 to properly handle this +reg sprite_bank = 0; +reg old_vsync; +always_ff @(posedge CK49) begin + old_vsync <= VSYC; + if(!VSYC) + sprite_bank <= 0; + else if(!old_vsync && VSYC) + sprite_bank <= ~(reg3[3] ^ SPFL); +end + +wire [11:0] spriteram_A = {3'b000, sprite_bank, sprite_index, sprite_offset}; + +//Address output to sprite LUT PROM +assign OCF = sprite_color; +assign OCB = sprite_pixel; + +//----------------------------------------------------- Sprite line buffer -----------------------------------------------------// + +//The sprite line buffer is external to the 005849 and consists of four 4416 DRAM chips. For simplicity, both the logic for the +//sprite line buffer and the sprite line buffer itself has been made internal to the 005849 implementation. + +//Enable writing to sprite line buffer when bit 4 of xcnt is 1 +wire wre = xcnt[4]; + +//Set sprite ID as bit 0 of the sprite vertical position +wire sprite_id = sprite_vpos[0]; + +//Sum sprite X position with the lower 4 bits of xcnt to address the sprite line buffer +wire [8:0] wpx = sprite_x + xcnt[3:0]; + +//Generate sprite line buffer write addresses +reg [9:0] lbuff_A; +reg lbuff_we; +wire [3:0] lbuff_Din = OCD; + +always_ff @(posedge CK49) begin + lbuff_A <= {~sprite_id, wpx}; + lbuff_we <= wre & S_req == S_ack; +end + +//Generate read address for sprite line buffer on the rising edge of the pixel clock +reg [9:0] radr0 = 10'd0; +reg [9:0] radr1 = 10'd1; +always_ff @(posedge CK49) begin + if(cen_6m) + radr0 <= {sprite_id, flipscreen ? sprite_hpos - 9'd241 : sprite_hpos}; +end + +//Sprite line buffer +wire [3:0] lbuff_Dout; +dpram_dc #(.widthad_a(10)) LBUFF +( + .clock_a(CK49), + .address_a(lbuff_A), + .data_a({4'd0, lbuff_Din}), + .wren_a(lbuff_we & (lbuff_Din != 0)), + + .clock_b(CK49), + .address_b(radr0), + .data_b(8'h0), + .wren_b(radr0 == radr1), + .q_b({4'bZZZZ, lbuff_Dout}) +); + +//Latch sprite data from the sprite line buffer +wire lbuff_read_en = (div[2:0] == 3'b100); +reg [3:0] sprite_D = 4'd0; +always_ff @(posedge CK49) begin + if(lbuff_read_en) begin + if(radr0 != radr1) + sprite_D <= lbuff_Dout; + radr1 <= radr0; + end +end + +//--------------------------------------------------------- Color mixer --------------------------------------------------------// + +//Multiplex tile and sprite data, then output the final result +wire tile_sprite_sel = (tilemap_en | ~(|sprite_D)); +wire [3:0] tile_sprite_D = tile_sprite_sel ? tilemap_D : sprite_D; + +//Latch and output pixel data +reg [4:0] pixel_D; +always_ff @(posedge CK49) begin + if(cen_6m) + pixel_D <= {tile_sprite_sel, tile_sprite_D}; +end +//If the horizontal mask is active, black out the left-most and right-most 8 columns to limit the display area to 240x224, otherwise +//output the full 256x224 +assign COL = hmask ? 5'd0 : pixel_D; + +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/pll.qip b/Arcade_MiST/Konami ScooterShooter/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/pll.v b/Arcade_MiST/Konami ScooterShooter/rtl/pll.v new file mode 100644 index 00000000..1960b7f8 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/pll.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 105, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 382, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 105, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 191, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "105" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "105" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "98.228569" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "49.114285" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "382" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.15200000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31818000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "105" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "382" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "105" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/rom_loader.sv b/Arcade_MiST/Konami ScooterShooter/rtl/rom_loader.sv new file mode 100644 index 00000000..5e1c2907 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/rom_loader.sv @@ -0,0 +1,344 @@ +//============================================================================ +// +// SD card ROM loader and ROM selector for MISTer. +// Copyright (C) 2019, 2020 Kitrinx (aka Rysha) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +//============================================================================ + +// Rom layout for Scooter Shooter: +// 0x0000 - 0x3FFF = eprom_1 +// 0x4000 - 0x7FFF = eprom_2 +// 0x8000 - 0xBFFF = eprom_3 +// 0xC000 - 0xFFFF = eprom_4 +// 0x10000 - 0x13FFF = eprom_5 +// 0x14000 - 0x17FFF = eprom_6 +// 0x18000 - 0x1BFFF = eprom_7 +// 0x1C000 - 0x1FFFF = eprom_8 +// 0x20000 - 0x23FFF = eprom_9 +// 0x24000 - 0x240FF = sprite_lut_prom +// 0x24100 - 0x241FF = tile_lut_prom +// 0x24200 - 0x2421F = color_prom_1 +// 0x24220 - 0x2423F = color_prom_2 + +module selector +( + input logic [24:0] ioctl_addr, + output logic ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, cp1_cs, cp2_cs, cp3_cs, tl_cs, sl_cs +); + + always_comb begin + {ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, cp1_cs, cp2_cs, cp3_cs, tl_cs, sl_cs} = 0; + if(ioctl_addr < 'h8000) + ep1_cs = 1; // 0x8000 15 + else if(ioctl_addr < 'hC000) + ep2_cs = 1; // 0x4000 14 + else if(ioctl_addr < 'h10000) + ep3_cs = 1; // 0x4000 14 + else if(ioctl_addr < 'h18000) + ep4_cs = 1; // 0x8000 15 + else if(ioctl_addr < 'h20000) + ep5_cs = 1; // 0x8000 15 + else if(ioctl_addr < 'h28000) + ep6_cs = 1; // 0x8000 15 + else if(ioctl_addr < 'h28100) + cp1_cs = 1; // 0x100 8 + else if(ioctl_addr < 'h28200) + cp2_cs = 1; // 0x100 8 + else if(ioctl_addr < 'h28300) + cp3_cs = 1; // 0x100 8 + else if(ioctl_addr < 'h28400) + tl_cs = 1; // 0x100 8 + else + sl_cs = 1; // 0x100 8 + end +endmodule + +//////////// +// EPROMS // +//////////// + +module eprom_1 +( + input logic CLK, + input logic CLK_DL, + input logic [14:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(15)) eprom_1 + ( + .clock_a(CLK), + .address_a(ADDR[14:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[14:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module eprom_2 +( + input logic CLK, + input logic CLK_DL, + input logic [13:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(14)) eprom_2 + ( + .clock_a(CLK), + .address_a(ADDR[13:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[13:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module eprom_3 +( + input logic CLK, + input logic CLK_DL, + input logic [13:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(14)) eprom_3 + ( + .clock_a(CLK), + .address_a(ADDR[13:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[13:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module eprom_4 +( + input logic CLK, + input logic CLK_DL, + input logic [14:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(15)) eprom_4 + ( + .clock_a(CLK), + .address_a(ADDR[14:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[14:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module eprom_5 +( + input logic CLK, + input logic CLK_DL, + input logic [14:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(15)) eprom_5 + ( + .clock_a(CLK), + .address_a(ADDR[14:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[14:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module eprom_6 +( + input logic CLK, + input logic CLK_DL, + input logic [14:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [7:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [7:0] DATA +); + dpram_dc #(.widthad_a(15)) eprom_6 + ( + .clock_a(CLK), + .address_a(ADDR[14:0]), + .q_a(DATA[7:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[14:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +/////////// +// PROMS // +/////////// + +module color_prom_1 +( + input logic CLK, + input logic CLK_DL, + input logic [7:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [3:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [3:0] DATA +); + dpram_dc #(.widthad_a(8)) color_prom_1 + ( + .clock_a(CLK), + .address_a(ADDR[7:0]), + .q_a(DATA[3:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[7:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module color_prom_2 +( + input logic CLK, + input logic CLK_DL, + input logic [7:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [3:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [3:0] DATA +); + dpram_dc #(.widthad_a(8)) color_prom_2 + ( + .clock_a(CLK), + .address_a(ADDR[7:0]), + .q_a(DATA[3:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[7:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module color_prom_3 +( + input logic CLK, + input logic CLK_DL, + input logic [7:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [3:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [3:0] DATA +); + dpram_dc #(.widthad_a(8)) color_prom_3 + ( + .clock_a(CLK), + .address_a(ADDR[7:0]), + .q_a(DATA[3:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[7:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module tile_lut_prom +( + input logic CLK, + input logic CLK_DL, + input logic [7:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [3:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [3:0] DATA +); + dpram_dc #(.widthad_a(8)) tile_lut_prom + ( + .clock_a(CLK), + .address_a(ADDR[7:0]), + .q_a(DATA[3:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[7:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule + +module sprite_lut_prom +( + input logic CLK, + input logic CLK_DL, + input logic [7:0] ADDR, + input logic [24:0] ADDR_DL, + input logic [3:0] DATA_IN, + input logic CS_DL, + input logic WR, + output logic [3:0] DATA +); + dpram_dc #(.widthad_a(8)) sprite_lut_prom + ( + .clock_a(CLK), + .address_a(ADDR[7:0]), + .q_a(DATA[3:0]), + + .clock_b(CLK_DL), + .address_b(ADDR_DL[7:0]), + .data_b(DATA_IN), + .wren_b(WR & CS_DL) + ); +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/sdram.sv b/Arcade_MiST/Konami ScooterShooter/rtl/sdram.sv new file mode 100644 index 00000000..328e7e58 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/sdram.sv @@ -0,0 +1,347 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output reg [15:0] port1_q, + + input [15:1] cpu1_addr, + output reg [15:0] cpu1_q, + input [15:1] cpu2_addr, + output reg [15:0] cpu2_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output reg [15:0] port2_q, + input [15:1] ch1_addr, + output reg [15:0] ch1_q, + input sp1_req, + input [16:1] sp1_addr, + output reg [15:0] sp1_q, + output reg sp1_ack +); + +parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us +localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 cas1 + 1 ras0 + 2 data1 returned + 3 CAS0 + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_LAST = 3'd6; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [15:1] addr_last[4]; +reg [16:1] addr_last2[4]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +reg port1_state; +reg port2_state; + +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_CPU2 = 2'd2; +localparam PORT_CH1 = 2'd1; +localparam PORT_SP1 = 2'd2; +localparam PORT_REQ = 2'd3; + +reg [1:0] next_port[2]; +reg [1:0] port[2]; + +reg refresh; +reg [10:0] refresh_cnt; +wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end else if (port1_req ^ port1_state) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1]) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 9'd0, cpu1_addr }; + end else if (cpu2_addr != addr_last[PORT_CPU2]) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 9'd0, cpu2_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT1: bank 2,3 +always @(*) begin + if (port2_req ^ port2_state) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (ch1_addr != addr_last2[PORT_CH1]) begin + next_port[1] = PORT_CH1; + addr_latch_next[1] = { 1'b1, 5'd0, 3'b000, ch1_addr }; + end else if (sp1_req != sp1_ack) begin + next_port[1] = PORT_SP1; + addr_latch_next[1] = { 1'b1, 5'd0, 2'b00, sp1_addr }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + port1_state <= port1_req; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 1'b0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][16:1]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + port2_state <= port2_req; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end + + if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin + refresh <= 1'b1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + PORT_CPU2: begin cpu2_q <= sd_din; end + default: ; + endcase; + end + + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end + PORT_CH1 : ch1_q <= sd_din; + PORT_SP1 : begin sp1_q <= sd_din; sp1_ack <= sp1_req; end + default: ; + endcase; + end + + end +end + +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/spram.vhd b/Arcade_MiST/Konami ScooterShooter/rtl/spram.vhd new file mode 100644 index 00000000..38302277 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/spram.vhd @@ -0,0 +1,46 @@ +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +entity spram is + + generic + ( + DATA_WIDTH : natural := 8; + ADDR_WIDTH : natural := 10 + ); + + port + ( + clk : in std_logic; + addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0); + data : in std_logic_vector((DATA_WIDTH - 1) downto 0); + q : out std_logic_vector((DATA_WIDTH - 1) downto 0); + we : in std_logic := '0' + ); + +end spram; + +architecture rtl of spram is + + subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); + type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; + + shared variable ram : memory_t; + +begin + + process(clk) + begin + if(rising_edge(clk)) then + if(we = '1') then + ram(to_integer(unsigned(addr))) := data; + q <= data; + else + q <= ram(to_integer(unsigned(addr))); + end if; + end if; + end process; + +end rtl; diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_fm_lpf.sv b/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_fm_lpf.sv new file mode 100644 index 00000000..84759c87 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_fm_lpf.sv @@ -0,0 +1,60 @@ +/*MIT License + +Copyright (c) 2019 Gregory Hogan (Soltan_G42) + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +//This is a variation of Gregory Hogan's MISTer Genesis core low-pass filter +//tuned to low-pass filter the FM part of the YM2203 on Scooter Shooter. + +module sshooter_fm_lpf( + input clk, + input reset, + input signed [15:0] in, + output signed [15:0] out); + + localparam [9:0] div = 128; //Sample at 49.152MHz/128 = 384000Hz + + //Coefficients computed with Octave/Matlab/Online filter calculators. + //or with scipy.signal.bessel or similar tools + + //0.037979203, 0.037979203 + //1.0000000, -0.92404159 + reg signed [17:0] A2; + reg signed [17:0] B2; + reg signed [17:0] B1; + + wire signed [15:0] audio_post_lpf1; + + always @ (*) begin + A2 = -18'd30278; + B1 = 18'd1245; + B2 = 18'd1245; + end + + iir_1st_order lpf6db(.clk(clk), + .reset(reset), + .div(div), + .A2(A2), + .B1(B1), + .B2(B2), + .in(in), + .out(audio_post_lpf1)); + + assign out = audio_post_lpf1; + +endmodule diff --git a/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_ssg_lpf.sv b/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_ssg_lpf.sv new file mode 100644 index 00000000..64db75b4 --- /dev/null +++ b/Arcade_MiST/Konami ScooterShooter/rtl/sshooter_ssg_lpf.sv @@ -0,0 +1,61 @@ +/*MIT License + +Copyright (c) 2019 Gregory Hogan (Soltan_G42) + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE.*/ + +//This is a variation of Gregory Hogan's MISTer Genesis core low-pass filter +//tuned for the switchable low-pass filters the SSG part of the YM2203 on +//Scooter Shooter. + +module sshooter_ssg_lpf( + input clk, + input reset, + input signed [15:0] in, + output signed [15:0] out); + + localparam [9:0] div = 256; //Sample at 49.152MHz/96 = 192000Hz + + //Coefficients computed with Octave/Matlab/Online filter calculators. + //or with scipy.signal.bessel or similar tools + + //0.0079883055, 0.0079883055 + //1.0000000, -0.98402339 + reg signed [17:0] A2; + reg signed [17:0] B2; + reg signed [17:0] B1; + + wire signed [15:0] audio_post_lpf1; + + always @ (*) begin + A2 = -18'd32244; + B1 = 18'd262; + B2 = 18'd262; + end + + iir_1st_order lpf6db(.clk(clk), + .reset(reset), + .div(div), + .A2(A2), + .B1(B1), + .B2(B2), + .in(in), + .out(audio_post_lpf1)); + + assign out = audio_post_lpf1; + +endmodule