From afd8b08c3596067edd034ce84790af0483142599 Mon Sep 17 00:00:00 2001 From: Marcel Date: Fri, 18 Jun 2021 00:24:43 +0200 Subject: [PATCH] New Core, Subs --- .../Atari BW Raster Hardware/Subs/README.txt | 9 + .../Atari BW Raster Hardware/Subs/Subs.qpf | 30 + .../Atari BW Raster Hardware/Subs/Subs.qsf | 185 ++ .../Atari BW Raster Hardware/Subs/clean.bat | 16 + .../Atari BW Raster Hardware/Subs/rtl/SVF.v | 140 ++ .../Subs/rtl/Subs_MiST.sv | 205 ++ .../Subs/rtl/audio.vhd | 309 +++ .../Subs/rtl/build_id.sv | 2 + .../Subs/rtl/cpu_mem.vhd | 381 +++ .../Subs/rtl/input.vhd | 149 ++ .../Subs/rtl/joy2quad.sv | 100 + .../Subs/rtl/mixer.vhd | 97 + .../Subs/rtl/motion.vhd | 339 +++ .../Subs/rtl/playfield.vhd | 185 ++ .../Atari BW Raster Hardware/Subs/rtl/pll.v | 365 +++ .../Subs/rtl/ram1k.vhd | 181 ++ .../Subs/rtl/roms/PROM_SYNC.vhd | 38 + .../Subs/rtl/roms/ROM_D7.vhd | 54 + .../Subs/rtl/roms/ROM_D8.vhd | 54 + .../Subs/rtl/roms/ROM_E1.vhd | 38 + .../Subs/rtl/roms/ROM_E2.vhd | 38 + .../Subs/rtl/roms/ROM_E7.vhd | 54 + .../Subs/rtl/roms/ROM_E8.vhd | 54 + .../Subs/rtl/roms/ROM_M4.vhd | 150 ++ .../Subs/rtl/roms/ROM_N2.vhd | 150 ++ .../Subs/rtl/roms/ROM_P1.vhd | 150 ++ .../Subs/rtl/roms/ROM_P2.vhd | 150 ++ .../Subs/rtl/sid_coeffs.vhd | 2076 +++++++++++++++++ .../Subs/rtl/subs_core.vhd | 274 +++ .../Subs/rtl/svfilter.vhd | 246 ++ .../Subs/rtl/sync.vhd | 158 ++ 31 files changed, 6377 insertions(+) create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/README.txt create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qpf create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qsf create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/clean.bat create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/SVF.v create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/Subs_MiST.sv create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/audio.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/build_id.sv create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/cpu_mem.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/input.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/joy2quad.sv create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/mixer.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/motion.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/playfield.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/pll.v create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/ram1k.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/PROM_SYNC.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D7.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D8.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E1.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E2.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E7.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E8.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_M4.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_N2.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P1.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P2.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sid_coeffs.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/subs_core.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/svfilter.vhd create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sync.vhd diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/README.txt b/Arcade_MiST/Atari BW Raster Hardware/Subs/README.txt new file mode 100644 index 00000000..214c27e4 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/README.txt @@ -0,0 +1,9 @@ +---------------------------------------------------------------- +-- +-- Arcade: Subs from james10952001 +-- Port to MiST by Gehstock +-- 17 June 2021 + + +only One Player Game, Game had 2 Video Outputs +---------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qpf b/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qpf new file mode 100644 index 00000000..2041418b --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 19:51:47 November 12, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "19:51:47 November 12, 2017" + +# Revisions + +PROJECT_REVISION = "Subs" diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qsf b/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qsf new file mode 100644 index 00000000..0f7558f7 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/Subs.qsf @@ -0,0 +1,185 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 23:43:03 June 17, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Subs_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_46 -to UART_TX +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Subs_MiST +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ----------------------- +# start ENTITY(Subs_MiST) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Subs_MiST) +# --------------------- + +# --------------------------- +# start ENTITY(SuperBug_MiST) + +# end ENTITY(SuperBug_MiST) +# ------------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Subs_MiST.sv +set_global_assignment -name VHDL_FILE rtl/subs_core.vhd +set_global_assignment -name VHDL_FILE rtl/sync.vhd +set_global_assignment -name VHDL_FILE rtl/svfilter.vhd +set_global_assignment -name VERILOG_FILE rtl/SVF.v +set_global_assignment -name VHDL_FILE rtl/sid_coeffs.vhd +set_global_assignment -name VHDL_FILE rtl/ram1k.vhd +set_global_assignment -name VHDL_FILE rtl/playfield.vhd +set_global_assignment -name VHDL_FILE rtl/motion.vhd +set_global_assignment -name VHDL_FILE rtl/mixer.vhd +set_global_assignment -name VHDL_FILE rtl/input.vhd +set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd +set_global_assignment -name VHDL_FILE rtl/audio.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv +set_global_assignment -name VHDL_FILE rtl/roms/ROM_M4.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_D8.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_D7.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_E7.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_E8.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_E1.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_E2.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_P1.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_P2.vhd +set_global_assignment -name VHDL_FILE rtl/roms/ROM_N2.vhd +set_global_assignment -name VHDL_FILE rtl/roms/PROM_SYNC.vhd +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/clean.bat b/Arcade_MiST/Atari BW Raster Hardware/Subs/clean.bat new file mode 100644 index 00000000..ac9bf0a8 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/clean.bat @@ -0,0 +1,16 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s build_id.v +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/SVF.v b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/SVF.v new file mode 100644 index 00000000..4e06e116 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/SVF.v @@ -0,0 +1,140 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Engineer: Scott R. Gravenhorst +// music.maker@gte.net +// Create Date: 09/10/2007 +// Design Name: SVF +// Module Name: SVF +// Project Name: State Variable Filter +// Description: SVF with shared multiplier. +// +// maximum Q = 23.464375 (q = 18'sb000001010111010010) +// maximum input amplitude = +/- 2047 (12 bits) +// +// Execution time = 4 clocks +// +////////////////////////////////////////////////////////////////////////////////// + +module SVF( + clk, // system clock + ena, // Tell the filter to go + f, // f (not Hz, but usable to control frequency) + q, // q (1/Q) + DataIn, + DataOut + ); + + input clk; + input ena; + input signed [17:0] f; + input signed [17:0] q; + input signed [17:0] DataIn; // Data input for one calculation cycle. + output signed [17:0] DataOut; // Data output from this calculation cycle. + + wire clk; + wire ena; + wire signed [17:0] f; + wire signed [17:0] q; + wire signed [17:0] DataIn; + wire signed [17:0] DataOut; + + reg signed [35:0] z1 = 36'sd0; // feedback #1 + reg signed [35:0] z2 = 36'sd0; // feedback #2 + + reg signed [17:0] mA = 18'd0; + reg signed [17:0] mB = 18'd0; + wire signed [35:0] mP; + + assign DataOut = z2 >>> 18; + +// SVF state machine, shares a multiplier + reg run = 1'b0; + reg [2:0] state = 3'b0; + + always @ ( posedge clk ) + begin + if ( ena == 1'b1 ) + begin + run <= 1'b1; + state <= 3'd0; + mA <= z1 >>> 17; + mB <= q; + end + else + begin + if ( run == 1'b1 ) + begin + state <= state + 1; + + case ( state ) + + 3'd0: + begin + mA <= f; + mB <= ((DataIn << 18) - mP - z2) >>> 17; + end + + 3'd1: + begin + mA <= f; + mB <= z1 >>> 17; + + z1 <= mP + z1; + end + + 3'd2: + begin + z2 <= mP + z2; + + run <= 1'b0; + end + + + endcase + + end + end + end + + MULT18X18SIO #( + .AREG(0), // Enable the input registers on the A port (1=on, 0=off) + .BREG(0), // Enable the input registers on the B port (1=on, 0=off) + .B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE" + .PREG(0) // Enable the input registers on the P port (1=on, 0=off) + ) MULT0 ( + .BCOUT(), // 18-bit cascade output + .P( mP ), // 36-bit multiplier output + .A( mA ), // 18-bit multiplier input + .B( mB ), // 18-bit multiplier input + .BCIN(18'h00000), + .CEA(1'b0), .CEB(1'b0), .CEP(1'b0), .CLK(1'b0), .RSTA(1'b0), .RSTB(1'b0), .RSTP(1'b0) + ); + +////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////// +// C source for working floating point SVF: + +/* +while ( fgets( buf, BUFSIZE, stdin ) != NULL ) + { + input = atof( buf ); + + multq = fb1 * q; + + sum1 = input + (-multq) + (-output); + mult1 = f * sum1; + + sum2 = mult1 + fb1; + mult2 = f * fb1; + + sum3 = mult2 + fb2; + + fb1 = sum2; + fb2 = sum3; + + output = sum3; + printf( "%20.18lf\n", output ); + } +*/ + +endmodule diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/Subs_MiST.sv b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/Subs_MiST.sv new file mode 100644 index 00000000..8d88a031 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/Subs_MiST.sv @@ -0,0 +1,205 @@ +//FPGA implementation of Subs arcade game released by Kee Games in 1978 +//james10952001 +module Subs_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.sv" + +localparam CONF_STR = { + "Subs;;", + "O1,Test Mode,Off,On;", + "O2,Monitor ,1,2;", + "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", + "T0,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1'b1; +wire clk_24, clk_12, locked; +pll pll( + .inclk0(CLOCK_27), + .c0(clk_24),//24.192 + .c1(clk_12),//12.096 + .locked(locked) + ); + +// Configuration DIP switches, these can be brought out to external switches if desired +// making it easier to change options, otherwise it's just more stuff to hook up. + +// See Subs manual for complete information. Active low (0 = On, 1 = Off) * indicates Default +// 1 Ping in attract mode [*(0-On) (1-Off)] +// 2 Time/Cred [*(0-Each coin buys time) (1-1 Coin/Player fixed)] +// 3 4 Language [*(00-English) (10-French) (01-Spanish) (11-German)] +// 5 Free play [*(0-Coin per play) (1-Free Play)] +// 6 7 8 Time [(000-0:30) (100-1:00) *(010-1:30) (110-2:00) (001-2:30) (101-3:00) (011-3:30) (111-4:00)] + +wire [7:0] DIP_Sw = "11111111"; // Config dip switches 3min +//fixing tomorrow + + +wire [63:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [11:0] kbjoy; +wire [31:0] joystick_0, joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; +wire [7:0] audio_l, audio_r; +wire Display_1, Display_2; +wire vid = status[2] ? Display_2 : Display_1; + +wire hs, vs, cs, hb, vb; +wire blankn = ~(hb | vb); +wire compositesync;//todo +wire Steer_1A, Steer_1B; + +subs_core subs_core( + .clk12(clk_12), + .Clk_50_I(), + .Reset_I(~(status[0] | buttons[1])), + .Vid1_O(Display_1), + .Vid2_O(Display_2), + .CompSync_O(), + .CompBlank_O(), + .HBlank(hb), + .VBlank(vb), + .HSync(hs), + .VSync(vs), + .Coin1_I(~m_coin1), + .Coin2_I(1'b1),//On player only, we have only one Video Output + .Start1_I(~m_one_player), + .Start2_I(1'b1),//On player only, we have only one Video Output + .Fire1_I(~m_fireA), + .Fire2_I(1'b1),//On player only, we have only one Video Output + .Steer_1A_I(Steer_1A), + .Steer_1B_I(Steer_1B), + .Steer_2A_I(),//On player only, we have only one Video Output + .Steer_2B_I(),//On player only, we have only one Video Output + .Test_I(~status[1]), + .DiagStep_I(1'b1), + .DiagHold_I(1'b1), + .Slam_I(~m_tilt), + .DIP_Sw(DIP_Sw), + .P1_audio(audio_l), + .P2_audio(audio_r), + .LED1_O(), + .LED2_O(), + .CCounter_O() + ); + +joy2quad joy2quad( + .CLK(clk_12), + .clkdiv(45000), + .c_right(m_right), + .c_left(m_left), + .steerA(Steer_1A), + .steerB(Steer_1B) +); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys ( clk_24 ), + .conf_str ( CONF_STR ), + .SPI_CLK ( SPI_SCK ), + .SPI_SS_IO ( CONF_DATA0 ), + .SPI_MISO ( SPI_DO ), + .SPI_MOSI ( SPI_DI ), + .buttons ( buttons ), + .switches ( switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr ( ypbpr ), + .no_csync ( no_csync ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .status ( status ) + ); + +mist_video #( + .COLOR_DEPTH(1), + .SD_HCNT_WIDTH(9)) +mist_video( + .clk_sys ( clk_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? vid : 0 ), + .G ( blankn ? vid : 0 ), + .B ( blankn ? vid : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .scanlines ( status[4:3] ), +// .rotate ( { 1'b1, rotate } ), +// .ce_divider ( 1'b1 ), +// .blend ( status[6] ), + .scandoubler_disable(scandoublerD ), + .no_csync ( no_csync ), + .ypbpr ( ypbpr ) + ); + +dac #( + .C_bits(8)) +dac_l( + .clk_i(clk_24), + .res_n_i(1), + .dac_i(audio_l), + .dac_o(AUDIO_L) + ); + +dac #( + .C_bits(8)) +dac_r( + .clk_i(clk_24), + .res_n_i(1), + .dac_i(audio_r), + .dac_o(AUDIO_R) + ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; + +arcade_inputs inputs ( + .clk ( clk_24 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), +// .rotate ( rotate ), +// .orientation ( 2'b11 ), + .joyswap ( 1'b0 ), + .oneplayer ( 1'b1 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/audio.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/audio.vhd new file mode 100644 index 00000000..acfdff84 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/audio.vhd @@ -0,0 +1,309 @@ +-- Audio for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use ieee.numeric_std.all; + +entity audio is +port( + Clk_50 : in std_logic; + Clk_12 : in std_logic; + Clk_6 : in std_logic; + Ena_3k : in std_logic; + Reset_n : in std_logic; + Load_n : in std_logic_vector(8 downto 1); + SnrStart1 : in std_logic; + SnrStart2 : in std_logic; + Noise_reset_n : in std_logic; + Crash : in std_logic; + Explode : in std_logic; + PRAM : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + VCount : in std_logic_vector(7 downto 0); + P1_audio : out std_logic_vector(7 downto 0); + P2_audio : out std_logic_vector(7 downto 0) + ); +end audio; + +architecture rtl of audio is + + +signal reset : std_logic; + +signal V8 : std_logic; +signal H4 : std_logic; +signal H256 : std_logic; + +signal RNoise : std_logic := '0'; +signal Gated_noise : std_logic := '0'; +signal Noise_Shift : std_logic_vector(15 downto 0) := (others => '0'); +signal Shift_in : std_logic := '0'; + +signal Bang : std_logic_vector(3 downto 0) := (others => '0'); +signal Crash_raw : std_logic_vector(3 downto 0) := (others => '0'); +signal Crash_snd : std_logic_vector(3 downto 0) := (others => '0'); +signal Explosion : std_logic_vector(5 downto 0) := (others => '0'); +signal Launch_raw : std_logic_vector(3 downto 0) := (others => '0'); +signal Launch : std_logic_vector(3 downto 0) := (others => '0'); + +signal explosion_prefilter : std_logic_vector(3 downto 0) := (others => '0'); +signal explosion_filter_t1 : std_logic_vector(3 downto 0) := (others => '0'); +signal explosion_filter_t2 : std_logic_vector(3 downto 0) := (others => '0'); +signal explosion_filter_t3 : std_logic_vector(3 downto 0) := (others => '0'); +signal explosion_filtered : std_logic_vector(5 downto 0) := (others => '0'); + +signal Ping_duration1 : std_logic_vector(11 downto 0); +signal Ping_duration2 : std_logic_vector(11 downto 0); + +signal Sonar1 : std_logic_vector(5 downto 0); +signal Sonar2 : std_logic_vector(5 downto 0); + + + +signal clk_count : std_logic_vector(3 downto 0); +signal clk_1k : std_logic; + +signal Snr1_envelope : std_logic_vector(8 downto 0); +signal Snr1_prefilter : std_logic_vector(8 downto 0); +signal Snr1_ping : std_logic_vector(7 downto 0); +signal Snr2_envelope : std_logic_vector(8 downto 0); +signal Snr2_prefilter : std_logic_vector(8 downto 0); +signal Snr2_ping : std_logic_vector(7 downto 0); + + +signal unsigned_filt : std_logic_vector(18 downto 0); +signal filtered_audio : signed(18 downto 0); +signal audio_data : std_logic_vector(17 downto 0); +signal voice1_signed : signed(12 downto 0); +signal unsigned_audio : std_logic_vector(17 downto 0); +signal input_valid : std_logic; +signal tick_q1 : std_logic; +signal tick_q2 : std_logic; +signal ff1 : std_logic; + +signal testcount : std_logic_vector(25 downto 0); + +begin + +-- HCount +-- (0) 1H 3 MHz +-- (1) 2H 1.5MHz +-- (2) 4H 750 kHz +-- (3) 8H 375 kHz +-- (4) 16H 187 kHz +-- (5) 32H 93 kHz +-- (6) 64H 46 kHz +-- (7) 128H 23 kHz +-- (8) 256H 12 kHz + + +reset <= (not reset_n); + +H4 <= HCount(2); +H256 <= HCount(8); +V8 <= VCount(3); + +--process(clk_6, ena_3k) +--begin +--if rising_edge(clk_6) then +-- if ena_3k = '1' then +-- if clk_count = "0001" then +-- clk_count <= (others => '0'); +-- clk_1k <= (not clk_1k); +-- else +-- clk_count <= clk_count + 1; +-- end if; +-- end if; +--end if; +--end process; + + + + +-- Sonar ping envelope generator, this is a 0.1 second decaying burst of rnoise +Ping1_envelope: process(Clk_6, ena_3k, SnrStart1) +begin + if SnrStart1 = '0' then + Snr1_envelope <= "100101100"; -- 300 decremented at 3kHz gives 0.1 second + elsif rising_edge(clk_6) then + if Ena_3k = '1' then + if Snr1_envelope > 0 then + Snr1_envelope <= Snr1_envelope - 1; + end if; + end if; + end if; +end process; + +Ping2_envelope: process(Clk_6, ena_3k, SnrStart2) +begin + if SnrStart2 = '0' then + --Snr2_envelope <= "100101100"; -- 300 decremented at 3kHz gives 0.1 second + Snr2_envelope <= "111111110"; + elsif rising_edge(clk_6) then + if Ena_3k = '1' then + if Snr2_envelope > 0 then + Snr2_envelope <= Snr2_envelope - 1; + end if; + end if; + end if; +end process; + + +-- Envelope is modulated by rnoise +Snr1_prefilter <= Snr1_envelope when rnoise = '1' and SnrStart1 = '1' else (others => '0'); + +Snr2_prefilter <= Snr2_envelope when rnoise = '1' and SnrStart2 = '1' else (others => '0'); + + +process(h256) +begin +if rising_edge(h256) then + testcount <= testcount + 1; +end if; +end process; + + + +-- State Variable Filter with 1kHz bandpass + +--voice1_signed <= signed("0000" & Snr1_prefilter) - 2048; +-- +--SnrFilter1: entity work.sid_filters +-- port map ( +-- clk => Clk_12, +-- rst => Reset, +-- -- SID registers. +-- Fc_lo => "00000101", +-- Fc_hi => "11111111", +-- Res_Filt => testcount(22 downto 15), +-- Mode_Vol => "01111111", +-- -- Voices - resampled to 13 bit +-- voice1 => voice1_signed, +-- voice2 => voice1_signed, +-- voice3 => voice1_signed, +-- -- +-- input_valid => '1', +-- ext_in => voice1_signed, +-- +-- sound => filtered_audio, +-- valid => open +-- ); +-- +-- +-- +-- unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000"); +-- unsigned_audio <= unsigned_filt(18 downto 1); +-- audio_data <= unsigned_audio; +-- + +-- Temporary test: +--Snr1_ping <= audio_data(8 downto 1); +--Snr2_ping <= audio_data(8 downto 1); --Snr2_prefilter(8 downto 1); + +snr1_ping <= Snr1_prefilter(8 downto 1); +snr2_ping <= Snr2_prefilter(8 downto 1); + + +---- LFSR consisting of K11 and K12 that generates pseudo-random noise (sounds like crap, is schematic wrong?) +--Noise_gen: process(H256, noise_reset_n) +--begin +---- if (noise_reset_n = '0') then +---- noise_shift <= (others => '0'); +---- rnoise <= '0'; +-- if rising_edge(H256) then +-- shift_in <= (not noise_shift(1)) xor noise_shift(2); +-- --shift_in <= not (noise_shift(1) xor noise_shift(2)); +-- noise_shift <= shift_in & noise_shift(15 downto 1); +-- rnoise <= noise_shift(2); +-- end if; +--end process; + + +-- LFSR that generates pseudo-random noise (from Ultra Tank, this one sounds right) +Noise_gentank: process(H256, noise_reset_n) +begin + if (noise_reset_n = '0') then + noise_shift <= (others => '0'); + rnoise <= '0'; + elsif rising_edge(H256) then + shift_in <= (not noise_shift(6)) xor noise_shift(8); + noise_shift <= shift_in & noise_shift(15 downto 1); + rnoise <= noise_shift(0); + end if; +end process; + + +NoiseGate: process(V8, rnoise) +begin + if rising_edge(V8) then + gated_noise <= rnoise; + end if; +end process; + +-- Generate the Launch sound +Launch_Gen: process(PRAM, Load_n(3)) +begin + if rising_edge(Load_n(3)) then + launch_raw <= PRAM(3 downto 0); + end if; +end process; +launch <= launch_raw when rnoise = '1' else "0000"; + + +-- Generate the bang sound which is used for the crash and explosion sounds +Crash_gen: process(Clk_6, PRAM, Load_n(3), gated_noise) +begin + if rising_edge(Load_n(3)) then + crash_raw <= PRAM(7 downto 4); + end if; +end process; +bang <= crash_raw when gated_noise = '1' else "0000"; +explosion_prefilter <= bang; -- Explosion sound comes from the same source as crash sound + +-- Very simple low pass filter, borrowed from MikeJ's Asteroids code +Explosion_filter: process(clk_6) +begin + if rising_edge(clk_6) then + if (Ena_3k = '1') then + explosion_filter_t1 <= explosion_prefilter; + explosion_filter_t2 <= explosion_filter_t1; + explosion_filter_t3 <= explosion_filter_t2; + end if; + explosion_filtered <= ("00" & explosion_filter_t1) + + ('0' & explosion_filter_t2 & '0') + + ("00" & explosion_filter_t3); + + end if; +end process; + + +explosion <= explosion_filtered when explode = '1' else "000000"; + +crash_snd <= bang when crash = '1' else "0000"; + + +-- ToDo: Tweak volume of individual sounds + +-- Audio mixer +P1_Audio <= ("00000") + Snr1_ping + ('0' & explosion & '0') + ('0' & crash_snd & '0') + ("00" & launch); + + +P2_Audio <= ("00000") + Snr2_ping + ('0' & explosion & '0') + ('0' & crash_snd & '0') + ("00" & launch); + + + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/build_id.sv b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/build_id.sv new file mode 100644 index 00000000..a4e69e93 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/build_id.sv @@ -0,0 +1,2 @@ +`define BUILD_DATE "210524" +`define BUILD_TIME "140250" diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/cpu_mem.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/cpu_mem.vhd new file mode 100644 index 00000000..ac4a570b --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/cpu_mem.vhd @@ -0,0 +1,381 @@ +-- CPU, RAM, ROM and address decoder for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity CPU_mem is +port( + Clk6 : in std_logic; -- 6MHz on schematic + Ena_3k : buffer std_logic; -- 3kHz clock enable, used by sound circuit + Reset_I : in std_logic; + Reset_n : buffer std_logic; + VCount : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + Test_n : in std_logic; + DBus_in : in std_logic_vector(7 downto 0); + PRAM : buffer std_logic_vector(7 downto 0); + Adr : out std_logic_vector(10 downto 0); + Control_Read_n : buffer std_logic; + Steer_Reset_n : out std_logic; + Options_Read_n : buffer std_logic; + Coin_Read_n : buffer std_logic; + LED1 : out std_logic; + LED2 : out std_logic; + SnrStart1 : out std_logic; + SnrStart2 : out std_logic; + Noise_Reset_n : out std_logic; + Crash : out std_logic; + Explode : out std_logic; + Invert1 : out std_logic; + Invert2 : out std_logic; + PHI1 : buffer std_logic; + PHI2 : buffer std_logic; + DMA : out std_logic_vector(7 downto 0); + DMA_n : out std_logic_vector(7 downto 0) + ); +end CPU_mem; + +architecture rtl of CPU_mem is + +signal H2 : std_logic; +signal H4 : std_logic; +signal H8 : std_logic; +signal H16 : std_logic; +signal H32 : std_logic; +signal H64 : std_logic; +signal H128 : std_logic; +signal H256 : std_logic; +signal H256_n : std_logic; + +signal V8 : std_logic; +signal V16 : std_logic; +signal V32 : std_logic; +signal V64 : std_logic; +signal V128 : std_logic; + +signal ena_count : std_logic_vector(10 downto 0) := (others => '0'); +signal ena_750k : std_logic; +signal ena_750k_2 : std_logic; + +signal A : std_logic_vector(15 downto 0) := (others => '0'); +signal BA : std_logic_vector(10 downto 0); +signal WRAM : std_logic; +signal RnW : std_logic; +signal RAM_n : std_logic; +signal RAM : std_logic; +signal Write_n : std_logic; +signal Display_n : std_logic; + +signal cpu_Din : std_logic_vector(7 downto 0); +signal cpu_Dout : std_logic_vector(7 downto 0); +signal DBuS_n : std_logic_vector(7 downto 0); +signal NMI_n : std_logic; +signal RW_n : std_logic; + +signal ROM0_n : std_logic; +signal ROM1_n : std_logic; +signal ROM2_n : std_logic; +signal ROM3_n : std_logic; + +signal ROM0_dout : std_logic_vector(7 downto 0); +signal ROM1_dout : std_logic_vector(7 downto 0); +signal ROM2_dout : std_logic_vector(7 downto 0); +signal ROM3_dout : std_logic_vector(7 downto 0); + +signal RAM_addr : std_logic_vector(9 downto 0) := (others => '0'); +signal Vram_addr : std_logic_vector(9 downto 0); +signal Vram_dout : std_logic_vector(7 downto 0); +signal RAM_dout : std_logic_vector(7 downto 0); +signal ram_we : std_logic; + +signal Inputs_n : std_logic := '1'; +signal Timer_Reset_n : std_logic := '1'; + +signal WDog_Clear : std_logic; +signal WDog_count : std_logic_vector(3 downto 0); + + +begin + +-- In the original hardware the CPU is clocked directly by the 4H signal from the horizontal +-- line counter. This attemps to do thins in a manner that is more proper for a synchronous +-- FPGA design using the main 6MHz clock in conjunction with a 750kHz clock enable for the CPU. +-- This also creates a 3kHz clock enable used by filters in the sound module. +Clock_ena: process(Clk6) +begin + if rising_edge(Clk6) then + ena_count <= ena_count + "1"; + ena_750k <= '0'; + ena_750k_2 <= '0'; + if (ena_count(2 downto 0) = "000") then + ena_750k <= '1'; -- 750 kHz + end if; + if (ena_count(2 downto 0) = "100") then + ena_750k_2 <= '1'; -- 750kHz phase 2 + end if; + ena_3k <= '0'; + if (ena_count(10 downto 0) = "00000000000") then + ena_3k <= '1'; + end if; + end if; +end process; + + +H2 <= HCount(1); +H4 <= HCount(2); +H8 <= HCount(3); +H16 <= HCount(4); +H32 <= HCount(5); +H64 <= HCount(6); +H128 <= HCount(7); +H256 <= HCount(8); +H256_n <= (not HCount(8)); + +V8 <= VCount(3); +V16 <= VCount(4); +V32 <= VCount(5); +V64 <= VCount(6); +V128 <= VCount(7); + + +-- Watchdog timer, counts pulses from V128 and resets CPU if not cleared by Timer_Reset_n +Watchdog: process(V128, WDog_Clear, Reset_I) +begin + if Reset_I = '0' then + WDog_count <= "1111"; + elsif Wdog_Clear = '1' then + WDog_count <= "0000"; + elsif rising_edge(V128) then + WDog_count <= WDog_count + 1; + end if; +end process; +WDog_Clear <= (Test_n nand Timer_Reset_n); +Reset_n <= (not WDog_count(3)); + + +CPU: entity work.T65 +port map( + Enable => ena_750k, + Mode => "00", + Res_n => reset_n, + Clk => clk6, + Rdy => '1', + Abort_n => '1', + IRQ_n => '1', + NMI_n => NMI_n, + SO_n => '1', + R_W_n => RW_n, + A(15 downto 0) => A, + DI => cpu_Din, + DO => cpu_Dout + ); +BA(7 downto 0) <= A(7 downto 0); +BA(8) <= WRAM or A(8); +BA(9) <= WRAM or A(9); +BA(10) <= A(10); +Adr <= BA; +DBuS_n <= (not cpu_Dout); +RnW <= (not RW_n); +NMI_n <= V32 nand Test_n; + +Write_n <= (Phi2 nand H2) or RW_n; + +Phi2 <= (H4); +Phi1 <= not Phi2; + + +-- Program ROMs +-- E1 and E2 hold only French and Spanish text strings and may be omitted in English/German +-- boards, but causes ROM error in self test if they are missing +--E1: entity work.ProgROM0a +--port map( +-- clock => clk6, +-- address => BA(8 downto 0), +-- q => ROM0_dout(3 downto 0) +-- ); + +E1: entity work.ROM_E1 +port map( + clk => clk6, + addr => BA(7 downto 0), + data => ROM0_dout(3 downto 0) +); + +--E2: entity work.ProgROM0b +--port map( +-- clock => clk6, +-- address => BA(8 downto 0), +-- q => ROM0_dout(7 downto 4) +-- ); + +E2: entity work.ROM_E2 +port map( + clk => clk6, + addr => BA(7 downto 0), + data => ROM0_dout(7 downto 4) +); + +--P1: entity work.ProgROM1 +--port map( +-- clock => clk6, +-- address => BA(10 downto 0), +-- q => ROM1_dout +-- ); + +P1: entity work.ROM_P1 +port map( + clk => clk6, + addr => BA(10 downto 0), + data => ROM1_dout +); + +--P2: entity work.ProgROM2 +--port map( +-- clock => clk6, +-- address => BA(10 downto 0), +-- q => ROM2_dout +-- ); + +P2: entity work.ROM_P2 +port map( + clk => clk6, + addr => BA(10 downto 0), + data => ROM2_dout +); + +--N2: entity work.ProgROM3 +--port map( +-- clock => clk6, +-- address => BA(10 downto 0), +-- q => ROM3_dout +-- ); + +N2: entity work.ROM_N2 +port map( + clk => clk6, + addr => BA(10 downto 0), + data => ROM3_dout +); + +-- Video RAM +RAM1k: entity work.ram1k +port map( + clock => clk6, + address => RAM_addr, + wren => ram_we, + data => DBus_n, + q => RAM_dout + ); + + +PRAM <= (not RAM_dout); +ram_we <= (not Write_n) and (not Display_n); +Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & (V8 and H256) & H128 & H64 & H32 & H16 & H8; + +-- Selects control of RAM address between CPU and video circuit +VRAM_mux: process(clk6) +begin + if rising_edge(clk6) then + if phi2 = '0' then + RAM_addr <= Vram_addr; + else + RAM_addr <= BA(9 downto 0); + end if; + end if; +end process; + +--Latches data from RAM bus on rising edge of Phi2 clock +D5_6: process(clk6) --fix +begin + if rising_edge(phi2) then + DMA_n <= RAM_dout; + DMA <= (not RAM_dout); + end if; +end process; + + +-- Address decoder +-- Using more of a behavioral modeling technique here rather than copying +-- the whole original circuit as that caused some timing problems. +-- 74LS42 at B9 decodes ROM and RAM enable signals +ROM0_n <= '0' when A(13 downto 11) = "100" else '1'; +ROM1_n <= '0' when A(13 downto 11) = "101" else '1'; +ROM2_n <= '0' when A(13 downto 11) = "110" else '1'; +ROM3_n <= '0' when A(13 downto 11) = "111" else '1'; +WRAM <= '1' when A(13 downto 11) = "000" and BA(7) = '1' else '0'; +Display_n <= '0' when A(13 downto 11) = "001" or WRAM = '1' else '1'; + +RAM_n <= RnW or Display_n; +RAM <= (not RAM_n); + +-- 74LS42 at D9 decodes IO enable signals +-- Write to outputs +Noise_Reset_n <= '0' when Write_n = '0' and A(13 downto 11) = "000" and BA(7 downto 5) = "000" else '1'; +Steer_Reset_n <= '0' when Write_n = '0' and A(13 downto 11) = "000" and BA(7 downto 5) = "001" else '1'; +Timer_Reset_n <= '0' when Write_n = '0' and A(13 downto 11) = "000" and BA(7 downto 5) = "010" else '1'; + +-- Read to inputs +Control_Read_n <= '0' when Write_n = '1' and A(13 downto 11) = "000" and BA(7 downto 5) = "000" else '1'; +Coin_Read_n <= '0' when Write_n = '1' and A(13 downto 11) = "000" and BA(7 downto 5) = "001" else '1'; +Options_Read_n <= '0' when Write_n = '1' and A(13 downto 11) = "000" and BA(7 downto 5) = "011" else '1'; + +-- Combine these to simplify CPU data in mux +Inputs_n <= Control_Read_n and Coin_Read_n and Options_Read_n; + + +-- 74LS259 addressable latch at C9, this drives outputs +C9: process(clk6, Reset_n, Write_n) -- added write_n +begin + if (Reset_n = '0') then + LED1 <= '0'; -- Player 1 Start LED + LED2 <= '0'; -- Player 2 Start LED + SnrStart2 <= '0'; -- Player 1 Sonar ping trigger + SnrStart1 <= '0'; -- Player 2 Sonar ping trigger + Crash <= '0'; -- Crash sound enable + Explode <= '0'; -- Explosion sound enable + Invert1 <= '0'; -- Player 1 video invert + Invert2 <= '0'; -- Player 2 video invert + elsif rising_edge(clk6) then + -- This next line models part of the address decoder that enables this latch + if (Write_n = '0' and A(13 downto 11) = "000" and BA(7 downto 5) = "011") then + case A(3 downto 1) is + when "000" => LED1 <= A(0); + when "001" => LED2 <= A(0); + when "010" => SnrStart2 <= A(0); + when "011" => SnrStart1 <= A(0); + when "100" => Crash <= A(0); + when "101" => Explode <= A(0); + when "110" => Invert1 <= A(0); + when "111" => Invert2 <= A(0); + when others => null; + end case; + end if; + end if; +end process; + + +-- CPU Data-in mux, selects whether CPU is reading RAM, ROM, or inputs +cpu_Din <= PRAM when (RAM_n or Display_n) = '0' else + ROM0_dout when ROM0_n = '0' else + ROM1_dout when ROM1_n = '0' else + ROM2_dout when ROM2_n = '0' else + ROM3_dout when ROM3_n = '0' else + DBus_in when Inputs_n = '0' else + x"FF"; + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/input.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/input.vhd new file mode 100644 index 00000000..e6ace3f1 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/input.vhd @@ -0,0 +1,149 @@ +-- Switch and steering input circuitry for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity input is +port( + Clk6 : in std_logic; + Sw_F9 : in std_logic_vector(7 downto 0); -- DIP switches + Coin1_n : in std_logic; -- Coin switches + Coin2_n : in std_logic; + Start1 : in std_logic; -- 1 and 2 player start switches + Start2 : in std_logic; + Fire1 : in std_logic; + Fire2 : in std_logic; + Test_n : in std_logic; -- Self test switch + Diag_step : in std_logic; + Diag_hold : in std_logic; + Slam : in std_logic; + Steering1A_n : in std_logic; -- Steering wheel signals + Steering1B_n : in std_logic; + Steering2A_n : in std_logic; + Steering2B_n : in std_logic; + SteerReset_n : in std_logic; + Coin_Rd_n : in std_logic; + Control_Rd_n : in std_logic; + Options_Rd_n : in std_logic; + VBlank_n_s : in std_logic; + Adr : in std_logic_vector(2 downto 0); -- Adress bus, only the lower 3 bits used by IO circuitry + DBus : out std_logic_vector(7 downto 0); -- Out to data bus, only bits 7, 1, and 0 used + Coin_Ctr : out std_logic -- Coin counter output + ); +end input; + +architecture rtl of input is + + +signal Coin1 : std_logic; +signal Coin2 : std_logic; + +signal SteerDir1 : std_logic; +signal SteerDir2 : std_logic; +signal SteerFlag1 : std_logic; +signal SteerFlag2 : std_logic; + +signal E10_y : std_logic; +signal F10_y : std_logic; +signal E9_y : std_logic_vector(1 downto 0); + + + +begin + +Coin1 <= (not Coin1_n); -- Coin inputs are inverted by gates in H11 +Coin2 <= (not Coin2_n); +Coin_Ctr <= Coin1 or Coin2; -- Coin counter uses a simple OR gate, not CPU controlled + + +-- Steering inputs, handled by 7474's at H10 and J10 +SteeringA: process(Steering1A_n, Steering1B_n, SteerReset_n) +begin + if SteerReset_n = '0' then -- Asynchronous clear + SteerFlag1 <= '0'; + elsif rising_edge(Steering1B_n) then + SteerFlag1 <= '1'; + SteerDir1 <= (not Steering1A_n); -- Steering encoders are active low but inverted on board + end if; +end process; + +SteeringB: process(Steering2A_n, Steering2B_n, SteerReset_n) +begin + if SteerReset_n = '0' then -- Asynchronous clear + SteerFlag2 <= '0'; + elsif rising_edge(Steering2B_n) then + SteerFlag2 <= '1'; + SteerDir2 <= (not Steering2A_n); + end if; +end process; + + +-- 74LS251 data selector/multiplexer at E10 +E10: process(Adr, Start1, Start2, Fire1, Fire2, Coin1, Coin2, Test_n, VBlank_n_s) +begin + case Adr(2 downto 0) is + when "000" => E10_y <= Coin2; + when "001" => E10_y <= Start1; + when "010" => E10_y <= Coin1; + when "011" => E10_y <= Start2; + when "100" => E10_y <= VBlank_n_s; + when "101" => E10_y <= Fire1; + when "110" => E10_y <= Test_n; + when "111" => E10_y <= Fire2; + when others => E10_y <= '1'; + end case; +end process; + + +-- 74LS251 data selector/multiplexer at F10 +F10: process(Adr, Diag_step, Diag_hold, Slam, SteerDir1, SteerDir2, SteerFlag1, SteerFlag2, VBlank_n_s) +begin + case Adr(2 downto 0) is + when "000" => F10_y <= Diag_step; + when "001" => F10_y <= Diag_hold; + when "010" => F10_y <= Slam; + when "011" => F10_y <= '1'; -- 'Spare' on schematic + when "100" => F10_y <= SteerDir1; + when "101" => F10_y <= SteerFlag1; + when "110" => F10_y <= SteerDir2; + when "111" => F10_y <= SteerFlag2; + when others => F10_y <= '1'; + end case; +end process; + + +-- 74LS253 dual selector/multiplexer at E9 +E9: process(Adr, Sw_F9) +begin + case Adr(1 downto 0) is + when "00" => E9_y <= Sw_F9(0) & Sw_F9(1); + when "01" => E9_y <= Sw_F9(2) & Sw_F9(3); + when "10" => E9_y <= Sw_F9(4) & Sw_F9(5); + when "11" => E9_y <= Sw_F9(6) & Sw_F9(7); + when others => E9_y <= "11"; + end case; +end process; + + +-- Input data mux +DBus <= E10_y & "1111111" when Coin_Rd_n = '0' else + F10_y & "1111111" when Control_Rd_n = '0' else + "111111" & E9_y when Options_Rd_n = '0' else + x"FF"; + +end rtl; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/joy2quad.sv b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/joy2quad.sv new file mode 100644 index 00000000..d2eaeabb --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/joy2quad.sv @@ -0,0 +1,100 @@ +//============================================================================ +// joy2quad +// +// Take in digital joystick buttons, and try to estimate a quadrature encoder +// +// +// This makes an offset wave pattern for each keyboard stroke. It might +// be a good extension to change the size of the wave based on how long the joystick +// is held down. +// +// Copyright (c) 2019 Alan Steremberg - alanswx +// +// +//============================================================================ +// digital joystick button to quadrature encoder + +module joy2quad +( + input CLK, + input [31:0] clkdiv, + + input c_right, + input c_left, + output reg steerA, + output reg steerB +); + + +reg [3:0] state = 0; + +always @(posedge CLK) begin + reg [31:0] count = 0; + if (count >0) + begin + count=count-1; + end + else + begin + count=clkdiv; + casex(state) + 4'b0000: + begin + {steerB,steerA} =2'b00; + if (c_left==1) + begin + state=4'b0001; + end + if (c_right==1) + begin + state=4'b0101; + end + + end + 4'b0001: + begin + {steerB,steerA}=2'b00; + state=4'b0010; + end + 4'b0010: + begin + {steerB,steerA}=2'b01; + state=3'b0011; + end + 4'b0011: + begin + {steerB,steerA}=2'b11; + state=4'b0100; + end + 4'b0100: + begin + {steerB,steerA}=2'b10; + state=4'b000; + end + 4'b0101: + begin + {steerB,steerA}=2'b00; + state=4'b0110; + end + 4'b0110: + begin + {steerB,steerA}=2'b10; + state=4'b0111; + end + 4'b0111: + begin + {steerB,steerA}=2'b11; + state=4'b1000; + end + 4'b1000: + begin + {steerB,steerA}=2'b01; + state=4'b0000; + + end + + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/mixer.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/mixer.vhd new file mode 100644 index 00000000..5177f450 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/mixer.vhd @@ -0,0 +1,97 @@ +-- Video mixer circuitry for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity mixer is +port( + Clk6 : in std_logic; + PRAM : in std_logic_vector(7 downto 0); + VBlank_n_s : in std_logic; -- VBLANK* on the schematic + Load_n : in std_logic_vector(7 downto 0); + Invert1 : in std_logic; + Invert2 : in std_logic; + PFld1_n : in std_logic; + PFld2_n : in std_logic; + Sub1_n : in std_logic; + Sub2_n : in std_logic; + Torp1 : in std_logic; + Torp2 : in std_logic; + H256_s : in std_logic; -- 256H* on schematic + Video1 : out std_logic; + Video2 : out std_logic + ); +end mixer; + +architecture rtl of mixer is + +signal SubEn1_n : std_logic; +signal SubEn2_n : std_logic; +signal Sub1_n_Q : std_logic; +signal Sub2_n_Q : std_logic; +signal PFld1_n_Q : std_logic; +signal PFld2_n_Q : std_logic; +signal Torp1_2_Q : std_logic; +signal RawVid1 : std_logic; +signal RawVid2 : std_logic; +signal VidInvert1 : std_logic; +signal VidInvert2 : std_logic; + + +begin + +L9_A: process(Load_n(1), PRAM) +begin + if rising_edge(Load_n(1)) then + SubEn1_n <= (not PRAM(7)); + end if; +end process; + +L9_B: process(Load_n(2), PRAM) +begin + if rising_edge(Load_n(2)) then + SubEn2_n <= (not PRAM(7)); + end if; +end process; + + + +-- 74LS174 latches video signals with rising edge of 6MHz clock +L8: process(Clk6) +begin + if rising_edge(Clk6) then + Sub1_n_Q <= Sub1_n; + PFld1_n_Q <= PFld1_n; + Torp1_2_Q <= Torp1 nor Torp2; + PFld2_n_Q <= PFld2_n; + Sub2_n_Q <= Sub2_n; + end if; +end process; + +RawVid1 <= not ((SubEn2_n or Sub2_n_Q) and Sub1_n_Q and PFld1_n_Q and Torp1_2_Q); +RawVid2 <= not ((SubEn1_n or Sub1_n_Q) and Sub2_n_Q and PFld2_n_Q and Torp1_2_Q); + +VidInvert1 <= (H256_s nand VBlank_n_s) nor Invert1; +VidInvert2 <= (H256_s nand VBlank_n_s) nor Invert2; +Video1 <= (VidInvert1 xor RawVid1); +Video2 <= (VidInvert2 xor RawVid2); + + +end rtl; + + diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/motion.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/motion.vhd new file mode 100644 index 00000000..c0d1259f --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/motion.vhd @@ -0,0 +1,339 @@ +-- Motion object generation circuitry for Atari Subs +-- This generates the two submarines, two torpedos and explosions for the submarines and torpedos +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity motion is +port( + CLK6 : in std_logic; -- 6MHz* on schematic + PHI2 : in std_logic; + DMA_n : in std_logic_vector(7 downto 0); + PRAM : in std_logic_vector(7 downto 0); + H256_s : in std_logic; -- 256H* on schematic + VCount : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + Load_n : buffer std_logic_vector(8 downto 1); + Sub1_n : out std_logic; + Sub2_n : out std_logic; + Torp1 : out std_logic; + Torp2 : out std_logic + ); +end motion; + +architecture rtl of motion is + +signal phi0 : std_logic; +signal phi1 : std_logic; + +signal Sub1_Inh : std_logic; +signal Sub2_Inh : std_logic; +signal Torp1_Inh : std_logic; +signal Torp2_Inh : std_logic; + +signal VPos_sum : std_logic_vector(7 downto 0); +signal Vcount_match : std_logic; +signal Sum_H64 : std_logic; +signal C5_8 : std_logic; + +signal K9_in : std_logic_vector(3 downto 0) := (others => '0'); +signal K9_out : std_logic_vector(9 downto 0) := (others => '0'); + +signal H256_n : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H16 : std_logic; +signal H8 : std_logic; + +signal R6_6 : std_logic; +signal R6_8 : std_logic; + +signal ROM_D7Q : std_logic_vector(7 downto 0); +signal ROM_D8Q : std_logic_vector(7 downto 0); +signal ROM_E7Q : std_logic_vector(7 downto 0); +signal ROM_E8Q : std_logic_vector(7 downto 0); + + +signal Sub1_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Sub2_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Torp1_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Torp2_Hpos : std_logic_vector(7 downto 0) := x"00"; + +signal SubROM_dout : std_logic_vector(14 downto 0); +signal TorpROM_dout : std_logic_vector(14 downto 0); + +signal Sub1_reg : std_logic_vector(15 downto 0) := x"0000"; +signal Sub2_reg : std_logic_vector(15 downto 0) := x"0000"; +signal Torp1_reg : std_logic_vector(15 downto 0) := x"0000"; +signal Torp2_reg : std_logic_vector(15 downto 0) := x"0000"; + +signal Vid : std_logic_vector(15 downto 1) := (others => '0'); + + +begin + +Phi0 <= Phi2; +Phi1 <= (not Phi2); + +H8 <= Hcount(3); +H16 <= Hcount(4); +H32 <= Hcount(5); +H64 <= Hcount(6); +H256_n <= not(Hcount(8)); + + +-- Vertical line comparator +VPos_sum <= DMA_n + VCount; +VCount_match <= not (Vpos_sum(7) and Vpos_sum(6) and Vpos_sum(5) and Vpos_sum(4)); +Sum_H64 <= VCount_match nand H64; +C5_8 <= not(H8 and phi1 and H256_n and Sum_H64); + + +-- Load_n signal decoder +K9_in <= C5_8 & H64 & H32 & H16; +K9: process(K9_in) +begin + case K9_in is + when "0000" => + K9_out <= "1111111110"; + when "0001" => + K9_out <= "1111111101"; + when "0010" => + K9_out <= "1111111011"; + when "0011" => + K9_out <= "1111110111"; + when "0100" => + K9_out <= "1111101111"; + when "0101" => + K9_out <= "1111011111"; + when "0110" => + K9_out <= "1110111111"; + when "0111" => + K9_out <= "1101111111"; + when others => + K9_out <= "1111111111"; + end case; +end process; +Load_n(8) <= K9_out(7); +Load_n(7) <= K9_out(6); +Load_n(6) <= K9_out(5); +Load_n(5) <= K9_out(4); +Load_n(4) <= K9_out(3); +Load_n(3) <= K9_out(2); +Load_n(2) <= K9_out(1); +Load_n(1) <= K9_out(0); + + +-- Motion object ROMs +--D8: entity work.D8_ROM +--port map( +-- clock => Clk6, +-- address => PRAM(7 downto 3) & VPos_sum(3 downto 0), +-- q => ROM_D8Q +-- ); + +D8: entity work.ROM_D8 +port map( + clk => clk6, + addr => PRAM(7 downto 3) & VPos_sum(3 downto 0), + data => ROM_D8Q +); + +--E8: entity work.E8_ROM +--port map( +-- clock => Clk6, +-- address => PRAM(7 downto 3) & VPos_sum(3 downto 0), +-- q => ROM_E8Q +-- ); + +E8: entity work.ROM_E8 +port map( + clk => clk6, + addr => PRAM(7 downto 3) & VPos_sum(3 downto 0), + data => ROM_E8Q +); + +--D7: entity work.D7_ROM +--port map( +-- clock => Clk6, +-- address => PRAM(7 downto 3) & VPos_sum(3 downto 0), +-- q => ROM_D7Q +-- ); + +D7: entity work.ROM_D7 +port map( + clk => clk6, + addr => PRAM(7 downto 3) & VPos_sum(3 downto 0), + data => ROM_D7Q +); + +--E7: entity work.E7_ROM +--port map( +-- clock => Clk6, +-- address => PRAM(7 downto 3) & VPos_sum(3 downto 0), +-- q => ROM_E7Q +-- ); + +E7: entity work.ROM_E7 +port map( + clk => clk6, + addr => PRAM(7 downto 3) & VPos_sum(3 downto 0), + data => ROM_E7Q +); + +-- Motion object ROM mux +-- Sub images are held in D7 and D8, Torpedo images in E7 and E8 selected by PRAM0 +-- Note the odd bit ordering of the ROM data outputs +SubROM_dout <= ROM_D7Q(2 downto 0) & ROM_D7Q(7 downto 4) & ROM_D8Q(3 downto 0) & ROM_D8Q(7 downto 4); +TorpROM_dout <= ROM_E7Q(2 downto 0) & ROM_E7Q(7 downto 4)& ROM_E8Q(3 downto 0) & ROM_E8Q(7 downto 4); +Vid <= SubROM_dout when PRAM(0) = '0' else + TorpROM_dout; + + +-- Submarine 1 Horizontal position counter +-- This combines two 74163s at locations K6 and K5 on the PCB +K5_6: process(clk6, H256_s, Load_n, DMA_n) +begin + if rising_edge(clk6) then + if Load_n(1) = '0' then -- preload the counter + Sub1_Hpos <= DMA_n; + elsif H256_s = '1' then -- increment the counter + Sub1_Hpos <= Sub1_Hpos + '1'; + end if; + if Sub1_Hpos(7 downto 4) = "1111" then + Sub1_Inh <= '0'; + else + Sub1_Inh <= '1'; + end if; + end if; +end process; + +-- Submarine 1 video shift register +-- This combines two 74165s at locations K7 and K8 on the PCB +K7_8: process(clk6, Sub1_Inh, Load_n, Vid) +begin + if Load_n(5) = '0' then + Sub1_reg <= Vid & '0'; -- Preload the register + elsif rising_edge(clk6) then + if Sub1_Inh = '0' then + Sub1_reg <= '0' & Sub1_reg(15 downto 1); + end if; + end if; +end process; +Sub1_n <= not (Sub1_reg(0)); + + +-- Submarine 2 Horizontal position counter +-- This combines two 74163s at locations J6 and J5 on the PCB +J6_5: process(clk6, H256_s, Load_n, DMA_n) +begin + if rising_edge(clk6) then + if Load_n(2) = '0' then -- preload the counter + Sub2_Hpos <= DMA_n; + elsif H256_s = '1' then -- increment the counter + Sub2_Hpos <= Sub2_Hpos + '1'; + end if; + if Sub2_Hpos(7 downto 4) = "1111" then + Sub2_Inh <= '0'; + else + Sub2_Inh <= '1'; + end if; + end if; +end process; + +-- Submarine 2 video shift register +-- This combines two 74165s at locations J7 and J8 on the PCB +J7_8: process(clk6, Sub2_Inh, Load_n, Vid) +begin + if Load_n(6) = '0' then + Sub2_reg <= Vid & '0'; -- Preload the register + elsif rising_edge(clk6) then + if Sub2_Inh = '0' then + Sub2_reg <= '0' & Sub2_reg(15 downto 1); + end if; + end if; +end process; +Sub2_n <= not (Sub2_reg(0)); + + +-- Torpedo 1 Horizontal position counter +-- This combines two 74163s at locations J6 and J5 on the PCB +H6_5: process(clk6, H256_s, Load_n, DMA_n) +begin + if rising_edge(clk6) then + if Load_n(3) = '0' then -- preload the counter + Torp1_Hpos <= DMA_n; + elsif H256_s = '1' then -- increment the counter + Torp1_Hpos <= Torp1_Hpos + '1'; + end if; + if Torp1_Hpos(7 downto 4) = "1111" then + Torp1_Inh <= '0'; + else + Torp1_Inh <= '1'; + end if; + end if; +end process; + +-- Torpedo 1 video shift register +-- This combines two 74165s at locations H7 and H8 on the PCB +H7_8: process(clk6, Torp1_Inh, Load_n, Vid) +begin + if Load_n(7) = '0' then + Torp1_reg <= Vid & '0'; -- Preload the register + elsif rising_edge(clk6) then + if Torp1_Inh = '0' then + Torp1_reg <= '0' & Torp1_reg(15 downto 1); + end if; + end if; +end process; +Torp1 <= Torp1_reg(0); + + +-- Torpedo 2 Horizontal position counter +-- This combines two 74163s at locations F6 and F5 on the PCB +F6_5: process(clk6, H256_s, Load_n, DMA_n) +begin + if rising_edge(clk6) then + if Load_n(4) = '0' then -- preload the counter + Torp2_Hpos <= DMA_n; + elsif H256_s = '1' then -- increment the counter + Torp2_Hpos <= Torp2_Hpos + '1'; + end if; + if Torp2_Hpos(7 downto 4) = "1111" then + Torp2_Inh <= '0'; + else + Torp2_Inh <= '1'; + end if; + end if; +end process; + +-- Torpedo 2 video shift register +-- This combines two 74165s at locations F7 and F8 on the PCB +F7_8: process(clk6, Torp2_Inh, Load_n, Vid) +begin + if Load_n(8) = '0' then + Torp2_reg <= Vid & '0'; -- Preload the register + elsif rising_edge(clk6) then + if Torp2_Inh = '0' then + Torp2_reg <= '0' & Torp2_reg(15 downto 1); + end if; + end if; +end process; +Torp2 <= Torp2_reg(0); + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/playfield.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/playfield.vhd new file mode 100644 index 00000000..3c6f42e3 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/playfield.vhd @@ -0,0 +1,185 @@ +-- Playfield generation circuitry for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity playfield is +port( + Clk6 : in std_logic; + DMA : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + VCount : in std_logic_vector(7 downto 0); + VBlank_n_s : in std_logic; -- VBLANK* on the schematic + HSync : in std_logic; + H256_s : out std_logic; -- 256H* on schematic + PFld1_n : out std_logic; + Pfld2_n : out std_logic + ); +end playfield; + +architecture rtl of playfield is + +signal HSync_n : std_logic; + +signal H256 : std_logic; +signal H256_n : std_logic; +signal H128 : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H8 : std_logic; +signal H4 : std_logic; +signal H2 : std_logic; +signal H1 : std_logic; + +signal V128 : std_logic; +signal V64 : std_logic; +signal V128_V64_n : std_logic := '1'; +signal V128_V64 : std_logic := '0'; + +signal Sonar : std_logic := '0'; +signal SnrWndo_n : std_logic := '0'; +signal SnrWndo1_n : std_logic := '0'; +signal SnrWndo2_n : std_logic := '0'; +signal M6_AQ_n : std_logic := '1'; +signal M6_BQ_n : std_logic := '1'; +signal M8_Q_n : std_logic := '1'; +signal DMA_n : std_logic_vector(7 downto 0); +signal SnrDMA_n : std_logic_vector(1 downto 0); + +signal Char_Load_n : std_logic := '1'; +signal SLoad_n : std_logic; +signal Shift_data : std_logic_vector(7 downto 0) := (others => '0'); +signal PField : std_logic := '0'; +signal Dispd : std_logic_vector(7 downto 0) := (others => '0'); + +signal L6_reg : std_logic_vector(2 downto 0); + + + +begin + +H1 <= HCount(0); +H2 <= HCount(1); +H4 <= HCount(2); +H8 <= HCount(3); +H32 <= HCount(5); +H64 <= HCount(6); +H128 <= HCount(7); +H256 <= HCount(8); +H256_n <= (not HCount(8)); +Hsync_n <= (not HSync); + +V64 <= VCount(6); +V128 <= VCount(7); + + +DMA_n <= (not DMA); +SnrDMA_n(1) <= DMA_n(7) nor SnrWndo_n; +SnrDMA_n(0) <= DMA_n(6) nor SnrWndo_n; + + + +--M4: entity work.pf_rom +--port map( +-- clock => clk6, +-- address => SnrDMA_n(1) & SnrDMA_n(0) & DMA(5 downto 0) & VCount(2 downto 0), +-- q => Dispd +-- ); + +M4: entity work.ROM_M4 +port map( + clk => clk6, + addr => SnrDMA_n(1) & SnrDMA_n(0) & DMA(5 downto 0) & VCount(2 downto 0), + data => Dispd +); + +Char_Load_n <= not (H1 and H2 and H4); +SLoad_n <= Char_Load_n or H256_n; + +-- 74LS166 video shift register +N4: process(clk6, SLoad_n, VBlank_n_s, Dispd, shift_data) +begin + if VBlank_n_s = '0' then -- Connected Clear input + shift_data <= (others => '0'); + elsif rising_edge(clk6) then + if SLoad_n = '0' then -- Parallel load + shift_data <= Dispd; + else + shift_data <= shift_data(6 downto 0) & '0'; + end if; + end if; + PField <= shift_data(7); +end process; + + +-- Sonar window circuit +V128_V64_n <= V128 nand V64; +V128_V64 <= (not V128_V64_n); +Sonar <= not (V128_V64 and H128 and H64); + +M6_A: process(Sonar, H256, H32) +begin + if H256 = '0' then -- asynchronous preset + M6_AQ_n <= '0'; + elsif rising_edge(H32) then + M6_AQ_n <= (not Sonar); + end if; +end process; + +M6_B: process(V128_V64_n, HSync_n, M8_Q_n) +begin + if M8_Q_n = '0' then -- asynchronous preset + M6_BQ_n <= '0'; + elsif rising_edge(HSync_n) then + M6_BQ_n <= (not V128_V64_n); + end if; +end process; + +M8: process(H32, H256) +begin + if rising_edge(H32) then + M8_Q_n <= (not H256); + end if; +end process; + +SnrWndo_n <= (M6_AQ_n nor M6_BQ_n); + +M7: process(H8, M6_AQ_n, M6_BQ_n) +begin + if rising_edge(H8) then + SnrWndo1_n <= (not M6_BQ_n); + SnrWndo2_n <= (not M6_AQ_n); + end if; +end process; + + +-- 74LS163 counter at L6 +-- CEP and CET tied to ground, counter is used only as a synchronous latch +L6: process(clk6, H256, Char_Load_n, DMA_n, SnrWndo_n) +begin + if rising_edge(clk6) then + if Char_Load_n = '0' then + L6_reg <= (DMA_n(7) nand SnrWndo_n) & (DMA_n(6) nand SnrWndo_n) & H256; + end if; + end if; +end process; +H256_s <= L6_reg(0); +PFLd1_n <= not (L6_reg(1) and SnrWndo1_n and PField); +PFLd2_n <= not (L6_reg(2) and SnrWndo2_n and PField); + +end rtl; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/pll.v b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/pll.v new file mode 100644 index 00000000..aec82b25 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/pll.v @@ -0,0 +1,365 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + c2, + locked); + + input inclk0; + output c0; + output c1; + output c2; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 125, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 112, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 125, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 56, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 125, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 28, + altpll_component.clk2_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/ram1k.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/ram1k.vhd new file mode 100644 index 00000000..03c350b8 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/ram1k.vhd @@ -0,0 +1,181 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: ram1k.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY ram1k IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END ram1k; + + +ARCHITECTURE SYN OF ram1k IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 1024, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + power_up_uninitialized => "FALSE", + widthad_a => 10, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + data_a => data, + wren_a => wren, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/PROM_SYNC.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/PROM_SYNC.vhd new file mode 100644 index 00000000..fb01db2d --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/PROM_SYNC.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM_SYNC is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of PROM_SYNC is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"8", + X"A",X"A",X"A",X"A",X"A",X"E",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"A", + X"A",X"A",X"B",X"B",X"B",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D7.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D7.vhd new file mode 100644 index 00000000..7fddb4f6 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D7.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_D7 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_D7 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"10",X"10",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"10",X"10",X"00",X"10", + X"00",X"60",X"F0",X"F0",X"F0",X"F0",X"70",X"70",X"30",X"30",X"30",X"10",X"10",X"00",X"00",X"00", + X"00",X"00",X"C0",X"E1",X"F1",X"F1",X"F0",X"F0",X"60",X"60",X"30",X"10",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"C0",X"F1",X"F1",X"F0",X"F0",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"C1",X"F3",X"F3",X"F1",X"F0",X"70",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"C3",X"F7",X"F7",X"F3",X"F1",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"F1",X"F7",X"F7",X"F7",X"F1",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"F1",X"F3",X"F7",X"F7",X"C3",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"70",X"F0",X"F1",X"F3",X"F3",X"C1",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"70",X"F0",X"F0",X"F1",X"F1",X"C0",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"60",X"60",X"F0",X"F0",X"F1",X"F1",X"E1",X"C0",X"00", + X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"30",X"30",X"70",X"70",X"F0",X"F0",X"F0",X"F0",X"60", + X"00",X"10",X"00",X"10",X"10",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"30",X"10",X"10", + X"00",X"30",X"70",X"30",X"30",X"20",X"20",X"30",X"30",X"10",X"10",X"10",X"00",X"00",X"00",X"00", + X"00",X"20",X"60",X"F0",X"30",X"30",X"30",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"81",X"C3",X"F0",X"50",X"60",X"30",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"03",X"E7",X"F1",X"C0",X"60",X"30",X"10",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"F7",X"97",X"C5",X"F0",X"30",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"F5",X"C7",X"F5",X"70",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"F0",X"C5",X"97",X"F7",X"02",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"60",X"C0",X"F1",X"E7",X"03",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"30",X"60",X"50",X"F0",X"C3",X"81",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"30",X"30",X"30",X"F0",X"60",X"20", + X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"30",X"30",X"20",X"20",X"30",X"30",X"70",X"30", + X"00",X"00",X"40",X"80",X"21",X"00",X"12",X"00",X"29",X"00",X"20",X"04",X"40",X"01",X"00",X"20", + X"20",X"00",X"41",X"10",X"84",X"10",X"44",X"00",X"40",X"24",X"12",X"80",X"01",X"00",X"50",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D8.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D8.vhd new file mode 100644 index 00000000..f541c271 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_D8.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_D8 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_D8 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"06",X"06",X"06",X"0E",X"0C",X"0C",X"08",X"0C", + X"00",X"00",X"00",X"08",X"08",X"0C",X"0C",X"0C",X"0E",X"06",X"02",X"0A",X"0E",X"0E",X"07",X"0E", + X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"0C",X"0C",X"04",X"06",X"0E",X"0E",X"87",X"03",X"02", + X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"0E",X"06",X"0B",X"0D",X"87",X"E1",X"C0",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"0C",X"0E",X"03",X"89",X"CF",X"F3",X"60",X"40",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"0E",X"8F",X"D9",X"FC",X"FF",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"0F",X"DF",X"F1",X"DF",X"0F",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"20",X"FF",X"FC",X"D9",X"8F",X"0E",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"40",X"60",X"F3",X"CF",X"89",X"03",X"0E",X"0C",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"C0",X"E1",X"87",X"0D",X"0B",X"06",X"0E",X"0C",X"08",X"00",X"00",X"00",X"00", + X"00",X"02",X"03",X"87",X"0E",X"0E",X"06",X"04",X"0C",X"0C",X"08",X"08",X"00",X"00",X"00",X"00", + X"00",X"0E",X"07",X"0E",X"0E",X"0A",X"02",X"06",X"0E",X"0C",X"0C",X"0C",X"08",X"08",X"00",X"00", + X"00",X"0C",X"08",X"0C",X"0C",X"0E",X"06",X"06",X"06",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"0C", + X"00",X"08",X"00",X"08",X"0C",X"0C",X"06",X"06",X"0E",X"0F",X"0F",X"8F",X"8F",X"8F",X"87",X"03", + X"00",X"00",X"00",X"00",X"08",X"0C",X"06",X"03",X"0B",X"8F",X"8F",X"CF",X"C7",X"C3",X"81",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0E",X"07",X"8F",X"8F",X"CF",X"C7",X"81",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0F",X"87",X"CF",X"EF",X"E7",X"C1",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0F",X"CF",X"EF",X"FF",X"F7",X"E1",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"CF",X"FF",X"F7",X"FF",X"CF",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"E1",X"F7",X"FF",X"EF",X"CF",X"0F",X"08",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"C1",X"E7",X"EF",X"CF",X"87",X"0F",X"0C",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"81",X"C7",X"CF",X"8F",X"8F",X"07",X"0E",X"0C",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"81",X"C3",X"C7",X"CF",X"8F",X"8F",X"0B",X"03",X"06",X"0C",X"08",X"00",X"00",X"00", + X"00",X"03",X"87",X"8F",X"8F",X"8F",X"0F",X"0F",X"0E",X"06",X"06",X"0C",X"0C",X"08",X"00",X"08", + X"00",X"0A",X"00",X"80",X"01",X"48",X"28",X"02",X"00",X"22",X"08",X"21",X"08",X"82",X"00",X"04", + X"04",X"00",X"80",X"02",X"20",X"04",X"00",X"94",X"00",X"48",X"00",X"84",X"01",X"02",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E1.vhd new file mode 100644 index 00000000..e3311767 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E1.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_E1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of ROM_E1 is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"C",X"C",X"C",X"F",X"0",X"1",X"2",X"0",X"0",X"9",X"5",X"3",X"5",X"0",X"0",X"F", + X"2",X"0",X"6",X"9",X"3",X"8",X"1",X"0",X"0",X"0",X"1",X"0",X"0",X"5",X"9",X"5", + X"2",X"0",X"3",X"5",X"2",X"0",X"3",X"4",X"1",X"2",X"4",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"5",X"C",X"3",X"1",X"2",X"0",X"3",X"4",X"1",X"2",X"4",X"0",X"0",X"0", + X"0",X"0",X"9",X"E",X"4",X"2",X"F",X"4",X"5",X"9",X"2",X"5",X"0",X"C",X"5",X"3", + X"0",X"0",X"9",X"5",X"3",X"5",X"3",X"0",X"0",X"0",X"9",X"E",X"3",X"5",X"2",X"4", + X"5",X"0",X"6",X"9",X"3",X"8",X"1",X"3",X"0",X"0",X"0",X"0",X"6",X"F",X"5",X"3", + X"0",X"1",X"6",X"5",X"A",X"0",X"0",X"0",X"3",X"2",X"5",X"4",X"9",X"4",X"3",X"0", + X"4",X"9",X"5",X"E",X"5",X"0",X"0",X"0",X"3",X"2",X"5",X"4",X"9",X"4",X"F",X"3", + X"0",X"0",X"1",X"0",X"0",X"9",X"5",X"3",X"5",X"0",X"1",X"0",X"D",X"F",X"E",X"5", + X"4",X"1",X"0",X"1",X"2",X"0",X"A",X"F",X"5",X"5",X"5",X"2",X"0",X"0",X"F",X"2", + X"0",X"A",X"5",X"7",X"1",X"4",X"F",X"2",X"6",X"F",X"3",X"0",X"0",X"F",X"9",X"E", + X"4",X"3",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"8", + X"5",X"E",X"E",X"5",X"D",X"9",X"0",X"0",X"3",X"5",X"3",X"0",X"0",X"5",X"E",X"4", + X"F",X"3",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"4",X"5",X"C", + X"0",X"5",X"E",X"5",X"D",X"9",X"7",X"F",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E2.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E2.vhd new file mode 100644 index 00000000..742cd042 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E2.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_E2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of ROM_E2 is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"4",X"1",X"3",X"6",X"5",X"4",X"5",X"4",X"5",X"4",X"4",X"4",X"4",X"4",X"5",X"4", + X"5",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"5",X"5",X"5",X"5",X"4", + X"5",X"4",X"5",X"5",X"5",X"4",X"5",X"5",X"4",X"5",X"5",X"4",X"4",X"4",X"4",X"4", + X"4",X"5",X"5",X"4",X"5",X"4",X"5",X"4",X"5",X"5",X"4",X"5",X"5",X"4",X"4",X"4", + X"4",X"4",X"4",X"4",X"5",X"5",X"4",X"4",X"5",X"4",X"5",X"4",X"4",X"4",X"4",X"5", + X"4",X"5",X"4",X"4",X"4",X"4",X"5",X"4",X"4",X"4",X"4",X"4",X"5",X"4",X"5",X"5", + X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"5",X"4",X"4",X"4",X"4",X"5",X"4",X"5",X"5", + X"4",X"4",X"5",X"4",X"5",X"4",X"4",X"4",X"4",X"5",X"4",X"4",X"4",X"5",X"5",X"4", + X"5",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"5",X"4",X"4",X"4",X"5",X"4",X"5", + X"4",X"4",X"3",X"4",X"5",X"4",X"4",X"4",X"4",X"4",X"3",X"4",X"4",X"4",X"4",X"4", + X"4",X"4",X"5",X"4",X"5",X"4",X"4",X"4",X"5",X"4",X"5",X"5",X"4",X"5",X"4",X"5", + X"4",X"4",X"5",X"4",X"4",X"4",X"4",X"5",X"5",X"4",X"5",X"4",X"5",X"4",X"4",X"4", + X"5",X"5",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"5", + X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"5",X"5",X"5",X"4",X"5",X"5",X"4",X"5", + X"4",X"5",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4", + X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"4",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E7.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E7.vhd new file mode 100644 index 00000000..2e191753 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E7.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_E7 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_E7 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"20",X"00",X"10",X"00",X"21",X"00",X"20",X"00",X"40",X"00",X"00",X"00", + X"00",X"00",X"00",X"10",X"80",X"10",X"40",X"00",X"40",X"20",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E8.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E8.vhd new file mode 100644 index 00000000..abae3db8 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_E8.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_E8 is +port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_E8 is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"02",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_M4.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_M4.vhd new file mode 100644 index 00000000..3192d26a --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_M4.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_M4 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_M4 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"6C",X"C6",X"C6",X"FE",X"C6",X"C6", + X"00",X"FC",X"C6",X"C6",X"FC",X"C6",X"C6",X"FC",X"00",X"3C",X"66",X"C0",X"C0",X"C0",X"66",X"3C", + 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Hardware/Subs/rtl/roms/ROM_N2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_N2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_N2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"BD",X"DC",X"38",X"85",X"8F",X"A0",X"14",X"B1",X"8E",X"29",X"3F",X"05",X"8D",X"99",X"A6",X"0A", + X"88",X"10",X"F4",X"E0",X"02",X"F0",X"26",X"E0",X"04",X"F0",X"22",X"A5",X"8C",X"0A",X"0A",X"0A", + X"0A",X"29",X"C0",X"85",X"8D",X"BD",X"E3",X"38",X"85",X"8E",X"BD",X"E4",X"38",X"85",X"8F",X"A0", + X"11",X"B1",X"8E",X"29",X"3F",X"05",X"8D",X"99",X"C7",X"0A",X"88",X"10",X"F4",X"A5",X"8C",X"6A", + X"6A",X"6A",X"29",X"C0",X"85",X"8D",X"A9",X"FF",X"85",X"D0",X"A5",X"63",X"29",X"02",X"F0",X"0A", + X"A5",X"80",X"29",X"10",X"D0",X"04",X"A9",X"00",X"85",X"D0",X"BD",X"EB",X"38",X"85",X"8E",X"BD", + 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X"D3",X"CC",X"C1",X"CD",X"00",X"C3",X"CF",X"C9",X"CE",X"CC",X"C5",X"C6",X"D4",X"00",X"D2",X"C9", + X"C7",X"C8",X"D4",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"EB",X"2C",X"1C",X"3C",X"1C",X"3C"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P1.vhd new file mode 100644 index 00000000..12f0139f --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_P1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_P1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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Hardware/Subs/rtl/roms/ROM_P2.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P2.vhd new file mode 100644 index 00000000..d9ffef90 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/roms/ROM_P2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_P2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_P2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F2",X"A5",X"8F",X"10",X"0D",X"A9",X"00",X"38",X"E5",X"D2",X"85",X"D2",X"A9",X"00",X"E5",X"D3", + X"85",X"D3",X"60",X"BD",X"00",X"00",X"A9",X"00",X"85",X"D3",X"A5",X"8F",X"38",X"E9",X"07",X"AA", + X"29",X"07",X"85",X"8F",X"8A",X"29",X"F8",X"0A",X"26",X"D3",X"0A",X"26",X"D3",X"85",X"D2",X"A5", + X"8E",X"38",X"E9",X"06",X"AA",X"29",X"07",X"85",X"8E",X"8A",X"4A",X"4A",X"4A",X"18",X"65",X"D2", + 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X"8E",X"29",X"3F",X"05",X"8D",X"99",X"C7",X"09",X"88",X"10",X"DB",X"BC",X"BD",X"39",X"A9",X"04", + X"C5",X"97",X"90",X"02",X"A5",X"97",X"09",X"30",X"05",X"8D",X"99",X"C7",X"09",X"A5",X"8C",X"0A", + X"0A",X"29",X"C0",X"85",X"8D",X"10",X"02",X"85",X"62",X"24",X"8D",X"50",X"02",X"85",X"60",X"A5", + X"A0",X"10",X"02",X"85",X"60",X"A5",X"A2",X"10",X"02",X"85",X"62",X"BD",X"DB",X"38",X"85",X"8E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sid_coeffs.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sid_coeffs.vhd new file mode 100644 index 00000000..f4df542d --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sid_coeffs.vhd @@ -0,0 +1,2076 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sid_coeffs is + port ( + clk: in std_logic; + addr: in integer range 0 to 2047; + val: out std_logic_vector(15 downto 0) + ); +end entity; + +architecture beh of sid_coeffs is + +type mtype is array(0 to 2047) of std_logic_vector(15 downto 0); + +constant coef: mtype := ( +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d5", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02d8", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02db", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02df", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e2", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e5", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02e8", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ec", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02ef", +x"02f2", +x"02f2", +x"02f2", +x"02f2", +x"02f2", +x"02f2", +x"02f2", +x"02f2", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f6", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02f9", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"02fc", +x"0300", +x"0300", +x"0300", +x"0300", +x"0300", +x"0300", +x"0300", +x"0300", +x"0300", +x"0303", +x"0303", +x"0303", +x"0303", +x"0303", +x"0303", +x"0303", +x"0303", +x"0303", +x"0306", +x"0306", +x"0306", +x"0306", +x"0306", +x"0306", +x"0306", +x"0306", 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+x"e5fa", +x"e601", +x"e607", +x"e60e", +x"e618", +x"e61e", +x"e625", +x"e62b", +x"e632", +x"e639", +x"e642", +x"e649", +x"e650", +x"e656", +x"e65d", +x"e663", +x"e66a", +x"e671", +x"e677", +x"e67e", +x"e684", +x"e68b", +x"e691", +x"e698", +x"e69f", +x"e6a5", +x"e6ac", +x"e6b2", +x"e6b9", +x"e6c0", +x"e6c6", +x"e6cd", +x"e6d3", +x"e6da", +x"e6dd", +x"e6e4", +x"e6ea", +x"e6f1", +x"e6f8", +x"e6fe", +x"e705", +x"e708", +x"e70f", +x"e715", +x"e71c", +x"e722", +x"e729", +x"e72c", +x"e733", +x"e739", +x"e740", +x"e747", +x"e74d", +x"e751", +x"e757", +x"e75e", +x"e764", +x"e768", +x"e76e", +x"e775", +x"e77b", +x"e782", +x"e785", +x"e78c", +x"e792", +x"e799", +x"e7a0"); + +begin + +process(clk) +begin +if rising_edge(clk) then + val <= coef(addr); +end if; +end process; + +end beh; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/subs_core.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/subs_core.vhd new file mode 100644 index 00000000..abab0bd2 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/subs_core.vhd @@ -0,0 +1,274 @@ +-- Top level file for Atari Subs +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple +-- See Subs manual Figure 4-11 for video output details. Resistor values listed here have been scaled +-- for 3.3V logic. Original game supported two types of monitors but composite video will work for +-- almost all displays. + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity subs_core is +port( + clk12 : in std_logic; + Clk_50_I : in std_logic; -- 50MHz input clock + Reset_I : in std_logic; -- Reset button (Active low) + Vid1_O : out std_logic; -- Display 1 video output, 680R resistor to CompVid1 + Vid2_O : out std_logic; -- Display 2 video output, 680R resistor to CompVid2 + CompSync_O : out std_logic; -- Composite sync output, 1.2k resistor to each CompVid output + CompBlank_O : out std_logic; -- Composite blank output, 1.2k resistor to each CompVid output + HBlank : out std_logic; + VBlank : out std_logic; + HSync : out std_logic; + VSync : out std_logic; + Coin1_I : in std_logic; -- Coin switches (Active low) + Coin2_I : in std_logic; + Start1_I : in std_logic; -- Start buttons + Start2_I : in std_logic; + Fire1_I : in std_logic; + Fire2_I : in std_logic; + Steer_1A_I : in std_logic; -- Steering wheel inputs, these are quadrature encoders + Steer_1B_I : in std_logic; + Steer_2A_I : in std_logic; + Steer_2B_I : in std_logic; + Test_I : in std_logic; -- Self-test switch + DiagStep_I : in std_logic; -- Self-test advance button + DiagHold_I : in std_logic; + Slam_I : in std_logic; + DIP_Sw : in std_logic_vector(7 downto 0); + P1_audio : out std_logic_vector(7 downto 0); + P2_audio : out std_logic_vector(7 downto 0); + LED1_O : out std_logic; -- Player 1 and 2 start button LEDs + LED2_O : out std_logic; + CCounter_O : out std_logic -- Coin counter + ); +end subs_core; + +architecture rtl of subs_core is + +signal Clk6 : std_logic; +signal Ena_3k : std_logic; +signal Phi1 : std_logic; +signal Phi2 : std_logic; +signal Reset_n : std_logic; + +signal HCount : std_logic_vector(8 downto 0); +signal VCount : std_logic_vector(7 downto 0); +--signal HSync : std_logic; +signal HBlank_s : std_logic; +--signal VBlank : std_logic; +signal HSync_s : std_logic; +signal VBlank_s : std_logic; +signal VBlank_n_s : std_logic; +signal VReset : std_logic; +signal VSync_s : std_logic; +signal VSync_n : std_logic; + +signal H256_s : std_logic; +signal PFLd1_n : std_logic; +signal PFLd2_n : std_logic; + +signal Sub1_n : std_logic; +signal Sub2_n : std_logic; +signal Torp1 : std_logic; +signal Torp2 : std_logic; + +signal Invert1 : std_logic; +signal Invert2 : std_logic; + +signal Adr : std_logic_vector(10 downto 0); + +signal DBus_in : std_logic_vector(7 downto 0); +signal DMA : std_logic_vector(7 downto 0); +signal DMA_n : std_logic_vector(7 downto 0); +signal PRAM : std_logic_vector(7 downto 0); +signal Load_n : std_logic_vector(8 downto 1); + +signal Control_Read_n : std_logic := '1'; +signal Steer_Reset_n : std_logic := '1'; +signal Options_Read_n : std_logic := '1'; +signal Coin_Read_n : std_logic := '1'; +signal SW_F9 : std_logic_vector(7 downto 0); + +signal Noise_Reset_n : std_logic := '1'; +signal SnrStart1 : std_logic := '0'; +signal SnrStart2 : std_logic := '0'; +signal Crash : std_logic := '0'; +signal Explode : std_logic := '0'; +signal Video : std_logic_vector(1 downto 0); + +begin + +Vid_sync: entity work.synchronizer +port map( + Clk_12 => Clk12, + Clk_6 => Clk6, + HCount => HCount, + VCount => VCount, + HSync => HSync_s, + HBlank => HBlank_s, + VBlank_s => VBlank_s, + VBlank_n_s => VBlank_n_s, + VBlank => VBlank_s, + VSync => VSync_s, + VSync_n => VSync_n + ); + + +PF: entity work.playfield +port map( + Clk6 => Clk6, + DMA => DMA, + HCount => HCount, + VCount => VCount, + VBlank_n_s => VBlank_n_s, + HSync => HSync_s, + H256_s => H256_s, + PFld1_n => PFld1_n, + Pfld2_n => PFLd2_n + ); + + +Objects: entity work.motion +port map( + Clk6 => Clk6, + PHI2 => Phi2, + DMA_n => DMA_n, + PRAM => PRAM, + H256_s => H256_s, + VCount => VCount, + HCount => Hcount, + Load_n => Load_n, + Sub1_n => Sub1_n, + Sub2_n => Sub2_n, + Torp1 => Torp1, + Torp2 => Torp2 + ); + + +VidMixer: entity work.mixer +port map( + Clk6 => Clk6, + PRAM => PRAM, + VBlank_n_s => VBlank_n_s, + Load_n => Load_n, + Invert1 => Invert1, + Invert2 => Invert2, + PFld1_n => PFld1_n, + PFld2_n => PFld2_n, + Sub1_n => Sub1_n, + Sub2_n => Sub2_n, + Torp1 => Torp1, + Torp2 => Torp2, + H256_s => H256_s, + Video1 => Vid1_O, + Video2 => Vid2_O + ); + + +CPU: entity work.cpu_mem +port map( + Clk6 => Clk6, + Ena_3k => Ena_3k, + Reset_I => Reset_I, + Reset_n => Reset_n, + VCount => VCount, + HCount => HCount, + Test_n => Test_I, + DBus_in => DBus_in, + PRAM => PRAM, + Adr => Adr, + Control_Read_n => Control_Read_n, + Steer_Reset_n => Steer_Reset_n, + Options_Read_n => Options_Read_n, + Coin_Read_n => Coin_Read_n, + LED1 => LED1_O, + LED2 => LED2_O, + SnrStart1 => SnrStart1, + SnrStart2 => SnrStart2, + Noise_Reset_n => Noise_Reset_n, + Crash => Crash, + Explode => Explode, + Invert1 => Invert1, + Invert2 => Invert2, + PHI1 => Phi1, + PHI2 => Phi2, + DMA => DMA, + DMA_n => DMA_n + ); + +Inputs: entity work.input +port map( + Clk6 => Clk6, + Sw_F9 => "10000000",--DIP_Sw, + Coin1_n => Coin1_I, + Coin2_n => Coin2_I, + Start1 => Start1_I, + Start2 => Start2_I, + Fire1 => Fire1_I, + Fire2 => Fire2_I, + Test_n => Test_I, + Diag_step => DiagStep_I, + Diag_hold => DiagHold_I, + Slam => Slam_I, + Steering1A_n => Steer_1A_I, + Steering1B_n => Steer_1B_I, + Steering2A_n => Steer_2A_I, + Steering2B_n => Steer_2B_I, + SteerReset_n => Steer_Reset_n, + Coin_Rd_n => Coin_Read_n, + Control_Rd_n => Control_Read_n, + Options_Rd_n => Options_Read_n, + VBlank_n_s => VBlank_n_s, + Adr => Adr(2 downto 0), + DBus => DBus_in, + Coin_Ctr => CCounter_O + ); + +Sound: Entity work.audio +port map( + Clk_50 => Clk_50_I, + Clk_12 => Clk12, + Clk_6 => Clk6, + Ena_3k => Ena_3k, + Reset_n => Reset_n, + Load_n => Load_n, + SnrStart1 => SnrStart1, + SnrStart2 => SnrStart2, + Noise_reset_n => Noise_Reset_n, + Crash => Crash, + Explode => Explode, + PRAM => PRAM, + HCount => HCount, + VCount => VCount, + P1_audio => P1_audio, + P2_audio => P2_audio + ); + + +-- Some logic to combine the video blanking and sync signals +CompBlank_O <= HBlank_s nor VBlank_s; +CompSync_O <= HSync_s nor VSync_s; +HBlank <= HBlank_s; +VBlank <= not VBlank_n_s; +HSync <= HSync_s; +VSync <= VSync_s; + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/svfilter.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/svfilter.vhd new file mode 100644 index 00000000..7ae5a07a --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/svfilter.vhd @@ -0,0 +1,246 @@ +-- +-- (C) Alvaro Lopes All Rights Reserved +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity sid_filters is +port ( + clk : in std_logic; -- At least 12Mhz + rst : in std_logic; + -- SID registers. + Fc_lo : in std_logic_vector(7 downto 0); + Fc_hi : in std_logic_vector(7 downto 0); + Res_Filt : in std_logic_vector(7 downto 0); + Mode_Vol : in std_logic_vector(7 downto 0); + -- Voices - resampled to 13 bit + voice1 : in signed(12 downto 0); + voice2 : in signed(12 downto 0); + voice3 : in signed(12 downto 0); + -- + input_valid : in std_logic; + ext_in : in signed(12 downto 0); + + sound : out signed(18 downto 0); + valid : out std_logic +); +end entity; + +architecture beh of sid_filters is + + alias filt : std_logic_vector(3 downto 0) is Res_Filt(3 downto 0); + alias res : std_logic_vector(3 downto 0) is Res_Filt(7 downto 4); + alias volume : std_logic_vector(3 downto 0) is Mode_Vol(3 downto 0); + alias hp_bp_lp : std_logic_vector(2 downto 0) is Mode_Vol(6 downto 4); + alias voice3off : std_logic is Mode_Vol(7); + + constant mixer_DC : integer := -475; -- NOTE to self: this might be wrong. + + type regs_type is record + Vhp : signed(17 downto 0); + Vbp : signed(17 downto 0); + dVbp : signed(17 downto 0); + Vlp : signed(17 downto 0); + dVlp : signed(17 downto 0); + Vi : signed(17 downto 0); + Vnf : signed(17 downto 0); + Vf : signed(17 downto 0); + w0 : signed(17 downto 0); + q : signed(17 downto 0); + vout : signed(18 downto 0); + state : integer; + done : std_logic; + end record; + + signal addr : integer range 0 to 2047; + signal val : std_logic_vector(15 downto 0); + + type divmul_t is array(0 to 15) of integer; + constant divmul: divmul_t := ( + 1448, 1323, 1218, 1128, 1051, 984, 925, 872, 825, 783, 745, 710, 679, 650, 624, 599 + ); + + signal r : regs_type; + + signal mula : signed(17 downto 0); + signal mulb : signed(17 downto 0); + signal mulr : signed(35 downto 0); + signal mulen : std_logic; + + function s13_to_18(a: in signed(12 downto 0)) return signed is + begin + return a(12)&a(12)&a(12)&a(12)&a(12)&a; + end function; + + signal fc : std_logic_vector(10 downto 0); + +begin + + process(clk) + begin + if rising_edge(clk) then + if mulen='1' then + mulr <= mula * mulb; + end if; + end if; + end process; + + fc <= Fc_hi & Fc_lo(2 downto 0); + + c: entity work.sid_coeffs + port map ( + clk => clk, + addr => addr, + val => val + ); + + addr <= to_integer(unsigned(fc)); + + process(clk, rst, r, input_valid, val, filt, voice1, voice2, voice3, voice3off, mulr, ext_in, hp_bp_lp, Mode_Vol) + variable w: regs_type; + begin + w:=r; + mula <= (others => 'X'); + mulb <= (others => 'X'); + mulen <= '0'; + + case r.state is + when 0 => + w.done := '0'; + if input_valid = '1' then + w.state := 1; + -- Reset Vin, Vnf + w.vi := (others => '0'); + w.vnf := (others => '0'); + end if; + + when 1 => + w.state := 2; + -- already have W0 ready. Always positive + w.w0 := "00" & signed(val); + -- 1st accumulation + if filt(0)='1' then + w.vi := r.vi + s13_to_18(voice1); + else + w.vnf := r.vnf + s13_to_18(voice1); + end if; + + when 2 => + w.state := 3; + -- 2nd accumulation + if filt(1)='1' then + w.vi := r.vi + s13_to_18(voice2); + else + w.vnf := r.vnf + s13_to_18(voice2); + end if; + -- Mult + mula <= r.w0; + mulb <= r.vhp; + mulen <= '1'; + + when 3 => + w.state := 4; + -- 3rd accumulation + if filt(2)='1' then + w.vi := r.vi + s13_to_18(voice3); + else + if voice3off='0' then + w.vnf := r.vnf + s13_to_18(voice3); + end if; + end if; + -- Mult + mula <= r.w0; + mulb <= r.vbp; + mulen <= '1'; + w.dVbp := mulr(35) & mulr(35 downto 19); + + when 4 => + w.state := 5; + -- 4th accumulation + if filt(3)='1' then + w.vi := r.vi + s13_to_18(ext_in); + else + w.vnf := r.vnf + s13_to_18(ext_in); + end if; + w.dVlp := mulr(35) & mulr(35 downto 19); + w.Vbp := r.Vbp - r.dVbp; + -- Get Q, synchronous. + w.q := to_signed(divmul(to_integer(unsigned(res))), 18); + + when 5 => + w.state := 6; + -- Ok, we have all summed. We performed multiplications for dVbp and dVlp. + -- new Vbp already computed. + mulen <= '1'; + mula <= r.q; + mulb <= r.Vbp; + w.vlp := r.Vlp - r.dVlp; + -- Start computing output; + if hp_bp_lp(1)='1' then + w.Vf := r.Vbp; + else + w.Vf := (others => '0'); + end if; + + when 6 => + w.state := 7; + -- Adjust Vbp*Q, shift by 10 + w.Vhp := (mulr(35)&mulr(26 downto 10)) - r.vlp; + if hp_bp_lp(0)='1' then + w.Vf := r.Vf + r.Vlp; + end if; + + when 7 => + w.state := 8; + w.Vhp := r.Vhp - r.Vi; + + when 8 => + w.state := 9; + if hp_bp_lp(2)='1' then + w.Vf := r.Vf + r.Vhp; + end if; + + when 9 => + w.state := 10; + w.Vf := r.Vf + r.Vnf; + + when 10 => + w.state := 11; + -- Add mixer DC + w.Vf := r.Vf + to_signed(mixer_DC, r.Vf'LENGTH); + + when 11 => + w.state := 12; + -- Process volume + mulen <= '1'; + mula <= r.Vf; + mulb <= (others => '0'); + mulb(3 downto 0) <= signed(volume); + + when 12 => + w.state := 0; + w.done := '1'; + w.vout(18) := mulr(35); + w.vout(17 downto 0) := mulr(17 downto 0); + + when others => null; + end case; + + if rst='1' then + w.done := '0'; + w.state := 0; + w.Vlp := (others => '0'); + w.Vbp := (others => '0'); + w.Vhp := (others => '0'); + end if; + + if rising_edge(clk) then + r<=w; + end if; + end process; + + sound <= r.vout; + valid <= r.done; + +end beh; diff --git a/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sync.vhd b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sync.vhd new file mode 100644 index 00000000..836393a3 --- /dev/null +++ b/Arcade_MiST/Atari BW Raster Hardware/Subs/rtl/sync.vhd @@ -0,0 +1,158 @@ +-- Video synchronizer circuit for Atari Subs +-- Similar circuit used in many other Atari and Kee Games arcade games +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity synchronizer is +port( + Clk_12 : in std_logic; + Clk_6 : out std_logic; + HCount : out std_logic_vector(8 downto 0); + VCount : out std_logic_vector(7 downto 0); + HSync : buffer std_logic; + HBlank : buffer std_logic; + VBlank_s : buffer std_logic; + VBlank_n_s : out std_logic; + VBlank : out std_logic; + VSync : out std_logic; + VSync_n : out std_logic); +end synchronizer; + +architecture rtl of synchronizer is + +signal H_counter : std_logic_vector(9 downto 0) := (others => '0'); +signal H256 : std_logic; +signal H256_n : std_logic; +signal H128 : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H16 : std_logic; +signal H8 : std_logic; +signal H4 : std_logic; +signal H2 : std_logic; +signal H1 : std_logic; + +signal V_counter : std_logic_vector(7 downto 0) := (others => '0'); +signal V128 : std_logic; +signal V64 : std_logic; +signal V32 : std_logic; +signal V16 : std_logic; +signal V8 : std_logic; +signal V4 : std_logic; +signal V2 : std_logic; +signal V1 : std_logic; + +signal HSync_n : std_logic := '1'; +signal VReset_n : std_logic := '1'; + +signal sync_data : std_logic_vector(3 downto 0); + +begin + +Clk_6 <= H_counter(0); +H8 <= H_counter(4); +H32 <= H_counter(6); +H64 <= H_counter(7); +H128 <= H_counter(8); +H256 <= H_counter(9); +H256_n <= (not H_counter(9)); +HCount <= H_counter(9 downto 1); + +V64 <= V_counter(6); +V128 <= V_counter(7); +VCount <= V_counter(7 downto 0); + +-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 +-- using only the last three count states +H_count: process(clk_12) +begin + if rising_edge(clk_12) then + if h_counter = "1111111111" then + h_counter <= "0100000000"; + else + h_counter <= h_counter + 1; + end if; + end if; +end process; + +-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line +V_count: process(HSync) +begin + if rising_edge(HSync) then + if vreset_n = '0' then + v_counter <= (others => '0'); + else + v_counter <= v_counter + '1'; + end if; + end if; +end process; + +-- A pair of D type flip-flops that generate the HBlank and HSync signals +M9_A: process(H256_n, H64, H32) +begin + if H256_n = '0' then + HBlank <= '0'; + else + if rising_edge(H32) then + HBlank <= not H64; + end if; + end if; +end process; + +M9_B: process(HBlank, H8) +begin + if HBlank = '0' then + HSync <= '0'; + hsync_n <= '1'; + else + if rising_edge(H8) then + HSync <= H32; + hsync_n <= (not H32); + end if; + end if; +end process; + +-- Many Kee and Atari games used a small bipolar PROM to decode the VSync signals +--N8: entity work.prom +--port map( +-- address => Vblank_s & V_counter(7 downto 6) & V_counter(4 downto 0), +-- data => sync_data +-- ); + +N8: entity work.PROM_SYNC +port map( + clk => Clk_12, + addr => Vblank_s & V_counter(7 downto 6) & V_counter(4 downto 0), + data => sync_data +); + +-- Latch on output of sync PROM +N9: process(HSync, sync_data) +begin + if rising_edge(HSync) then + VBlank_s <= sync_data(3); + VBlank_n_s <= (not sync_data(3)); + VReset_n <= (not sync_data(2)); + VBlank <= sync_data(1); + Vsync <= sync_data(0); + Vsync_n <= (not sync_data(0)); + end if; +end process; + +end rtl; \ No newline at end of file